Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	40011700	1			T13	11		T16	11		T18	5
all_pins[1]	40011700	1			T13	11		T16	11		T18	5
all_pins[2]	40011700	1			T13	11		T16	11		T18	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	87413854	1			T13	26		T16	26		T18	14
values[0x1]	32621246	1			T13	7		T16	7		T18	1
transitions[0x0=>0x1]	28823565	1			T13	6		T16	4		T18	1
transitions[0x1=>0x0]	28823588	1			T13	6		T16	4		T18	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	39840475	1			T13	9		T16	9		T18	5
all_pins[0]	values[0x1]	171225	1			T13	2		T16	2		T20	3
all_pins[0]	transitions[0x0=>0x1]	170990	1			T13	2		T16	2		T20	2
all_pins[0]	transitions[0x1=>0x0]	14911526	1			T13	2		T16	1		T18	1
all_pins[1]	values[0x0]	22473417	1			T13	8		T16	7		T18	5
all_pins[1]	values[0x1]	17538283	1			T13	3		T16	4		T20	1
all_pins[1]	transitions[0x0=>0x1]	17404201	1			T13	3		T16	2		T20	1
all_pins[1]	transitions[0x1=>0x0]	37143	1			T13	2		T20	3		T23	4
all_pins[2]	values[0x0]	25099962	1			T13	9		T16	10		T18	4
all_pins[2]	values[0x1]	14911738	1			T13	2		T16	1		T18	1
all_pins[2]	transitions[0x0=>0x1]	11248374	1			T13	1		T18	1		T20	1
all_pins[2]	transitions[0x1=>0x0]	13874919	1			T13	2		T16	3		T32	1