Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 4255 1 T13 10 T16 10 T18 4
all_values[1] 4255 1 T13 10 T16 10 T18 4
all_values[2] 4255 1 T13 10 T16 10 T18 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6108 1 T13 20 T16 20 T18 8
auto[1] 6657 1 T13 10 T16 10 T18 4


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4856 1 T13 11 T16 10 T18 6
auto[1] 7909 1 T13 19 T16 20 T18 6


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7302 1 T13 15 T16 14 T18 8
auto[1] 5463 1 T13 15 T16 16 T18 4


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 776 1 T13 3 T16 4 T18 3
all_values[0] auto[0] auto[0] auto[1] 377 1 T16 1 T20 1 T32 1
all_values[0] auto[0] auto[1] auto[0] 858 1 T16 1 T23 1 T32 1
all_values[0] auto[0] auto[1] auto[1] 395 1 T13 1 T20 1 T23 3
all_values[0] auto[1] auto[0] auto[1] 877 1 T13 5 T16 2 T18 1
all_values[0] auto[1] auto[1] auto[1] 972 1 T13 1 T16 2 T20 1
all_values[1] auto[0] auto[0] auto[0] 764 1 T13 2 T16 3 T18 1
all_values[1] auto[0] auto[0] auto[1] 451 1 T18 1 T20 3 T23 1
all_values[1] auto[0] auto[1] auto[0] 835 1 T13 2 T16 1 T23 1
all_values[1] auto[0] auto[1] auto[1] 413 1 T13 1 T16 1 T32 2
all_values[1] auto[1] auto[0] auto[1] 835 1 T13 3 T16 1 T18 2
all_values[1] auto[1] auto[1] auto[1] 957 1 T13 2 T16 4 T20 1
all_values[2] auto[0] auto[0] auto[0] 739 1 T13 3 T16 1 T20 3
all_values[2] auto[0] auto[0] auto[1] 415 1 T13 2 T16 2 T23 1
all_values[2] auto[0] auto[1] auto[0] 884 1 T13 1 T18 2 T20 1
all_values[2] auto[0] auto[1] auto[1] 395 1 T18 1 T20 1 T23 1
all_values[2] auto[1] auto[0] auto[1] 874 1 T13 2 T16 6 T23 4
all_values[2] auto[1] auto[1] auto[1] 948 1 T13 2 T16 1 T18 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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