Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.53 98.69 100.00 100.00 99.76 99.49 99.86


Total test records in report: 880
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T757 /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.1865098138 Jan 07 01:17:10 PM PST 24 Jan 07 01:27:36 PM PST 24 13297520963 ps
T758 /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.339395532 Jan 07 01:16:56 PM PST 24 Jan 07 02:00:44 PM PST 24 496632975438 ps
T759 /workspace/coverage/default/49.hmac_burst_wr.3281653791 Jan 07 01:16:29 PM PST 24 Jan 07 01:17:13 PM PST 24 3407889750 ps
T760 /workspace/coverage/default/14.hmac_wipe_secret.3804714074 Jan 07 01:14:47 PM PST 24 Jan 07 01:15:03 PM PST 24 1619227255 ps
T761 /workspace/coverage/default/6.hmac_test_hmac_vectors.1230913050 Jan 07 01:14:02 PM PST 24 Jan 07 01:14:04 PM PST 24 506836745 ps
T58 /workspace/coverage/default/1.hmac_sec_cm.4081018446 Jan 07 01:13:39 PM PST 24 Jan 07 01:13:41 PM PST 24 94479754 ps
T762 /workspace/coverage/default/25.hmac_long_msg.3275480785 Jan 07 01:15:03 PM PST 24 Jan 07 01:16:27 PM PST 24 4869592375 ps
T763 /workspace/coverage/default/31.hmac_back_pressure.1708700827 Jan 07 01:15:28 PM PST 24 Jan 07 01:15:48 PM PST 24 3276851368 ps
T764 /workspace/coverage/default/19.hmac_error.2204398975 Jan 07 01:14:52 PM PST 24 Jan 07 01:14:56 PM PST 24 268129223 ps
T765 /workspace/coverage/default/0.hmac_test_hmac_vectors.4270143261 Jan 07 01:13:42 PM PST 24 Jan 07 01:13:45 PM PST 24 64879881 ps
T766 /workspace/coverage/default/28.hmac_alert_test.2919641490 Jan 07 01:15:27 PM PST 24 Jan 07 01:15:28 PM PST 24 16755720 ps
T767 /workspace/coverage/default/42.hmac_burst_wr.1199348272 Jan 07 01:16:09 PM PST 24 Jan 07 01:16:54 PM PST 24 4381723867 ps
T768 /workspace/coverage/default/44.hmac_test_sha_vectors.1767933424 Jan 07 01:16:20 PM PST 24 Jan 07 01:23:01 PM PST 24 51183059256 ps
T769 /workspace/coverage/default/8.hmac_error.2011180977 Jan 07 01:14:01 PM PST 24 Jan 07 01:17:07 PM PST 24 39892687129 ps
T770 /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.3066872886 Jan 07 01:17:12 PM PST 24 Jan 07 02:17:07 PM PST 24 168162423262 ps
T771 /workspace/coverage/default/39.hmac_error.3289002625 Jan 07 01:16:06 PM PST 24 Jan 07 01:17:32 PM PST 24 13906530181 ps
T772 /workspace/coverage/default/14.hmac_stress_all.3040794851 Jan 07 01:14:46 PM PST 24 Jan 07 01:37:43 PM PST 24 120279893374 ps
T773 /workspace/coverage/default/7.hmac_wipe_secret.4086825543 Jan 07 01:14:02 PM PST 24 Jan 07 01:15:09 PM PST 24 24558277945 ps
T774 /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.4261848908 Jan 07 01:17:14 PM PST 24 Jan 07 02:05:40 PM PST 24 341438812831 ps
T775 /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.3608670257 Jan 07 01:17:11 PM PST 24 Jan 07 02:16:19 PM PST 24 174536888352 ps
T776 /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.1473278163 Jan 07 01:17:11 PM PST 24 Jan 07 01:46:35 PM PST 24 90920046524 ps
T777 /workspace/coverage/default/14.hmac_long_msg.14377575 Jan 07 01:14:47 PM PST 24 Jan 07 01:15:24 PM PST 24 2942972511 ps
T778 /workspace/coverage/default/18.hmac_long_msg.4256815040 Jan 07 01:14:49 PM PST 24 Jan 07 01:15:40 PM PST 24 1787960324 ps
T779 /workspace/coverage/default/47.hmac_stress_all.120328591 Jan 07 01:16:24 PM PST 24 Jan 07 01:32:17 PM PST 24 20111734453 ps
T780 /workspace/coverage/default/14.hmac_datapath_stress.2414790963 Jan 07 01:14:49 PM PST 24 Jan 07 01:16:04 PM PST 24 5381867752 ps
T781 /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.3161561148 Jan 07 01:16:22 PM PST 24 Jan 07 02:32:39 PM PST 24 199769312781 ps
T782 /workspace/coverage/default/8.hmac_datapath_stress.3104339446 Jan 07 01:14:03 PM PST 24 Jan 07 01:14:09 PM PST 24 97333427 ps
T783 /workspace/coverage/default/20.hmac_datapath_stress.2776760548 Jan 07 01:14:55 PM PST 24 Jan 07 01:16:19 PM PST 24 3197454310 ps
T784 /workspace/coverage/default/4.hmac_datapath_stress.3875621329 Jan 07 01:14:02 PM PST 24 Jan 07 01:15:00 PM PST 24 1043541153 ps
T785 /workspace/coverage/default/11.hmac_datapath_stress.19965712 Jan 07 01:14:45 PM PST 24 Jan 07 01:16:33 PM PST 24 2866122465 ps
T786 /workspace/coverage/default/22.hmac_error.2591949993 Jan 07 01:14:58 PM PST 24 Jan 07 01:17:13 PM PST 24 33631578435 ps
T787 /workspace/coverage/default/48.hmac_smoke.1044057296 Jan 07 01:16:33 PM PST 24 Jan 07 01:16:35 PM PST 24 44324986 ps
T788 /workspace/coverage/default/40.hmac_alert_test.3843783098 Jan 07 01:16:05 PM PST 24 Jan 07 01:16:10 PM PST 24 47320089 ps
T789 /workspace/coverage/default/32.hmac_test_sha_vectors.3601043650 Jan 07 01:15:42 PM PST 24 Jan 07 01:22:57 PM PST 24 8352158188 ps
T790 /workspace/coverage/default/48.hmac_long_msg.3708263000 Jan 07 01:16:25 PM PST 24 Jan 07 01:16:33 PM PST 24 124280384 ps
T791 /workspace/coverage/default/36.hmac_alert_test.320090939 Jan 07 01:15:53 PM PST 24 Jan 07 01:15:56 PM PST 24 53951167 ps
T792 /workspace/coverage/default/22.hmac_alert_test.3619578243 Jan 07 01:15:02 PM PST 24 Jan 07 01:15:05 PM PST 24 36928730 ps
T793 /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.232028734 Jan 07 01:17:10 PM PST 24 Jan 07 02:52:55 PM PST 24 235515476461 ps
T794 /workspace/coverage/default/48.hmac_alert_test.627222481 Jan 07 01:16:33 PM PST 24 Jan 07 01:16:34 PM PST 24 11729075 ps
T795 /workspace/coverage/default/16.hmac_smoke.126445596 Jan 07 01:14:45 PM PST 24 Jan 07 01:14:49 PM PST 24 989114246 ps
T796 /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.3012253555 Jan 07 01:17:11 PM PST 24 Jan 07 01:29:36 PM PST 24 138959197140 ps
T797 /workspace/coverage/default/46.hmac_smoke.2550029923 Jan 07 01:16:21 PM PST 24 Jan 07 01:16:28 PM PST 24 404161969 ps
T798 /workspace/coverage/default/49.hmac_alert_test.3476975504 Jan 07 01:16:44 PM PST 24 Jan 07 01:16:45 PM PST 24 33119865 ps
T799 /workspace/coverage/default/41.hmac_datapath_stress.225156331 Jan 07 01:16:10 PM PST 24 Jan 07 01:16:18 PM PST 24 97884672 ps
T800 /workspace/coverage/default/17.hmac_test_sha_vectors.1657144665 Jan 07 01:14:48 PM PST 24 Jan 07 01:22:05 PM PST 24 12827557385 ps
T801 /workspace/coverage/default/35.hmac_smoke.760811942 Jan 07 01:15:53 PM PST 24 Jan 07 01:15:58 PM PST 24 1809007516 ps
T802 /workspace/coverage/default/26.hmac_stress_all.2922204532 Jan 07 01:15:11 PM PST 24 Jan 07 01:26:13 PM PST 24 153298471975 ps
T803 /workspace/coverage/default/28.hmac_smoke.806033889 Jan 07 01:15:10 PM PST 24 Jan 07 01:15:12 PM PST 24 22748906 ps
T804 /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.3531754073 Jan 07 01:17:11 PM PST 24 Jan 07 01:55:58 PM PST 24 95105331139 ps
T805 /workspace/coverage/default/9.hmac_error.563976938 Jan 07 01:14:35 PM PST 24 Jan 07 01:18:19 PM PST 24 19015432085 ps
T806 /workspace/coverage/default/44.hmac_back_pressure.1578053785 Jan 07 01:16:20 PM PST 24 Jan 07 01:16:34 PM PST 24 1469139694 ps
T807 /workspace/coverage/default/2.hmac_burst_wr.1316325050 Jan 07 01:13:42 PM PST 24 Jan 07 01:14:27 PM PST 24 917980285 ps
T808 /workspace/coverage/default/15.hmac_alert_test.4198251356 Jan 07 01:14:47 PM PST 24 Jan 07 01:14:51 PM PST 24 15879707 ps
T809 /workspace/coverage/default/39.hmac_wipe_secret.3836406783 Jan 07 01:16:07 PM PST 24 Jan 07 01:17:05 PM PST 24 12650530952 ps
T810 /workspace/coverage/default/29.hmac_long_msg.2351372249 Jan 07 01:15:37 PM PST 24 Jan 07 01:16:07 PM PST 24 924862220 ps
T811 /workspace/coverage/default/46.hmac_back_pressure.1412145578 Jan 07 01:16:23 PM PST 24 Jan 07 01:16:43 PM PST 24 8780331745 ps
T812 /workspace/coverage/default/8.hmac_test_hmac_vectors.2791757548 Jan 07 01:14:04 PM PST 24 Jan 07 01:14:06 PM PST 24 44402089 ps
T813 /workspace/coverage/default/12.hmac_alert_test.2429022316 Jan 07 01:14:45 PM PST 24 Jan 07 01:14:47 PM PST 24 32430871 ps
T814 /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.2018850420 Jan 07 01:16:22 PM PST 24 Jan 07 01:56:48 PM PST 24 203795030357 ps
T815 /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.4194595232 Jan 07 01:17:10 PM PST 24 Jan 07 01:50:55 PM PST 24 106384346388 ps
T816 /workspace/coverage/default/26.hmac_back_pressure.2961171857 Jan 07 01:15:21 PM PST 24 Jan 07 01:15:47 PM PST 24 771102617 ps
T817 /workspace/coverage/default/44.hmac_stress_all.3391438377 Jan 07 01:16:23 PM PST 24 Jan 07 01:33:30 PM PST 24 86601808261 ps
T818 /workspace/coverage/default/17.hmac_long_msg.458986174 Jan 07 01:14:49 PM PST 24 Jan 07 01:15:48 PM PST 24 25251834004 ps
T819 /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.2404779217 Jan 07 01:17:11 PM PST 24 Jan 07 01:29:57 PM PST 24 180653730252 ps
T820 /workspace/coverage/default/3.hmac_test_sha_vectors.1480751658 Jan 07 01:13:43 PM PST 24 Jan 07 01:21:19 PM PST 24 54997419879 ps
T821 /workspace/coverage/default/2.hmac_smoke.1425499507 Jan 07 01:13:41 PM PST 24 Jan 07 01:13:47 PM PST 24 316134006 ps
T822 /workspace/coverage/default/26.hmac_datapath_stress.3868813797 Jan 07 01:15:12 PM PST 24 Jan 07 01:15:52 PM PST 24 4704801413 ps
T823 /workspace/coverage/default/40.hmac_smoke.2188539635 Jan 07 01:16:07 PM PST 24 Jan 07 01:16:15 PM PST 24 380014434 ps
T824 /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.3091795328 Jan 07 01:17:12 PM PST 24 Jan 07 01:46:04 PM PST 24 181942426715 ps
T825 /workspace/coverage/default/13.hmac_datapath_stress.1528672928 Jan 07 01:14:46 PM PST 24 Jan 07 01:17:01 PM PST 24 26036398863 ps
T826 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1217313374 Jan 07 12:38:35 PM PST 24 Jan 07 12:39:59 PM PST 24 157209087 ps
T85 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2697319654 Jan 07 12:38:16 PM PST 24 Jan 07 12:39:19 PM PST 24 164653791 ps
T827 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.573424698 Jan 07 12:38:34 PM PST 24 Jan 07 12:39:37 PM PST 24 116861843 ps
T828 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1613180753 Jan 07 12:38:47 PM PST 24 Jan 07 12:40:11 PM PST 24 14483378 ps
T829 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3927799092 Jan 07 12:39:26 PM PST 24 Jan 07 12:40:46 PM PST 24 42553949 ps
T830 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3984418777 Jan 07 12:39:02 PM PST 24 Jan 07 12:40:40 PM PST 24 17796424 ps
T831 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2046702012 Jan 07 12:38:43 PM PST 24 Jan 07 12:40:15 PM PST 24 148389579 ps
T832 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1063144878 Jan 07 12:38:43 PM PST 24 Jan 07 12:39:55 PM PST 24 14478944 ps
T833 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2383131872 Jan 07 12:38:42 PM PST 24 Jan 07 12:40:39 PM PST 24 181790520 ps
T834 /workspace/coverage/cover_reg_top/11.hmac_intr_test.367270991 Jan 07 12:39:11 PM PST 24 Jan 07 12:40:39 PM PST 24 11318364 ps
T835 /workspace/coverage/cover_reg_top/30.hmac_intr_test.221624698 Jan 07 12:39:00 PM PST 24 Jan 07 12:40:37 PM PST 24 23050793 ps
T66 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1534732657 Jan 07 12:38:48 PM PST 24 Jan 07 12:40:31 PM PST 24 108249807 ps
T836 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.211549058 Jan 07 12:37:56 PM PST 24 Jan 07 12:39:11 PM PST 24 4055490254 ps
T837 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1184524409 Jan 07 12:38:23 PM PST 24 Jan 07 12:39:35 PM PST 24 342093136 ps
T838 /workspace/coverage/cover_reg_top/3.hmac_intr_test.491739494 Jan 07 12:38:32 PM PST 24 Jan 07 12:39:52 PM PST 24 26348795 ps
T839 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1403996169 Jan 07 12:38:34 PM PST 24 Jan 07 12:40:15 PM PST 24 70041135 ps
T840 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4087526342 Jan 07 12:38:27 PM PST 24 Jan 07 12:39:38 PM PST 24 27930248 ps
T841 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1159705754 Jan 07 12:38:43 PM PST 24 Jan 07 12:39:58 PM PST 24 70557979 ps
T86 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3377019538 Jan 07 12:39:03 PM PST 24 Jan 07 12:40:17 PM PST 24 27325084 ps
T842 /workspace/coverage/cover_reg_top/45.hmac_intr_test.175015783 Jan 07 12:38:37 PM PST 24 Jan 07 12:40:18 PM PST 24 31886765 ps
T843 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3939751002 Jan 07 12:38:38 PM PST 24 Jan 07 12:39:45 PM PST 24 109977749 ps
T844 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3341906543 Jan 07 12:38:39 PM PST 24 Jan 07 12:39:45 PM PST 24 143041320 ps
T845 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3972130189 Jan 07 12:38:41 PM PST 24 Jan 07 12:40:03 PM PST 24 16480980 ps
T846 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4105766896 Jan 07 12:38:54 PM PST 24 Jan 07 12:40:10 PM PST 24 21188948 ps
T847 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2325724860 Jan 07 12:39:07 PM PST 24 Jan 07 12:40:43 PM PST 24 84186782 ps
T848 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3390557027 Jan 07 12:38:53 PM PST 24 Jan 07 12:40:32 PM PST 24 148721262 ps
T849 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1158840284 Jan 07 12:38:16 PM PST 24 Jan 07 12:39:27 PM PST 24 220042232 ps
T850 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.902986993 Jan 07 12:38:42 PM PST 24 Jan 07 12:40:12 PM PST 24 33265988 ps
T851 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1950728546 Jan 07 12:38:53 PM PST 24 Jan 07 12:40:22 PM PST 24 33161399 ps
T852 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.283648161 Jan 07 12:38:21 PM PST 24 Jan 07 12:40:19 PM PST 24 34871276 ps
T853 /workspace/coverage/cover_reg_top/20.hmac_intr_test.4014968419 Jan 07 12:39:00 PM PST 24 Jan 07 12:40:37 PM PST 24 12733779 ps
T854 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2591763128 Jan 07 12:38:51 PM PST 24 Jan 07 12:40:10 PM PST 24 107657152 ps
T855 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2863368270 Jan 07 12:38:46 PM PST 24 Jan 07 12:40:07 PM PST 24 24841936 ps
T856 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.64574697 Jan 07 12:38:52 PM PST 24 Jan 07 12:40:14 PM PST 24 470405131 ps
T857 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1264555943 Jan 07 12:38:30 PM PST 24 Jan 07 12:39:49 PM PST 24 36705310 ps
T858 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2511960474 Jan 07 12:39:27 PM PST 24 Jan 07 12:40:57 PM PST 24 40528800 ps
T859 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1906921571 Jan 07 12:38:10 PM PST 24 Jan 07 12:39:25 PM PST 24 94497462 ps
T860 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4252609270 Jan 07 12:38:38 PM PST 24 Jan 07 12:40:18 PM PST 24 28865405 ps
T861 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.431520917 Jan 07 12:38:28 PM PST 24 Jan 07 12:39:44 PM PST 24 51986841 ps
T129 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2924038889 Jan 07 12:38:36 PM PST 24 Jan 07 12:39:42 PM PST 24 49853220 ps
T862 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.5899659 Jan 07 12:38:32 PM PST 24 Jan 07 12:39:54 PM PST 24 133437703 ps
T863 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1623958797 Jan 07 12:39:04 PM PST 24 Jan 07 12:40:22 PM PST 24 75395374 ps
T864 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2041414498 Jan 07 12:39:00 PM PST 24 Jan 07 12:40:19 PM PST 24 43129531 ps
T865 /workspace/coverage/cover_reg_top/34.hmac_intr_test.4173711527 Jan 07 12:39:02 PM PST 24 Jan 07 12:40:17 PM PST 24 23623133 ps
T866 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1428324369 Jan 07 12:38:39 PM PST 24 Jan 07 12:40:01 PM PST 24 99400366 ps
T867 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3971514988 Jan 07 12:38:19 PM PST 24 Jan 07 12:39:38 PM PST 24 173035922 ps
T868 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2609402689 Jan 07 12:39:03 PM PST 24 Jan 07 12:40:26 PM PST 24 13159810 ps
T869 /workspace/coverage/cover_reg_top/0.hmac_intr_test.485701553 Jan 07 12:38:25 PM PST 24 Jan 07 12:39:37 PM PST 24 20974036 ps
T870 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2730348039 Jan 07 12:38:16 PM PST 24 Jan 07 12:39:24 PM PST 24 369616622 ps
T871 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2726950928 Jan 07 12:38:57 PM PST 24 Jan 07 12:40:16 PM PST 24 25370147 ps
T872 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3874418160 Jan 07 12:38:40 PM PST 24 Jan 07 12:39:49 PM PST 24 22836199 ps
T873 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1945799418 Jan 07 12:38:52 PM PST 24 Jan 07 12:40:13 PM PST 24 241547502 ps
T874 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1832600731 Jan 07 12:38:27 PM PST 24 Jan 07 12:39:28 PM PST 24 31105730 ps
T875 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4119426329 Jan 07 12:38:17 PM PST 24 Jan 07 12:39:43 PM PST 24 21417587 ps
T876 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1718661148 Jan 07 12:38:50 PM PST 24 Jan 07 12:39:57 PM PST 24 142277360 ps
T877 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2774361944 Jan 07 12:38:39 PM PST 24 Jan 07 12:40:07 PM PST 24 48922307 ps
T878 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4246061804 Jan 07 12:38:31 PM PST 24 Jan 07 12:40:28 PM PST 24 31093816 ps
T87 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2882547110 Jan 07 12:38:34 PM PST 24 Jan 07 12:40:10 PM PST 24 448899213 ps
T879 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1627557732 Jan 07 12:39:05 PM PST 24 Jan 07 12:40:36 PM PST 24 47819420 ps
T880 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3363942196 Jan 07 12:38:38 PM PST 24 Jan 07 12:39:52 PM PST 24 59551117 ps

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1879005139
Short name T12
Test name
Test status
Simulation time 152367613 ps
CPU time 1.6 seconds
Started Jan 07 12:38:10 PM PST 24
Finished Jan 07 12:39:54 PM PST 24
Peak memory 197972 kb
Host smart-80f1af31-2210-48ee-becc-105744a9d532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879005139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1879005139
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.828231375
Short name T5
Test name
Test status
Simulation time 76594729693 ps
CPU time 574.02 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:26:47 PM PST 24
Peak memory 223384 kb
Host smart-c437d3e7-6881-4ea5-8e25-b3513cef005b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828231375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.828231375
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3319814663
Short name T36
Test name
Test status
Simulation time 156811342 ps
CPU time 0.57 seconds
Started Jan 07 12:38:30 PM PST 24
Finished Jan 07 12:39:53 PM PST 24
Peak memory 183580 kb
Host smart-5a78561d-a5c1-46c3-8ecf-32ece74c1740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319814663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3319814663
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1534612684
Short name T67
Test name
Test status
Simulation time 754691720 ps
CPU time 2.32 seconds
Started Jan 07 12:39:01 PM PST 24
Finished Jan 07 12:40:48 PM PST 24
Peak memory 198064 kb
Host smart-312c96c0-63b2-4ef4-ba4f-3f739f84b1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534612684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1534612684
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1204890795
Short name T42
Test name
Test status
Simulation time 192260548304 ps
CPU time 3245.11 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 02:07:48 PM PST 24
Peak memory 264440 kb
Host smart-4c0500a4-416d-45cb-ac48-dc48c22061c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204890795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1204890795
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1180194472
Short name T21
Test name
Test status
Simulation time 670218631 ps
CPU time 1.77 seconds
Started Jan 07 12:39:32 PM PST 24
Finished Jan 07 12:41:10 PM PST 24
Peak memory 198416 kb
Host smart-3fcaac03-46a7-4385-ae55-3af23311455a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180194472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1180194472
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.74585025
Short name T17
Test name
Test status
Simulation time 53104405 ps
CPU time 2.26 seconds
Started Jan 07 12:38:33 PM PST 24
Finished Jan 07 12:39:53 PM PST 24
Peak memory 183700 kb
Host smart-1046c62c-27f4-4151-8543-9eb7ca5501fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74585025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.74585025
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.1117733699
Short name T6
Test name
Test status
Simulation time 59317610703 ps
CPU time 675.34 seconds
Started Jan 07 01:17:13 PM PST 24
Finished Jan 07 01:28:30 PM PST 24
Peak memory 247056 kb
Host smart-1171f871-e4b7-4872-b56d-aab82a7946f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117733699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.1117733699
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4220293402
Short name T54
Test name
Test status
Simulation time 64117730 ps
CPU time 0.76 seconds
Started Jan 07 01:13:40 PM PST 24
Finished Jan 07 01:13:43 PM PST 24
Peak memory 215816 kb
Host smart-36a78687-f1c3-49d9-9524-c41d32fc32c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220293402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4220293402
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.3148379371
Short name T84
Test name
Test status
Simulation time 59056209905 ps
CPU time 2287.12 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:52:59 PM PST 24
Peak memory 255500 kb
Host smart-21e1c0c7-655b-4141-aa0c-c5be442bdc68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148379371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.3148379371
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.17457732
Short name T23
Test name
Test status
Simulation time 59461614 ps
CPU time 0.58 seconds
Started Jan 07 12:39:23 PM PST 24
Finished Jan 07 12:40:43 PM PST 24
Peak memory 183592 kb
Host smart-7f912a83-b965-40d3-a02c-c9a0908cf6a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17457732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.17457732
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.4184002763
Short name T50
Test name
Test status
Simulation time 26263198883 ps
CPU time 1319.63 seconds
Started Jan 07 01:17:00 PM PST 24
Finished Jan 07 01:39:02 PM PST 24
Peak memory 215324 kb
Host smart-dbc505b9-7c05-4e9c-9f66-9e99807b0a1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4184002763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.4184002763
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1534732657
Short name T66
Test name
Test status
Simulation time 108249807 ps
CPU time 2.26 seconds
Started Jan 07 12:38:48 PM PST 24
Finished Jan 07 12:40:31 PM PST 24
Peak memory 198212 kb
Host smart-dbb613b2-9831-45fb-a55e-b0bb49962610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534732657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1534732657
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.4083433418
Short name T111
Test name
Test status
Simulation time 310074108740 ps
CPU time 3268 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 02:11:42 PM PST 24
Peak memory 259356 kb
Host smart-02038413-a8df-4d86-9028-0a2894f322b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083433418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.4083433418
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.558478155
Short name T113
Test name
Test status
Simulation time 205011004934 ps
CPU time 739 seconds
Started Jan 07 01:15:33 PM PST 24
Finished Jan 07 01:27:53 PM PST 24
Peak memory 231604 kb
Host smart-72f570c0-5dfe-419b-974c-2a76dc693cd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558478155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.558478155
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.3161561148
Short name T781
Test name
Test status
Simulation time 199769312781 ps
CPU time 4573.96 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 02:32:39 PM PST 24
Peak memory 262112 kb
Host smart-84a46aa3-9839-45d5-ab77-d4721600242e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161561148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.3161561148
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.464912748
Short name T76
Test name
Test status
Simulation time 66304227 ps
CPU time 1.34 seconds
Started Jan 07 12:38:12 PM PST 24
Finished Jan 07 12:39:24 PM PST 24
Peak memory 197008 kb
Host smart-49fc9e21-cc4a-4331-9115-bc0ee9a7d6e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464912748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.464912748
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.hmac_alert_test.308673760
Short name T52
Test name
Test status
Simulation time 12205562 ps
CPU time 0.57 seconds
Started Jan 07 01:14:33 PM PST 24
Finished Jan 07 01:14:35 PM PST 24
Peak memory 193068 kb
Host smart-6ae5680a-ba7d-4a70-89e4-18fc6643af06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308673760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.308673760
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3971514988
Short name T867
Test name
Test status
Simulation time 173035922 ps
CPU time 2.44 seconds
Started Jan 07 12:38:19 PM PST 24
Finished Jan 07 12:39:38 PM PST 24
Peak memory 198108 kb
Host smart-7c5b1c11-f3cb-4d06-8c8b-ae6928ce6fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971514988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3971514988
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3315565630
Short name T175
Test name
Test status
Simulation time 11139449765 ps
CPU time 30.89 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:14:14 PM PST 24
Peak memory 198832 kb
Host smart-3bd09bab-2f3e-4b26-a40f-2491fa0903b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315565630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3315565630
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.2457539407
Short name T90
Test name
Test status
Simulation time 460881216656 ps
CPU time 3127.92 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 02:09:21 PM PST 24
Peak memory 248024 kb
Host smart-4dc842f2-760c-427d-b5bf-2915c73bd93a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457539407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.2457539407
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.2155249463
Short name T128
Test name
Test status
Simulation time 42475257128 ps
CPU time 793.52 seconds
Started Jan 07 01:16:38 PM PST 24
Finished Jan 07 01:29:53 PM PST 24
Peak memory 231328 kb
Host smart-d04801b9-1c09-4118-9e79-6fe52df87c7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155249463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.2155249463
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2354848096
Short name T144
Test name
Test status
Simulation time 237294477 ps
CPU time 3.43 seconds
Started Jan 07 12:38:50 PM PST 24
Finished Jan 07 12:39:59 PM PST 24
Peak memory 192080 kb
Host smart-4c9b5cda-332b-4e65-a033-18a7c18db545
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354848096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2354848096
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.378467437
Short name T77
Test name
Test status
Simulation time 261360220 ps
CPU time 0.67 seconds
Started Jan 07 12:38:17 PM PST 24
Finished Jan 07 12:39:20 PM PST 24
Peak memory 194300 kb
Host smart-0be57979-08c9-4f36-85cf-ca0e6e577ead
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378467437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.378467437
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4087526342
Short name T840
Test name
Test status
Simulation time 27930248 ps
CPU time 0.64 seconds
Started Jan 07 12:38:27 PM PST 24
Finished Jan 07 12:39:38 PM PST 24
Peak memory 194076 kb
Host smart-11cd5c5a-04f8-410c-96b6-a079ce0dc8a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087526342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4087526342
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.485701553
Short name T869
Test name
Test status
Simulation time 20974036 ps
CPU time 0.57 seconds
Started Jan 07 12:38:25 PM PST 24
Finished Jan 07 12:39:37 PM PST 24
Peak memory 183584 kb
Host smart-9a808435-1db3-4cab-88ee-517b0775eeac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485701553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.485701553
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.902986993
Short name T850
Test name
Test status
Simulation time 33265988 ps
CPU time 1.73 seconds
Started Jan 07 12:38:42 PM PST 24
Finished Jan 07 12:40:12 PM PST 24
Peak memory 198496 kb
Host smart-1bcbe5b6-3769-48b6-a50e-66a133a8a221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902986993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.902986993
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2494450283
Short name T75
Test name
Test status
Simulation time 236767252 ps
CPU time 1.72 seconds
Started Jan 07 12:38:27 PM PST 24
Finished Jan 07 12:39:35 PM PST 24
Peak memory 192016 kb
Host smart-9c53d1e1-2e18-45c2-a2fa-2a994f51ebe2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494450283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2494450283
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.211549058
Short name T836
Test name
Test status
Simulation time 4055490254 ps
CPU time 9.16 seconds
Started Jan 07 12:37:56 PM PST 24
Finished Jan 07 12:39:11 PM PST 24
Peak memory 192076 kb
Host smart-eda757e3-852d-4633-94c9-522931a884e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211549058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.211549058
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.952078524
Short name T35
Test name
Test status
Simulation time 93459635 ps
CPU time 0.69 seconds
Started Jan 07 12:38:30 PM PST 24
Finished Jan 07 12:39:44 PM PST 24
Peak memory 194120 kb
Host smart-efd72184-9a86-4dbb-94f1-0308bd0a4198
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952078524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.952078524
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2497736849
Short name T27
Test name
Test status
Simulation time 83850786 ps
CPU time 1.18 seconds
Started Jan 07 12:37:58 PM PST 24
Finished Jan 07 12:39:00 PM PST 24
Peak memory 198420 kb
Host smart-18d58948-051d-47f9-b0ae-0fe3c3a589b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497736849 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2497736849
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1906921571
Short name T859
Test name
Test status
Simulation time 94497462 ps
CPU time 0.66 seconds
Started Jan 07 12:38:10 PM PST 24
Finished Jan 07 12:39:25 PM PST 24
Peak memory 194520 kb
Host smart-12d7774b-462f-4efb-b4eb-0012e4783e09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906921571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1906921571
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4238155707
Short name T16
Test name
Test status
Simulation time 20099018 ps
CPU time 0.59 seconds
Started Jan 07 12:38:55 PM PST 24
Finished Jan 07 12:40:43 PM PST 24
Peak memory 183580 kb
Host smart-d8c73a8e-ba64-47ce-b4a4-21ea7d798549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238155707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4238155707
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1264555943
Short name T857
Test name
Test status
Simulation time 36705310 ps
CPU time 0.78 seconds
Started Jan 07 12:38:30 PM PST 24
Finished Jan 07 12:39:49 PM PST 24
Peak memory 195040 kb
Host smart-c787dc9c-ed30-4971-b681-1fd3ab7f4af4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264555943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1264555943
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.573424698
Short name T827
Test name
Test status
Simulation time 116861843 ps
CPU time 2.61 seconds
Started Jan 07 12:38:34 PM PST 24
Finished Jan 07 12:39:37 PM PST 24
Peak memory 198472 kb
Host smart-51ee7db7-9d54-4b4e-bdab-a8364d3e86fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573424698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.573424698
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.902321751
Short name T130
Test name
Test status
Simulation time 108557774 ps
CPU time 2.22 seconds
Started Jan 07 12:38:19 PM PST 24
Finished Jan 07 12:39:21 PM PST 24
Peak memory 198400 kb
Host smart-8b53a878-00ff-49b8-a55a-785f93760618
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902321751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.902321751
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4086531894
Short name T31
Test name
Test status
Simulation time 425704171 ps
CPU time 1.31 seconds
Started Jan 07 12:39:06 PM PST 24
Finished Jan 07 12:40:26 PM PST 24
Peak memory 198420 kb
Host smart-765289db-f785-4cde-a5e6-5863f06084b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086531894 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4086531894
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2726950928
Short name T871
Test name
Test status
Simulation time 25370147 ps
CPU time 0.59 seconds
Started Jan 07 12:38:57 PM PST 24
Finished Jan 07 12:40:16 PM PST 24
Peak memory 193652 kb
Host smart-e5d54506-7277-4242-8b23-49e8b55d7c77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726950928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2726950928
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2453491074
Short name T141
Test name
Test status
Simulation time 38956220 ps
CPU time 0.55 seconds
Started Jan 07 12:38:28 PM PST 24
Finished Jan 07 12:39:39 PM PST 24
Peak memory 183492 kb
Host smart-89aa0684-b062-4e9c-a77c-0c08af33afff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453491074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2453491074
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1284840355
Short name T25
Test name
Test status
Simulation time 93340621 ps
CPU time 2.1 seconds
Started Jan 07 12:39:33 PM PST 24
Finished Jan 07 12:40:52 PM PST 24
Peak memory 198484 kb
Host smart-f6092aba-4fe5-472d-93a7-4620a29f74db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284840355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1284840355
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2924038889
Short name T129
Test name
Test status
Simulation time 49853220 ps
CPU time 1.08 seconds
Started Jan 07 12:38:36 PM PST 24
Finished Jan 07 12:39:42 PM PST 24
Peak memory 197768 kb
Host smart-7d5ece91-31c4-49a1-842e-816c1f33934f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924038889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2924038889
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.30238620
Short name T78
Test name
Test status
Simulation time 13967505 ps
CPU time 0.58 seconds
Started Jan 07 12:39:08 PM PST 24
Finished Jan 07 12:40:48 PM PST 24
Peak memory 193556 kb
Host smart-8e29349d-4ad8-4f10-8159-68448dc19223
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30238620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.30238620
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.367270991
Short name T834
Test name
Test status
Simulation time 11318364 ps
CPU time 0.55 seconds
Started Jan 07 12:39:11 PM PST 24
Finished Jan 07 12:40:39 PM PST 24
Peak memory 183564 kb
Host smart-f63e250f-a397-4f68-a2c1-28f46ccb6c39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367270991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.367270991
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3427054879
Short name T71
Test name
Test status
Simulation time 164151831 ps
CPU time 1.33 seconds
Started Jan 07 12:39:13 PM PST 24
Finished Jan 07 12:40:49 PM PST 24
Peak memory 196116 kb
Host smart-9e4682c1-c556-4d1d-b073-2713cd18fffc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427054879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3427054879
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1403996169
Short name T839
Test name
Test status
Simulation time 70041135 ps
CPU time 1.3 seconds
Started Jan 07 12:38:34 PM PST 24
Finished Jan 07 12:40:15 PM PST 24
Peak memory 198540 kb
Host smart-70d6dd17-4baf-4a7a-b89f-8ce74ea82482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403996169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1403996169
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3725638062
Short name T134
Test name
Test status
Simulation time 647677603 ps
CPU time 2.33 seconds
Started Jan 07 12:39:10 PM PST 24
Finished Jan 07 12:40:42 PM PST 24
Peak memory 198296 kb
Host smart-ca78e475-f131-4fed-9095-0d8c8c05a248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725638062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3725638062
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1718661148
Short name T876
Test name
Test status
Simulation time 142277360 ps
CPU time 1.27 seconds
Started Jan 07 12:38:50 PM PST 24
Finished Jan 07 12:39:57 PM PST 24
Peak memory 198440 kb
Host smart-8d3f0ddd-a2ba-4635-a90c-d27254362d89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718661148 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1718661148
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2041414498
Short name T864
Test name
Test status
Simulation time 43129531 ps
CPU time 0.58 seconds
Started Jan 07 12:39:00 PM PST 24
Finished Jan 07 12:40:19 PM PST 24
Peak memory 193668 kb
Host smart-38325a5c-43d7-48c9-bdd3-25355f021312
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041414498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2041414498
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2534167617
Short name T72
Test name
Test status
Simulation time 42973328 ps
CPU time 0.56 seconds
Started Jan 07 12:39:09 PM PST 24
Finished Jan 07 12:40:37 PM PST 24
Peak memory 183484 kb
Host smart-eb65bfd4-2790-406a-a3b7-fea33c7c7754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534167617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2534167617
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.421344555
Short name T24
Test name
Test status
Simulation time 213320514 ps
CPU time 2.7 seconds
Started Jan 07 12:38:32 PM PST 24
Finished Jan 07 12:39:50 PM PST 24
Peak memory 198656 kb
Host smart-9b256260-d6a3-496b-aadf-365b8d645a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421344555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.421344555
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.606225197
Short name T19
Test name
Test status
Simulation time 83262724 ps
CPU time 1.73 seconds
Started Jan 07 12:38:28 PM PST 24
Finished Jan 07 12:39:40 PM PST 24
Peak memory 198012 kb
Host smart-4c088722-b938-4d3e-b405-cf5151c1c28b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606225197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.606225197
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4105766896
Short name T846
Test name
Test status
Simulation time 21188948 ps
CPU time 1.04 seconds
Started Jan 07 12:38:54 PM PST 24
Finished Jan 07 12:40:10 PM PST 24
Peak memory 198252 kb
Host smart-1b3a326e-4443-44e3-88bc-5385d58fb2e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105766896 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.4105766896
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3377019538
Short name T86
Test name
Test status
Simulation time 27325084 ps
CPU time 0.74 seconds
Started Jan 07 12:39:03 PM PST 24
Finished Jan 07 12:40:17 PM PST 24
Peak memory 194276 kb
Host smart-5d001d16-1852-41f8-a353-9b3ea7ce6f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377019538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3377019538
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3984418777
Short name T830
Test name
Test status
Simulation time 17796424 ps
CPU time 0.81 seconds
Started Jan 07 12:39:02 PM PST 24
Finished Jan 07 12:40:40 PM PST 24
Peak memory 191852 kb
Host smart-7f85e622-81ba-4863-b6d3-fb4e856ce554
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984418777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3984418777
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.64574697
Short name T856
Test name
Test status
Simulation time 470405131 ps
CPU time 2.54 seconds
Started Jan 07 12:38:52 PM PST 24
Finished Jan 07 12:40:14 PM PST 24
Peak memory 198496 kb
Host smart-5be36801-b76c-455b-8bf1-655c4d4f7d71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64574697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.64574697
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3341906543
Short name T844
Test name
Test status
Simulation time 143041320 ps
CPU time 1.58 seconds
Started Jan 07 12:38:39 PM PST 24
Finished Jan 07 12:39:45 PM PST 24
Peak memory 198512 kb
Host smart-76e4f2e9-e521-48b6-a824-3f105e3891bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341906543 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3341906543
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3293394675
Short name T37
Test name
Test status
Simulation time 18799697 ps
CPU time 0.59 seconds
Started Jan 07 12:39:10 PM PST 24
Finished Jan 07 12:40:46 PM PST 24
Peak memory 193896 kb
Host smart-a0aa0805-03d8-4bf0-92f6-64a74e02b987
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293394675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3293394675
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1891360627
Short name T151
Test name
Test status
Simulation time 112775073 ps
CPU time 1.03 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:39:48 PM PST 24
Peak memory 191996 kb
Host smart-4128baf3-ec44-4fae-b48b-f584971d10d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891360627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1891360627
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1945799418
Short name T873
Test name
Test status
Simulation time 241547502 ps
CPU time 2.59 seconds
Started Jan 07 12:38:52 PM PST 24
Finished Jan 07 12:40:13 PM PST 24
Peak memory 198408 kb
Host smart-557e9792-c96c-4943-af2b-299819fecd8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945799418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1945799418
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1063144878
Short name T832
Test name
Test status
Simulation time 14478944 ps
CPU time 0.91 seconds
Started Jan 07 12:38:43 PM PST 24
Finished Jan 07 12:39:55 PM PST 24
Peak memory 198220 kb
Host smart-8c7693be-30d4-444e-9382-1d1eb2b55f6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063144878 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1063144878
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3478865543
Short name T152
Test name
Test status
Simulation time 142808224 ps
CPU time 1.08 seconds
Started Jan 07 12:38:18 PM PST 24
Finished Jan 07 12:40:14 PM PST 24
Peak memory 191944 kb
Host smart-35a5f83d-a139-4442-a3d3-93b33cbd98ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478865543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3478865543
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3390557027
Short name T848
Test name
Test status
Simulation time 148721262 ps
CPU time 2.8 seconds
Started Jan 07 12:38:53 PM PST 24
Finished Jan 07 12:40:32 PM PST 24
Peak memory 198512 kb
Host smart-39c5be0b-b4f8-4bf2-950d-26cd87a57981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390557027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3390557027
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1546918493
Short name T132
Test name
Test status
Simulation time 313898610 ps
CPU time 1.72 seconds
Started Jan 07 12:38:47 PM PST 24
Finished Jan 07 12:40:23 PM PST 24
Peak memory 197960 kb
Host smart-8f8e4c70-3b98-495f-8678-44dd62cc5563
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546918493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1546918493
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3972130189
Short name T845
Test name
Test status
Simulation time 16480980 ps
CPU time 0.6 seconds
Started Jan 07 12:38:41 PM PST 24
Finished Jan 07 12:40:03 PM PST 24
Peak memory 194148 kb
Host smart-09b31b07-728b-4822-ae42-dad9bac348ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972130189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3972130189
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2609402689
Short name T868
Test name
Test status
Simulation time 13159810 ps
CPU time 0.61 seconds
Started Jan 07 12:39:03 PM PST 24
Finished Jan 07 12:40:26 PM PST 24
Peak memory 183576 kb
Host smart-0cd4893a-e88f-4ff1-9b14-dad275423ec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609402689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2609402689
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2533976721
Short name T30
Test name
Test status
Simulation time 697079431 ps
CPU time 2.85 seconds
Started Jan 07 12:38:19 PM PST 24
Finished Jan 07 12:39:49 PM PST 24
Peak memory 198428 kb
Host smart-ffee2009-21ed-44eb-a903-ae47dba5f2e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533976721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2533976721
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1950728546
Short name T851
Test name
Test status
Simulation time 33161399 ps
CPU time 0.67 seconds
Started Jan 07 12:38:53 PM PST 24
Finished Jan 07 12:40:22 PM PST 24
Peak memory 194504 kb
Host smart-cb7ad01e-01ee-475d-9dab-005aaf713bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950728546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1950728546
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2474981464
Short name T147
Test name
Test status
Simulation time 22273459 ps
CPU time 0.54 seconds
Started Jan 07 12:38:47 PM PST 24
Finished Jan 07 12:40:22 PM PST 24
Peak memory 183556 kb
Host smart-b723b8ef-d6c8-49d4-b9cd-41c4358a18fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474981464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2474981464
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2325724860
Short name T847
Test name
Test status
Simulation time 84186782 ps
CPU time 1.02 seconds
Started Jan 07 12:39:07 PM PST 24
Finished Jan 07 12:40:43 PM PST 24
Peak memory 192088 kb
Host smart-d710d097-08a2-4b99-921b-14f0843bbbc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325724860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2325724860
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1700355640
Short name T65
Test name
Test status
Simulation time 105070819 ps
CPU time 2.64 seconds
Started Jan 07 12:38:56 PM PST 24
Finished Jan 07 12:40:27 PM PST 24
Peak memory 198492 kb
Host smart-d0a0fb47-d517-4306-a748-947cfe528f04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700355640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1700355640
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4134804785
Short name T73
Test name
Test status
Simulation time 477541039 ps
CPU time 2.23 seconds
Started Jan 07 12:38:42 PM PST 24
Finished Jan 07 12:40:23 PM PST 24
Peak memory 198180 kb
Host smart-29492d50-40ab-4922-be2b-662e8566c915
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134804785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.4134804785
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3874418160
Short name T872
Test name
Test status
Simulation time 22836199 ps
CPU time 1 seconds
Started Jan 07 12:38:40 PM PST 24
Finished Jan 07 12:39:49 PM PST 24
Peak memory 198208 kb
Host smart-0077c7be-bb92-4728-83bd-c5807db41687
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874418160 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3874418160
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.431520917
Short name T861
Test name
Test status
Simulation time 51986841 ps
CPU time 0.58 seconds
Started Jan 07 12:38:28 PM PST 24
Finished Jan 07 12:39:44 PM PST 24
Peak memory 193728 kb
Host smart-f41f16e5-30b8-4866-81b6-e541c6f2d99f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431520917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.431520917
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2014637713
Short name T146
Test name
Test status
Simulation time 17831100 ps
CPU time 0.56 seconds
Started Jan 07 12:38:59 PM PST 24
Finished Jan 07 12:40:37 PM PST 24
Peak memory 183580 kb
Host smart-d265fe1f-f44e-490d-8b12-843c649a03ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014637713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2014637713
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.773504508
Short name T92
Test name
Test status
Simulation time 60298725 ps
CPU time 1.27 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:40:05 PM PST 24
Peak memory 192004 kb
Host smart-c68e7012-e40b-4442-9397-871c543f9570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773504508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.773504508
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2312793685
Short name T26
Test name
Test status
Simulation time 240183079 ps
CPU time 3.2 seconds
Started Jan 07 12:39:03 PM PST 24
Finished Jan 07 12:40:32 PM PST 24
Peak memory 198428 kb
Host smart-67e6541d-7b76-44e4-a146-8c5664089682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312793685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2312793685
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.54442432
Short name T68
Test name
Test status
Simulation time 156091809 ps
CPU time 2.31 seconds
Started Jan 07 12:38:44 PM PST 24
Finished Jan 07 12:40:11 PM PST 24
Peak memory 198424 kb
Host smart-f5d944f5-9d4f-445e-a13b-f2eeaa8b31b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54442432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.54442432
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4252609270
Short name T860
Test name
Test status
Simulation time 28865405 ps
CPU time 0.89 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:40:18 PM PST 24
Peak memory 198160 kb
Host smart-f0269127-243c-43f2-bd70-c1ea52959f3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252609270 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4252609270
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.515820118
Short name T82
Test name
Test status
Simulation time 20864718 ps
CPU time 0.65 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:39:48 PM PST 24
Peak memory 194008 kb
Host smart-a40ee276-b986-4545-a9ef-0684e3bc1f6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515820118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.515820118
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2445173016
Short name T135
Test name
Test status
Simulation time 42762262 ps
CPU time 0.55 seconds
Started Jan 07 12:38:31 PM PST 24
Finished Jan 07 12:39:33 PM PST 24
Peak memory 183436 kb
Host smart-793db3c9-52de-42ba-bc10-0ad6719b576f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445173016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2445173016
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1623958797
Short name T863
Test name
Test status
Simulation time 75395374 ps
CPU time 1.23 seconds
Started Jan 07 12:39:04 PM PST 24
Finished Jan 07 12:40:22 PM PST 24
Peak memory 192024 kb
Host smart-9f5caa55-317b-4ae5-a2d9-91257d74b0f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623958797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1623958797
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.134785885
Short name T81
Test name
Test status
Simulation time 461488782 ps
CPU time 2.67 seconds
Started Jan 07 12:38:42 PM PST 24
Finished Jan 07 12:40:29 PM PST 24
Peak memory 183924 kb
Host smart-5b80cd75-3a21-449f-879a-fbf88d2d84e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134785885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.134785885
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3073084654
Short name T70
Test name
Test status
Simulation time 1705319138 ps
CPU time 6.25 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:39:49 PM PST 24
Peak memory 192128 kb
Host smart-b7a0f310-352b-4239-924e-8d57a3464142
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073084654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3073084654
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3817474671
Short name T69
Test name
Test status
Simulation time 39078044 ps
CPU time 0.66 seconds
Started Jan 07 12:39:09 PM PST 24
Finished Jan 07 12:40:53 PM PST 24
Peak memory 193960 kb
Host smart-f8777877-7956-4bdc-87af-9a5859624513
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817474671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3817474671
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1141472766
Short name T156
Test name
Test status
Simulation time 112959608 ps
CPU time 0.9 seconds
Started Jan 07 12:38:32 PM PST 24
Finished Jan 07 12:40:21 PM PST 24
Peak memory 198248 kb
Host smart-7e1170fb-1834-4d0b-b663-e548a550ed13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141472766 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1141472766
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3208562838
Short name T153
Test name
Test status
Simulation time 19825390 ps
CPU time 0.66 seconds
Started Jan 07 12:38:54 PM PST 24
Finished Jan 07 12:40:23 PM PST 24
Peak memory 194280 kb
Host smart-4564ec85-3647-4c0c-8c26-a35dd42d2a58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208562838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3208562838
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2320206099
Short name T93
Test name
Test status
Simulation time 47156710 ps
CPU time 0.72 seconds
Started Jan 07 12:38:39 PM PST 24
Finished Jan 07 12:39:47 PM PST 24
Peak memory 195068 kb
Host smart-afb2eefa-da19-428b-84d0-4b7be8d97875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320206099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2320206099
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1158840284
Short name T849
Test name
Test status
Simulation time 220042232 ps
CPU time 2.38 seconds
Started Jan 07 12:38:16 PM PST 24
Finished Jan 07 12:39:27 PM PST 24
Peak memory 198404 kb
Host smart-28eabdd0-a6ab-402d-84ed-08b080060498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158840284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1158840284
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2113011069
Short name T131
Test name
Test status
Simulation time 204245216 ps
CPU time 1.87 seconds
Started Jan 07 12:38:44 PM PST 24
Finished Jan 07 12:40:10 PM PST 24
Peak memory 198164 kb
Host smart-be0f38f2-07b3-42c8-9163-4503276c5c37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113011069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2113011069
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.4014968419
Short name T853
Test name
Test status
Simulation time 12733779 ps
CPU time 0.56 seconds
Started Jan 07 12:39:00 PM PST 24
Finished Jan 07 12:40:37 PM PST 24
Peak memory 183660 kb
Host smart-38696f67-2e0b-44cb-b853-1b875a82dce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014968419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.4014968419
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.4216010819
Short name T137
Test name
Test status
Simulation time 14559703 ps
CPU time 0.55 seconds
Started Jan 07 12:38:58 PM PST 24
Finished Jan 07 12:40:19 PM PST 24
Peak memory 183544 kb
Host smart-7a6df1b4-dca5-4e40-9775-1a32f46a2836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216010819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.4216010819
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1627557732
Short name T879
Test name
Test status
Simulation time 47819420 ps
CPU time 0.53 seconds
Started Jan 07 12:39:05 PM PST 24
Finished Jan 07 12:40:36 PM PST 24
Peak memory 183592 kb
Host smart-295c3e21-bbdc-41b8-ac10-b925163ca4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627557732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1627557732
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1613180753
Short name T828
Test name
Test status
Simulation time 14483378 ps
CPU time 0.57 seconds
Started Jan 07 12:38:47 PM PST 24
Finished Jan 07 12:40:11 PM PST 24
Peak memory 183436 kb
Host smart-7e6149af-4434-4c52-8550-a8be544c6b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613180753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1613180753
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3539757386
Short name T32
Test name
Test status
Simulation time 27546008 ps
CPU time 0.59 seconds
Started Jan 07 12:39:02 PM PST 24
Finished Jan 07 12:40:25 PM PST 24
Peak memory 183588 kb
Host smart-100a6a74-204b-4880-8172-ba6b0c153d87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539757386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3539757386
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2863368270
Short name T855
Test name
Test status
Simulation time 24841936 ps
CPU time 0.55 seconds
Started Jan 07 12:38:46 PM PST 24
Finished Jan 07 12:40:07 PM PST 24
Peak memory 183580 kb
Host smart-8bb5d27c-f73c-477e-975e-a370c761abc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863368270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2863368270
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.4086304022
Short name T18
Test name
Test status
Simulation time 14614001 ps
CPU time 0.53 seconds
Started Jan 07 12:38:48 PM PST 24
Finished Jan 07 12:40:30 PM PST 24
Peak memory 183588 kb
Host smart-3725c417-84b6-470c-890e-c8fe58e5227c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086304022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.4086304022
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3927799092
Short name T829
Test name
Test status
Simulation time 42553949 ps
CPU time 0.55 seconds
Started Jan 07 12:39:26 PM PST 24
Finished Jan 07 12:40:46 PM PST 24
Peak memory 183564 kb
Host smart-0dc63fa0-d832-4910-bc02-8da610975147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927799092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3927799092
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2832714590
Short name T20
Test name
Test status
Simulation time 30437212 ps
CPU time 0.55 seconds
Started Jan 07 12:38:50 PM PST 24
Finished Jan 07 12:39:56 PM PST 24
Peak memory 183556 kb
Host smart-62557097-385d-41fb-9915-4047effa9c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832714590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2832714590
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1871669459
Short name T158
Test name
Test status
Simulation time 22428566 ps
CPU time 0.55 seconds
Started Jan 07 12:38:43 PM PST 24
Finished Jan 07 12:39:46 PM PST 24
Peak memory 183492 kb
Host smart-3a4a9fc8-620e-4f3e-ae57-a3a38e7dcec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871669459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1871669459
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2697319654
Short name T85
Test name
Test status
Simulation time 164653791 ps
CPU time 2.49 seconds
Started Jan 07 12:38:16 PM PST 24
Finished Jan 07 12:39:19 PM PST 24
Peak memory 192024 kb
Host smart-d6653f67-1bb3-4cb6-afad-f6dcf24c2fb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697319654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2697319654
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.977011290
Short name T95
Test name
Test status
Simulation time 41806907 ps
CPU time 0.61 seconds
Started Jan 07 12:38:06 PM PST 24
Finished Jan 07 12:39:17 PM PST 24
Peak memory 193728 kb
Host smart-13833f0d-5d6c-46cd-ba69-a190a95eb823
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977011290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.977011290
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1328197119
Short name T28
Test name
Test status
Simulation time 36114621 ps
CPU time 2.78 seconds
Started Jan 07 12:38:13 PM PST 24
Finished Jan 07 12:39:34 PM PST 24
Peak memory 198520 kb
Host smart-1dac4d18-e78c-4fe4-8078-d41978909b51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328197119 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1328197119
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.4183663938
Short name T157
Test name
Test status
Simulation time 68774819 ps
CPU time 0.65 seconds
Started Jan 07 12:38:00 PM PST 24
Finished Jan 07 12:39:15 PM PST 24
Peak memory 193692 kb
Host smart-df88929d-7727-4024-a7a2-d1f83e167926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183663938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.4183663938
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.491739494
Short name T838
Test name
Test status
Simulation time 26348795 ps
CPU time 0.57 seconds
Started Jan 07 12:38:32 PM PST 24
Finished Jan 07 12:39:52 PM PST 24
Peak memory 183572 kb
Host smart-fe0dd98a-4802-4f2b-9820-84f9f8583c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491739494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.491739494
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1832600731
Short name T874
Test name
Test status
Simulation time 31105730 ps
CPU time 1.21 seconds
Started Jan 07 12:38:27 PM PST 24
Finished Jan 07 12:39:28 PM PST 24
Peak memory 191920 kb
Host smart-d33a2b91-188e-474d-9e6e-b22f3f918093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832600731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1832600731
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.5899659
Short name T862
Test name
Test status
Simulation time 133437703 ps
CPU time 2.58 seconds
Started Jan 07 12:38:32 PM PST 24
Finished Jan 07 12:39:54 PM PST 24
Peak memory 198472 kb
Host smart-91f51840-bf3a-4e9d-acb4-27eb4d6fd8f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5899659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.5899659
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2245348492
Short name T133
Test name
Test status
Simulation time 1668986984 ps
CPU time 1.75 seconds
Started Jan 07 12:38:23 PM PST 24
Finished Jan 07 12:39:29 PM PST 24
Peak memory 198108 kb
Host smart-22a9177a-e924-48e6-ac2a-cb8e8fcfe268
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245348492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2245348492
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.221624698
Short name T835
Test name
Test status
Simulation time 23050793 ps
CPU time 0.56 seconds
Started Jan 07 12:39:00 PM PST 24
Finished Jan 07 12:40:37 PM PST 24
Peak memory 183592 kb
Host smart-d98df6f9-88c5-4d32-890e-a942289b72b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221624698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.221624698
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.470059481
Short name T33
Test name
Test status
Simulation time 46316519 ps
CPU time 0.56 seconds
Started Jan 07 12:38:41 PM PST 24
Finished Jan 07 12:40:14 PM PST 24
Peak memory 183592 kb
Host smart-9f9d4421-76c4-4929-b31d-2df24ed2cdb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470059481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.470059481
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.46739582
Short name T138
Test name
Test status
Simulation time 24485155 ps
CPU time 0.57 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:40:13 PM PST 24
Peak memory 183580 kb
Host smart-6bbbed2e-8c80-413c-bfd5-e3bcd6b60bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46739582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.46739582
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3676624418
Short name T13
Test name
Test status
Simulation time 17640396 ps
CPU time 0.57 seconds
Started Jan 07 12:39:00 PM PST 24
Finished Jan 07 12:40:37 PM PST 24
Peak memory 183580 kb
Host smart-bca6b698-015d-4f3c-b721-abc6bc307323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676624418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3676624418
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.4173711527
Short name T865
Test name
Test status
Simulation time 23623133 ps
CPU time 0.59 seconds
Started Jan 07 12:39:02 PM PST 24
Finished Jan 07 12:40:17 PM PST 24
Peak memory 183588 kb
Host smart-aed07ca1-f5cb-4da8-8e48-ae5e6704ebfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173711527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.4173711527
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3156048331
Short name T154
Test name
Test status
Simulation time 18057057 ps
CPU time 0.53 seconds
Started Jan 07 12:38:49 PM PST 24
Finished Jan 07 12:40:27 PM PST 24
Peak memory 183540 kb
Host smart-56965bef-23b0-4336-b69a-cd0525b0db35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156048331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3156048331
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3363942196
Short name T880
Test name
Test status
Simulation time 59551117 ps
CPU time 0.54 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:39:52 PM PST 24
Peak memory 183732 kb
Host smart-e10fe3a6-6d00-4058-aa3f-8b60fd65d02d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363942196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3363942196
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2511960474
Short name T858
Test name
Test status
Simulation time 40528800 ps
CPU time 0.55 seconds
Started Jan 07 12:39:27 PM PST 24
Finished Jan 07 12:40:57 PM PST 24
Peak memory 183568 kb
Host smart-0952dd75-6a93-44f2-891c-a58fb115e0b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511960474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2511960474
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2882547110
Short name T87
Test name
Test status
Simulation time 448899213 ps
CPU time 1.17 seconds
Started Jan 07 12:38:34 PM PST 24
Finished Jan 07 12:40:10 PM PST 24
Peak memory 183820 kb
Host smart-8671452e-6230-42d7-aec2-f662f8b742c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882547110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2882547110
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4246061804
Short name T878
Test name
Test status
Simulation time 31093816 ps
CPU time 1.54 seconds
Started Jan 07 12:38:31 PM PST 24
Finished Jan 07 12:40:28 PM PST 24
Peak memory 198380 kb
Host smart-2b6d7ba7-625e-48cd-9f6b-a88ae52899d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246061804 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4246061804
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.18860883
Short name T143
Test name
Test status
Simulation time 12306160 ps
CPU time 0.55 seconds
Started Jan 07 12:38:41 PM PST 24
Finished Jan 07 12:40:18 PM PST 24
Peak memory 183532 kb
Host smart-245ae9c5-43ef-4f4d-a18f-cf11508e6542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18860883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.18860883
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3939751002
Short name T843
Test name
Test status
Simulation time 109977749 ps
CPU time 0.81 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:39:45 PM PST 24
Peak memory 191812 kb
Host smart-fa8b77d4-9584-4df8-b243-00848285068b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939751002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3939751002
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.802109680
Short name T160
Test name
Test status
Simulation time 240267072 ps
CPU time 1.2 seconds
Started Jan 07 12:38:33 PM PST 24
Finished Jan 07 12:40:15 PM PST 24
Peak memory 197664 kb
Host smart-74682060-5d69-4e4b-b880-320e8b215752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802109680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.802109680
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1942324006
Short name T136
Test name
Test status
Simulation time 22425946 ps
CPU time 0.54 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:40:14 PM PST 24
Peak memory 183580 kb
Host smart-99f3238e-aeb5-46b7-a21e-cb7d4bb48fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942324006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1942324006
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2230169219
Short name T148
Test name
Test status
Simulation time 11457236 ps
CPU time 0.58 seconds
Started Jan 07 12:39:04 PM PST 24
Finished Jan 07 12:40:24 PM PST 24
Peak memory 183492 kb
Host smart-94aefda7-41c4-49d1-858b-a17eda82c26d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230169219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2230169219
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1159705754
Short name T841
Test name
Test status
Simulation time 70557979 ps
CPU time 0.53 seconds
Started Jan 07 12:38:43 PM PST 24
Finished Jan 07 12:39:58 PM PST 24
Peak memory 183672 kb
Host smart-61752569-a12b-44fa-9934-8c76722e421c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159705754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1159705754
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2591763128
Short name T854
Test name
Test status
Simulation time 107657152 ps
CPU time 0.53 seconds
Started Jan 07 12:38:51 PM PST 24
Finished Jan 07 12:40:10 PM PST 24
Peak memory 183520 kb
Host smart-15527ee6-4c3c-4f06-bddf-580f8d994aac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591763128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2591763128
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2383131872
Short name T833
Test name
Test status
Simulation time 181790520 ps
CPU time 0.57 seconds
Started Jan 07 12:38:42 PM PST 24
Finished Jan 07 12:40:39 PM PST 24
Peak memory 183564 kb
Host smart-f1a56fc8-7c7f-4723-941c-4c94826acf15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383131872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2383131872
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.175015783
Short name T842
Test name
Test status
Simulation time 31886765 ps
CPU time 0.57 seconds
Started Jan 07 12:38:37 PM PST 24
Finished Jan 07 12:40:18 PM PST 24
Peak memory 183480 kb
Host smart-113ccc44-5788-4e75-b621-31cfcc023a3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175015783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.175015783
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3083709370
Short name T140
Test name
Test status
Simulation time 12992892 ps
CPU time 0.54 seconds
Started Jan 07 12:38:37 PM PST 24
Finished Jan 07 12:40:13 PM PST 24
Peak memory 183584 kb
Host smart-885fbb4d-e559-404a-8f11-8e35a47da633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083709370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3083709370
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4128522826
Short name T149
Test name
Test status
Simulation time 54948825 ps
CPU time 0.57 seconds
Started Jan 07 12:38:58 PM PST 24
Finished Jan 07 12:40:22 PM PST 24
Peak memory 183620 kb
Host smart-6ca0d063-6bfa-4d55-a639-2f1963fc4f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128522826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4128522826
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2016438314
Short name T142
Test name
Test status
Simulation time 62746835 ps
CPU time 0.58 seconds
Started Jan 07 12:38:31 PM PST 24
Finished Jan 07 12:39:36 PM PST 24
Peak memory 183556 kb
Host smart-0ffcd68e-517e-429d-ac88-f09d53e1f8ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016438314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2016438314
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2611877166
Short name T150
Test name
Test status
Simulation time 117611314 ps
CPU time 0.53 seconds
Started Jan 07 12:38:36 PM PST 24
Finished Jan 07 12:39:57 PM PST 24
Peak memory 183568 kb
Host smart-859f97d3-b8bc-40d3-9a7d-e55779a0a0ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611877166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2611877166
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3248105318
Short name T29
Test name
Test status
Simulation time 61088897 ps
CPU time 1.4 seconds
Started Jan 07 12:39:08 PM PST 24
Finished Jan 07 12:40:26 PM PST 24
Peak memory 198440 kb
Host smart-645f004f-9663-4367-8ae0-49d72dd9c69c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248105318 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3248105318
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.545663663
Short name T14
Test name
Test status
Simulation time 38239569 ps
CPU time 0.65 seconds
Started Jan 07 12:38:43 PM PST 24
Finished Jan 07 12:40:07 PM PST 24
Peak memory 194112 kb
Host smart-dfdaa21c-0aca-486d-80a4-b8ddfc317740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545663663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.545663663
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1217313374
Short name T826
Test name
Test status
Simulation time 157209087 ps
CPU time 0.55 seconds
Started Jan 07 12:38:35 PM PST 24
Finished Jan 07 12:39:59 PM PST 24
Peak memory 183568 kb
Host smart-536f71b5-2a6a-45aa-a677-8b6603c16dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217313374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1217313374
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4119426329
Short name T875
Test name
Test status
Simulation time 21417587 ps
CPU time 0.91 seconds
Started Jan 07 12:38:17 PM PST 24
Finished Jan 07 12:39:43 PM PST 24
Peak memory 192032 kb
Host smart-120603d9-06e1-42f1-8642-b18ebedbecaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119426329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4119426329
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.728177782
Short name T155
Test name
Test status
Simulation time 61360506 ps
CPU time 2.95 seconds
Started Jan 07 12:38:09 PM PST 24
Finished Jan 07 12:39:36 PM PST 24
Peak memory 198368 kb
Host smart-d96fa016-d525-427f-8b05-c4b708190f05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728177782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.728177782
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1433339866
Short name T34
Test name
Test status
Simulation time 470791172 ps
CPU time 1.77 seconds
Started Jan 07 12:38:33 PM PST 24
Finished Jan 07 12:40:10 PM PST 24
Peak memory 198168 kb
Host smart-a6e30d64-c8c5-4008-b90f-c02f1727da3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433339866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1433339866
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1818722768
Short name T22
Test name
Test status
Simulation time 137146713 ps
CPU time 1.64 seconds
Started Jan 07 12:39:02 PM PST 24
Finished Jan 07 12:40:18 PM PST 24
Peak memory 198400 kb
Host smart-77c2249d-c112-44cd-bc9e-29afabf77549
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818722768 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1818722768
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4023543769
Short name T79
Test name
Test status
Simulation time 12931176 ps
CPU time 0.67 seconds
Started Jan 07 12:38:43 PM PST 24
Finished Jan 07 12:40:02 PM PST 24
Peak memory 194148 kb
Host smart-fbea1889-3816-4c53-a7bd-54fd3a97cf34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023543769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4023543769
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2667148105
Short name T145
Test name
Test status
Simulation time 24963748 ps
CPU time 0.53 seconds
Started Jan 07 12:38:30 PM PST 24
Finished Jan 07 12:39:43 PM PST 24
Peak memory 183548 kb
Host smart-23dcec1c-d5ff-45e6-9614-b39e470fa21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667148105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2667148105
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3200507140
Short name T94
Test name
Test status
Simulation time 582054854 ps
CPU time 0.81 seconds
Started Jan 07 12:38:14 PM PST 24
Finished Jan 07 12:39:28 PM PST 24
Peak memory 191704 kb
Host smart-ec9d03e1-71a4-434b-8320-c6625bd9bdcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200507140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3200507140
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2730348039
Short name T870
Test name
Test status
Simulation time 369616622 ps
CPU time 2.5 seconds
Started Jan 07 12:38:16 PM PST 24
Finished Jan 07 12:39:24 PM PST 24
Peak memory 198380 kb
Host smart-724feb65-4f66-4919-a2a3-ad7f11b21223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730348039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2730348039
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3853822141
Short name T74
Test name
Test status
Simulation time 13710690 ps
CPU time 0.64 seconds
Started Jan 07 12:38:40 PM PST 24
Finished Jan 07 12:39:56 PM PST 24
Peak memory 194152 kb
Host smart-5179b429-7a18-4bdf-a60f-80d3f079bd55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853822141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3853822141
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1428324369
Short name T866
Test name
Test status
Simulation time 99400366 ps
CPU time 0.54 seconds
Started Jan 07 12:38:39 PM PST 24
Finished Jan 07 12:40:01 PM PST 24
Peak memory 183552 kb
Host smart-f0f2b266-293c-4248-849f-20b8ce251722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428324369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1428324369
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.283648161
Short name T852
Test name
Test status
Simulation time 34871276 ps
CPU time 1.27 seconds
Started Jan 07 12:38:21 PM PST 24
Finished Jan 07 12:40:19 PM PST 24
Peak memory 198464 kb
Host smart-c94ccea6-cad8-485b-b22d-84ad1abea122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283648161 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.283648161
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.94547846
Short name T91
Test name
Test status
Simulation time 34894653 ps
CPU time 0.59 seconds
Started Jan 07 12:38:31 PM PST 24
Finished Jan 07 12:39:48 PM PST 24
Peak memory 193812 kb
Host smart-c651eb10-7da7-4171-98ac-1f86a30aeefa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94547846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.94547846
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3345691260
Short name T139
Test name
Test status
Simulation time 18776717 ps
CPU time 0.54 seconds
Started Jan 07 12:38:47 PM PST 24
Finished Jan 07 12:40:23 PM PST 24
Peak memory 183664 kb
Host smart-82ff23a6-65f3-4771-972d-585053eb007f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345691260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3345691260
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3898091953
Short name T159
Test name
Test status
Simulation time 241015610 ps
CPU time 1.31 seconds
Started Jan 07 12:38:13 PM PST 24
Finished Jan 07 12:39:42 PM PST 24
Peak memory 192008 kb
Host smart-85829e5e-e2a6-42d8-930a-156e2e006714
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898091953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3898091953
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1184524409
Short name T837
Test name
Test status
Simulation time 342093136 ps
CPU time 3.04 seconds
Started Jan 07 12:38:23 PM PST 24
Finished Jan 07 12:39:35 PM PST 24
Peak memory 198452 kb
Host smart-0954b14a-d344-4dda-ab2d-960a5640acb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184524409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1184524409
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1548838210
Short name T15
Test name
Test status
Simulation time 105509338 ps
CPU time 1.08 seconds
Started Jan 07 12:38:26 PM PST 24
Finished Jan 07 12:39:27 PM PST 24
Peak memory 197628 kb
Host smart-1941479e-7644-4044-aea9-8e65da039921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548838210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1548838210
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2774361944
Short name T877
Test name
Test status
Simulation time 48922307 ps
CPU time 1.47 seconds
Started Jan 07 12:38:39 PM PST 24
Finished Jan 07 12:40:07 PM PST 24
Peak memory 198456 kb
Host smart-b52c4c7b-a729-4a4f-a83d-f8c1cd49040b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774361944 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2774361944
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4247955607
Short name T83
Test name
Test status
Simulation time 38028268 ps
CPU time 0.65 seconds
Started Jan 07 12:38:39 PM PST 24
Finished Jan 07 12:39:40 PM PST 24
Peak memory 194604 kb
Host smart-f1d6e2d9-1264-47dd-b530-3c3d2bf867f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247955607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.4247955607
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.657977079
Short name T80
Test name
Test status
Simulation time 52966903 ps
CPU time 1.23 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:40:14 PM PST 24
Peak memory 192024 kb
Host smart-dae196ab-e55d-4778-ac0f-bf043149c0ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657977079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.657977079
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2046702012
Short name T831
Test name
Test status
Simulation time 148389579 ps
CPU time 1.08 seconds
Started Jan 07 12:38:43 PM PST 24
Finished Jan 07 12:40:15 PM PST 24
Peak memory 197444 kb
Host smart-f90f829c-b7c8-4c8a-93db-74ec02d78bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046702012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2046702012
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4158499130
Short name T400
Test name
Test status
Simulation time 10931363 ps
CPU time 0.58 seconds
Started Jan 07 01:13:43 PM PST 24
Finished Jan 07 01:13:45 PM PST 24
Peak memory 193192 kb
Host smart-9afd77df-6693-447a-a541-9cae9aee441f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158499130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4158499130
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2384523550
Short name T444
Test name
Test status
Simulation time 1722768231 ps
CPU time 53.87 seconds
Started Jan 07 01:13:44 PM PST 24
Finished Jan 07 01:14:39 PM PST 24
Peak memory 237760 kb
Host smart-4b12a5d1-e19c-41f2-960a-1200120a54c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384523550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2384523550
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1000213623
Short name T599
Test name
Test status
Simulation time 1870725619 ps
CPU time 21.56 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:14:06 PM PST 24
Peak memory 198600 kb
Host smart-7786683a-8c16-417f-81cc-17ba775d9e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000213623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1000213623
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1028001117
Short name T500
Test name
Test status
Simulation time 218411363 ps
CPU time 10.06 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:13:55 PM PST 24
Peak memory 198772 kb
Host smart-53f4ca13-2d1e-4026-8c46-9c5d0a3fa54e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028001117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1028001117
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.463184013
Short name T722
Test name
Test status
Simulation time 13556902888 ps
CPU time 118.01 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:15:42 PM PST 24
Peak memory 198824 kb
Host smart-8a42c09d-3f65-4344-8321-28cce359aed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463184013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.463184013
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.4133552155
Short name T161
Test name
Test status
Simulation time 3684266141 ps
CPU time 7.43 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:13:50 PM PST 24
Peak memory 198852 kb
Host smart-dd635139-1798-4a9d-acfe-d6fc3e92348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133552155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4133552155
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2483762710
Short name T57
Test name
Test status
Simulation time 153862353 ps
CPU time 0.97 seconds
Started Jan 07 01:13:44 PM PST 24
Finished Jan 07 01:13:46 PM PST 24
Peak memory 217140 kb
Host smart-ef4925b5-9072-4d7e-9d33-f2a21ee24b1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483762710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2483762710
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1540254537
Short name T341
Test name
Test status
Simulation time 287647578 ps
CPU time 3.48 seconds
Started Jan 07 01:13:39 PM PST 24
Finished Jan 07 01:13:43 PM PST 24
Peak memory 198700 kb
Host smart-bc862e3d-c249-4b7c-9edf-264915137291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540254537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1540254537
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2827306594
Short name T256
Test name
Test status
Simulation time 182964624571 ps
CPU time 737.77 seconds
Started Jan 07 01:13:44 PM PST 24
Finished Jan 07 01:26:03 PM PST 24
Peak memory 207048 kb
Host smart-f966ea20-004f-46a4-b124-038d4e8a140e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827306594 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2827306594
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2352468288
Short name T705
Test name
Test status
Simulation time 148646449283 ps
CPU time 1487.87 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:38:31 PM PST 24
Peak memory 248072 kb
Host smart-c65eb71c-c94b-4bd1-a84a-b72048a55404
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352468288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2352468288
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.4270143261
Short name T765
Test name
Test status
Simulation time 64879881 ps
CPU time 1.13 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:13:45 PM PST 24
Peak memory 196300 kb
Host smart-4d859d15-e302-4ebb-990c-5f036e5ce24d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270143261 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.4270143261
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2253558592
Short name T407
Test name
Test status
Simulation time 8354040107 ps
CPU time 408.06 seconds
Started Jan 07 01:13:43 PM PST 24
Finished Jan 07 01:20:33 PM PST 24
Peak memory 198856 kb
Host smart-c4bd1258-b5af-44c2-8787-34411114f276
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253558592 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.2253558592
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3026131195
Short name T206
Test name
Test status
Simulation time 865862685 ps
CPU time 42.33 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:14:26 PM PST 24
Peak memory 198588 kb
Host smart-583a918b-05e9-4a85-afe3-13fa13c5211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026131195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3026131195
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3732718518
Short name T353
Test name
Test status
Simulation time 15387783 ps
CPU time 0.57 seconds
Started Jan 07 01:13:40 PM PST 24
Finished Jan 07 01:13:42 PM PST 24
Peak memory 193220 kb
Host smart-3a80360e-4faf-43ac-aee1-374ee2511e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732718518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3732718518
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2640174716
Short name T565
Test name
Test status
Simulation time 384278262 ps
CPU time 11.5 seconds
Started Jan 07 01:13:45 PM PST 24
Finished Jan 07 01:13:57 PM PST 24
Peak memory 206784 kb
Host smart-c863b222-2d3f-4df3-8811-75ac41d66c2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640174716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2640174716
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3718562998
Short name T428
Test name
Test status
Simulation time 2145648900 ps
CPU time 48.27 seconds
Started Jan 07 01:13:44 PM PST 24
Finished Jan 07 01:14:34 PM PST 24
Peak memory 198704 kb
Host smart-cad79ac4-0a2f-4213-8938-a9fd4d5999d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718562998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3718562998
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3541834906
Short name T357
Test name
Test status
Simulation time 4624557328 ps
CPU time 64.29 seconds
Started Jan 07 01:13:45 PM PST 24
Finished Jan 07 01:14:50 PM PST 24
Peak memory 198768 kb
Host smart-37ea2751-02d9-49f1-a0c5-208a806d6545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541834906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3541834906
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.799317303
Short name T339
Test name
Test status
Simulation time 5250088691 ps
CPU time 90.64 seconds
Started Jan 07 01:13:40 PM PST 24
Finished Jan 07 01:15:11 PM PST 24
Peak memory 198740 kb
Host smart-a3f13854-8b07-4564-8883-7633b5117a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799317303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.799317303
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4081018446
Short name T58
Test name
Test status
Simulation time 94479754 ps
CPU time 0.79 seconds
Started Jan 07 01:13:39 PM PST 24
Finished Jan 07 01:13:41 PM PST 24
Peak memory 215804 kb
Host smart-909a33dd-f07a-4b1f-9dda-05d57c3d14e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081018446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4081018446
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3979962451
Short name T546
Test name
Test status
Simulation time 98338625 ps
CPU time 0.9 seconds
Started Jan 07 01:13:43 PM PST 24
Finished Jan 07 01:13:45 PM PST 24
Peak memory 195996 kb
Host smart-1c6ca9b7-5d04-464b-a051-9a0805901402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979962451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3979962451
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3987990717
Short name T701
Test name
Test status
Simulation time 35751805076 ps
CPU time 161.2 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:16:25 PM PST 24
Peak memory 198836 kb
Host smart-382a3d28-28b4-4b46-8473-adb2002c1428
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987990717 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3987990717
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3167423189
Short name T427
Test name
Test status
Simulation time 130863077050 ps
CPU time 3133.38 seconds
Started Jan 07 01:13:43 PM PST 24
Finished Jan 07 02:05:58 PM PST 24
Peak memory 246436 kb
Host smart-1210bcf4-36fd-48c7-9797-7caf7eaa3bd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167423189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3167423189
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.718050409
Short name T190
Test name
Test status
Simulation time 75649191 ps
CPU time 1.21 seconds
Started Jan 07 01:13:44 PM PST 24
Finished Jan 07 01:13:46 PM PST 24
Peak memory 197044 kb
Host smart-c7e2dcc8-3221-4762-8eae-27e4dc3a33ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718050409 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.718050409
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.4230551695
Short name T213
Test name
Test status
Simulation time 122651706882 ps
CPU time 420.6 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:20:45 PM PST 24
Peak memory 198816 kb
Host smart-039e6442-edd5-4244-80a2-24447f6084cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230551695 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.4230551695
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2386025738
Short name T689
Test name
Test status
Simulation time 1634726414 ps
CPU time 26.83 seconds
Started Jan 07 01:13:40 PM PST 24
Finished Jan 07 01:14:08 PM PST 24
Peak memory 198736 kb
Host smart-6863a2cd-6917-4516-9aa1-88a94579cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386025738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2386025738
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1672893238
Short name T601
Test name
Test status
Simulation time 15675982 ps
CPU time 0.55 seconds
Started Jan 07 01:14:34 PM PST 24
Finished Jan 07 01:14:35 PM PST 24
Peak memory 193160 kb
Host smart-ab15e147-658a-47da-9fa6-d19a501b2ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672893238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1672893238
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3070104664
Short name T521
Test name
Test status
Simulation time 12742772215 ps
CPU time 38.29 seconds
Started Jan 07 01:14:34 PM PST 24
Finished Jan 07 01:15:14 PM PST 24
Peak memory 206940 kb
Host smart-48b2ceff-683e-4df8-8cc8-5ba79dab6cb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070104664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3070104664
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2901911298
Short name T641
Test name
Test status
Simulation time 755434045 ps
CPU time 5.96 seconds
Started Jan 07 01:14:35 PM PST 24
Finished Jan 07 01:14:42 PM PST 24
Peak memory 198676 kb
Host smart-6a59d95b-9eb6-462c-bcf1-ef9120ce028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901911298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2901911298
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.468800709
Short name T481
Test name
Test status
Simulation time 3121000187 ps
CPU time 68.39 seconds
Started Jan 07 01:14:33 PM PST 24
Finished Jan 07 01:15:43 PM PST 24
Peak memory 198812 kb
Host smart-6d0eecdc-d54b-401a-ba13-e7351a5c282d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468800709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.468800709
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.672942281
Short name T734
Test name
Test status
Simulation time 7962224811 ps
CPU time 95.36 seconds
Started Jan 07 01:14:45 PM PST 24
Finished Jan 07 01:16:21 PM PST 24
Peak memory 198796 kb
Host smart-d9d87ab9-a9fb-471e-b3ba-f357d89afd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672942281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.672942281
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2919969859
Short name T10
Test name
Test status
Simulation time 1938026295 ps
CPU time 71.06 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:15:57 PM PST 24
Peak memory 198664 kb
Host smart-14f4d8c5-3553-4004-a38a-b00d273751d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919969859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2919969859
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2632111933
Short name T183
Test name
Test status
Simulation time 134345095 ps
CPU time 3.03 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:14:48 PM PST 24
Peak memory 198684 kb
Host smart-d4643276-002c-4d50-8d7c-872496b8ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632111933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2632111933
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1777915000
Short name T48
Test name
Test status
Simulation time 70717827044 ps
CPU time 971.97 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:30:57 PM PST 24
Peak memory 198828 kb
Host smart-552e2804-4f7f-454e-8d64-f26352a8f532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777915000 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1777915000
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.100184104
Short name T680
Test name
Test status
Simulation time 179804260734 ps
CPU time 2134.25 seconds
Started Jan 07 01:14:34 PM PST 24
Finished Jan 07 01:50:10 PM PST 24
Peak memory 231568 kb
Host smart-f3a7473d-d132-4825-b159-301c6de79d36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100184104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.100184104
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.4250146865
Short name T365
Test name
Test status
Simulation time 46067880 ps
CPU time 0.92 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:14:46 PM PST 24
Peak memory 196288 kb
Host smart-ba40a4d1-200e-4620-9414-0b99e75deae3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250146865 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.4250146865
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.4142041961
Short name T194
Test name
Test status
Simulation time 99857566499 ps
CPU time 398.24 seconds
Started Jan 07 01:14:43 PM PST 24
Finished Jan 07 01:21:22 PM PST 24
Peak memory 198824 kb
Host smart-3530155e-965e-4e0b-ad8b-f5517e29b5fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142041961 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.4142041961
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2396917080
Short name T617
Test name
Test status
Simulation time 1405982768 ps
CPU time 21.86 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:12 PM PST 24
Peak memory 198660 kb
Host smart-a246759b-69ff-4941-8414-2c5a6297052a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396917080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2396917080
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.4132714218
Short name T252
Test name
Test status
Simulation time 146910796849 ps
CPU time 348.6 seconds
Started Jan 07 01:17:01 PM PST 24
Finished Jan 07 01:22:51 PM PST 24
Peak memory 224812 kb
Host smart-bf6f0d42-58a4-4433-af50-cc1870a617a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4132714218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.4132714218
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.3639975239
Short name T464
Test name
Test status
Simulation time 1577014058747 ps
CPU time 1758.36 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:46:29 PM PST 24
Peak memory 257524 kb
Host smart-34384f82-dc2e-4210-ba3a-08c6e88bf55c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639975239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.3639975239
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.4208757072
Short name T311
Test name
Test status
Simulation time 209557946709 ps
CPU time 2134.36 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:52:48 PM PST 24
Peak memory 247968 kb
Host smart-3a051f2b-5232-43b8-9b1a-dac71c83ed86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208757072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.4208757072
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.232028734
Short name T793
Test name
Test status
Simulation time 235515476461 ps
CPU time 5743.06 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 02:52:55 PM PST 24
Peak memory 264428 kb
Host smart-422f8568-0c60-4622-b299-f46c53098e37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232028734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.232028734
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.3259991685
Short name T579
Test name
Test status
Simulation time 129101768867 ps
CPU time 498.88 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:25:31 PM PST 24
Peak memory 223468 kb
Host smart-7ed3123d-b062-46fc-a4b8-63dea4749e77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259991685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.3259991685
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.1671104020
Short name T289
Test name
Test status
Simulation time 118067856956 ps
CPU time 1126.5 seconds
Started Jan 07 01:17:00 PM PST 24
Finished Jan 07 01:35:48 PM PST 24
Peak memory 215332 kb
Host smart-1f93178a-87ec-4a1d-bb4e-d2c27d536773
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671104020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.1671104020
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.372777904
Short name T528
Test name
Test status
Simulation time 37993611366 ps
CPU time 1729.5 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:46:00 PM PST 24
Peak memory 224564 kb
Host smart-eeb264e0-b428-4b3c-b0a9-110b7a8236fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=372777904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.372777904
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.3625287273
Short name T120
Test name
Test status
Simulation time 50944084622 ps
CPU time 733.02 seconds
Started Jan 07 01:17:00 PM PST 24
Finished Jan 07 01:29:14 PM PST 24
Peak memory 248076 kb
Host smart-64662072-f2fa-4089-9f7d-099ee190bfc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625287273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.3625287273
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.2600776817
Short name T670
Test name
Test status
Simulation time 40108212973 ps
CPU time 291.39 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:22:03 PM PST 24
Peak memory 198884 kb
Host smart-e195eef9-2b10-493e-a817-ea745d51802e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600776817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.2600776817
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.568965712
Short name T471
Test name
Test status
Simulation time 2120697737 ps
CPU time 29.35 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:18 PM PST 24
Peak memory 207012 kb
Host smart-a78b6073-901a-4254-af8f-1048e389f4d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568965712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.568965712
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1618192078
Short name T3
Test name
Test status
Simulation time 3020847198 ps
CPU time 33.99 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:23 PM PST 24
Peak memory 198856 kb
Host smart-068a8668-4353-40b6-a3f7-043793bbadcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618192078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1618192078
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.19965712
Short name T785
Test name
Test status
Simulation time 2866122465 ps
CPU time 106.67 seconds
Started Jan 07 01:14:45 PM PST 24
Finished Jan 07 01:16:33 PM PST 24
Peak memory 198756 kb
Host smart-27fde173-3f91-4b25-9fad-e70a9cadb3cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19965712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.19965712
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3918555910
Short name T610
Test name
Test status
Simulation time 6442044728 ps
CPU time 106.2 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:16:31 PM PST 24
Peak memory 198888 kb
Host smart-98cac79d-a6cf-47f7-a844-d858e63ac34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918555910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3918555910
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.182504983
Short name T185
Test name
Test status
Simulation time 1481844785 ps
CPU time 39.85 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:15:24 PM PST 24
Peak memory 198688 kb
Host smart-90f76ec6-0572-4fc5-b89c-2f1dc767a6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182504983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.182504983
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1526872466
Short name T448
Test name
Test status
Simulation time 2911470479 ps
CPU time 2.91 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:14:47 PM PST 24
Peak memory 198736 kb
Host smart-9bf19292-85f6-46fa-b751-72f1ec137c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526872466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1526872466
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.4064313838
Short name T685
Test name
Test status
Simulation time 5169381908 ps
CPU time 59.02 seconds
Started Jan 07 01:14:35 PM PST 24
Finished Jan 07 01:15:35 PM PST 24
Peak memory 229560 kb
Host smart-a127d2a3-41b2-42e8-b02b-3fa6fe911857
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064313838 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.4064313838
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.322419597
Short name T377
Test name
Test status
Simulation time 8607126420 ps
CPU time 69.58 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:15:56 PM PST 24
Peak memory 198800 kb
Host smart-d7a18248-ccd5-4c0b-b8f1-822316db4400
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=322419597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.322419597
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1094223203
Short name T524
Test name
Test status
Simulation time 249006542 ps
CPU time 0.93 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:14:45 PM PST 24
Peak memory 196632 kb
Host smart-63df411b-4744-4f2d-a745-251d1207ae51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094223203 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1094223203
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3137006860
Short name T363
Test name
Test status
Simulation time 1819635673 ps
CPU time 41.18 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:15:26 PM PST 24
Peak memory 198744 kb
Host smart-9f1f142e-a327-4083-a8cf-1afc9b063c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137006860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3137006860
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.2997608109
Short name T688
Test name
Test status
Simulation time 112779269570 ps
CPU time 560.28 seconds
Started Jan 07 01:17:01 PM PST 24
Finished Jan 07 01:26:23 PM PST 24
Peak memory 231704 kb
Host smart-3413121b-bd77-4166-94ab-3beeca2ed919
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2997608109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.hmac_stress_all_with_rand_reset.2997608109
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.2404779217
Short name T819
Test name
Test status
Simulation time 180653730252 ps
CPU time 764.37 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:29:57 PM PST 24
Peak memory 247768 kb
Host smart-8e538f7d-00c5-461f-bda2-4cdeaa268567
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404779217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.2404779217
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.4079143605
Short name T303
Test name
Test status
Simulation time 129859268189 ps
CPU time 380.59 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:23:33 PM PST 24
Peak memory 231672 kb
Host smart-28b7c783-208c-4017-83c4-6e1752abbaef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079143605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.4079143605
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.1175627326
Short name T614
Test name
Test status
Simulation time 82235481137 ps
CPU time 3102.52 seconds
Started Jan 07 01:17:07 PM PST 24
Finished Jan 07 02:08:51 PM PST 24
Peak memory 260916 kb
Host smart-c4510408-069e-4b32-a3bd-235614183378
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175627326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.1175627326
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.3012253555
Short name T796
Test name
Test status
Simulation time 138959197140 ps
CPU time 743.48 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:29:36 PM PST 24
Peak memory 223536 kb
Host smart-5f3e6c85-f2cb-498b-8af4-5d6a6578c37e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012253555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.3012253555
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.3390662837
Short name T613
Test name
Test status
Simulation time 224194208152 ps
CPU time 802.92 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:30:34 PM PST 24
Peak memory 255736 kb
Host smart-a8cb0020-3980-4310-addc-d5ffdc6a3b2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390662837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.3390662837
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.1599101339
Short name T392
Test name
Test status
Simulation time 592384801431 ps
CPU time 3642.28 seconds
Started Jan 07 01:17:07 PM PST 24
Finished Jan 07 02:17:51 PM PST 24
Peak memory 264432 kb
Host smart-930ffa2d-633d-4d5c-bf0f-1015158a988c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599101339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.1599101339
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.3145503559
Short name T219
Test name
Test status
Simulation time 43699234517 ps
CPU time 517.4 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:25:51 PM PST 24
Peak memory 207068 kb
Host smart-4910e5ba-1d73-473c-84a9-1e3f7ed1c392
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145503559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.3145503559
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.1772202416
Short name T496
Test name
Test status
Simulation time 59908649544 ps
CPU time 512.07 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:25:46 PM PST 24
Peak memory 231588 kb
Host smart-2f18cc37-0618-47a3-a744-5f0acf369ef5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772202416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.1772202416
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2429022316
Short name T813
Test name
Test status
Simulation time 32430871 ps
CPU time 0.55 seconds
Started Jan 07 01:14:45 PM PST 24
Finished Jan 07 01:14:47 PM PST 24
Peak memory 193220 kb
Host smart-363ac01d-5575-4432-b9e9-f1f4400dc333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429022316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2429022316
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3816215000
Short name T700
Test name
Test status
Simulation time 13493368875 ps
CPU time 62.6 seconds
Started Jan 07 01:14:45 PM PST 24
Finished Jan 07 01:15:48 PM PST 24
Peak memory 247456 kb
Host smart-7d63e93f-0082-40e4-a3f5-f793214ebdca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816215000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3816215000
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.526920303
Short name T336
Test name
Test status
Simulation time 2465261495 ps
CPU time 28.62 seconds
Started Jan 07 01:14:34 PM PST 24
Finished Jan 07 01:15:03 PM PST 24
Peak memory 198840 kb
Host smart-d87e35fa-68da-4c1d-a9e9-90b99e525705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526920303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.526920303
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.261573351
Short name T562
Test name
Test status
Simulation time 6958815833 ps
CPU time 48.24 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:37 PM PST 24
Peak memory 198872 kb
Host smart-3ff6a395-0f34-4694-988f-c2a410eb7e66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261573351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.261573351
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1623429057
Short name T720
Test name
Test status
Simulation time 7334998353 ps
CPU time 91.45 seconds
Started Jan 07 01:14:45 PM PST 24
Finished Jan 07 01:16:17 PM PST 24
Peak memory 198804 kb
Host smart-55510871-58af-4195-ab2d-d24e90e44cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623429057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1623429057
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2472197894
Short name T184
Test name
Test status
Simulation time 556006602 ps
CPU time 6.96 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:14:51 PM PST 24
Peak memory 198728 kb
Host smart-c9db36b6-1af7-4356-bd77-2e59eced74c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472197894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2472197894
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1758210346
Short name T704
Test name
Test status
Simulation time 351855872 ps
CPU time 4.23 seconds
Started Jan 07 01:14:34 PM PST 24
Finished Jan 07 01:14:40 PM PST 24
Peak memory 198692 kb
Host smart-6bdd506f-697d-4fa3-ac7a-a61cd249f6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758210346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1758210346
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1604385091
Short name T346
Test name
Test status
Simulation time 3664285045 ps
CPU time 78.56 seconds
Started Jan 07 01:14:35 PM PST 24
Finished Jan 07 01:15:55 PM PST 24
Peak memory 227788 kb
Host smart-f5dbd9ba-3e71-4ed8-b8eb-55c9bdb3294e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604385091 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1604385091
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.1324723836
Short name T653
Test name
Test status
Simulation time 205517874097 ps
CPU time 776.32 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:27:47 PM PST 24
Peak memory 215348 kb
Host smart-ddb6ee90-6ef5-443e-9868-1e47a05a1c93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324723836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.1324723836
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2873603432
Short name T681
Test name
Test status
Simulation time 79036203 ps
CPU time 1.02 seconds
Started Jan 07 01:14:33 PM PST 24
Finished Jan 07 01:14:34 PM PST 24
Peak memory 196796 kb
Host smart-0f2d990d-0b14-4390-b0a8-b357ca816d69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873603432 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2873603432
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3241642051
Short name T202
Test name
Test status
Simulation time 5015614753 ps
CPU time 81.7 seconds
Started Jan 07 01:14:45 PM PST 24
Finished Jan 07 01:16:08 PM PST 24
Peak memory 198812 kb
Host smart-ba5e6619-b639-44f9-8c55-dafd81a50b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241642051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3241642051
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.668239899
Short name T121
Test name
Test status
Simulation time 91950083020 ps
CPU time 821.81 seconds
Started Jan 07 01:17:03 PM PST 24
Finished Jan 07 01:30:46 PM PST 24
Peak memory 224512 kb
Host smart-caee386b-0408-42a1-bb13-6bb987f00077
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668239899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.668239899
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.4214578814
Short name T656
Test name
Test status
Simulation time 38239674225 ps
CPU time 1651.65 seconds
Started Jan 07 01:17:00 PM PST 24
Finished Jan 07 01:44:34 PM PST 24
Peak memory 239940 kb
Host smart-b21813e7-0c9a-48c5-a778-98328f117619
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4214578814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.4214578814
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.4194595232
Short name T815
Test name
Test status
Simulation time 106384346388 ps
CPU time 2023.69 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:50:55 PM PST 24
Peak memory 223460 kb
Host smart-b52563df-f7ad-465c-a69a-79a6e14f54e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194595232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.4194595232
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.3525081757
Short name T307
Test name
Test status
Simulation time 272606598399 ps
CPU time 2823.01 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 02:04:15 PM PST 24
Peak memory 247968 kb
Host smart-a930e6e5-110c-4271-853a-5230ef023da8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525081757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.3525081757
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.3203688923
Short name T49
Test name
Test status
Simulation time 15847203971 ps
CPU time 309.28 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:22:23 PM PST 24
Peak memory 223448 kb
Host smart-96a8c655-7ee2-4023-ab89-8f44dadc4770
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203688923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.3203688923
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.1473278163
Short name T776
Test name
Test status
Simulation time 90920046524 ps
CPU time 1762.43 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:46:35 PM PST 24
Peak memory 248108 kb
Host smart-fbaaf6f0-9586-4345-84e4-cff9871292c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1473278163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.1473278163
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.3271699142
Short name T438
Test name
Test status
Simulation time 85441252262 ps
CPU time 281.6 seconds
Started Jan 07 01:17:06 PM PST 24
Finished Jan 07 01:21:49 PM PST 24
Peak memory 207112 kb
Host smart-6fc3d959-d480-4a83-9ac8-334780a1d4d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271699142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.3271699142
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.1424607300
Short name T557
Test name
Test status
Simulation time 160016180809 ps
CPU time 372.47 seconds
Started Jan 07 01:17:13 PM PST 24
Finished Jan 07 01:23:27 PM PST 24
Peak memory 239876 kb
Host smart-3373645c-9cdc-46cc-9294-945752446247
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1424607300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.1424607300
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1619068493
Short name T424
Test name
Test status
Simulation time 28378186 ps
CPU time 0.55 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:14:49 PM PST 24
Peak memory 193084 kb
Host smart-10a5de1f-aca8-4660-98b2-6160f3877672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619068493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1619068493
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1587155878
Short name T450
Test name
Test status
Simulation time 1146847955 ps
CPU time 36.93 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:27 PM PST 24
Peak memory 215132 kb
Host smart-e472324a-7395-4bc1-93a8-6a5ade45fcc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1587155878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1587155878
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.262751054
Short name T254
Test name
Test status
Simulation time 771936163 ps
CPU time 33.17 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:21 PM PST 24
Peak memory 198704 kb
Host smart-ae2aef09-b757-46bc-bcbf-59f2d2479f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262751054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.262751054
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1528672928
Short name T825
Test name
Test status
Simulation time 26036398863 ps
CPU time 133.83 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:17:01 PM PST 24
Peak memory 198764 kb
Host smart-5335bc3f-f97b-4e11-ae00-898df2cb9bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528672928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1528672928
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2968394091
Short name T409
Test name
Test status
Simulation time 4975285627 ps
CPU time 61.49 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:51 PM PST 24
Peak memory 198780 kb
Host smart-db04adc5-4551-4a14-8ebb-3ea2092995bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968394091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2968394091
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1533386099
Short name T197
Test name
Test status
Simulation time 3498199023 ps
CPU time 41.63 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:15:32 PM PST 24
Peak memory 198764 kb
Host smart-b870e635-909d-45dd-81d5-801320af2d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533386099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1533386099
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3247260775
Short name T342
Test name
Test status
Simulation time 1111364665 ps
CPU time 2.66 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:14:51 PM PST 24
Peak memory 198612 kb
Host smart-83dd7b9a-693d-41ed-80e8-22b3a0a26535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247260775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3247260775
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3182656920
Short name T731
Test name
Test status
Simulation time 50094332259 ps
CPU time 559.84 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:24:07 PM PST 24
Peak memory 226500 kb
Host smart-feba77aa-e092-4a40-a35e-383cdcfab2d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182656920 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3182656920
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.3340603258
Short name T51
Test name
Test status
Simulation time 145013071235 ps
CPU time 642.09 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:25:34 PM PST 24
Peak memory 231644 kb
Host smart-828b4167-02f9-45f6-9fb4-8689902a5219
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3340603258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.3340603258
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1863628155
Short name T466
Test name
Test status
Simulation time 30635713 ps
CPU time 1.21 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:14:54 PM PST 24
Peak memory 198028 kb
Host smart-7ce76198-76ac-4988-b64e-45079aa80907
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863628155 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.1863628155
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1044603565
Short name T404
Test name
Test status
Simulation time 27738299844 ps
CPU time 437.66 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:22:06 PM PST 24
Peak memory 198832 kb
Host smart-70b64579-9367-4e81-baa3-1ab7eb37b8ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044603565 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.1044603565
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.66018019
Short name T372
Test name
Test status
Simulation time 7297029174 ps
CPU time 54.07 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:15:46 PM PST 24
Peak memory 198740 kb
Host smart-75594548-1d00-4146-a5b8-5d6cf834a7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66018019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.66018019
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.1425261004
Short name T412
Test name
Test status
Simulation time 91643069701 ps
CPU time 1708.77 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:45:42 PM PST 24
Peak memory 231564 kb
Host smart-e6faa191-73b7-47c0-8f32-52d738797748
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425261004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.1425261004
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.3948723214
Short name T198
Test name
Test status
Simulation time 14325716088 ps
CPU time 226.51 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 01:20:56 PM PST 24
Peak memory 231340 kb
Host smart-3091c95d-29ed-408c-841b-ae03c5741616
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3948723214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.3948723214
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.2763430886
Short name T454
Test name
Test status
Simulation time 113844059876 ps
CPU time 456.63 seconds
Started Jan 07 01:17:02 PM PST 24
Finished Jan 07 01:24:40 PM PST 24
Peak memory 239860 kb
Host smart-d000d4d4-e2da-4fea-a55d-fc86f67264fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763430886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.2763430886
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.352199435
Short name T492
Test name
Test status
Simulation time 101774136561 ps
CPU time 1398.29 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:40:32 PM PST 24
Peak memory 248032 kb
Host smart-4f17575f-a077-4d6f-8111-2fd5de11c420
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352199435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.352199435
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.705966363
Short name T697
Test name
Test status
Simulation time 33831076481 ps
CPU time 1640.97 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 01:44:30 PM PST 24
Peak memory 243960 kb
Host smart-feb4a832-97c3-487f-86c6-387ff611c55a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705966363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.705966363
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.2879583262
Short name T126
Test name
Test status
Simulation time 84153740907 ps
CPU time 3984 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 02:23:37 PM PST 24
Peak memory 257932 kb
Host smart-39a11ec2-05dd-4e0d-96e6-7f22c8cff5ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879583262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.2879583262
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.3505089718
Short name T581
Test name
Test status
Simulation time 40504336257 ps
CPU time 330.81 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:22:42 PM PST 24
Peak memory 214992 kb
Host smart-4323a9f0-5d45-42ca-91c7-fcc008850650
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505089718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.3505089718
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.4261848908
Short name T774
Test name
Test status
Simulation time 341438812831 ps
CPU time 2904.9 seconds
Started Jan 07 01:17:14 PM PST 24
Finished Jan 07 02:05:40 PM PST 24
Peak memory 258520 kb
Host smart-ef6c9a8a-e474-4e39-92d3-4aacbf947694
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4261848908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.4261848908
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.264659141
Short name T417
Test name
Test status
Simulation time 46235900 ps
CPU time 0.56 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:14:49 PM PST 24
Peak memory 193132 kb
Host smart-4bf9afc1-16dc-4ea3-8f31-16bd2522aa09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264659141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.264659141
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1656062846
Short name T262
Test name
Test status
Simulation time 75148147 ps
CPU time 0.76 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:14:49 PM PST 24
Peak memory 196580 kb
Host smart-828f7968-5617-46db-a547-7673f8c990e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656062846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1656062846
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.611003890
Short name T393
Test name
Test status
Simulation time 3607290492 ps
CPU time 30.12 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:20 PM PST 24
Peak memory 198768 kb
Host smart-9a01a66c-ff39-4c90-8aa9-9960b7460061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611003890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.611003890
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2414790963
Short name T780
Test name
Test status
Simulation time 5381867752 ps
CPU time 72.18 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:16:04 PM PST 24
Peak memory 198772 kb
Host smart-1ca44252-e591-4cb4-a27b-580ffa4d1f92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414790963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2414790963
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3032154721
Short name T414
Test name
Test status
Simulation time 11522442812 ps
CPU time 144.92 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:17:17 PM PST 24
Peak memory 198816 kb
Host smart-2aa93bb8-fd76-41d5-a79b-1109434c999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032154721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3032154721
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.14377575
Short name T777
Test name
Test status
Simulation time 2942972511 ps
CPU time 35.25 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:24 PM PST 24
Peak memory 198884 kb
Host smart-54323227-2e78-4a80-bd00-546a96e0daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14377575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.14377575
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.323059745
Short name T698
Test name
Test status
Simulation time 2081277779 ps
CPU time 2.22 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:14:51 PM PST 24
Peak memory 198744 kb
Host smart-f282c2c2-6500-417e-8a80-2801759020bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323059745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.323059745
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3040794851
Short name T772
Test name
Test status
Simulation time 120279893374 ps
CPU time 1376.32 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:37:43 PM PST 24
Peak memory 239716 kb
Host smart-37adab50-d075-47a5-83cc-bd720c69744b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040794851 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3040794851
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.2231229880
Short name T317
Test name
Test status
Simulation time 42783893859 ps
CPU time 154.21 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:17:26 PM PST 24
Peak memory 215256 kb
Host smart-14b1ca9f-02b4-4bb9-bde7-5e1f1da8518b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2231229880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.2231229880
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2491956309
Short name T539
Test name
Test status
Simulation time 48405093 ps
CPU time 0.91 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:14:49 PM PST 24
Peak memory 195920 kb
Host smart-d327acd2-5f07-4715-ad51-c1fb51e84b62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491956309 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2491956309
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.394215874
Short name T399
Test name
Test status
Simulation time 76905583527 ps
CPU time 474.29 seconds
Started Jan 07 01:14:45 PM PST 24
Finished Jan 07 01:22:41 PM PST 24
Peak memory 198828 kb
Host smart-d4ce4434-4733-48d0-ac5b-0edfc57811b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394215874 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.hmac_test_sha_vectors.394215874
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3804714074
Short name T760
Test name
Test status
Simulation time 1619227255 ps
CPU time 13.67 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:03 PM PST 24
Peak memory 198604 kb
Host smart-328d247a-c10a-40d2-95ad-7064ed009152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804714074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3804714074
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.3436167179
Short name T271
Test name
Test status
Simulation time 23885806430 ps
CPU time 314.71 seconds
Started Jan 07 01:17:14 PM PST 24
Finished Jan 07 01:22:30 PM PST 24
Peak memory 214592 kb
Host smart-9b386a6b-6895-46b5-81de-53f91d1bb356
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436167179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.3436167179
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.265652804
Short name T644
Test name
Test status
Simulation time 562883278674 ps
CPU time 823.91 seconds
Started Jan 07 01:17:14 PM PST 24
Finished Jan 07 01:30:59 PM PST 24
Peak memory 239556 kb
Host smart-24a701c7-c694-43fe-a4a9-ac48241caf0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=265652804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.265652804
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.3892812147
Short name T503
Test name
Test status
Simulation time 409227239992 ps
CPU time 1705.22 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:45:37 PM PST 24
Peak memory 248004 kb
Host smart-1d3ff240-a477-482e-9f97-6bb7a28df817
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892812147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.3892812147
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.2898178815
Short name T580
Test name
Test status
Simulation time 311899276633 ps
CPU time 1358 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:39:51 PM PST 24
Peak memory 257168 kb
Host smart-5c834cf4-64a5-4d21-b753-c0adbbbc37e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2898178815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.2898178815
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.2513338995
Short name T426
Test name
Test status
Simulation time 75582450731 ps
CPU time 1102.37 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 01:35:32 PM PST 24
Peak memory 245964 kb
Host smart-c8f9dd49-1557-4dd3-a367-70c6f2f5dfd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513338995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.2513338995
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.705236804
Short name T590
Test name
Test status
Simulation time 312666606085 ps
CPU time 2893.85 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 02:05:28 PM PST 24
Peak memory 257708 kb
Host smart-a5fec1ab-18d0-4926-a71f-e903108a1160
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705236804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.705236804
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.2600291907
Short name T403
Test name
Test status
Simulation time 48055967409 ps
CPU time 2434.42 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 01:57:45 PM PST 24
Peak memory 247652 kb
Host smart-a2fbd452-1da1-4c30-8ef1-0beaa066af7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600291907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.2600291907
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.2791384876
Short name T411
Test name
Test status
Simulation time 216784311476 ps
CPU time 2181.77 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 01:53:31 PM PST 24
Peak memory 231748 kb
Host smart-ee13439e-d574-4017-86dc-4a20a2a9871c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791384876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.2791384876
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.2374055802
Short name T635
Test name
Test status
Simulation time 267662156590 ps
CPU time 1849.91 seconds
Started Jan 07 01:17:07 PM PST 24
Finished Jan 07 01:47:58 PM PST 24
Peak memory 255220 kb
Host smart-0f44802c-73cd-4a02-abdf-e26523c7abfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374055802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.2374055802
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4198251356
Short name T808
Test name
Test status
Simulation time 15879707 ps
CPU time 0.56 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:14:51 PM PST 24
Peak memory 193128 kb
Host smart-33232bbe-8510-4307-984e-65e9ab4e4b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198251356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4198251356
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2883673630
Short name T732
Test name
Test status
Simulation time 613360709 ps
CPU time 19.02 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:08 PM PST 24
Peak memory 215080 kb
Host smart-0b506e14-8593-4b67-94a3-4d4a110ead6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883673630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2883673630
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3291420508
Short name T99
Test name
Test status
Simulation time 2174858568 ps
CPU time 22.96 seconds
Started Jan 07 01:14:45 PM PST 24
Finished Jan 07 01:15:09 PM PST 24
Peak memory 198788 kb
Host smart-bbc4eb79-3d1b-4dad-8ce6-d073d385f03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291420508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3291420508
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1735815950
Short name T1
Test name
Test status
Simulation time 2039989011 ps
CPU time 100.93 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:16:29 PM PST 24
Peak memory 198640 kb
Host smart-7b262d2e-abf5-44c4-bf2f-9ad4a02a59d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735815950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1735815950
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3213387095
Short name T504
Test name
Test status
Simulation time 12387821640 ps
CPU time 141.87 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:17:10 PM PST 24
Peak memory 198844 kb
Host smart-c009188e-7ec8-4258-adc4-2d5f483df42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213387095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3213387095
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1191745183
Short name T240
Test name
Test status
Simulation time 39379839 ps
CPU time 1.12 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:14:49 PM PST 24
Peak memory 198700 kb
Host smart-8b8b1816-fbbe-47fe-8796-b7542e37b3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191745183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1191745183
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.391348732
Short name T638
Test name
Test status
Simulation time 64994124 ps
CPU time 1.1 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:14:49 PM PST 24
Peak memory 197416 kb
Host smart-eada0eb9-ddba-4319-95b2-1d201e7a841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391348732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.391348732
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.439886438
Short name T200
Test name
Test status
Simulation time 5155168829 ps
CPU time 130.34 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:16:58 PM PST 24
Peak memory 231036 kb
Host smart-700b6192-487c-4415-8ac9-300bf956d9fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439886438 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.439886438
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3382056288
Short name T285
Test name
Test status
Simulation time 1193777089 ps
CPU time 1.15 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:14:53 PM PST 24
Peak memory 196936 kb
Host smart-119e7f58-2bba-4bdf-91bd-2d485fd2cbbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382056288 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3382056288
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.41500125
Short name T195
Test name
Test status
Simulation time 2509905025 ps
CPU time 41.67 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:31 PM PST 24
Peak memory 198868 kb
Host smart-6c19d891-84f6-4a5e-86be-2b03ac0a163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41500125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.41500125
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.1758184500
Short name T628
Test name
Test status
Simulation time 12319521411 ps
CPU time 158.88 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 01:19:49 PM PST 24
Peak memory 214684 kb
Host smart-24d91bd3-8438-46be-b507-f03a693ad8b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1758184500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.1758184500
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.23312108
Short name T267
Test name
Test status
Simulation time 330048450937 ps
CPU time 1043.83 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:34:36 PM PST 24
Peak memory 239916 kb
Host smart-81a74ceb-8f97-481b-a3f2-b00f469eecc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23312108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.23312108
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.518843811
Short name T621
Test name
Test status
Simulation time 50892601365 ps
CPU time 745.76 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:29:38 PM PST 24
Peak memory 208032 kb
Host smart-7428ab4c-a71a-4ff2-92c6-27ad4c94e6d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518843811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.518843811
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.2774132152
Short name T672
Test name
Test status
Simulation time 21143834733 ps
CPU time 492.76 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 01:25:22 PM PST 24
Peak memory 236208 kb
Host smart-e13ce6c2-1898-41d2-9983-41d5fa90ea12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774132152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.2774132152
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.2363065919
Short name T110
Test name
Test status
Simulation time 16510907752 ps
CPU time 794 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:30:26 PM PST 24
Peak memory 223424 kb
Host smart-e57a24a3-2d0d-4b07-9e63-e00a291d0466
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2363065919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.2363065919
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.3720481172
Short name T321
Test name
Test status
Simulation time 73110640111 ps
CPU time 880.68 seconds
Started Jan 07 01:17:13 PM PST 24
Finished Jan 07 01:31:55 PM PST 24
Peak memory 245704 kb
Host smart-9cc4b7f5-bc8a-4a20-af43-82ff2e53122a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720481172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.3720481172
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.2411524855
Short name T666
Test name
Test status
Simulation time 144419613299 ps
CPU time 984.06 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:33:35 PM PST 24
Peak memory 212860 kb
Host smart-416f80f6-3268-43b2-8608-0ba76ac3ec8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2411524855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.2411524855
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.4000715035
Short name T485
Test name
Test status
Simulation time 604738619829 ps
CPU time 2820.32 seconds
Started Jan 07 01:17:14 PM PST 24
Finished Jan 07 02:04:16 PM PST 24
Peak memory 255880 kb
Host smart-ade20f7d-2b53-4765-8ef3-a2b4e97a3991
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4000715035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.4000715035
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.3296100452
Short name T324
Test name
Test status
Simulation time 31209047066 ps
CPU time 432.36 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 01:24:22 PM PST 24
Peak memory 214016 kb
Host smart-499a0813-b62b-44c7-ac52-75a81e8715e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296100452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.3296100452
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1022691077
Short name T394
Test name
Test status
Simulation time 38410903 ps
CPU time 0.6 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:14:53 PM PST 24
Peak memory 193124 kb
Host smart-caca0cb9-3002-46ce-aa27-1be4ac9f6e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022691077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1022691077
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.4221942275
Short name T329
Test name
Test status
Simulation time 501823415 ps
CPU time 15.64 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:04 PM PST 24
Peak memory 206924 kb
Host smart-441352ed-8a6a-4ce5-8daa-27daa0eb54d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221942275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4221942275
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.360788187
Short name T186
Test name
Test status
Simulation time 211891339 ps
CPU time 1.41 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:14:53 PM PST 24
Peak memory 198628 kb
Host smart-fac7d722-926f-43f7-9eca-84a7123b6a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360788187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.360788187
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2421694309
Short name T105
Test name
Test status
Simulation time 2767687567 ps
CPU time 27.5 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:15:17 PM PST 24
Peak memory 198732 kb
Host smart-1053173f-bda7-48ce-9265-37b14105584b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421694309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2421694309
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.4290121998
Short name T468
Test name
Test status
Simulation time 59959331436 ps
CPU time 162.05 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:17:33 PM PST 24
Peak memory 198788 kb
Host smart-ed74c1bd-3d45-46a9-a153-d1332ddb5dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290121998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.4290121998
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1274066737
Short name T238
Test name
Test status
Simulation time 561233167 ps
CPU time 5.27 seconds
Started Jan 07 01:14:45 PM PST 24
Finished Jan 07 01:14:52 PM PST 24
Peak memory 198732 kb
Host smart-bb302ffc-8ba3-410f-870e-a48c49961fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274066737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1274066737
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.126445596
Short name T795
Test name
Test status
Simulation time 989114246 ps
CPU time 3.15 seconds
Started Jan 07 01:14:45 PM PST 24
Finished Jan 07 01:14:49 PM PST 24
Peak memory 198616 kb
Host smart-e4a82142-4984-4a73-a565-571ca18cff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126445596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.126445596
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3716321994
Short name T38
Test name
Test status
Simulation time 15618531001 ps
CPU time 249.06 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:18:57 PM PST 24
Peak memory 198884 kb
Host smart-d2aa124a-be04-4c1d-bf48-40a3dd1933e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716321994 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3716321994
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.1125651845
Short name T366
Test name
Test status
Simulation time 56569410906 ps
CPU time 2242.81 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:52:13 PM PST 24
Peak memory 243048 kb
Host smart-2e715d04-9eaa-41cf-addb-3f1cdbe0b153
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125651845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.1125651845
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2363132814
Short name T344
Test name
Test status
Simulation time 44905478 ps
CPU time 0.99 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:14:53 PM PST 24
Peak memory 195824 kb
Host smart-f3091699-3abf-4cfc-9307-26b6f0f57f68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363132814 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2363132814
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3279777012
Short name T171
Test name
Test status
Simulation time 15945978550 ps
CPU time 404.32 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:21:36 PM PST 24
Peak memory 198900 kb
Host smart-0575c736-2958-4cdc-82df-ee099a525207
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279777012 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.3279777012
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3964854859
Short name T279
Test name
Test status
Simulation time 1831743402 ps
CPU time 67.56 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:15:59 PM PST 24
Peak memory 198652 kb
Host smart-cae7eec1-2443-45c5-b8c2-abed862f813a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964854859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3964854859
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.747984109
Short name T395
Test name
Test status
Simulation time 294074539311 ps
CPU time 2888.22 seconds
Started Jan 07 01:17:13 PM PST 24
Finished Jan 07 02:05:23 PM PST 24
Peak memory 231084 kb
Host smart-836b1b9a-93c5-4cf5-8fc7-3aff7d45f33e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747984109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.747984109
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.1865098138
Short name T757
Test name
Test status
Simulation time 13297520963 ps
CPU time 625.41 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:27:36 PM PST 24
Peak memory 247556 kb
Host smart-66bb779e-cefb-4311-ac9c-866ff513e9a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1865098138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.1865098138
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.2388816648
Short name T331
Test name
Test status
Simulation time 216451007972 ps
CPU time 1468.47 seconds
Started Jan 07 01:17:13 PM PST 24
Finished Jan 07 01:41:43 PM PST 24
Peak memory 231668 kb
Host smart-371cef1a-d372-477e-9b7e-4f266ab02932
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388816648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.2388816648
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.670483944
Short name T649
Test name
Test status
Simulation time 162524431755 ps
CPU time 1227.76 seconds
Started Jan 07 01:17:06 PM PST 24
Finished Jan 07 01:37:35 PM PST 24
Peak memory 256316 kb
Host smart-33fe1e4d-a4a5-4eec-bcb1-25c506bf411c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670483944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.670483944
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.1238111184
Short name T347
Test name
Test status
Simulation time 336511566602 ps
CPU time 2902.65 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 02:05:32 PM PST 24
Peak memory 262772 kb
Host smart-55f85965-85b4-41cf-b351-7abe811996b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238111184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.1238111184
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.4237564035
Short name T479
Test name
Test status
Simulation time 493578178733 ps
CPU time 4472.34 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 02:31:43 PM PST 24
Peak memory 255508 kb
Host smart-802a154c-7091-4328-a8b3-9a3e76f282e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237564035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.4237564035
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.409610932
Short name T115
Test name
Test status
Simulation time 44573218513 ps
CPU time 2092.91 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:52:06 PM PST 24
Peak memory 247236 kb
Host smart-a4a6394c-3fb2-4932-8258-dfd213ac61f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409610932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.409610932
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.3509246146
Short name T108
Test name
Test status
Simulation time 420560716864 ps
CPU time 3279.98 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 02:11:54 PM PST 24
Peak memory 248044 kb
Host smart-217b9a77-7e2e-4d92-914a-ff006685b55e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509246146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.3509246146
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.355508366
Short name T570
Test name
Test status
Simulation time 34343291526 ps
CPU time 653.51 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:28:06 PM PST 24
Peak memory 226488 kb
Host smart-589a513b-c0b2-4c05-9a2b-66371a40c369
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355508366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.355508366
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.421315109
Short name T431
Test name
Test status
Simulation time 72056884711 ps
CPU time 1309.37 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 01:38:59 PM PST 24
Peak memory 236744 kb
Host smart-6c819d90-fedb-4742-bbe4-2473e2fd1302
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421315109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.421315109
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3428360752
Short name T269
Test name
Test status
Simulation time 19141873 ps
CPU time 0.63 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:14:54 PM PST 24
Peak memory 193148 kb
Host smart-7d115b2a-bdf9-4dfb-80cd-d24ddeb858a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428360752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3428360752
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2692866950
Short name T410
Test name
Test status
Simulation time 2218367841 ps
CPU time 18 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:15:10 PM PST 24
Peak memory 217248 kb
Host smart-250b29c5-fbd2-4d6a-b2a7-36d9f1776abf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692866950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2692866950
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1158376907
Short name T207
Test name
Test status
Simulation time 1134763341 ps
CPU time 16.05 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:15:09 PM PST 24
Peak memory 198592 kb
Host smart-38068c1c-8606-44a8-a41d-c370c78bfd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158376907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1158376907
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3697875847
Short name T280
Test name
Test status
Simulation time 11569356380 ps
CPU time 131.99 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:17:05 PM PST 24
Peak memory 198868 kb
Host smart-d849f47d-ed5e-4f82-8032-c8430da06a54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3697875847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3697875847
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.4054138400
Short name T319
Test name
Test status
Simulation time 29362854568 ps
CPU time 94.76 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:16:27 PM PST 24
Peak memory 198756 kb
Host smart-e6dac932-ca20-4535-9268-933c7af767fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054138400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.4054138400
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.458986174
Short name T818
Test name
Test status
Simulation time 25251834004 ps
CPU time 55.88 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:15:48 PM PST 24
Peak memory 198856 kb
Host smart-885f16c0-d08c-430e-ba7c-4a9668a286db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458986174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.458986174
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3808713092
Short name T430
Test name
Test status
Simulation time 46366086 ps
CPU time 0.94 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:14:53 PM PST 24
Peak memory 196804 kb
Host smart-a98ccab4-00d7-4500-b501-a475b5b01a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808713092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3808713092
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.881565670
Short name T517
Test name
Test status
Simulation time 31506053159 ps
CPU time 140.11 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:17:12 PM PST 24
Peak memory 198708 kb
Host smart-08838b49-319c-46f5-994a-95811242b317
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881565670 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.881565670
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.1524379257
Short name T127
Test name
Test status
Simulation time 206391110804 ps
CPU time 879.78 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:29:32 PM PST 24
Peak memory 237820 kb
Host smart-d947cd7f-1c92-4787-b862-8f95e436eeac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524379257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.1524379257
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.4294631401
Short name T375
Test name
Test status
Simulation time 40035273 ps
CPU time 0.95 seconds
Started Jan 07 01:14:47 PM PST 24
Finished Jan 07 01:14:51 PM PST 24
Peak memory 196344 kb
Host smart-51cac4bd-7f19-4322-a1b3-2af26b4c4e1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294631401 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.4294631401
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1657144665
Short name T800
Test name
Test status
Simulation time 12827557385 ps
CPU time 433.25 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:22:05 PM PST 24
Peak memory 198744 kb
Host smart-9fd0c432-cbfd-46fa-8f10-02a3e8d6df38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657144665 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_sha_vectors.1657144665
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2415815653
Short name T368
Test name
Test status
Simulation time 825657676 ps
CPU time 35.57 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:15:27 PM PST 24
Peak memory 198704 kb
Host smart-b96c7379-7fe8-4579-b20c-ecbf25063b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415815653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2415815653
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.382709354
Short name T325
Test name
Test status
Simulation time 193551492513 ps
CPU time 2136.47 seconds
Started Jan 07 01:17:07 PM PST 24
Finished Jan 07 01:52:45 PM PST 24
Peak memory 248056 kb
Host smart-886bb70d-ae5c-4e5b-9392-212c238bfd92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382709354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.382709354
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.2836899171
Short name T4
Test name
Test status
Simulation time 373624843129 ps
CPU time 465.48 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:24:57 PM PST 24
Peak memory 250168 kb
Host smart-f1da6b58-f97d-43f6-aea9-fda75d9de416
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2836899171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.2836899171
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.748248793
Short name T536
Test name
Test status
Simulation time 228456629270 ps
CPU time 880.35 seconds
Started Jan 07 01:17:07 PM PST 24
Finished Jan 07 01:31:48 PM PST 24
Peak memory 245964 kb
Host smart-fffaee34-8365-4f4c-ac43-d36272d1c5db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748248793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.748248793
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.775658250
Short name T98
Test name
Test status
Simulation time 180789115396 ps
CPU time 4197.44 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 02:27:10 PM PST 24
Peak memory 259448 kb
Host smart-8209e071-e6be-41fe-affe-8aee4af7612e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775658250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.775658250
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.2407565435
Short name T455
Test name
Test status
Simulation time 34251839798 ps
CPU time 839.46 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:31:13 PM PST 24
Peak memory 215280 kb
Host smart-19cd7689-276e-4384-81f9-04cf060b9e50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407565435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.2407565435
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.2958164517
Short name T288
Test name
Test status
Simulation time 44887485889 ps
CPU time 865.29 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 01:31:35 PM PST 24
Peak memory 236152 kb
Host smart-7b0732ee-854f-4b9f-8452-065ffaead938
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958164517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.2958164517
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.2158564825
Short name T527
Test name
Test status
Simulation time 29320153240 ps
CPU time 443.39 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:24:36 PM PST 24
Peak memory 215036 kb
Host smart-187f5d9b-aad5-4b0a-96ac-91a0fe2fde05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158564825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.2158564825
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.390940048
Short name T228
Test name
Test status
Simulation time 27469000712 ps
CPU time 259.53 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 01:21:30 PM PST 24
Peak memory 198908 kb
Host smart-ab98d021-154d-42d1-a149-45ed620aaf69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390940048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.390940048
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.1314566300
Short name T380
Test name
Test status
Simulation time 19636003785 ps
CPU time 301.08 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 01:22:11 PM PST 24
Peak memory 215268 kb
Host smart-bae1a50c-093a-453c-b9fe-85025c43be67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314566300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.1314566300
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.3439974484
Short name T572
Test name
Test status
Simulation time 276249575082 ps
CPU time 1270.85 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 01:38:20 PM PST 24
Peak memory 248124 kb
Host smart-ed33f241-2c4a-4bed-8076-63a9b7f6768f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439974484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.3439974484
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.170108125
Short name T446
Test name
Test status
Simulation time 14052886 ps
CPU time 0.56 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:14:52 PM PST 24
Peak memory 193124 kb
Host smart-ef12c25f-a98c-43db-8171-f4f2617c700e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170108125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.170108125
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2226416259
Short name T612
Test name
Test status
Simulation time 3185144843 ps
CPU time 29.05 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:15:21 PM PST 24
Peak memory 231604 kb
Host smart-4e993578-d86b-4638-9403-914c6364eef9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226416259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2226416259
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.388127001
Short name T566
Test name
Test status
Simulation time 3234079010 ps
CPU time 36.64 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:15:29 PM PST 24
Peak memory 198820 kb
Host smart-b180b5d0-48a5-4ebf-b995-598f554e8401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388127001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.388127001
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2606853771
Short name T658
Test name
Test status
Simulation time 692783406 ps
CPU time 35.96 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:15:29 PM PST 24
Peak memory 198748 kb
Host smart-d3e72f7b-c5a0-426a-8227-1c18fd744673
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606853771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2606853771
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2684005992
Short name T511
Test name
Test status
Simulation time 3704808476 ps
CPU time 49.5 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:15:42 PM PST 24
Peak memory 198840 kb
Host smart-065d05ef-f70b-433b-b089-20c0340af3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684005992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2684005992
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.4256815040
Short name T778
Test name
Test status
Simulation time 1787960324 ps
CPU time 47.06 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:15:40 PM PST 24
Peak memory 198732 kb
Host smart-e1a9f43a-f5e2-4419-a07d-dc0cba095263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256815040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4256815040
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3404031735
Short name T332
Test name
Test status
Simulation time 43482911 ps
CPU time 1.26 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:14:53 PM PST 24
Peak memory 198064 kb
Host smart-9216762e-1ce4-45cb-a7d1-978857f6290f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404031735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3404031735
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.107959199
Short name T96
Test name
Test status
Simulation time 78366696179 ps
CPU time 509.05 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:23:22 PM PST 24
Peak memory 198856 kb
Host smart-81c7c714-51c9-4717-9d0e-0cc8c6d6e0db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107959199 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.107959199
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.4190187874
Short name T415
Test name
Test status
Simulation time 129688486541 ps
CPU time 915.72 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:30:09 PM PST 24
Peak memory 223516 kb
Host smart-449ad8a8-9129-4c4d-b462-a845ca63e769
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190187874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.4190187874
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.1908808188
Short name T445
Test name
Test status
Simulation time 25981435 ps
CPU time 0.88 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:14:53 PM PST 24
Peak memory 195728 kb
Host smart-358a050e-4e7b-490a-aeba-723f69f994e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908808188 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.1908808188
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1615285302
Short name T726
Test name
Test status
Simulation time 23971159157 ps
CPU time 330.72 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:20:24 PM PST 24
Peak memory 198800 kb
Host smart-978c742e-9987-4706-93d4-ba0016688b8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615285302 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.1615285302
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1657763388
Short name T189
Test name
Test status
Simulation time 1925677334 ps
CPU time 11.21 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:15:03 PM PST 24
Peak memory 198728 kb
Host smart-8f8a3762-45c7-4d7c-a097-96782016b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657763388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1657763388
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.764916023
Short name T537
Test name
Test status
Simulation time 34306529796 ps
CPU time 329.34 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:22:40 PM PST 24
Peak memory 214908 kb
Host smart-fefce2d6-09a7-4049-ab82-c63bf29abac6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764916023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.764916023
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.223081996
Short name T106
Test name
Test status
Simulation time 45606532195 ps
CPU time 758.07 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:29:49 PM PST 24
Peak memory 244644 kb
Host smart-23b7d8c5-6f86-48c7-b055-d87472acd110
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223081996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.223081996
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.2038400455
Short name T379
Test name
Test status
Simulation time 167101905646 ps
CPU time 1996.73 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:50:31 PM PST 24
Peak memory 215320 kb
Host smart-3d7c52fd-586d-4637-b306-31a5662ff484
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038400455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.2038400455
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.3091795328
Short name T824
Test name
Test status
Simulation time 181942426715 ps
CPU time 1730.59 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:46:04 PM PST 24
Peak memory 225176 kb
Host smart-f9e8f884-70f3-4f4a-b0da-6d162ac14db6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091795328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.3091795328
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.3366370951
Short name T44
Test name
Test status
Simulation time 78056773880 ps
CPU time 969.08 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:33:20 PM PST 24
Peak memory 215212 kb
Host smart-9d127552-b476-4a98-aa81-bda03cc2addd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366370951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.3366370951
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.2904299290
Short name T522
Test name
Test status
Simulation time 379665931130 ps
CPU time 1873.2 seconds
Started Jan 07 01:17:07 PM PST 24
Finished Jan 07 01:48:22 PM PST 24
Peak memory 261592 kb
Host smart-fad20b17-658d-49fe-9727-d8399ef8cd6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904299290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.2904299290
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.1120953090
Short name T678
Test name
Test status
Simulation time 79888524335 ps
CPU time 833.97 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 01:31:04 PM PST 24
Peak memory 239868 kb
Host smart-b8a0ff6f-d8bc-48a4-96ec-f5edb2132e08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120953090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.1120953090
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.3205165520
Short name T589
Test name
Test status
Simulation time 2614840071583 ps
CPU time 2308.7 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 01:55:40 PM PST 24
Peak memory 247692 kb
Host smart-d73c5b0c-c5a5-4759-b7a4-c29fc4860dfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205165520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.3205165520
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.364199407
Short name T196
Test name
Test status
Simulation time 229852371667 ps
CPU time 848.23 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 01:31:17 PM PST 24
Peak memory 245396 kb
Host smart-76de2867-61de-4165-93a1-e6667f7a75c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364199407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.364199407
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.103149972
Short name T717
Test name
Test status
Simulation time 31167036 ps
CPU time 0.55 seconds
Started Jan 07 01:14:54 PM PST 24
Finished Jan 07 01:14:55 PM PST 24
Peak memory 193068 kb
Host smart-8ff26fda-4c37-42a4-9e91-877cb11eb584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103149972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.103149972
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3458814392
Short name T263
Test name
Test status
Simulation time 3400461499 ps
CPU time 55.22 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:15:48 PM PST 24
Peak memory 231536 kb
Host smart-ee659779-ac33-4c16-b395-0499714f4c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458814392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3458814392
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2162033078
Short name T391
Test name
Test status
Simulation time 7970468272 ps
CPU time 36.42 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:15:29 PM PST 24
Peak memory 198792 kb
Host smart-37ee77f2-ea06-4c66-90d9-b06d73557a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162033078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2162033078
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3921320229
Short name T328
Test name
Test status
Simulation time 8125444921 ps
CPU time 102.96 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:16:36 PM PST 24
Peak memory 198780 kb
Host smart-3165ae3e-7239-4f91-8f98-6b82614cf10b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3921320229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3921320229
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2204398975
Short name T764
Test name
Test status
Simulation time 268129223 ps
CPU time 2.39 seconds
Started Jan 07 01:14:52 PM PST 24
Finished Jan 07 01:14:56 PM PST 24
Peak memory 198652 kb
Host smart-a29239d6-d5de-4db6-954c-d81f6c9a2d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204398975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2204398975
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3046239395
Short name T675
Test name
Test status
Simulation time 3639577506 ps
CPU time 66.22 seconds
Started Jan 07 01:14:49 PM PST 24
Finished Jan 07 01:15:59 PM PST 24
Peak memory 198840 kb
Host smart-a85dcf50-6f77-4b25-af66-ed62ae9337c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046239395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3046239395
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1607818578
Short name T611
Test name
Test status
Simulation time 1282256533 ps
CPU time 3.54 seconds
Started Jan 07 01:14:51 PM PST 24
Finished Jan 07 01:14:57 PM PST 24
Peak memory 198336 kb
Host smart-deb5f12f-b9ad-486b-bf12-a5ee65df257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607818578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1607818578
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3894651053
Short name T749
Test name
Test status
Simulation time 41658619250 ps
CPU time 1765.26 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:44:18 PM PST 24
Peak memory 234676 kb
Host smart-aca18c05-3789-4c89-a8c7-2f73fd606d0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894651053 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3894651053
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.1658610682
Short name T39
Test name
Test status
Simulation time 61273459059 ps
CPU time 2081.68 seconds
Started Jan 07 01:14:54 PM PST 24
Finished Jan 07 01:49:37 PM PST 24
Peak memory 246952 kb
Host smart-eea1e543-4985-4948-a211-7a39255a9830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1658610682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.1658610682
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3275564963
Short name T462
Test name
Test status
Simulation time 192017373 ps
CPU time 1.11 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:14:53 PM PST 24
Peak memory 196876 kb
Host smart-b3e4af98-9802-4380-8440-07da8d3099ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275564963 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.3275564963
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3759639887
Short name T166
Test name
Test status
Simulation time 94953870084 ps
CPU time 505.72 seconds
Started Jan 07 01:14:54 PM PST 24
Finished Jan 07 01:23:20 PM PST 24
Peak memory 198796 kb
Host smart-cddef796-51f9-467e-b46c-1afb307e92d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759639887 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.3759639887
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.108190477
Short name T227
Test name
Test status
Simulation time 4130672412 ps
CPU time 79.63 seconds
Started Jan 07 01:14:50 PM PST 24
Finished Jan 07 01:16:13 PM PST 24
Peak memory 198844 kb
Host smart-4fd4b58c-c451-4420-a180-baf7dd1c746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108190477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.108190477
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.3498755329
Short name T88
Test name
Test status
Simulation time 133943595466 ps
CPU time 2651.71 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 02:01:22 PM PST 24
Peak memory 256288 kb
Host smart-7267bcc6-cf57-4f73-a95a-b28f4633ae49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498755329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.3498755329
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.806339743
Short name T534
Test name
Test status
Simulation time 2456107918963 ps
CPU time 2315.57 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:55:48 PM PST 24
Peak memory 252376 kb
Host smart-810af70d-3719-482e-961b-61b532a8e4ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806339743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.806339743
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.1304198837
Short name T237
Test name
Test status
Simulation time 46301168187 ps
CPU time 799.31 seconds
Started Jan 07 01:17:07 PM PST 24
Finished Jan 07 01:30:28 PM PST 24
Peak memory 239736 kb
Host smart-6fe359ee-c22a-40d4-9599-7534cd5ecd42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1304198837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.1304198837
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.44209940
Short name T646
Test name
Test status
Simulation time 298742309706 ps
CPU time 1216.43 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:37:28 PM PST 24
Peak memory 246416 kb
Host smart-736d23b4-d0c9-4075-a441-fcb964fb6b37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44209940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.44209940
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.1642931769
Short name T345
Test name
Test status
Simulation time 72285923361 ps
CPU time 1093.11 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 01:35:23 PM PST 24
Peak memory 241832 kb
Host smart-3a615a4a-8f26-448a-ad91-e96f3f2c0a81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642931769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.1642931769
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.3531754073
Short name T804
Test name
Test status
Simulation time 95105331139 ps
CPU time 2325.08 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:55:58 PM PST 24
Peak memory 225484 kb
Host smart-277c94b0-623f-423b-afeb-716ff1cd42e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531754073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.3531754073
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.3903663354
Short name T298
Test name
Test status
Simulation time 169932075793 ps
CPU time 646.09 seconds
Started Jan 07 01:17:13 PM PST 24
Finished Jan 07 01:28:00 PM PST 24
Peak memory 244004 kb
Host smart-58bd826b-f62d-4195-a94f-b23cb1cacf13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903663354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.3903663354
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.424764805
Short name T107
Test name
Test status
Simulation time 221263285752 ps
CPU time 3854.12 seconds
Started Jan 07 01:17:08 PM PST 24
Finished Jan 07 02:21:24 PM PST 24
Peak memory 240880 kb
Host smart-2f4056e5-f0c2-49c1-91aa-64e9820e3fdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424764805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.424764805
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.4176905726
Short name T89
Test name
Test status
Simulation time 372363337252 ps
CPU time 1224.24 seconds
Started Jan 07 01:17:20 PM PST 24
Finished Jan 07 01:37:46 PM PST 24
Peak memory 250304 kb
Host smart-924f6a98-2371-405e-acc1-87fc85a2f09a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4176905726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.4176905726
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2576217007
Short name T753
Test name
Test status
Simulation time 14506623 ps
CPU time 0.59 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:13:43 PM PST 24
Peak memory 193140 kb
Host smart-fc57a397-1a7d-4c1a-9cb9-99a36847643b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576217007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2576217007
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2867370317
Short name T434
Test name
Test status
Simulation time 547238889 ps
CPU time 4.41 seconds
Started Jan 07 01:13:40 PM PST 24
Finished Jan 07 01:13:46 PM PST 24
Peak memory 198652 kb
Host smart-04227cd4-bb74-4608-b40d-5267b38bfafc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2867370317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2867370317
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1316325050
Short name T807
Test name
Test status
Simulation time 917980285 ps
CPU time 42.71 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:14:27 PM PST 24
Peak memory 198580 kb
Host smart-39113269-3b51-4ac4-baa8-0f0badb8c258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316325050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1316325050
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2056492032
Short name T178
Test name
Test status
Simulation time 633663129 ps
CPU time 7.52 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:13:49 PM PST 24
Peak memory 198572 kb
Host smart-eb0a921b-bca8-4894-9bd7-8f42c130f25f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056492032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2056492032
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1808304720
Short name T586
Test name
Test status
Simulation time 34137967 ps
CPU time 0.67 seconds
Started Jan 07 01:13:40 PM PST 24
Finished Jan 07 01:13:42 PM PST 24
Peak memory 193800 kb
Host smart-066eb63c-4d4c-4836-ba61-864fb3d5d5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808304720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1808304720
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2719713423
Short name T11
Test name
Test status
Simulation time 8974320874 ps
CPU time 55.8 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:14:39 PM PST 24
Peak memory 198792 kb
Host smart-1c35d486-0951-4ab0-badb-a6042fbdf23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719713423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2719713423
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.1425499507
Short name T821
Test name
Test status
Simulation time 316134006 ps
CPU time 3.52 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:13:47 PM PST 24
Peak memory 198660 kb
Host smart-4f52fc02-5dec-4dca-9ecb-fea4431e5fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425499507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1425499507
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3008992432
Short name T530
Test name
Test status
Simulation time 3367922038 ps
CPU time 44.29 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:14:27 PM PST 24
Peak memory 198764 kb
Host smart-2f3d6717-8738-4dc1-ae21-24868971f018
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008992432 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3008992432
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1568836655
Short name T676
Test name
Test status
Simulation time 121368129 ps
CPU time 1.11 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:13:45 PM PST 24
Peak memory 196752 kb
Host smart-7fcc99d7-d638-4d65-92e6-a9683c4ff169
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568836655 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1568836655
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.1787360551
Short name T467
Test name
Test status
Simulation time 80703182762 ps
CPU time 445.89 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:21:10 PM PST 24
Peak memory 198864 kb
Host smart-36b3b81a-5d28-479b-a047-0be691ff1b97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787360551 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.1787360551
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.97259599
Short name T567
Test name
Test status
Simulation time 6027476099 ps
CPU time 71.59 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:14:54 PM PST 24
Peak memory 198844 kb
Host smart-2e8ad7d8-7fa2-4a0b-a450-9aca8e3f2e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97259599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.97259599
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2699231317
Short name T483
Test name
Test status
Simulation time 12767545 ps
CPU time 0.55 seconds
Started Jan 07 01:15:02 PM PST 24
Finished Jan 07 01:15:05 PM PST 24
Peak memory 193044 kb
Host smart-2638edb8-4295-4e71-9f86-c0c863347187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699231317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2699231317
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1093658650
Short name T8
Test name
Test status
Simulation time 1741130235 ps
CPU time 56.42 seconds
Started Jan 07 01:14:55 PM PST 24
Finished Jan 07 01:15:52 PM PST 24
Peak memory 215032 kb
Host smart-76f2c8ce-f325-44b8-9a08-35b697880ac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093658650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1093658650
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2129116540
Short name T173
Test name
Test status
Simulation time 560925670 ps
CPU time 25.19 seconds
Started Jan 07 01:14:51 PM PST 24
Finished Jan 07 01:15:19 PM PST 24
Peak memory 198648 kb
Host smart-ef7c2a12-638f-4143-bbf1-43d2fccc4268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129116540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2129116540
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2776760548
Short name T783
Test name
Test status
Simulation time 3197454310 ps
CPU time 82.69 seconds
Started Jan 07 01:14:55 PM PST 24
Finished Jan 07 01:16:19 PM PST 24
Peak memory 198788 kb
Host smart-29aafc46-de1b-4c65-b6ca-aa8eb680a296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776760548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2776760548
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3170336270
Short name T563
Test name
Test status
Simulation time 5183631182 ps
CPU time 7.58 seconds
Started Jan 07 01:15:08 PM PST 24
Finished Jan 07 01:15:17 PM PST 24
Peak memory 198864 kb
Host smart-5e360e32-d226-4103-b911-57a0945620a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170336270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3170336270
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2663158726
Short name T354
Test name
Test status
Simulation time 1801801521 ps
CPU time 17.05 seconds
Started Jan 07 01:14:55 PM PST 24
Finished Jan 07 01:15:13 PM PST 24
Peak memory 198704 kb
Host smart-16831616-7e15-40b3-9d58-ec3313f5cf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663158726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2663158726
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3443257460
Short name T416
Test name
Test status
Simulation time 254039367 ps
CPU time 2.42 seconds
Started Jan 07 01:14:54 PM PST 24
Finished Jan 07 01:14:57 PM PST 24
Peak memory 198712 kb
Host smart-95b2435e-90db-443d-a238-ae7746a20479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443257460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3443257460
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3209707396
Short name T340
Test name
Test status
Simulation time 334271368425 ps
CPU time 1332.99 seconds
Started Jan 07 01:14:59 PM PST 24
Finished Jan 07 01:37:12 PM PST 24
Peak memory 198872 kb
Host smart-cd41ccc5-7cd6-44b1-900f-2ef39137a819
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209707396 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3209707396
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.1520021706
Short name T510
Test name
Test status
Simulation time 37054441041 ps
CPU time 700.32 seconds
Started Jan 07 01:15:07 PM PST 24
Finished Jan 07 01:26:49 PM PST 24
Peak memory 222052 kb
Host smart-92dc4273-20db-43a7-aef3-a0aed63806f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520021706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.1520021706
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1659716355
Short name T292
Test name
Test status
Simulation time 50379736 ps
CPU time 0.96 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:15:02 PM PST 24
Peak memory 195824 kb
Host smart-4895b2c5-92e7-4a1d-ac5f-02a84241a2f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659716355 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1659716355
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2879656518
Short name T744
Test name
Test status
Simulation time 38719786719 ps
CPU time 472.56 seconds
Started Jan 07 01:14:58 PM PST 24
Finished Jan 07 01:22:52 PM PST 24
Peak memory 198776 kb
Host smart-083ff958-7b39-4d69-b027-af9dc42b2250
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879656518 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.2879656518
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3104746217
Short name T402
Test name
Test status
Simulation time 3458079535 ps
CPU time 45.78 seconds
Started Jan 07 01:14:59 PM PST 24
Finished Jan 07 01:15:45 PM PST 24
Peak memory 198792 kb
Host smart-cb4938f1-8ef5-45c6-96e6-6a464050f8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104746217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3104746217
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2583957814
Short name T221
Test name
Test status
Simulation time 19411232 ps
CPU time 0.55 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:15:01 PM PST 24
Peak memory 193116 kb
Host smart-3d2c1096-4cf2-473e-ae13-2634e2aceb45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583957814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2583957814
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3083212813
Short name T208
Test name
Test status
Simulation time 1722639583 ps
CPU time 15.74 seconds
Started Jan 07 01:14:59 PM PST 24
Finished Jan 07 01:15:16 PM PST 24
Peak memory 224736 kb
Host smart-f8a2ef09-9ad9-4fac-bcdb-66a8614c7ab7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083212813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3083212813
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4294836957
Short name T587
Test name
Test status
Simulation time 3114762264 ps
CPU time 70.47 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:16:12 PM PST 24
Peak memory 198836 kb
Host smart-6230d675-4a46-40e7-a253-b7ec6fd305a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294836957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4294836957
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1595922043
Short name T713
Test name
Test status
Simulation time 1772595180 ps
CPU time 87.27 seconds
Started Jan 07 01:15:08 PM PST 24
Finished Jan 07 01:16:36 PM PST 24
Peak memory 198708 kb
Host smart-c65c4c39-8d67-41e5-8799-befe8188c698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595922043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1595922043
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.8814448
Short name T679
Test name
Test status
Simulation time 4896618955 ps
CPU time 114.72 seconds
Started Jan 07 01:15:02 PM PST 24
Finished Jan 07 01:17:00 PM PST 24
Peak memory 198756 kb
Host smart-67afe3c6-fdfd-4d66-a84b-9cd6e71cb839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8814448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.8814448
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.74301423
Short name T361
Test name
Test status
Simulation time 20857648581 ps
CPU time 49.8 seconds
Started Jan 07 01:14:59 PM PST 24
Finished Jan 07 01:15:50 PM PST 24
Peak memory 198824 kb
Host smart-78b2b424-e431-438d-bd00-35d55f27312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74301423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.74301423
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.662173617
Short name T529
Test name
Test status
Simulation time 54616155 ps
CPU time 1.15 seconds
Started Jan 07 01:15:03 PM PST 24
Finished Jan 07 01:15:06 PM PST 24
Peak memory 197944 kb
Host smart-3d6d0539-8ab3-4d8e-a27e-1281fd6b4944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662173617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.662173617
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.137398653
Short name T63
Test name
Test status
Simulation time 31583447702 ps
CPU time 531.36 seconds
Started Jan 07 01:15:09 PM PST 24
Finished Jan 07 01:24:01 PM PST 24
Peak memory 198888 kb
Host smart-caf040d3-575f-4bc8-a253-b69bcd1125f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137398653 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.137398653
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.2969769214
Short name T382
Test name
Test status
Simulation time 28060201595 ps
CPU time 216.76 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:18:38 PM PST 24
Peak memory 247112 kb
Host smart-c374b49e-3254-4a45-bd98-ef90c36a6a07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969769214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.2969769214
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1854780123
Short name T740
Test name
Test status
Simulation time 31879311 ps
CPU time 1.16 seconds
Started Jan 07 01:15:01 PM PST 24
Finished Jan 07 01:15:04 PM PST 24
Peak memory 197384 kb
Host smart-318a4013-e4b5-4a0f-97d2-b8dbdfad8b45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854780123 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1854780123
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3453761436
Short name T576
Test name
Test status
Simulation time 121827208728 ps
CPU time 456.01 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:22:38 PM PST 24
Peak memory 198820 kb
Host smart-67bffce4-db11-4cea-b0c4-f29a2efbc50d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453761436 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.3453761436
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3103139754
Short name T362
Test name
Test status
Simulation time 7558777925 ps
CPU time 67.92 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:16:10 PM PST 24
Peak memory 198820 kb
Host smart-d842e304-0bb5-4135-986b-2552c8784aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103139754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3103139754
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3619578243
Short name T792
Test name
Test status
Simulation time 36928730 ps
CPU time 0.56 seconds
Started Jan 07 01:15:02 PM PST 24
Finished Jan 07 01:15:05 PM PST 24
Peak memory 192964 kb
Host smart-2ba8ba44-7ca3-499d-a922-94620015a276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619578243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3619578243
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3564418081
Short name T571
Test name
Test status
Simulation time 1162099857 ps
CPU time 3.91 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:15:06 PM PST 24
Peak memory 198568 kb
Host smart-2450c253-73bf-4a98-9fa6-e9772540b961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564418081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3564418081
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2169046269
Short name T602
Test name
Test status
Simulation time 1741770503 ps
CPU time 41.29 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:15:43 PM PST 24
Peak memory 198648 kb
Host smart-c298d0bc-aed3-405d-a4b7-ecde2671b095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169046269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2169046269
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2278422187
Short name T564
Test name
Test status
Simulation time 5633809444 ps
CPU time 61.13 seconds
Started Jan 07 01:15:01 PM PST 24
Finished Jan 07 01:16:04 PM PST 24
Peak memory 198860 kb
Host smart-eee91e6b-4463-42fd-848c-49e2a28651af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2278422187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2278422187
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2591949993
Short name T786
Test name
Test status
Simulation time 33631578435 ps
CPU time 134.16 seconds
Started Jan 07 01:14:58 PM PST 24
Finished Jan 07 01:17:13 PM PST 24
Peak memory 198812 kb
Host smart-e11771a4-ea7b-4ad7-a706-118a464d99ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591949993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2591949993
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3109459294
Short name T575
Test name
Test status
Simulation time 507493595 ps
CPU time 25.89 seconds
Started Jan 07 01:15:05 PM PST 24
Finished Jan 07 01:15:32 PM PST 24
Peak memory 198600 kb
Host smart-7c0846a7-6acb-4fcd-9dbd-5b8ea5955269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109459294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3109459294
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3956027357
Short name T241
Test name
Test status
Simulation time 106077314 ps
CPU time 2.8 seconds
Started Jan 07 01:14:58 PM PST 24
Finished Jan 07 01:15:02 PM PST 24
Peak memory 198716 kb
Host smart-028a5827-47fe-4804-b8e7-2b63dc4e5a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956027357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3956027357
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.25706218
Short name T730
Test name
Test status
Simulation time 33865651414 ps
CPU time 297.44 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:19:58 PM PST 24
Peak memory 230828 kb
Host smart-3a7c7589-05d9-4843-915d-34332964565d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25706218 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.25706218
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.3232231246
Short name T291
Test name
Test status
Simulation time 212398864873 ps
CPU time 675.31 seconds
Started Jan 07 01:14:59 PM PST 24
Finished Jan 07 01:26:15 PM PST 24
Peak memory 223408 kb
Host smart-6cc8e4df-10e5-4a74-9d46-14e0d440cf2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3232231246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.3232231246
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2084366163
Short name T683
Test name
Test status
Simulation time 90052773 ps
CPU time 0.86 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:15:03 PM PST 24
Peak memory 195728 kb
Host smart-dd3828b8-3c6e-4649-b60f-1f9eb1bbdce4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084366163 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2084366163
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3714349376
Short name T457
Test name
Test status
Simulation time 25433662497 ps
CPU time 350.6 seconds
Started Jan 07 01:15:03 PM PST 24
Finished Jan 07 01:20:56 PM PST 24
Peak memory 198752 kb
Host smart-c6c98099-4cfc-4999-b6d2-a9555e63005e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714349376 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.3714349376
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.914967668
Short name T397
Test name
Test status
Simulation time 2232256011 ps
CPU time 18.79 seconds
Started Jan 07 01:15:09 PM PST 24
Finished Jan 07 01:15:29 PM PST 24
Peak memory 198816 kb
Host smart-1af5bd3d-d421-41ac-8ed7-5d7055ffb43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914967668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.914967668
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2297439790
Short name T245
Test name
Test status
Simulation time 14257633 ps
CPU time 0.57 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:15:02 PM PST 24
Peak memory 193120 kb
Host smart-a403ae23-e53b-4b78-94f3-b0ee2731f904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297439790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2297439790
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3345511829
Short name T591
Test name
Test status
Simulation time 5075837433 ps
CPU time 21.17 seconds
Started Jan 07 01:15:03 PM PST 24
Finished Jan 07 01:15:27 PM PST 24
Peak memory 225392 kb
Host smart-a45aba72-cd0f-4699-bf43-acc91ab1bc9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345511829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3345511829
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2472727382
Short name T220
Test name
Test status
Simulation time 319966466 ps
CPU time 1.91 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:15:03 PM PST 24
Peak memory 198704 kb
Host smart-72579950-00e1-4237-ab1b-7f8fe7400fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472727382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2472727382
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1653604417
Short name T452
Test name
Test status
Simulation time 973941558 ps
CPU time 49.14 seconds
Started Jan 07 01:14:59 PM PST 24
Finished Jan 07 01:15:50 PM PST 24
Peak memory 198696 kb
Host smart-aab9be24-a2ca-4d7f-9641-7ff1bf485e0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653604417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1653604417
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3260684929
Short name T556
Test name
Test status
Simulation time 771830384 ps
CPU time 38.61 seconds
Started Jan 07 01:15:01 PM PST 24
Finished Jan 07 01:15:41 PM PST 24
Peak memory 198680 kb
Host smart-cf80b3b9-5b17-461e-840e-ea6c7956e345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260684929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3260684929
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4288822871
Short name T502
Test name
Test status
Simulation time 2853545012 ps
CPU time 74.42 seconds
Started Jan 07 01:15:01 PM PST 24
Finished Jan 07 01:16:17 PM PST 24
Peak memory 198800 kb
Host smart-25c007e9-2b4d-4f3e-8b3d-63363160f7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288822871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4288822871
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1795331293
Short name T714
Test name
Test status
Simulation time 327558023 ps
CPU time 2.34 seconds
Started Jan 07 01:15:02 PM PST 24
Finished Jan 07 01:15:07 PM PST 24
Peak memory 198584 kb
Host smart-58aa8fd3-b5e0-4591-9871-2c33cf12cbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795331293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1795331293
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3384558328
Short name T204
Test name
Test status
Simulation time 30967737233 ps
CPU time 96.04 seconds
Started Jan 07 01:15:01 PM PST 24
Finished Jan 07 01:16:38 PM PST 24
Peak memory 198848 kb
Host smart-2a82b7fb-444f-4a57-b056-f13af220aadf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384558328 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3384558328
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.1134055331
Short name T751
Test name
Test status
Simulation time 14333192617 ps
CPU time 127 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:17:08 PM PST 24
Peak memory 240892 kb
Host smart-e9209a59-951a-48aa-aa6a-f36c18d13a02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134055331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.1134055331
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1164843679
Short name T172
Test name
Test status
Simulation time 106053910 ps
CPU time 1.04 seconds
Started Jan 07 01:15:01 PM PST 24
Finished Jan 07 01:15:04 PM PST 24
Peak memory 197276 kb
Host smart-f243ae8c-3b46-49db-8315-8df04d164831
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164843679 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1164843679
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.2557408439
Short name T374
Test name
Test status
Simulation time 59445111059 ps
CPU time 436.52 seconds
Started Jan 07 01:15:01 PM PST 24
Finished Jan 07 01:22:20 PM PST 24
Peak memory 198828 kb
Host smart-b8430aa7-7fa0-404c-b8c5-7c3bfb61544d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557408439 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.2557408439
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3542547659
Short name T662
Test name
Test status
Simulation time 24021997283 ps
CPU time 72.6 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:16:14 PM PST 24
Peak memory 198852 kb
Host smart-cf52e72f-3cc5-415a-b0cb-96b411083a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542547659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3542547659
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1246620566
Short name T290
Test name
Test status
Simulation time 70256774 ps
CPU time 0.59 seconds
Started Jan 07 01:15:02 PM PST 24
Finished Jan 07 01:15:06 PM PST 24
Peak memory 193196 kb
Host smart-18eaeaa3-10bc-4227-9a01-7da78c213612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246620566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1246620566
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1751557570
Short name T278
Test name
Test status
Simulation time 2219927713 ps
CPU time 29.43 seconds
Started Jan 07 01:15:08 PM PST 24
Finished Jan 07 01:15:39 PM PST 24
Peak memory 207004 kb
Host smart-8ac6f350-08e2-440f-91ba-ef20157fd02f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751557570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1751557570
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2909191603
Short name T47
Test name
Test status
Simulation time 2619391435 ps
CPU time 25.66 seconds
Started Jan 07 01:14:59 PM PST 24
Finished Jan 07 01:15:26 PM PST 24
Peak memory 198848 kb
Host smart-89b6145e-e917-428a-b40e-73269bd6b617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909191603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2909191603
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.489071346
Short name T284
Test name
Test status
Simulation time 1274773481 ps
CPU time 61.5 seconds
Started Jan 07 01:15:00 PM PST 24
Finished Jan 07 01:16:03 PM PST 24
Peak memory 198696 kb
Host smart-e32c51e5-6f8d-4d5e-9287-8d86c20be9ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=489071346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.489071346
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3220501607
Short name T594
Test name
Test status
Simulation time 3291940461 ps
CPU time 160.73 seconds
Started Jan 07 01:15:08 PM PST 24
Finished Jan 07 01:17:50 PM PST 24
Peak memory 198840 kb
Host smart-a24a2da8-b950-4a79-ac97-e5de3d55a527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220501607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3220501607
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3451609597
Short name T642
Test name
Test status
Simulation time 6316284113 ps
CPU time 73.42 seconds
Started Jan 07 01:15:02 PM PST 24
Finished Jan 07 01:16:18 PM PST 24
Peak memory 198780 kb
Host smart-b8d41627-b89d-495c-b2d6-5e4906f98e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451609597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3451609597
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3527192455
Short name T248
Test name
Test status
Simulation time 223047696 ps
CPU time 2.48 seconds
Started Jan 07 01:15:03 PM PST 24
Finished Jan 07 01:15:08 PM PST 24
Peak memory 198556 kb
Host smart-f33fb273-b13b-42d3-97d2-bd070ab7bdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527192455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3527192455
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1508292110
Short name T657
Test name
Test status
Simulation time 35277421898 ps
CPU time 1616.39 seconds
Started Jan 07 01:15:02 PM PST 24
Finished Jan 07 01:42:01 PM PST 24
Peak memory 239136 kb
Host smart-3079b116-807d-420b-a826-94d5820dd212
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508292110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1508292110
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.2390905439
Short name T582
Test name
Test status
Simulation time 303194071409 ps
CPU time 1577.86 seconds
Started Jan 07 01:15:04 PM PST 24
Finished Jan 07 01:41:24 PM PST 24
Peak memory 225208 kb
Host smart-2c5b8661-0d5b-49c2-9672-c3de365afb41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2390905439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.2390905439
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2115060361
Short name T607
Test name
Test status
Simulation time 48178656 ps
CPU time 0.93 seconds
Started Jan 07 01:15:05 PM PST 24
Finished Jan 07 01:15:07 PM PST 24
Peak memory 195960 kb
Host smart-4c9908af-12f4-4091-abe8-385e082d5c91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115060361 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2115060361
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2189820574
Short name T211
Test name
Test status
Simulation time 14903705158 ps
CPU time 409.04 seconds
Started Jan 07 01:15:05 PM PST 24
Finished Jan 07 01:21:55 PM PST 24
Peak memory 198748 kb
Host smart-897f6def-55cd-449e-a88d-54ee78adbb15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189820574 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.2189820574
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3340194603
Short name T606
Test name
Test status
Simulation time 22666265434 ps
CPU time 82.6 seconds
Started Jan 07 01:15:04 PM PST 24
Finished Jan 07 01:16:28 PM PST 24
Peak memory 198852 kb
Host smart-e8b06822-0a2d-4b00-ba4a-ea12ae591f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340194603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3340194603
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2715161535
Short name T229
Test name
Test status
Simulation time 11200496 ps
CPU time 0.57 seconds
Started Jan 07 01:15:11 PM PST 24
Finished Jan 07 01:15:12 PM PST 24
Peak memory 193032 kb
Host smart-e2840e9c-21e8-458d-97e7-3f504b4d8322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715161535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2715161535
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1014275601
Short name T9
Test name
Test status
Simulation time 250319713 ps
CPU time 1.3 seconds
Started Jan 07 01:15:05 PM PST 24
Finished Jan 07 01:15:07 PM PST 24
Peak memory 198792 kb
Host smart-1bea25b2-9bad-4f75-8ec9-db5955b81671
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014275601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1014275601
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3803030060
Short name T296
Test name
Test status
Simulation time 623088644 ps
CPU time 9.11 seconds
Started Jan 07 01:15:04 PM PST 24
Finished Jan 07 01:15:15 PM PST 24
Peak memory 198748 kb
Host smart-dcdf6756-72a5-4fc2-8749-4f60fde6ff00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803030060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3803030060
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.4231766719
Short name T588
Test name
Test status
Simulation time 1683125533 ps
CPU time 44.95 seconds
Started Jan 07 01:15:02 PM PST 24
Finished Jan 07 01:15:50 PM PST 24
Peak memory 198680 kb
Host smart-fc47bc25-b850-4ecd-b5d9-550cba54c0a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231766719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.4231766719
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.763518859
Short name T216
Test name
Test status
Simulation time 3874028937 ps
CPU time 45.28 seconds
Started Jan 07 01:15:13 PM PST 24
Finished Jan 07 01:15:59 PM PST 24
Peak memory 198768 kb
Host smart-b5786d9f-9c04-4dc6-9a03-8337f4fdf308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763518859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.763518859
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3275480785
Short name T762
Test name
Test status
Simulation time 4869592375 ps
CPU time 81.52 seconds
Started Jan 07 01:15:03 PM PST 24
Finished Jan 07 01:16:27 PM PST 24
Peak memory 198848 kb
Host smart-604d1cfc-f7aa-447d-a9da-6feeb2dab676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275480785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3275480785
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1077782495
Short name T315
Test name
Test status
Simulation time 501854795 ps
CPU time 2.04 seconds
Started Jan 07 01:15:03 PM PST 24
Finished Jan 07 01:15:08 PM PST 24
Peak memory 198300 kb
Host smart-a8fe0ced-6f0d-40ed-95f9-9ec1640dc22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077782495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1077782495
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.547841145
Short name T116
Test name
Test status
Simulation time 446578407854 ps
CPU time 1289.09 seconds
Started Jan 07 01:15:09 PM PST 24
Finished Jan 07 01:36:40 PM PST 24
Peak memory 198808 kb
Host smart-c10e3918-4a63-4115-85f9-4ed260e6ebfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547841145 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.547841145
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.4097926871
Short name T327
Test name
Test status
Simulation time 9946403021 ps
CPU time 184.7 seconds
Started Jan 07 01:15:14 PM PST 24
Finished Jan 07 01:18:19 PM PST 24
Peak memory 207072 kb
Host smart-da20cb2a-e3b3-4c18-92a7-9e1b7693406e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097926871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.4097926871
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1288506496
Short name T477
Test name
Test status
Simulation time 67208000 ps
CPU time 1.21 seconds
Started Jan 07 01:15:14 PM PST 24
Finished Jan 07 01:15:16 PM PST 24
Peak memory 197172 kb
Host smart-e98a3c76-6706-4e69-8d62-3975b2c0c4ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288506496 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1288506496
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1737141457
Short name T447
Test name
Test status
Simulation time 9240603071 ps
CPU time 22.68 seconds
Started Jan 07 01:15:15 PM PST 24
Finished Jan 07 01:15:38 PM PST 24
Peak memory 198760 kb
Host smart-b12345d5-f020-4843-aa85-1bfb0c6586c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737141457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1737141457
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3201940164
Short name T708
Test name
Test status
Simulation time 18762655 ps
CPU time 0.56 seconds
Started Jan 07 01:15:12 PM PST 24
Finished Jan 07 01:15:13 PM PST 24
Peak memory 193012 kb
Host smart-f97b9e83-49b3-4184-bd6a-66472ce5e18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201940164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3201940164
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2961171857
Short name T816
Test name
Test status
Simulation time 771102617 ps
CPU time 25.35 seconds
Started Jan 07 01:15:21 PM PST 24
Finished Jan 07 01:15:47 PM PST 24
Peak memory 215100 kb
Host smart-b048d0e0-28e2-4e6c-9039-4c70c9a26709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961171857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2961171857
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.4054252658
Short name T165
Test name
Test status
Simulation time 532051931 ps
CPU time 5.67 seconds
Started Jan 07 01:15:12 PM PST 24
Finished Jan 07 01:15:19 PM PST 24
Peak memory 198588 kb
Host smart-8a600d62-975b-4983-ac19-58e3ee2bc005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054252658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.4054252658
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3868813797
Short name T822
Test name
Test status
Simulation time 4704801413 ps
CPU time 38.65 seconds
Started Jan 07 01:15:12 PM PST 24
Finished Jan 07 01:15:52 PM PST 24
Peak memory 198840 kb
Host smart-6a0344e8-e729-43b7-a15d-c8521afb9600
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868813797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3868813797
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.194446731
Short name T387
Test name
Test status
Simulation time 10679424491 ps
CPU time 136.72 seconds
Started Jan 07 01:15:09 PM PST 24
Finished Jan 07 01:17:27 PM PST 24
Peak memory 198808 kb
Host smart-d1f3b1aa-c6c3-40f5-9dc0-22d5883cd0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194446731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.194446731
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.847110861
Short name T718
Test name
Test status
Simulation time 119312994 ps
CPU time 1.65 seconds
Started Jan 07 01:15:09 PM PST 24
Finished Jan 07 01:15:12 PM PST 24
Peak memory 198476 kb
Host smart-2f9df35c-2c28-416f-86df-5665b46a2bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847110861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.847110861
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.495448286
Short name T482
Test name
Test status
Simulation time 54458303 ps
CPU time 1.38 seconds
Started Jan 07 01:15:08 PM PST 24
Finished Jan 07 01:15:11 PM PST 24
Peak memory 198144 kb
Host smart-cb508390-5fc7-42dd-bb59-8f0f10b28278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495448286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.495448286
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2922204532
Short name T802
Test name
Test status
Simulation time 153298471975 ps
CPU time 661.96 seconds
Started Jan 07 01:15:11 PM PST 24
Finished Jan 07 01:26:13 PM PST 24
Peak memory 245180 kb
Host smart-c76de1ed-05aa-4f9e-9d99-4957952f8bfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922204532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2922204532
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.3595280622
Short name T122
Test name
Test status
Simulation time 9807106659 ps
CPU time 445.72 seconds
Started Jan 07 01:15:12 PM PST 24
Finished Jan 07 01:22:39 PM PST 24
Peak memory 230556 kb
Host smart-7f8f9e06-5c70-467f-aba2-4880eb214682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595280622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.3595280622
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1472890153
Short name T752
Test name
Test status
Simulation time 134229114 ps
CPU time 0.96 seconds
Started Jan 07 01:15:09 PM PST 24
Finished Jan 07 01:15:11 PM PST 24
Peak memory 197048 kb
Host smart-aca3e2cc-3708-40a8-b37b-34c1913c45ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472890153 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1472890153
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2928979912
Short name T463
Test name
Test status
Simulation time 135818604987 ps
CPU time 419.26 seconds
Started Jan 07 01:15:14 PM PST 24
Finished Jan 07 01:22:15 PM PST 24
Peak memory 198844 kb
Host smart-26180ec8-23f5-4a40-8ad1-5f7481c36483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928979912 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.2928979912
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.4193504716
Short name T498
Test name
Test status
Simulation time 3302704127 ps
CPU time 65.24 seconds
Started Jan 07 01:15:21 PM PST 24
Finished Jan 07 01:16:27 PM PST 24
Peak memory 198788 kb
Host smart-30c03561-4652-4464-8be6-3095ac031ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193504716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4193504716
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2734788765
Short name T46
Test name
Test status
Simulation time 44228935 ps
CPU time 0.57 seconds
Started Jan 07 01:15:13 PM PST 24
Finished Jan 07 01:15:15 PM PST 24
Peak memory 193056 kb
Host smart-4504f138-1770-46d3-8739-21d2cbe5dddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734788765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2734788765
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.752752342
Short name T750
Test name
Test status
Simulation time 1097390431 ps
CPU time 37.74 seconds
Started Jan 07 01:15:11 PM PST 24
Finished Jan 07 01:15:50 PM PST 24
Peak memory 222548 kb
Host smart-0adb4fc8-3236-42ff-8541-ac068b37e67f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=752752342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.752752342
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.79349199
Short name T376
Test name
Test status
Simulation time 587968783 ps
CPU time 7.96 seconds
Started Jan 07 01:15:18 PM PST 24
Finished Jan 07 01:15:27 PM PST 24
Peak memory 198540 kb
Host smart-773d4ead-cced-4251-b496-5441432fbb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79349199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.79349199
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.853569075
Short name T301
Test name
Test status
Simulation time 2306503306 ps
CPU time 29.22 seconds
Started Jan 07 01:15:11 PM PST 24
Finished Jan 07 01:15:42 PM PST 24
Peak memory 198776 kb
Host smart-fe5b75ae-8d89-4a39-be9b-f923101eaedb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853569075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.853569075
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2945821676
Short name T168
Test name
Test status
Simulation time 1012373982 ps
CPU time 47.58 seconds
Started Jan 07 01:15:10 PM PST 24
Finished Jan 07 01:15:59 PM PST 24
Peak memory 198688 kb
Host smart-955e951c-2f3f-4a48-9b68-193c9bf7dd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945821676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2945821676
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1345980861
Short name T544
Test name
Test status
Simulation time 2793218014 ps
CPU time 30.05 seconds
Started Jan 07 01:15:20 PM PST 24
Finished Jan 07 01:15:50 PM PST 24
Peak memory 198744 kb
Host smart-e6ea0e50-09ea-40dc-8ebf-f524e7e4d421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345980861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1345980861
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2969177563
Short name T532
Test name
Test status
Simulation time 52156215 ps
CPU time 1.58 seconds
Started Jan 07 01:15:13 PM PST 24
Finished Jan 07 01:15:15 PM PST 24
Peak memory 198216 kb
Host smart-b2565e5a-a6aa-4d19-aa10-1a33bcc7a53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969177563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2969177563
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1934308195
Short name T338
Test name
Test status
Simulation time 111679685754 ps
CPU time 1426.64 seconds
Started Jan 07 01:15:11 PM PST 24
Finished Jan 07 01:38:59 PM PST 24
Peak memory 198876 kb
Host smart-0ada5c67-cd50-4fc1-9955-42d1f60ee380
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934308195 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1934308195
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.2976490908
Short name T101
Test name
Test status
Simulation time 246233256004 ps
CPU time 908.09 seconds
Started Jan 07 01:15:09 PM PST 24
Finished Jan 07 01:30:18 PM PST 24
Peak memory 245780 kb
Host smart-58923c3e-95f6-454e-ba93-bc83092a5508
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2976490908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.2976490908
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3397887193
Short name T281
Test name
Test status
Simulation time 107517299 ps
CPU time 1.15 seconds
Started Jan 07 01:15:10 PM PST 24
Finished Jan 07 01:15:12 PM PST 24
Peak memory 197064 kb
Host smart-0734d8de-50d0-4740-bdb7-865a27949176
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397887193 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3397887193
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3272260306
Short name T743
Test name
Test status
Simulation time 42796236524 ps
CPU time 330.37 seconds
Started Jan 07 01:15:13 PM PST 24
Finished Jan 07 01:20:45 PM PST 24
Peak memory 198760 kb
Host smart-882b4959-eb56-4fa0-ba9b-2ca8c7fb95f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272260306 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.3272260306
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3218057650
Short name T458
Test name
Test status
Simulation time 7465008986 ps
CPU time 65.54 seconds
Started Jan 07 01:15:10 PM PST 24
Finished Jan 07 01:16:17 PM PST 24
Peak memory 198832 kb
Host smart-c991bcc9-4b52-476a-addb-a4bcbcb2f957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218057650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3218057650
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2919641490
Short name T766
Test name
Test status
Simulation time 16755720 ps
CPU time 0.54 seconds
Started Jan 07 01:15:27 PM PST 24
Finished Jan 07 01:15:28 PM PST 24
Peak memory 193036 kb
Host smart-a32c29d9-eb31-4384-9e3b-c5fb7c02f7b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919641490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2919641490
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3391947126
Short name T124
Test name
Test status
Simulation time 1289554254 ps
CPU time 39.03 seconds
Started Jan 07 01:15:25 PM PST 24
Finished Jan 07 01:16:05 PM PST 24
Peak memory 231488 kb
Host smart-fd24b4bd-c139-481d-a520-e361155475c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391947126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3391947126
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3956768294
Short name T665
Test name
Test status
Simulation time 5959185344 ps
CPU time 44.17 seconds
Started Jan 07 01:15:27 PM PST 24
Finished Jan 07 01:16:13 PM PST 24
Peak memory 198804 kb
Host smart-3aee9bb1-8d52-4ff5-bf46-0a94b28ee1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956768294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3956768294
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3779824095
Short name T716
Test name
Test status
Simulation time 1485661906 ps
CPU time 77.06 seconds
Started Jan 07 01:15:37 PM PST 24
Finished Jan 07 01:16:54 PM PST 24
Peak memory 198620 kb
Host smart-6f4d3411-b1e4-405e-94c0-59962ef7a95d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779824095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3779824095
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1787829535
Short name T383
Test name
Test status
Simulation time 42516658470 ps
CPU time 176.76 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:18:26 PM PST 24
Peak memory 198800 kb
Host smart-427350d4-c836-4d4a-9c0a-ab8ae88c8c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787829535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1787829535
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1480107750
Short name T259
Test name
Test status
Simulation time 30839997808 ps
CPU time 43.4 seconds
Started Jan 07 01:15:29 PM PST 24
Finished Jan 07 01:16:14 PM PST 24
Peak memory 198820 kb
Host smart-b8a86eda-7cbf-415b-bc5f-209d79cc95d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480107750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1480107750
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.806033889
Short name T803
Test name
Test status
Simulation time 22748906 ps
CPU time 0.86 seconds
Started Jan 07 01:15:10 PM PST 24
Finished Jan 07 01:15:12 PM PST 24
Peak memory 195636 kb
Host smart-46553f49-c804-4d88-b06f-0e576d5623fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806033889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.806033889
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2834682078
Short name T647
Test name
Test status
Simulation time 521033060242 ps
CPU time 463.27 seconds
Started Jan 07 01:15:26 PM PST 24
Finished Jan 07 01:23:10 PM PST 24
Peak memory 198804 kb
Host smart-90d4cb61-4f4e-4427-a98c-16b66763a84c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834682078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2834682078
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2057402469
Short name T490
Test name
Test status
Simulation time 100194835 ps
CPU time 1.09 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:15:30 PM PST 24
Peak memory 196420 kb
Host smart-fcd34100-8951-46ab-b592-54bcb2f4e227
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057402469 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2057402469
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.962054833
Short name T724
Test name
Test status
Simulation time 44313883472 ps
CPU time 464.84 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:23:14 PM PST 24
Peak memory 198804 kb
Host smart-bbe45cc8-91e2-4412-becd-0508e3b67a3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962054833 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.hmac_test_sha_vectors.962054833
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3375737138
Short name T117
Test name
Test status
Simulation time 4440684931 ps
CPU time 40.3 seconds
Started Jan 07 01:15:27 PM PST 24
Finished Jan 07 01:16:09 PM PST 24
Peak memory 198796 kb
Host smart-0aad7fd6-2f6e-4d2c-bd4f-d50a0d9e9de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375737138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3375737138
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3540941384
Short name T616
Test name
Test status
Simulation time 13589105 ps
CPU time 0.57 seconds
Started Jan 07 01:15:30 PM PST 24
Finished Jan 07 01:15:32 PM PST 24
Peak memory 193148 kb
Host smart-e005fad0-9210-4ad2-9d75-97ea71182e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540941384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3540941384
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3613823225
Short name T249
Test name
Test status
Simulation time 1479018658 ps
CPU time 44.34 seconds
Started Jan 07 01:15:31 PM PST 24
Finished Jan 07 01:16:16 PM PST 24
Peak memory 215072 kb
Host smart-b433b441-d264-41dc-a73a-99f4fcbc05c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613823225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3613823225
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3630881888
Short name T419
Test name
Test status
Simulation time 5540945634 ps
CPU time 23.93 seconds
Started Jan 07 01:15:27 PM PST 24
Finished Jan 07 01:15:52 PM PST 24
Peak memory 198856 kb
Host smart-b2c39c58-ca28-43cf-bafb-56830509a6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630881888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3630881888
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2978566661
Short name T508
Test name
Test status
Simulation time 18678287588 ps
CPU time 47.23 seconds
Started Jan 07 01:15:26 PM PST 24
Finished Jan 07 01:16:14 PM PST 24
Peak memory 198812 kb
Host smart-2d5bb599-7516-45d4-8c78-f63a953dfac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978566661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2978566661
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2983795884
Short name T235
Test name
Test status
Simulation time 12758173358 ps
CPU time 153.87 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:18:03 PM PST 24
Peak memory 198848 kb
Host smart-a5e717c9-2021-4021-a9eb-cdedf5d9d1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983795884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2983795884
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2351372249
Short name T810
Test name
Test status
Simulation time 924862220 ps
CPU time 22.89 seconds
Started Jan 07 01:15:37 PM PST 24
Finished Jan 07 01:16:07 PM PST 24
Peak memory 198684 kb
Host smart-f43a1238-e82c-4f78-86c5-50241df920b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351372249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2351372249
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.303001374
Short name T622
Test name
Test status
Simulation time 116588965 ps
CPU time 0.88 seconds
Started Jan 07 01:15:35 PM PST 24
Finished Jan 07 01:15:38 PM PST 24
Peak memory 195944 kb
Host smart-9f3c6fca-d675-4303-833e-250620a51e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303001374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.303001374
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1028509222
Short name T461
Test name
Test status
Simulation time 20108121567 ps
CPU time 894.9 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:30:25 PM PST 24
Peak memory 239756 kb
Host smart-8efb1d43-da52-4c1f-8d84-2f9726029c8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028509222 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1028509222
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.3168157329
Short name T476
Test name
Test status
Simulation time 12587038788 ps
CPU time 109.26 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:17:19 PM PST 24
Peak memory 198964 kb
Host smart-7f062bcf-536e-42ac-a98d-14bb0eb2d26b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168157329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.3168157329
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3734453602
Short name T265
Test name
Test status
Simulation time 84646402 ps
CPU time 0.93 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:15:30 PM PST 24
Peak memory 195976 kb
Host smart-0b529e3f-4d60-4de4-a6a2-3d115f11a2cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734453602 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3734453602
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1740501971
Short name T645
Test name
Test status
Simulation time 90532843968 ps
CPU time 418.49 seconds
Started Jan 07 01:15:29 PM PST 24
Finished Jan 07 01:22:30 PM PST 24
Peak memory 198736 kb
Host smart-b857252c-6ba5-4abd-949b-d38c39d67a1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740501971 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.1740501971
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2914138726
Short name T359
Test name
Test status
Simulation time 24559237506 ps
CPU time 63.7 seconds
Started Jan 07 01:15:27 PM PST 24
Finished Jan 07 01:16:32 PM PST 24
Peak memory 198768 kb
Host smart-6a9891f8-de29-4f32-82b0-e2102c36a0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914138726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2914138726
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.180274731
Short name T648
Test name
Test status
Simulation time 54654858 ps
CPU time 0.58 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:05 PM PST 24
Peak memory 193196 kb
Host smart-796b418f-7b63-4c94-9cf1-332559ec4d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180274731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.180274731
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3124932285
Short name T334
Test name
Test status
Simulation time 2245413725 ps
CPU time 24.86 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:14:08 PM PST 24
Peak memory 206900 kb
Host smart-d260decb-c0e9-4a15-9a6d-620cf6263b63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124932285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3124932285
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2785717918
Short name T218
Test name
Test status
Simulation time 263948342 ps
CPU time 5.97 seconds
Started Jan 07 01:13:39 PM PST 24
Finished Jan 07 01:13:46 PM PST 24
Peak memory 198688 kb
Host smart-ebd50331-201e-44a6-815e-90ea59585666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785717918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2785717918
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.123819860
Short name T694
Test name
Test status
Simulation time 4086052921 ps
CPU time 102.2 seconds
Started Jan 07 01:13:40 PM PST 24
Finished Jan 07 01:15:24 PM PST 24
Peak memory 198864 kb
Host smart-e1d15dc0-5654-4c9b-aa0c-fba9590ec390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123819860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.123819860
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1775079384
Short name T712
Test name
Test status
Simulation time 2060601989 ps
CPU time 100.88 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:15:25 PM PST 24
Peak memory 198748 kb
Host smart-377a87e7-9ad5-4b8d-808d-330945c6dc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775079384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1775079384
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3332739960
Short name T169
Test name
Test status
Simulation time 207720898 ps
CPU time 10.49 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:13:53 PM PST 24
Peak memory 198724 kb
Host smart-5d0a9bcc-54fc-424b-a378-578e32c4dd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332739960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3332739960
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2980919268
Short name T55
Test name
Test status
Simulation time 38430026 ps
CPU time 0.8 seconds
Started Jan 07 01:13:43 PM PST 24
Finished Jan 07 01:13:46 PM PST 24
Peak memory 215904 kb
Host smart-41de0438-f723-4191-bd77-7da14ec1d217
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980919268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2980919268
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3622934508
Short name T59
Test name
Test status
Simulation time 693270022 ps
CPU time 2.8 seconds
Started Jan 07 01:13:39 PM PST 24
Finished Jan 07 01:13:42 PM PST 24
Peak memory 198716 kb
Host smart-e78a6eae-f9d6-4796-af5c-5f0dff245a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622934508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3622934508
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1655092825
Short name T597
Test name
Test status
Simulation time 81841628887 ps
CPU time 311.1 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:18:55 PM PST 24
Peak memory 198716 kb
Host smart-d231b11d-d173-45ee-be23-5970fb9010bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655092825 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1655092825
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3605499915
Short name T437
Test name
Test status
Simulation time 16773449839 ps
CPU time 799.89 seconds
Started Jan 07 01:13:42 PM PST 24
Finished Jan 07 01:27:04 PM PST 24
Peak memory 245064 kb
Host smart-e7b34b1e-0fad-4dfa-8371-779710544ee0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605499915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3605499915
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3008659299
Short name T180
Test name
Test status
Simulation time 119017365 ps
CPU time 1.04 seconds
Started Jan 07 01:13:44 PM PST 24
Finished Jan 07 01:13:46 PM PST 24
Peak memory 196276 kb
Host smart-e7b52621-be9b-44b6-a1b7-3f052bebfa02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008659299 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3008659299
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1480751658
Short name T820
Test name
Test status
Simulation time 54997419879 ps
CPU time 454.52 seconds
Started Jan 07 01:13:43 PM PST 24
Finished Jan 07 01:21:19 PM PST 24
Peak memory 198836 kb
Host smart-afe58056-15e2-4555-a8a0-1338b0564a6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480751658 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.1480751658
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3691543145
Short name T272
Test name
Test status
Simulation time 11755624033 ps
CPU time 76.15 seconds
Started Jan 07 01:13:41 PM PST 24
Finished Jan 07 01:14:59 PM PST 24
Peak memory 198720 kb
Host smart-0e51ad9c-7634-4ac3-8421-83766caf2cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691543145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3691543145
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2115273839
Short name T486
Test name
Test status
Simulation time 13055761 ps
CPU time 0.56 seconds
Started Jan 07 01:15:27 PM PST 24
Finished Jan 07 01:15:28 PM PST 24
Peak memory 193152 kb
Host smart-9d678490-8fa4-4738-a4e0-a63aed8a9ba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115273839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2115273839
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1090802113
Short name T465
Test name
Test status
Simulation time 2790359411 ps
CPU time 46.88 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:16:17 PM PST 24
Peak memory 231524 kb
Host smart-12e2e9cf-f73e-4849-bad5-3a61af28d3a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090802113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1090802113
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2002800118
Short name T696
Test name
Test status
Simulation time 5857100245 ps
CPU time 19.09 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:15:48 PM PST 24
Peak memory 198892 kb
Host smart-3146ba28-5bd7-4596-845d-f2c5dbba41a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002800118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2002800118
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1885717456
Short name T655
Test name
Test status
Simulation time 885951251 ps
CPU time 9.6 seconds
Started Jan 07 01:15:33 PM PST 24
Finished Jan 07 01:15:44 PM PST 24
Peak memory 198612 kb
Host smart-9caa63a2-c2de-46b2-ab67-35c0eaacb5b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885717456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1885717456
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3189365488
Short name T191
Test name
Test status
Simulation time 5471943303 ps
CPU time 70.36 seconds
Started Jan 07 01:15:30 PM PST 24
Finished Jan 07 01:16:42 PM PST 24
Peak memory 198796 kb
Host smart-95cf7796-9c34-49d4-b0a1-e5962924b9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189365488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3189365488
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1343917727
Short name T214
Test name
Test status
Simulation time 1402283554 ps
CPU time 68.56 seconds
Started Jan 07 01:15:29 PM PST 24
Finished Jan 07 01:16:39 PM PST 24
Peak memory 198704 kb
Host smart-efed1be5-ebad-427b-9b87-2114531dc492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343917727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1343917727
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1478697489
Short name T212
Test name
Test status
Simulation time 134945905 ps
CPU time 2.95 seconds
Started Jan 07 01:15:32 PM PST 24
Finished Jan 07 01:15:36 PM PST 24
Peak memory 198472 kb
Host smart-2651f653-343d-4fbd-923e-2ebcb43617fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478697489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1478697489
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1336075623
Short name T547
Test name
Test status
Simulation time 7943857251 ps
CPU time 281.22 seconds
Started Jan 07 01:15:31 PM PST 24
Finished Jan 07 01:20:13 PM PST 24
Peak memory 247252 kb
Host smart-029d609f-a760-4d75-8dbb-ddeb923eedee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336075623 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1336075623
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.626080539
Short name T413
Test name
Test status
Simulation time 130370076911 ps
CPU time 2864.89 seconds
Started Jan 07 01:15:30 PM PST 24
Finished Jan 07 02:03:16 PM PST 24
Peak memory 231620 kb
Host smart-0682b9ac-c541-4102-b812-0549aa80a7cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626080539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.626080539
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1351487127
Short name T746
Test name
Test status
Simulation time 108404499 ps
CPU time 1.07 seconds
Started Jan 07 01:15:29 PM PST 24
Finished Jan 07 01:15:32 PM PST 24
Peak memory 196148 kb
Host smart-492fcd1c-9b07-4de6-9c83-4f560f06ef9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351487127 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1351487127
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1481428631
Short name T244
Test name
Test status
Simulation time 25239601797 ps
CPU time 403.64 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:22:13 PM PST 24
Peak memory 198808 kb
Host smart-64e2d983-65a3-4acf-a86f-4a6796b3d46b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481428631 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.1481428631
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3613049318
Short name T707
Test name
Test status
Simulation time 954312974 ps
CPU time 15.44 seconds
Started Jan 07 01:15:27 PM PST 24
Finished Jan 07 01:15:43 PM PST 24
Peak memory 198720 kb
Host smart-eedc6060-ad30-474d-8347-86699ddc6807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613049318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3613049318
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2248772245
Short name T727
Test name
Test status
Simulation time 59548917 ps
CPU time 0.55 seconds
Started Jan 07 01:15:40 PM PST 24
Finished Jan 07 01:15:47 PM PST 24
Peak memory 193116 kb
Host smart-85cd2985-743e-4fa3-b926-073e42029e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248772245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2248772245
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1708700827
Short name T763
Test name
Test status
Simulation time 3276851368 ps
CPU time 18.25 seconds
Started Jan 07 01:15:28 PM PST 24
Finished Jan 07 01:15:48 PM PST 24
Peak memory 214356 kb
Host smart-c109c8a2-4629-4a69-bd46-f6249a4b424e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708700827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1708700827
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.176260761
Short name T162
Test name
Test status
Simulation time 1840707388 ps
CPU time 21.13 seconds
Started Jan 07 01:15:25 PM PST 24
Finished Jan 07 01:15:47 PM PST 24
Peak memory 198672 kb
Host smart-92cd227a-77fe-4485-95d4-7827442b987f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176260761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.176260761
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1146646142
Short name T40
Test name
Test status
Simulation time 1108386687 ps
CPU time 57.62 seconds
Started Jan 07 01:15:29 PM PST 24
Finished Jan 07 01:16:28 PM PST 24
Peak memory 198724 kb
Host smart-59335626-d78e-4efa-951c-535ae93a3728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146646142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1146646142
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3531764575
Short name T174
Test name
Test status
Simulation time 129216785 ps
CPU time 1.71 seconds
Started Jan 07 01:15:41 PM PST 24
Finished Jan 07 01:15:48 PM PST 24
Peak memory 198656 kb
Host smart-3875669f-a7db-4e75-bff8-b216cdf2951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531764575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3531764575
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.643186938
Short name T478
Test name
Test status
Simulation time 5487693526 ps
CPU time 70.59 seconds
Started Jan 07 01:15:26 PM PST 24
Finished Jan 07 01:16:38 PM PST 24
Peak memory 198792 kb
Host smart-aecb5a95-c7d6-4db1-8382-3abbb4214b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643186938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.643186938
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2073181164
Short name T623
Test name
Test status
Simulation time 98735143 ps
CPU time 2.33 seconds
Started Jan 07 01:15:29 PM PST 24
Finished Jan 07 01:15:33 PM PST 24
Peak memory 198500 kb
Host smart-c668f681-79c1-47ee-85e7-6f4dedf4da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073181164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2073181164
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.4161891145
Short name T626
Test name
Test status
Simulation time 49562210363 ps
CPU time 713.86 seconds
Started Jan 07 01:15:42 PM PST 24
Finished Jan 07 01:27:41 PM PST 24
Peak memory 198804 kb
Host smart-1a174338-374f-4c3b-a701-fd9fda1dfef9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161891145 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.4161891145
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.2317450015
Short name T193
Test name
Test status
Simulation time 361958629520 ps
CPU time 1617.62 seconds
Started Jan 07 01:15:42 PM PST 24
Finished Jan 07 01:42:44 PM PST 24
Peak memory 222624 kb
Host smart-10f57d9e-9d2d-457d-a935-5f64298a7ebf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2317450015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.2317450015
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.479508243
Short name T531
Test name
Test status
Simulation time 102404400 ps
CPU time 0.89 seconds
Started Jan 07 01:15:43 PM PST 24
Finished Jan 07 01:15:49 PM PST 24
Peak memory 195792 kb
Host smart-718979eb-6dbe-4ea5-a67c-bb630032a323
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479508243 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.479508243
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1328415593
Short name T459
Test name
Test status
Simulation time 84676733135 ps
CPU time 435.8 seconds
Started Jan 07 01:15:40 PM PST 24
Finished Jan 07 01:23:02 PM PST 24
Peak memory 198752 kb
Host smart-03dff1ea-9ff7-4e65-8dca-12ffb7120be5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328415593 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.1328415593
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.28760080
Short name T351
Test name
Test status
Simulation time 24994282305 ps
CPU time 65.56 seconds
Started Jan 07 01:15:41 PM PST 24
Finished Jan 07 01:16:52 PM PST 24
Peak memory 198828 kb
Host smart-b4f16296-33cb-4fd3-b274-73287c9f7db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28760080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.28760080
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1197469203
Short name T215
Test name
Test status
Simulation time 27567833 ps
CPU time 0.58 seconds
Started Jan 07 01:15:41 PM PST 24
Finished Jan 07 01:15:47 PM PST 24
Peak memory 194104 kb
Host smart-6bfca8f1-a195-4750-a4c9-957877c29020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197469203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1197469203
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.4135742943
Short name T487
Test name
Test status
Simulation time 1937826661 ps
CPU time 30.75 seconds
Started Jan 07 01:15:42 PM PST 24
Finished Jan 07 01:16:17 PM PST 24
Peak memory 226980 kb
Host smart-53edffeb-5d69-4aca-a88a-d32309a25423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135742943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.4135742943
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2998687065
Short name T260
Test name
Test status
Simulation time 4878895770 ps
CPU time 33.8 seconds
Started Jan 07 01:15:41 PM PST 24
Finished Jan 07 01:16:20 PM PST 24
Peak memory 198784 kb
Host smart-45eabe6c-d2e0-4875-ac54-42293548e2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998687065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2998687065
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3513239331
Short name T43
Test name
Test status
Simulation time 9152920785 ps
CPU time 113.28 seconds
Started Jan 07 01:15:41 PM PST 24
Finished Jan 07 01:17:40 PM PST 24
Peak memory 198792 kb
Host smart-6452fa16-b6f3-47c3-bbfa-e8e4263ec2a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513239331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3513239331
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.231582570
Short name T439
Test name
Test status
Simulation time 3037261792 ps
CPU time 76.96 seconds
Started Jan 07 01:15:42 PM PST 24
Finished Jan 07 01:17:04 PM PST 24
Peak memory 198848 kb
Host smart-54e7b7a6-1545-4766-811e-791a6ad9e78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231582570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.231582570
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3725914935
Short name T624
Test name
Test status
Simulation time 8181674732 ps
CPU time 22.93 seconds
Started Jan 07 01:15:40 PM PST 24
Finished Jan 07 01:16:09 PM PST 24
Peak memory 198692 kb
Host smart-30682643-74ad-4019-a004-b08ee5dbd997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725914935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3725914935
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1951806034
Short name T355
Test name
Test status
Simulation time 397266865 ps
CPU time 2.63 seconds
Started Jan 07 01:15:43 PM PST 24
Finished Jan 07 01:15:50 PM PST 24
Peak memory 198816 kb
Host smart-ee159b8e-4730-4c06-90ea-8bb1e471e042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951806034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1951806034
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2310160769
Short name T709
Test name
Test status
Simulation time 58865166618 ps
CPU time 1496.19 seconds
Started Jan 07 01:15:41 PM PST 24
Finished Jan 07 01:40:43 PM PST 24
Peak memory 214488 kb
Host smart-cec74914-56b8-487b-82d9-4607aeee4863
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310160769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2310160769
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.3065574864
Short name T348
Test name
Test status
Simulation time 68791147724 ps
CPU time 1581.45 seconds
Started Jan 07 01:15:42 PM PST 24
Finished Jan 07 01:42:08 PM PST 24
Peak memory 246020 kb
Host smart-7eb42155-297f-4da6-9155-c3d384964fba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065574864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.3065574864
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.4182032666
Short name T429
Test name
Test status
Simulation time 85045653 ps
CPU time 0.93 seconds
Started Jan 07 01:15:41 PM PST 24
Finished Jan 07 01:15:47 PM PST 24
Peak memory 196604 kb
Host smart-2ab85735-e531-48d5-84a5-f87bf55b4a9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182032666 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.4182032666
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3601043650
Short name T789
Test name
Test status
Simulation time 8352158188 ps
CPU time 429.93 seconds
Started Jan 07 01:15:42 PM PST 24
Finished Jan 07 01:22:57 PM PST 24
Peak memory 198824 kb
Host smart-76843c9b-6339-4f58-a121-2b10b2c34f97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601043650 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.3601043650
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3310279772
Short name T270
Test name
Test status
Simulation time 2093298753 ps
CPU time 34.87 seconds
Started Jan 07 01:15:42 PM PST 24
Finished Jan 07 01:16:21 PM PST 24
Peak memory 198724 kb
Host smart-d60a1f74-5ef5-4f92-b91c-fc7ac73b41b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310279772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3310279772
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2150266308
Short name T543
Test name
Test status
Simulation time 24395026 ps
CPU time 0.56 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:15:56 PM PST 24
Peak memory 193004 kb
Host smart-e4cab5d5-f849-404d-85c2-10b30679d093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150266308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2150266308
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3008543855
Short name T519
Test name
Test status
Simulation time 914546398 ps
CPU time 26.88 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:16:21 PM PST 24
Peak memory 214652 kb
Host smart-1fa73578-e028-4e75-ac43-0f3b717b13b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008543855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3008543855
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1672356963
Short name T441
Test name
Test status
Simulation time 818344930 ps
CPU time 4.16 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:16:01 PM PST 24
Peak memory 198620 kb
Host smart-9b408195-9a56-438b-b88b-715d756b434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672356963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1672356963
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.388906303
Short name T451
Test name
Test status
Simulation time 951470954 ps
CPU time 49.77 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:16:46 PM PST 24
Peak memory 198692 kb
Host smart-85c18266-58b4-434f-9101-5387f89fc436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=388906303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.388906303
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3109781350
Short name T2
Test name
Test status
Simulation time 1606188186 ps
CPU time 39.97 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:16:34 PM PST 24
Peak memory 198720 kb
Host smart-8fbf0f75-27c0-42c1-b809-efcb971c2cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109781350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3109781350
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2682021943
Short name T629
Test name
Test status
Simulation time 5468305384 ps
CPU time 22.83 seconds
Started Jan 07 01:15:57 PM PST 24
Finished Jan 07 01:16:21 PM PST 24
Peak memory 198856 kb
Host smart-a673027c-d530-4cee-9581-979f303e8fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682021943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2682021943
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2557850707
Short name T308
Test name
Test status
Simulation time 1260369558 ps
CPU time 1.88 seconds
Started Jan 07 01:15:42 PM PST 24
Finished Jan 07 01:15:49 PM PST 24
Peak memory 198300 kb
Host smart-bf35de5a-48bb-457b-ad1b-e6724ce064a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557850707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2557850707
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3255683856
Short name T386
Test name
Test status
Simulation time 19585134545 ps
CPU time 951.39 seconds
Started Jan 07 01:15:52 PM PST 24
Finished Jan 07 01:31:44 PM PST 24
Peak memory 214980 kb
Host smart-aa5030cb-8c85-4941-86da-fa30f3364300
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255683856 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3255683856
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.1434414489
Short name T673
Test name
Test status
Simulation time 133252556157 ps
CPU time 1069.33 seconds
Started Jan 07 01:15:55 PM PST 24
Finished Jan 07 01:33:47 PM PST 24
Peak memory 223592 kb
Host smart-48abfd8f-ca47-4f94-9d62-0f23e5c1f410
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434414489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.1434414489
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3855470229
Short name T418
Test name
Test status
Simulation time 137237071 ps
CPU time 0.87 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:15:56 PM PST 24
Peak memory 195496 kb
Host smart-b684866f-7abf-438b-a4e1-68ccbb5c958b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855470229 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3855470229
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3794659300
Short name T525
Test name
Test status
Simulation time 64186750085 ps
CPU time 385.42 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:22:20 PM PST 24
Peak memory 198780 kb
Host smart-824d58fa-63c0-470e-a190-05bcbed0053b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794659300 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.3794659300
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2443731688
Short name T389
Test name
Test status
Simulation time 8009772615 ps
CPU time 15.29 seconds
Started Jan 07 01:15:55 PM PST 24
Finished Jan 07 01:16:12 PM PST 24
Peak memory 198792 kb
Host smart-8fa54975-cf0a-434f-8e82-94cc48928c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443731688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2443731688
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1524781094
Short name T719
Test name
Test status
Simulation time 35926839 ps
CPU time 0.58 seconds
Started Jan 07 01:15:48 PM PST 24
Finished Jan 07 01:15:52 PM PST 24
Peak memory 193116 kb
Host smart-005a8f85-f639-4a57-850a-2f1c1b4fbcf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524781094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1524781094
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.338673796
Short name T442
Test name
Test status
Simulation time 72350084 ps
CPU time 2.45 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:15:58 PM PST 24
Peak memory 198748 kb
Host smart-15c73de7-a909-4a76-861c-19e1949b0ad8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338673796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.338673796
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2209710403
Short name T370
Test name
Test status
Simulation time 1114996955 ps
CPU time 15.06 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:16:10 PM PST 24
Peak memory 198632 kb
Host smart-4bd97fc0-152c-4433-9a7c-67895716c1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209710403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2209710403
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3086712479
Short name T250
Test name
Test status
Simulation time 3761929472 ps
CPU time 100.16 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:17:36 PM PST 24
Peak memory 198932 kb
Host smart-b34c068b-da55-4a97-a812-202fc2c49e70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086712479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3086712479
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1148632370
Short name T669
Test name
Test status
Simulation time 12169231330 ps
CPU time 146.89 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:18:22 PM PST 24
Peak memory 198888 kb
Host smart-89ed5345-9b7d-420b-855c-bbdecbfab8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148632370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1148632370
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1215440013
Short name T608
Test name
Test status
Simulation time 499455888 ps
CPU time 13 seconds
Started Jan 07 01:15:55 PM PST 24
Finished Jan 07 01:16:10 PM PST 24
Peak memory 198560 kb
Host smart-affc7b19-e001-4be6-9a4e-2e1541faa769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215440013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1215440013
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1806225054
Short name T514
Test name
Test status
Simulation time 320579909 ps
CPU time 2.18 seconds
Started Jan 07 01:15:52 PM PST 24
Finished Jan 07 01:15:55 PM PST 24
Peak memory 198724 kb
Host smart-6e97d64f-0a33-4a82-97cc-1b5b43b1d00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806225054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1806225054
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2183761993
Short name T176
Test name
Test status
Simulation time 55854003336 ps
CPU time 639.91 seconds
Started Jan 07 01:15:55 PM PST 24
Finished Jan 07 01:26:37 PM PST 24
Peak memory 230516 kb
Host smart-5ef7cc5c-097d-402d-8619-7f3da37a6a69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183761993 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2183761993
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.2738434167
Short name T693
Test name
Test status
Simulation time 50015538085 ps
CPU time 270.87 seconds
Started Jan 07 01:15:56 PM PST 24
Finished Jan 07 01:20:28 PM PST 24
Peak memory 207108 kb
Host smart-d726c968-dcfb-4842-9c73-70ba213615e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738434167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.2738434167
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3626494064
Short name T179
Test name
Test status
Simulation time 52931185 ps
CPU time 1.15 seconds
Started Jan 07 01:15:52 PM PST 24
Finished Jan 07 01:15:55 PM PST 24
Peak memory 197484 kb
Host smart-ad6d3591-59a8-44eb-b7da-fd102c8c6efb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626494064 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3626494064
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3206404832
Short name T671
Test name
Test status
Simulation time 68998231086 ps
CPU time 349.25 seconds
Started Jan 07 01:15:52 PM PST 24
Finished Jan 07 01:21:42 PM PST 24
Peak memory 198784 kb
Host smart-d3be8c5b-35a7-44a8-8778-63720ed43bfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206404832 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_sha_vectors.3206404832
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.643364624
Short name T275
Test name
Test status
Simulation time 1138658363 ps
CPU time 40.96 seconds
Started Jan 07 01:15:46 PM PST 24
Finished Jan 07 01:16:31 PM PST 24
Peak memory 198684 kb
Host smart-af508fab-30fa-4a56-80a8-c2b420745c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643364624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.643364624
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1821310990
Short name T352
Test name
Test status
Simulation time 17125017 ps
CPU time 0.57 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:15:54 PM PST 24
Peak memory 193160 kb
Host smart-b17614bd-2733-49e6-b8a1-5a9b8c72001f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821310990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1821310990
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.757295636
Short name T668
Test name
Test status
Simulation time 1044120593 ps
CPU time 17.63 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:16:14 PM PST 24
Peak memory 206924 kb
Host smart-a0497049-cf5f-414c-966d-4309834f14cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757295636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.757295636
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3885774500
Short name T548
Test name
Test status
Simulation time 3280405841 ps
CPU time 35.39 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:16:29 PM PST 24
Peak memory 198724 kb
Host smart-075ff02e-2eee-490c-95e8-d4b4bcd5173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885774500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3885774500
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2261175960
Short name T625
Test name
Test status
Simulation time 3495892243 ps
CPU time 29.26 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:16:25 PM PST 24
Peak memory 198740 kb
Host smart-d1e5e2fb-78e2-4ee1-b14f-1dc40d8c83ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261175960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2261175960
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.461069521
Short name T318
Test name
Test status
Simulation time 2753756110 ps
CPU time 138.17 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:18:12 PM PST 24
Peak memory 198852 kb
Host smart-f0d819f0-07a0-46c8-81c7-153cf13e03a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461069521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.461069521
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1595036062
Short name T513
Test name
Test status
Simulation time 1748278682 ps
CPU time 88.06 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:17:23 PM PST 24
Peak memory 198704 kb
Host smart-d912d047-9a40-448f-8606-c5692349bafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595036062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1595036062
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.760811942
Short name T801
Test name
Test status
Simulation time 1809007516 ps
CPU time 3.96 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:15:58 PM PST 24
Peak memory 198440 kb
Host smart-427ea92c-adc6-4432-9e23-aea84cc07edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760811942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.760811942
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1442070257
Short name T100
Test name
Test status
Simulation time 17155739540 ps
CPU time 798.46 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:29:15 PM PST 24
Peak memory 207084 kb
Host smart-9bc42457-0bcb-47d5-b4ae-430639cf71bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442070257 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1442070257
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.1435617149
Short name T650
Test name
Test status
Simulation time 78683987459 ps
CPU time 1171.96 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:35:26 PM PST 24
Peak memory 231684 kb
Host smart-43d7f7fd-6764-4182-bd8c-8b8f3efb4a52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435617149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.1435617149
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.782469512
Short name T384
Test name
Test status
Simulation time 30180495 ps
CPU time 1.05 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:15:57 PM PST 24
Peak memory 196112 kb
Host smart-5326e5a7-a795-4e42-b853-7af7bb91e94c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782469512 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.782469512
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3191997482
Short name T484
Test name
Test status
Simulation time 121362363883 ps
CPU time 471.04 seconds
Started Jan 07 01:15:45 PM PST 24
Finished Jan 07 01:23:41 PM PST 24
Peak memory 198808 kb
Host smart-3bf6f316-15d6-4d54-96e0-59ac14664a40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191997482 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_sha_vectors.3191997482
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1089001011
Short name T371
Test name
Test status
Simulation time 3124325065 ps
CPU time 15.58 seconds
Started Jan 07 01:16:01 PM PST 24
Finished Jan 07 01:16:23 PM PST 24
Peak memory 198792 kb
Host smart-93bdcd2b-2b7c-4fe3-ad74-a6b3fb8f38d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089001011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1089001011
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.320090939
Short name T791
Test name
Test status
Simulation time 53951167 ps
CPU time 0.61 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:15:56 PM PST 24
Peak memory 194056 kb
Host smart-59de77f9-1c33-4cf3-ab70-764ea388da67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320090939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.320090939
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1188581132
Short name T512
Test name
Test status
Simulation time 74911691 ps
CPU time 2.74 seconds
Started Jan 07 01:15:44 PM PST 24
Finished Jan 07 01:15:52 PM PST 24
Peak memory 198672 kb
Host smart-f64dcbff-b116-452b-9245-eb38be294377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188581132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1188581132
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.203147662
Short name T388
Test name
Test status
Simulation time 852904737 ps
CPU time 8.78 seconds
Started Jan 07 01:15:45 PM PST 24
Finished Jan 07 01:15:59 PM PST 24
Peak memory 198632 kb
Host smart-98ec9b1e-1f53-4226-83fd-14bccbec3a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203147662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.203147662
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.935245739
Short name T349
Test name
Test status
Simulation time 2450819060 ps
CPU time 62.35 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:16:58 PM PST 24
Peak memory 198792 kb
Host smart-3aa5916f-3178-4ca7-8d3a-433aa3b6d17c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935245739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.935245739
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.960244205
Short name T542
Test name
Test status
Simulation time 5971358921 ps
CPU time 69.78 seconds
Started Jan 07 01:15:46 PM PST 24
Finished Jan 07 01:17:00 PM PST 24
Peak memory 198720 kb
Host smart-e5002e51-05d4-4463-b7b4-1adbd8d466e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960244205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.960244205
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3991193823
Short name T661
Test name
Test status
Simulation time 1467910117 ps
CPU time 19.41 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:16:13 PM PST 24
Peak memory 198440 kb
Host smart-9e7518fa-2ab8-4530-ba8e-a1956a4b4ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991193823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3991193823
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2272055105
Short name T236
Test name
Test status
Simulation time 152181842 ps
CPU time 2.34 seconds
Started Jan 07 01:15:56 PM PST 24
Finished Jan 07 01:16:00 PM PST 24
Peak memory 198704 kb
Host smart-fd12a37a-4842-43fa-b14c-f1bed483c503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272055105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2272055105
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2629714684
Short name T554
Test name
Test status
Simulation time 11914405235 ps
CPU time 153.25 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:18:30 PM PST 24
Peak memory 198852 kb
Host smart-373a1fc9-2bca-42b3-a34d-48c394fea112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629714684 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2629714684
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.1843321166
Short name T104
Test name
Test status
Simulation time 32493111266 ps
CPU time 621.63 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:26:16 PM PST 24
Peak memory 223100 kb
Host smart-07ff20f4-6156-4148-848a-b1e128ea9c3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843321166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.1843321166
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.875865186
Short name T242
Test name
Test status
Simulation time 60762599 ps
CPU time 1.08 seconds
Started Jan 07 01:15:52 PM PST 24
Finished Jan 07 01:15:54 PM PST 24
Peak memory 197240 kb
Host smart-713c71c3-6df1-49d2-a1e3-63da32b0e847
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875865186 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_hmac_vectors.875865186
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2518036879
Short name T406
Test name
Test status
Simulation time 172429259375 ps
CPU time 478.75 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:23:54 PM PST 24
Peak memory 198796 kb
Host smart-a82acadf-96d7-4dec-984d-b67824cc4510
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518036879 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_sha_vectors.2518036879
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1710181864
Short name T299
Test name
Test status
Simulation time 300800423 ps
CPU time 5.3 seconds
Started Jan 07 01:15:56 PM PST 24
Finished Jan 07 01:16:03 PM PST 24
Peak memory 198680 kb
Host smart-25bdc3ee-84bd-47bd-800f-1b42428b720c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710181864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1710181864
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1965974634
Short name T515
Test name
Test status
Simulation time 37311219 ps
CPU time 0.54 seconds
Started Jan 07 01:15:56 PM PST 24
Finished Jan 07 01:15:58 PM PST 24
Peak memory 193060 kb
Host smart-e965dc15-201a-48a3-9d8d-fa959a951f56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965974634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1965974634
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2628835046
Short name T114
Test name
Test status
Simulation time 1412274592 ps
CPU time 48.02 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:16:43 PM PST 24
Peak memory 223336 kb
Host smart-1b7662fe-66cb-4090-9355-785a3314627c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628835046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2628835046
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2505639416
Short name T573
Test name
Test status
Simulation time 4630158872 ps
CPU time 12.05 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:16:08 PM PST 24
Peak memory 198760 kb
Host smart-106c21a4-a879-43c8-8141-cb197231ece6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505639416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2505639416
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.418235832
Short name T664
Test name
Test status
Simulation time 930452897 ps
CPU time 12.59 seconds
Started Jan 07 01:15:55 PM PST 24
Finished Jan 07 01:16:09 PM PST 24
Peak memory 198416 kb
Host smart-f9964630-42a0-4e6b-816a-0326dcf73c45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=418235832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.418235832
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.186396623
Short name T745
Test name
Test status
Simulation time 84191991831 ps
CPU time 213.84 seconds
Started Jan 07 01:15:56 PM PST 24
Finished Jan 07 01:19:32 PM PST 24
Peak memory 198832 kb
Host smart-6c686e31-3a6c-4a20-b408-3e1112c4fd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186396623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.186396623
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1030802258
Short name T578
Test name
Test status
Simulation time 1612429829 ps
CPU time 26.86 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:16:22 PM PST 24
Peak memory 198656 kb
Host smart-a42d8c7b-6cb6-47d2-8da6-f8379e76ed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030802258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1030802258
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.541781379
Short name T177
Test name
Test status
Simulation time 91355200 ps
CPU time 1.32 seconds
Started Jan 07 01:15:55 PM PST 24
Finished Jan 07 01:15:58 PM PST 24
Peak memory 198676 kb
Host smart-8b841c43-7a5d-4696-b4d0-f3b83ebe7e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541781379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.541781379
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1659183312
Short name T7
Test name
Test status
Simulation time 43691464661 ps
CPU time 582.34 seconds
Started Jan 07 01:15:55 PM PST 24
Finished Jan 07 01:25:39 PM PST 24
Peak memory 231664 kb
Host smart-1eaa917b-b70c-4ece-8f24-5c3652ae5096
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659183312 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1659183312
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.3868930097
Short name T112
Test name
Test status
Simulation time 49390778972 ps
CPU time 372.8 seconds
Started Jan 07 01:15:57 PM PST 24
Finished Jan 07 01:22:12 PM PST 24
Peak memory 207280 kb
Host smart-c9619a54-ab0a-4a61-8665-1b5c3ac6b644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868930097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all_with_rand_reset.3868930097
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3888245865
Short name T163
Test name
Test status
Simulation time 29543000 ps
CPU time 0.9 seconds
Started Jan 07 01:15:53 PM PST 24
Finished Jan 07 01:15:55 PM PST 24
Peak memory 195608 kb
Host smart-524a1cac-82f8-4fc3-8246-7bdcdc375f9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888245865 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3888245865
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.2876181153
Short name T230
Test name
Test status
Simulation time 24305805011 ps
CPU time 394.62 seconds
Started Jan 07 01:15:56 PM PST 24
Finished Jan 07 01:22:33 PM PST 24
Peak memory 198864 kb
Host smart-6ce06e50-be5e-4c71-8d06-b446e1c91cb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876181153 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.2876181153
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2696575439
Short name T711
Test name
Test status
Simulation time 5151212541 ps
CPU time 62.49 seconds
Started Jan 07 01:15:54 PM PST 24
Finished Jan 07 01:16:59 PM PST 24
Peak memory 198788 kb
Host smart-07f07b45-a433-449c-91e7-73c86e8d1ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696575439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2696575439
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2739906254
Short name T323
Test name
Test status
Simulation time 33091609 ps
CPU time 0.6 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:16:16 PM PST 24
Peak memory 193132 kb
Host smart-0579b783-e9d3-40f6-81bf-27df1d87397e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739906254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2739906254
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.613028307
Short name T595
Test name
Test status
Simulation time 8784518817 ps
CPU time 30.88 seconds
Started Jan 07 01:16:04 PM PST 24
Finished Jan 07 01:16:40 PM PST 24
Peak memory 225452 kb
Host smart-9e89ac61-fc0f-4f28-b897-357c1c88fc8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613028307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.613028307
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2045232581
Short name T273
Test name
Test status
Simulation time 1113301311 ps
CPU time 21.21 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:16:31 PM PST 24
Peak memory 198616 kb
Host smart-f91e36a8-a47e-4a3a-af2f-e50e9355f48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045232581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2045232581
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1312692663
Short name T561
Test name
Test status
Simulation time 3696452129 ps
CPU time 41.91 seconds
Started Jan 07 01:15:55 PM PST 24
Finished Jan 07 01:16:39 PM PST 24
Peak memory 198720 kb
Host smart-7647dff4-f5db-4032-b326-54287ff297ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312692663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1312692663
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3533654815
Short name T314
Test name
Test status
Simulation time 3245696266 ps
CPU time 10.43 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:16:26 PM PST 24
Peak memory 198780 kb
Host smart-2be4194e-5e5f-4556-892b-e522f4c2b2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533654815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3533654815
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1620362779
Short name T243
Test name
Test status
Simulation time 2066033536 ps
CPU time 16.16 seconds
Started Jan 07 01:15:56 PM PST 24
Finished Jan 07 01:16:14 PM PST 24
Peak memory 198708 kb
Host smart-151b7542-e59c-4068-8980-5aa8135b81db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620362779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1620362779
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2849985206
Short name T425
Test name
Test status
Simulation time 144497079 ps
CPU time 2.23 seconds
Started Jan 07 01:15:56 PM PST 24
Finished Jan 07 01:16:00 PM PST 24
Peak memory 198300 kb
Host smart-4c2d78c1-bfb7-4e29-8c9b-2ae4dab0c14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849985206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2849985206
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2207145305
Short name T277
Test name
Test status
Simulation time 21082714040 ps
CPU time 476.76 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:24:08 PM PST 24
Peak memory 223508 kb
Host smart-ff3dc407-91d9-4ded-9ec4-122377f009b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207145305 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2207145305
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.3490213303
Short name T723
Test name
Test status
Simulation time 22512581930 ps
CPU time 216.62 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:19:51 PM PST 24
Peak memory 207160 kb
Host smart-9f07b800-3bef-469f-bee7-d42fc0bfde73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490213303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.3490213303
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3799575782
Short name T721
Test name
Test status
Simulation time 30834522 ps
CPU time 1.06 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:16:12 PM PST 24
Peak memory 196840 kb
Host smart-0322ab77-dadf-460a-b7b3-5ea8b519f1fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799575782 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3799575782
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2257090281
Short name T630
Test name
Test status
Simulation time 53974541461 ps
CPU time 417.07 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:23:12 PM PST 24
Peak memory 198848 kb
Host smart-85f86d31-e686-417b-9654-bdb01f69f944
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257090281 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.2257090281
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1842361222
Short name T692
Test name
Test status
Simulation time 1463515458 ps
CPU time 63.89 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:17:17 PM PST 24
Peak memory 198724 kb
Host smart-42c1021d-c1ff-4b57-b0b8-4e7ea11e6016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842361222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1842361222
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.114016703
Short name T600
Test name
Test status
Simulation time 66940783 ps
CPU time 0.55 seconds
Started Jan 07 01:15:59 PM PST 24
Finished Jan 07 01:16:02 PM PST 24
Peak memory 193064 kb
Host smart-8a80169d-61d5-409b-b4ee-cd4e41901a02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114016703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.114016703
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3317423688
Short name T360
Test name
Test status
Simulation time 818211707 ps
CPU time 26.69 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:16:40 PM PST 24
Peak memory 227624 kb
Host smart-4ae1ba30-b28e-4458-bb91-3e2bc587dff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3317423688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3317423688
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1004624321
Short name T322
Test name
Test status
Simulation time 1687512307 ps
CPU time 79.65 seconds
Started Jan 07 01:16:09 PM PST 24
Finished Jan 07 01:17:36 PM PST 24
Peak memory 198596 kb
Host smart-28669317-dcfd-4595-9348-ec2439537591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004624321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1004624321
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2854242626
Short name T633
Test name
Test status
Simulation time 958068484 ps
CPU time 47.26 seconds
Started Jan 07 01:16:10 PM PST 24
Finished Jan 07 01:17:04 PM PST 24
Peak memory 198616 kb
Host smart-7e2024d3-917e-494b-8710-08440da4177a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2854242626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2854242626
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3289002625
Short name T771
Test name
Test status
Simulation time 13906530181 ps
CPU time 81.69 seconds
Started Jan 07 01:16:06 PM PST 24
Finished Jan 07 01:17:32 PM PST 24
Peak memory 198756 kb
Host smart-f1cb0d25-90ee-48cc-96a5-d423fe9b7bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289002625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3289002625
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.995912060
Short name T233
Test name
Test status
Simulation time 30489384111 ps
CPU time 102.73 seconds
Started Jan 07 01:16:00 PM PST 24
Finished Jan 07 01:17:49 PM PST 24
Peak memory 198784 kb
Host smart-307099e9-1eeb-4c89-b8e1-433f3a8e4242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995912060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.995912060
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.927892420
Short name T592
Test name
Test status
Simulation time 386807903 ps
CPU time 3.94 seconds
Started Jan 07 01:16:05 PM PST 24
Finished Jan 07 01:16:13 PM PST 24
Peak memory 198504 kb
Host smart-c96e7007-45bd-46de-b456-5116e071c7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927892420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.927892420
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.636952930
Short name T297
Test name
Test status
Simulation time 23637854614 ps
CPU time 92.78 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:17:43 PM PST 24
Peak memory 198880 kb
Host smart-176a5e34-0b90-4fdf-b2f7-8c3ffb2ade30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636952930 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.636952930
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.3910182875
Short name T102
Test name
Test status
Simulation time 103117374643 ps
CPU time 1670.48 seconds
Started Jan 07 01:16:05 PM PST 24
Finished Jan 07 01:44:00 PM PST 24
Peak memory 248084 kb
Host smart-f35d9a08-0b1d-4ec2-a801-308c22b6251a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910182875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.3910182875
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3131147301
Short name T545
Test name
Test status
Simulation time 44521511 ps
CPU time 0.94 seconds
Started Jan 07 01:15:58 PM PST 24
Finished Jan 07 01:16:02 PM PST 24
Peak memory 195788 kb
Host smart-4fac5171-f142-49d3-8055-f504dc7b58b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131147301 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3131147301
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.372423170
Short name T456
Test name
Test status
Simulation time 25612843600 ps
CPU time 407.6 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:23:02 PM PST 24
Peak memory 198816 kb
Host smart-e427d54a-fea1-45b1-b4e5-01a3e623a3a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372423170 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.hmac_test_sha_vectors.372423170
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3836406783
Short name T809
Test name
Test status
Simulation time 12650530952 ps
CPU time 51.54 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:17:05 PM PST 24
Peak memory 198892 kb
Host smart-3c584354-0cca-40c9-abb0-0aa92ff6aebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836406783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3836406783
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1439047259
Short name T188
Test name
Test status
Simulation time 22685228 ps
CPU time 0.56 seconds
Started Jan 07 01:14:06 PM PST 24
Finished Jan 07 01:14:08 PM PST 24
Peak memory 194120 kb
Host smart-00e2642f-6404-406e-96bd-50cafa0a82b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439047259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1439047259
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3214915632
Short name T603
Test name
Test status
Simulation time 1681417481 ps
CPU time 9.46 seconds
Started Jan 07 01:14:00 PM PST 24
Finished Jan 07 01:14:10 PM PST 24
Peak memory 214388 kb
Host smart-34b30b7d-ad2e-441d-a573-49ca7c6c0438
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3214915632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3214915632
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1694676173
Short name T703
Test name
Test status
Simulation time 4947803982 ps
CPU time 44.07 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:48 PM PST 24
Peak memory 198848 kb
Host smart-cff5ac32-d992-4fb8-ab48-bf391b37a2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694676173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1694676173
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3875621329
Short name T784
Test name
Test status
Simulation time 1043541153 ps
CPU time 56.07 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:15:00 PM PST 24
Peak memory 198692 kb
Host smart-0760d986-5bcd-4084-804a-8355de9d14c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875621329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3875621329
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3569389252
Short name T729
Test name
Test status
Simulation time 1725774420 ps
CPU time 87.72 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:15:30 PM PST 24
Peak memory 198640 kb
Host smart-3605b4c8-c804-4d19-a66e-6d99faa98b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569389252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3569389252
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.4077983114
Short name T408
Test name
Test status
Simulation time 4563113394 ps
CPU time 55.84 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:14:58 PM PST 24
Peak memory 198856 kb
Host smart-41da5d4d-e7b3-4118-adf5-e7938410dcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077983114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.4077983114
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3100127592
Short name T56
Test name
Test status
Simulation time 466985062 ps
CPU time 0.95 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:05 PM PST 24
Peak memory 217136 kb
Host smart-1484d858-1634-4350-95f1-f896b4abc26a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100127592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3100127592
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1194865722
Short name T268
Test name
Test status
Simulation time 184478980 ps
CPU time 4.3 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:14:07 PM PST 24
Peak memory 198708 kb
Host smart-dc26a337-f242-46a2-a5ce-515e82446ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194865722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1194865722
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.613140067
Short name T584
Test name
Test status
Simulation time 735665084269 ps
CPU time 2024.82 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:47:49 PM PST 24
Peak memory 231512 kb
Host smart-9389c494-437b-4796-9ec4-67e1edd3ebc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613140067 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.613140067
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1798948512
Short name T667
Test name
Test status
Simulation time 75011519485 ps
CPU time 911.97 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:29:14 PM PST 24
Peak memory 240828 kb
Host smart-ae7046af-906e-4bc9-90ee-4caaa8cad6b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1798948512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1798948512
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.290415591
Short name T282
Test name
Test status
Simulation time 30514552 ps
CPU time 1.04 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:14:03 PM PST 24
Peak memory 197100 kb
Host smart-7bcb85e7-0ae1-4e94-9af2-0df337111ab2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290415591 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.290415591
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.4085718630
Short name T551
Test name
Test status
Simulation time 2267778513 ps
CPU time 39.43 seconds
Started Jan 07 01:14:06 PM PST 24
Finished Jan 07 01:14:46 PM PST 24
Peak memory 198696 kb
Host smart-4e80e196-b271-496c-88aa-d4e34ee7db04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085718630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.4085718630
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3843783098
Short name T788
Test name
Test status
Simulation time 47320089 ps
CPU time 0.57 seconds
Started Jan 07 01:16:05 PM PST 24
Finished Jan 07 01:16:10 PM PST 24
Peak memory 193084 kb
Host smart-1a5f05f9-96e0-4fdc-afaf-a72cd0e7251b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843783098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3843783098
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2255035465
Short name T695
Test name
Test status
Simulation time 1457564788 ps
CPU time 12.76 seconds
Started Jan 07 01:16:06 PM PST 24
Finished Jan 07 01:16:23 PM PST 24
Peak memory 206884 kb
Host smart-46bf1211-a744-476d-a6be-011c9502b97c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2255035465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2255035465
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2264317705
Short name T677
Test name
Test status
Simulation time 77881878 ps
CPU time 1.82 seconds
Started Jan 07 01:16:01 PM PST 24
Finished Jan 07 01:16:09 PM PST 24
Peak memory 198628 kb
Host smart-32803ebf-649c-494f-8ed1-bc5756727839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264317705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2264317705
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3717462624
Short name T192
Test name
Test status
Simulation time 1628627620 ps
CPU time 85.02 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:17:40 PM PST 24
Peak memory 198608 kb
Host smart-1a5c1a5a-9a96-4a97-a919-3aed69fedb85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3717462624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3717462624
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1527637573
Short name T264
Test name
Test status
Simulation time 401621645 ps
CPU time 10.31 seconds
Started Jan 07 01:16:00 PM PST 24
Finished Jan 07 01:16:16 PM PST 24
Peak memory 198668 kb
Host smart-eadbf270-54b7-4237-9937-0c9f300c9358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527637573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1527637573
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1721778141
Short name T560
Test name
Test status
Simulation time 6597451298 ps
CPU time 83.14 seconds
Started Jan 07 01:15:59 PM PST 24
Finished Jan 07 01:17:25 PM PST 24
Peak memory 198884 kb
Host smart-7ce93083-0215-4c4f-b734-2a685e188c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721778141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1721778141
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2188539635
Short name T823
Test name
Test status
Simulation time 380014434 ps
CPU time 3.91 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:16:15 PM PST 24
Peak memory 198184 kb
Host smart-a0b7e726-5ca9-484c-b0c9-9a6f739970d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188539635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2188539635
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2124900722
Short name T333
Test name
Test status
Simulation time 124597748748 ps
CPU time 1756.3 seconds
Started Jan 07 01:16:09 PM PST 24
Finished Jan 07 01:45:33 PM PST 24
Peak memory 239736 kb
Host smart-1732ae2f-30b3-4a2f-bcd3-1bb2c4ebf372
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124900722 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2124900722
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.1163871020
Short name T109
Test name
Test status
Simulation time 528029660195 ps
CPU time 1769.26 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:45:45 PM PST 24
Peak memory 256228 kb
Host smart-7f95e311-e949-4dba-b870-f08d13e26e00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1163871020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.1163871020
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2766297667
Short name T627
Test name
Test status
Simulation time 232789358 ps
CPU time 0.97 seconds
Started Jan 07 01:16:06 PM PST 24
Finished Jan 07 01:16:11 PM PST 24
Peak memory 196984 kb
Host smart-dc6acf8c-6205-4ce1-8d10-9ebcc742c4a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766297667 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2766297667
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2563484859
Short name T369
Test name
Test status
Simulation time 34682763604 ps
CPU time 442.39 seconds
Started Jan 07 01:16:06 PM PST 24
Finished Jan 07 01:23:32 PM PST 24
Peak memory 198760 kb
Host smart-6310a94c-0c92-4d92-9550-a6e7184d4554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563484859 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.2563484859
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1092129454
Short name T550
Test name
Test status
Simulation time 1623944717 ps
CPU time 71.66 seconds
Started Jan 07 01:15:59 PM PST 24
Finished Jan 07 01:17:13 PM PST 24
Peak memory 198648 kb
Host smart-3e52ebf2-84b3-4bab-9c90-276123bbf11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092129454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1092129454
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3940608752
Short name T421
Test name
Test status
Simulation time 17228104 ps
CPU time 0.56 seconds
Started Jan 07 01:16:06 PM PST 24
Finished Jan 07 01:16:10 PM PST 24
Peak memory 193004 kb
Host smart-23914604-b91e-4804-b57b-d24a6248b0af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940608752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3940608752
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1960541279
Short name T313
Test name
Test status
Simulation time 2815217343 ps
CPU time 26.09 seconds
Started Jan 07 01:16:06 PM PST 24
Finished Jan 07 01:16:36 PM PST 24
Peak memory 238708 kb
Host smart-7666b51d-b23a-4319-8c75-b31d82b16c66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960541279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1960541279
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1774453727
Short name T654
Test name
Test status
Simulation time 1289850251 ps
CPU time 17.92 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:16:28 PM PST 24
Peak memory 198704 kb
Host smart-4500a154-7810-4cf1-a36f-042b37b9c3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774453727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1774453727
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.225156331
Short name T799
Test name
Test status
Simulation time 97884672 ps
CPU time 0.59 seconds
Started Jan 07 01:16:10 PM PST 24
Finished Jan 07 01:16:18 PM PST 24
Peak memory 193876 kb
Host smart-a6292dd0-d5fa-4de9-8d6a-655a24b397c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=225156331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.225156331
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1609153735
Short name T659
Test name
Test status
Simulation time 33464609431 ps
CPU time 149.1 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:18:44 PM PST 24
Peak memory 198780 kb
Host smart-0d4c6b8a-4fe1-4fb9-9be7-551018f37d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609153735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1609153735
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3351979194
Short name T187
Test name
Test status
Simulation time 18941661527 ps
CPU time 83.07 seconds
Started Jan 07 01:15:59 PM PST 24
Finished Jan 07 01:17:28 PM PST 24
Peak memory 198824 kb
Host smart-feddf76c-50da-47fc-9361-47249a9dad19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351979194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3351979194
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1462706769
Short name T287
Test name
Test status
Simulation time 274240249 ps
CPU time 3.21 seconds
Started Jan 07 01:16:01 PM PST 24
Finished Jan 07 01:16:11 PM PST 24
Peak memory 198536 kb
Host smart-87672416-e3f1-4d58-9cc1-cd1b49b9b151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462706769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1462706769
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3788780311
Short name T293
Test name
Test status
Simulation time 486276319704 ps
CPU time 1469.89 seconds
Started Jan 07 01:16:05 PM PST 24
Finished Jan 07 01:40:40 PM PST 24
Peak memory 239788 kb
Host smart-806ea370-74f7-4d27-8ebd-c3ba988abe98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788780311 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3788780311
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.1451754178
Short name T390
Test name
Test status
Simulation time 240677112653 ps
CPU time 1890.44 seconds
Started Jan 07 01:16:06 PM PST 24
Finished Jan 07 01:47:41 PM PST 24
Peak memory 249636 kb
Host smart-471ab74a-e556-4180-b091-576a33d91b29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451754178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.1451754178
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3221440360
Short name T559
Test name
Test status
Simulation time 31774419 ps
CPU time 1.04 seconds
Started Jan 07 01:16:05 PM PST 24
Finished Jan 07 01:16:10 PM PST 24
Peak memory 196300 kb
Host smart-0a915df6-a90a-46db-9465-d45d93cbf8b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221440360 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3221440360
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1557075480
Short name T609
Test name
Test status
Simulation time 23278613727 ps
CPU time 388.43 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:22:43 PM PST 24
Peak memory 198752 kb
Host smart-e502fff0-f22f-404c-b272-01376549871b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557075480 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.1557075480
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1863504459
Short name T274
Test name
Test status
Simulation time 24093454634 ps
CPU time 75.7 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:17:31 PM PST 24
Peak memory 198800 kb
Host smart-c970de4f-a89c-42a4-8e2d-2a95c3e6a1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863504459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1863504459
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1539261030
Short name T53
Test name
Test status
Simulation time 46280106 ps
CPU time 0.56 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:16:16 PM PST 24
Peak memory 193080 kb
Host smart-77f237ea-98bb-474d-8b18-09a8059af562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539261030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1539261030
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2392215379
Short name T398
Test name
Test status
Simulation time 5052856230 ps
CPU time 42.44 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:16:55 PM PST 24
Peak memory 239816 kb
Host smart-ffb65687-797c-41fc-801c-874c020f0627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392215379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2392215379
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1199348272
Short name T767
Test name
Test status
Simulation time 4381723867 ps
CPU time 38.05 seconds
Started Jan 07 01:16:09 PM PST 24
Finished Jan 07 01:16:54 PM PST 24
Peak memory 198844 kb
Host smart-7e637f44-b1c5-4915-8d18-f7903a7b7af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199348272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1199348272
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.328121941
Short name T480
Test name
Test status
Simulation time 2451597117 ps
CPU time 124.73 seconds
Started Jan 07 01:16:07 PM PST 24
Finished Jan 07 01:18:15 PM PST 24
Peak memory 198744 kb
Host smart-9fc9cd74-c377-4674-aa00-e7331893f0bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328121941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.328121941
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3338030883
Short name T634
Test name
Test status
Simulation time 42491586265 ps
CPU time 117.64 seconds
Started Jan 07 01:16:06 PM PST 24
Finished Jan 07 01:18:08 PM PST 24
Peak memory 198800 kb
Host smart-90d9670f-c4aa-46b2-b284-6ec7dd5ebd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338030883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3338030883
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.140847864
Short name T164
Test name
Test status
Simulation time 982361635 ps
CPU time 16.99 seconds
Started Jan 07 01:16:05 PM PST 24
Finished Jan 07 01:16:26 PM PST 24
Peak memory 198636 kb
Host smart-ef8e4270-2b7b-4cec-93c4-149bb5f23814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140847864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.140847864
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3922246761
Short name T443
Test name
Test status
Simulation time 433815732 ps
CPU time 2.83 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:16:17 PM PST 24
Peak memory 198740 kb
Host smart-1440ae8b-3ee7-4e1c-ba00-89c3c5bd2667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922246761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3922246761
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1548220301
Short name T125
Test name
Test status
Simulation time 2248490201 ps
CPU time 75.56 seconds
Started Jan 07 01:16:01 PM PST 24
Finished Jan 07 01:17:23 PM PST 24
Peak memory 207024 kb
Host smart-172ccdd6-f113-4cf3-926f-e01c67879aaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548220301 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1548220301
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.1300856807
Short name T118
Test name
Test status
Simulation time 31112222706 ps
CPU time 1440.64 seconds
Started Jan 07 01:16:08 PM PST 24
Finished Jan 07 01:40:16 PM PST 24
Peak memory 241684 kb
Host smart-d78f8042-e583-4425-9e9d-84758bc22f7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300856807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.1300856807
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2816567845
Short name T209
Test name
Test status
Simulation time 50270909 ps
CPU time 0.94 seconds
Started Jan 07 01:15:58 PM PST 24
Finished Jan 07 01:16:02 PM PST 24
Peak memory 197172 kb
Host smart-97e6a0cf-9458-473f-b09d-7bbcff77dea1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816567845 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2816567845
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2488241094
Short name T225
Test name
Test status
Simulation time 17226045378 ps
CPU time 420.2 seconds
Started Jan 07 01:16:05 PM PST 24
Finished Jan 07 01:23:10 PM PST 24
Peak memory 198796 kb
Host smart-81e6cfb9-06e9-422b-86a8-983823121b0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488241094 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.2488241094
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1991511726
Short name T558
Test name
Test status
Simulation time 6594307936 ps
CPU time 90.48 seconds
Started Jan 07 01:16:06 PM PST 24
Finished Jan 07 01:17:40 PM PST 24
Peak memory 198820 kb
Host smart-7d7f86d7-88df-40bb-a1ee-42da0a22360a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991511726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1991511726
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1183217696
Short name T381
Test name
Test status
Simulation time 15015177 ps
CPU time 0.58 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 01:16:24 PM PST 24
Peak memory 193248 kb
Host smart-574a9589-4ab3-4d67-bac3-b5b6b3256328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183217696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1183217696
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1428725610
Short name T41
Test name
Test status
Simulation time 202407926 ps
CPU time 5.82 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 01:16:30 PM PST 24
Peak memory 206904 kb
Host smart-24f1f7a8-d49c-4403-a74d-e68b53b5bbcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428725610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1428725610
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1380232394
Short name T203
Test name
Test status
Simulation time 1391973217 ps
CPU time 57.25 seconds
Started Jan 07 01:16:24 PM PST 24
Finished Jan 07 01:17:24 PM PST 24
Peak memory 198744 kb
Host smart-f57d40a5-f2c5-430e-b369-9506fba652db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380232394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1380232394
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.796490310
Short name T201
Test name
Test status
Simulation time 934235474 ps
CPU time 49.29 seconds
Started Jan 07 01:16:21 PM PST 24
Finished Jan 07 01:17:13 PM PST 24
Peak memory 198676 kb
Host smart-df2b45ca-36b1-43fc-b955-20c1ade95e49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=796490310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.796490310
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.712204257
Short name T305
Test name
Test status
Simulation time 1445176046 ps
CPU time 74.42 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:17:40 PM PST 24
Peak memory 198692 kb
Host smart-5c0beb6a-fab2-4449-83f1-06dadcabfb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712204257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.712204257
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2270325069
Short name T706
Test name
Test status
Simulation time 20890023316 ps
CPU time 22.41 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:16:48 PM PST 24
Peak memory 198748 kb
Host smart-82b3fc5b-bc49-46cc-a4a9-dd2757364b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270325069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2270325069
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3567776978
Short name T326
Test name
Test status
Simulation time 146417218 ps
CPU time 2.24 seconds
Started Jan 07 01:16:06 PM PST 24
Finished Jan 07 01:16:12 PM PST 24
Peak memory 198724 kb
Host smart-611942b0-d493-48a5-b15d-7137706b5a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567776978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3567776978
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1277571289
Short name T255
Test name
Test status
Simulation time 63734140342 ps
CPU time 540.77 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 01:25:25 PM PST 24
Peak memory 216304 kb
Host smart-d6a2898d-534c-4ac4-afe4-db38590fc81b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277571289 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1277571289
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2275529981
Short name T306
Test name
Test status
Simulation time 106762375 ps
CPU time 1.07 seconds
Started Jan 07 01:16:20 PM PST 24
Finished Jan 07 01:16:25 PM PST 24
Peak memory 196728 kb
Host smart-5c85fadf-9e86-4fd4-a398-65a93711549f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275529981 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2275529981
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2432994397
Short name T436
Test name
Test status
Simulation time 88546676853 ps
CPU time 358.03 seconds
Started Jan 07 01:16:24 PM PST 24
Finished Jan 07 01:22:24 PM PST 24
Peak memory 198860 kb
Host smart-1baf4cc6-e16f-4596-9756-9ca24edf8743
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432994397 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.2432994397
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.176402373
Short name T182
Test name
Test status
Simulation time 4995521333 ps
CPU time 82.97 seconds
Started Jan 07 01:16:27 PM PST 24
Finished Jan 07 01:17:51 PM PST 24
Peak memory 198848 kb
Host smart-bba55942-eaa0-464f-8860-91c537a0ad7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176402373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.176402373
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.358346881
Short name T742
Test name
Test status
Simulation time 15846397 ps
CPU time 0.56 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 01:16:24 PM PST 24
Peak memory 193140 kb
Host smart-1e9cac0c-cd86-4293-9ca8-430646588807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358346881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.358346881
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1578053785
Short name T806
Test name
Test status
Simulation time 1469139694 ps
CPU time 10.38 seconds
Started Jan 07 01:16:20 PM PST 24
Finished Jan 07 01:16:34 PM PST 24
Peak memory 198680 kb
Host smart-b84cd6e2-d8fd-434a-8115-49d105ac8392
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578053785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1578053785
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2684164140
Short name T585
Test name
Test status
Simulation time 1934390450 ps
CPU time 36.89 seconds
Started Jan 07 01:16:21 PM PST 24
Finished Jan 07 01:17:01 PM PST 24
Peak memory 198708 kb
Host smart-8a661d1d-b4c4-4015-a319-23ef4015497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684164140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2684164140
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2525039707
Short name T97
Test name
Test status
Simulation time 209829252 ps
CPU time 9.53 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 01:16:34 PM PST 24
Peak memory 198680 kb
Host smart-b17ac847-7db9-430b-854a-efe512b24141
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525039707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2525039707
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3942140979
Short name T520
Test name
Test status
Simulation time 17956009515 ps
CPU time 72.17 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:17:38 PM PST 24
Peak memory 198812 kb
Host smart-292cdbc7-6181-429e-8736-d8c2b0254370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942140979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3942140979
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3020435065
Short name T440
Test name
Test status
Simulation time 8263447173 ps
CPU time 137.95 seconds
Started Jan 07 01:16:29 PM PST 24
Finished Jan 07 01:18:48 PM PST 24
Peak memory 198800 kb
Host smart-fc45d1b9-4d9a-4db3-847a-cc12cc42cc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020435065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3020435065
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3973126524
Short name T358
Test name
Test status
Simulation time 226800938 ps
CPU time 1.75 seconds
Started Jan 07 01:16:12 PM PST 24
Finished Jan 07 01:16:19 PM PST 24
Peak memory 198360 kb
Host smart-61375f0b-1b3c-44e1-b6d9-1464e8131a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973126524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3973126524
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3391438377
Short name T817
Test name
Test status
Simulation time 86601808261 ps
CPU time 1024.19 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:33:30 PM PST 24
Peak memory 215264 kb
Host smart-dcc9660e-9a67-4c66-a547-f48ce788c994
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391438377 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3391438377
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.2226559347
Short name T266
Test name
Test status
Simulation time 135925459180 ps
CPU time 1204.38 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:36:30 PM PST 24
Peak memory 239928 kb
Host smart-b369f9ac-ab22-438d-874e-ebea6ad2e7c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226559347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.2226559347
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3876018834
Short name T302
Test name
Test status
Simulation time 32713798 ps
CPU time 1.1 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:16:27 PM PST 24
Peak memory 197224 kb
Host smart-d4e113aa-3563-400a-8269-975e08ab781f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876018834 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3876018834
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1767933424
Short name T768
Test name
Test status
Simulation time 51183059256 ps
CPU time 397.3 seconds
Started Jan 07 01:16:20 PM PST 24
Finished Jan 07 01:23:01 PM PST 24
Peak memory 198868 kb
Host smart-e4874f9b-b0eb-4013-8244-0c550829a35a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767933424 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.1767933424
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2482583116
Short name T736
Test name
Test status
Simulation time 3336520405 ps
CPU time 61.48 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:17:26 PM PST 24
Peak memory 198732 kb
Host smart-332bdf3d-e230-4b6d-a714-c2a8e2672331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482583116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2482583116
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.908318579
Short name T283
Test name
Test status
Simulation time 15909692 ps
CPU time 0.57 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:16:26 PM PST 24
Peak memory 193024 kb
Host smart-6d31b2bc-cc9c-4b41-83c8-b54911eaa791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908318579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.908318579
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3948101299
Short name T577
Test name
Test status
Simulation time 359524792 ps
CPU time 3.25 seconds
Started Jan 07 01:16:10 PM PST 24
Finished Jan 07 01:16:20 PM PST 24
Peak memory 206856 kb
Host smart-9ad4cb93-510b-45db-a983-dfc2c81adc20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3948101299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3948101299
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.4153141025
Short name T491
Test name
Test status
Simulation time 9986070553 ps
CPU time 50.24 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:17:15 PM PST 24
Peak memory 198784 kb
Host smart-a4c35a67-5934-4dec-b096-1f4e6634bb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153141025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.4153141025
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2065589522
Short name T472
Test name
Test status
Simulation time 1932399808 ps
CPU time 101.59 seconds
Started Jan 07 01:16:24 PM PST 24
Finished Jan 07 01:18:07 PM PST 24
Peak memory 198692 kb
Host smart-b58d72b6-81a0-43a8-8321-4ac82b81df74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065589522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2065589522
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2971548860
Short name T604
Test name
Test status
Simulation time 37034396689 ps
CPU time 152.3 seconds
Started Jan 07 01:16:24 PM PST 24
Finished Jan 07 01:18:59 PM PST 24
Peak memory 198800 kb
Host smart-ba1bcac1-6a81-4a5b-b463-65f0cb308991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971548860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2971548860
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2807292472
Short name T619
Test name
Test status
Simulation time 1035327758 ps
CPU time 19.25 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:16:44 PM PST 24
Peak memory 198692 kb
Host smart-349b0551-e2f4-4da2-8002-218209d353cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807292472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2807292472
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.423778752
Short name T199
Test name
Test status
Simulation time 182279146 ps
CPU time 4.23 seconds
Started Jan 07 01:16:10 PM PST 24
Finished Jan 07 01:16:21 PM PST 24
Peak memory 198484 kb
Host smart-61c657fe-d579-4b6c-a718-30bd14e57dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423778752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.423778752
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2568123031
Short name T300
Test name
Test status
Simulation time 317859277736 ps
CPU time 907.4 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 01:31:31 PM PST 24
Peak memory 198792 kb
Host smart-1c7db0c8-5569-41d2-a8d1-0a63f21817cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568123031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2568123031
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.4179684084
Short name T488
Test name
Test status
Simulation time 43090329 ps
CPU time 0.92 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:16:26 PM PST 24
Peak memory 196592 kb
Host smart-1b60f560-007f-4425-abee-48d42b044389
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179684084 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.4179684084
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3272373569
Short name T337
Test name
Test status
Simulation time 64881006140 ps
CPU time 402.09 seconds
Started Jan 07 01:16:21 PM PST 24
Finished Jan 07 01:23:06 PM PST 24
Peak memory 198756 kb
Host smart-a2bb57fc-9cea-4b81-8049-bedb80929bf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272373569 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.3272373569
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4259262156
Short name T470
Test name
Test status
Simulation time 3219491591 ps
CPU time 59.27 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 01:17:23 PM PST 24
Peak memory 198736 kb
Host smart-24d76182-42c0-4f0e-823e-ad19b02234e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259262156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4259262156
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.480457424
Short name T234
Test name
Test status
Simulation time 14318633 ps
CPU time 0.58 seconds
Started Jan 07 01:16:20 PM PST 24
Finished Jan 07 01:16:24 PM PST 24
Peak memory 193152 kb
Host smart-f5c45d59-6de3-4aa5-8ff3-8a6bbac06f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480457424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.480457424
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1412145578
Short name T811
Test name
Test status
Simulation time 8780331745 ps
CPU time 17.43 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:16:43 PM PST 24
Peak memory 207032 kb
Host smart-f9008cfd-ca46-4b17-b0ee-6acf07edaca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1412145578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1412145578
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1466678666
Short name T505
Test name
Test status
Simulation time 16831915458 ps
CPU time 51.7 seconds
Started Jan 07 01:16:28 PM PST 24
Finished Jan 07 01:17:21 PM PST 24
Peak memory 198796 kb
Host smart-bbe24267-6cca-45ab-b917-c2855b510aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466678666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1466678666
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.356624908
Short name T62
Test name
Test status
Simulation time 793716682 ps
CPU time 14.72 seconds
Started Jan 07 01:16:24 PM PST 24
Finished Jan 07 01:16:41 PM PST 24
Peak memory 198648 kb
Host smart-b38c55c6-c969-4b27-a286-09286924e4ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356624908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.356624908
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2022022616
Short name T489
Test name
Test status
Simulation time 3496412142 ps
CPU time 28.15 seconds
Started Jan 07 01:16:11 PM PST 24
Finished Jan 07 01:16:45 PM PST 24
Peak memory 198848 kb
Host smart-0c73d2c6-d125-4a39-93bd-7b2e79508696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022022616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2022022616
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1827761543
Short name T747
Test name
Test status
Simulation time 6662850399 ps
CPU time 88.8 seconds
Started Jan 07 01:16:26 PM PST 24
Finished Jan 07 01:17:57 PM PST 24
Peak memory 198836 kb
Host smart-b99999cf-7a3d-4728-a010-e3ba19725920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827761543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1827761543
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2550029923
Short name T797
Test name
Test status
Simulation time 404161969 ps
CPU time 4.22 seconds
Started Jan 07 01:16:21 PM PST 24
Finished Jan 07 01:16:28 PM PST 24
Peak memory 198504 kb
Host smart-996766ce-262e-433e-a64e-0144ffb444b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550029923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2550029923
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2797363883
Short name T598
Test name
Test status
Simulation time 304734213159 ps
CPU time 876.97 seconds
Started Jan 07 01:16:24 PM PST 24
Finished Jan 07 01:31:04 PM PST 24
Peak memory 198736 kb
Host smart-33fae9bc-4410-47de-9e73-90c71e56028d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797363883 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2797363883
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.2018850420
Short name T814
Test name
Test status
Simulation time 203795030357 ps
CPU time 2424.37 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 01:56:48 PM PST 24
Peak memory 248108 kb
Host smart-3a2080ab-45cc-4391-95a1-23af59f90b2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018850420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.2018850420
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2627168325
Short name T222
Test name
Test status
Simulation time 236989749 ps
CPU time 0.96 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 01:16:25 PM PST 24
Peak memory 196556 kb
Host smart-92aad19c-6c88-4b9d-97fc-b9463fc2f357
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627168325 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.2627168325
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.326043376
Short name T330
Test name
Test status
Simulation time 33536816910 ps
CPU time 368.48 seconds
Started Jan 07 01:16:23 PM PST 24
Finished Jan 07 01:22:34 PM PST 24
Peak memory 198812 kb
Host smart-9e7cc4dc-7c03-4b8a-8952-1e4a25b4b11e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326043376 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.hmac_test_sha_vectors.326043376
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2074626349
Short name T755
Test name
Test status
Simulation time 3349886026 ps
CPU time 43.69 seconds
Started Jan 07 01:16:20 PM PST 24
Finished Jan 07 01:17:07 PM PST 24
Peak memory 198804 kb
Host smart-130122dc-f1af-4d26-a3bf-679d17f496e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074626349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2074626349
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2981342821
Short name T475
Test name
Test status
Simulation time 48574516 ps
CPU time 0.56 seconds
Started Jan 07 01:16:27 PM PST 24
Finished Jan 07 01:16:29 PM PST 24
Peak memory 194156 kb
Host smart-5e83aff5-4a81-43aa-be22-9f62b5c0aad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981342821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2981342821
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1725147154
Short name T253
Test name
Test status
Simulation time 4233622946 ps
CPU time 31.92 seconds
Started Jan 07 01:16:25 PM PST 24
Finished Jan 07 01:17:00 PM PST 24
Peak memory 215220 kb
Host smart-2d501e59-128e-423f-942e-709aef6675d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725147154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1725147154
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1269813048
Short name T432
Test name
Test status
Simulation time 1762671237 ps
CPU time 25.42 seconds
Started Jan 07 01:16:26 PM PST 24
Finished Jan 07 01:16:54 PM PST 24
Peak memory 198624 kb
Host smart-9ccce506-a685-4e86-80c4-542e3338b7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269813048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1269813048
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.774944712
Short name T643
Test name
Test status
Simulation time 1134286517 ps
CPU time 53.72 seconds
Started Jan 07 01:16:34 PM PST 24
Finished Jan 07 01:17:29 PM PST 24
Peak memory 198512 kb
Host smart-8417bb63-02bd-42bd-a376-f26471c9e1ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=774944712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.774944712
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1117686233
Short name T205
Test name
Test status
Simulation time 13226553273 ps
CPU time 82.65 seconds
Started Jan 07 01:16:40 PM PST 24
Finished Jan 07 01:18:04 PM PST 24
Peak memory 198652 kb
Host smart-72716901-df6c-46fb-819e-ba782745b2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117686233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1117686233
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1293444104
Short name T737
Test name
Test status
Simulation time 615290824 ps
CPU time 16.29 seconds
Started Jan 07 01:16:25 PM PST 24
Finished Jan 07 01:16:44 PM PST 24
Peak memory 198704 kb
Host smart-7f6626e8-545c-4e7d-af1c-073aff0db0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293444104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1293444104
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.652576304
Short name T569
Test name
Test status
Simulation time 328004916 ps
CPU time 2.43 seconds
Started Jan 07 01:16:28 PM PST 24
Finished Jan 07 01:16:32 PM PST 24
Peak memory 198660 kb
Host smart-ba83345b-be9b-4d0e-a9e2-d073c2a8077d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652576304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.652576304
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.120328591
Short name T779
Test name
Test status
Simulation time 20111734453 ps
CPU time 950.12 seconds
Started Jan 07 01:16:24 PM PST 24
Finished Jan 07 01:32:17 PM PST 24
Peak memory 223380 kb
Host smart-3737de76-8d63-4a2b-a22d-b21634d4c857
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120328591 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.120328591
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.1707732289
Short name T61
Test name
Test status
Simulation time 35906207965 ps
CPU time 608.68 seconds
Started Jan 07 01:16:44 PM PST 24
Finished Jan 07 01:26:53 PM PST 24
Peak memory 206920 kb
Host smart-6c1bcb48-737e-4753-ac7d-ad04c65e1fc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707732289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.1707732289
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.9044969
Short name T605
Test name
Test status
Simulation time 26380116 ps
CPU time 0.82 seconds
Started Jan 07 01:16:32 PM PST 24
Finished Jan 07 01:16:34 PM PST 24
Peak memory 195768 kb
Host smart-c20fc270-0a23-4d1a-9314-b88b5c718bc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9044969 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.hmac_test_hmac_vectors.9044969
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2198719138
Short name T335
Test name
Test status
Simulation time 42729241763 ps
CPU time 378.64 seconds
Started Jan 07 01:16:24 PM PST 24
Finished Jan 07 01:22:46 PM PST 24
Peak memory 198792 kb
Host smart-f66bb56c-d415-41d8-bd2f-b7395e580725
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198719138 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.2198719138
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3453890785
Short name T725
Test name
Test status
Simulation time 1751037054 ps
CPU time 16.23 seconds
Started Jan 07 01:16:37 PM PST 24
Finished Jan 07 01:16:54 PM PST 24
Peak memory 198552 kb
Host smart-8e70214b-10c0-471c-84e7-eed18628f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453890785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3453890785
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.627222481
Short name T794
Test name
Test status
Simulation time 11729075 ps
CPU time 0.56 seconds
Started Jan 07 01:16:33 PM PST 24
Finished Jan 07 01:16:34 PM PST 24
Peak memory 193004 kb
Host smart-c1b9016c-0804-4754-86d6-8bfb39873d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627222481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.627222481
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4234334290
Short name T224
Test name
Test status
Simulation time 1383455654 ps
CPU time 51.05 seconds
Started Jan 07 01:16:28 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 227412 kb
Host smart-de4b5900-1539-47f6-96c3-8fb562681eec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234334290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4234334290
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2689629593
Short name T295
Test name
Test status
Simulation time 686452047 ps
CPU time 31.5 seconds
Started Jan 07 01:16:26 PM PST 24
Finished Jan 07 01:17:00 PM PST 24
Peak memory 198760 kb
Host smart-a84566bf-d51f-4d1f-b2ea-8a52c5a9df90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689629593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2689629593
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1542040140
Short name T420
Test name
Test status
Simulation time 1205025470 ps
CPU time 29.11 seconds
Started Jan 07 01:16:26 PM PST 24
Finished Jan 07 01:16:58 PM PST 24
Peak memory 198612 kb
Host smart-78c94fa2-e11d-48b0-b72a-18d0f86e7e14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1542040140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1542040140
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3543577562
Short name T247
Test name
Test status
Simulation time 11757329057 ps
CPU time 127.53 seconds
Started Jan 07 01:16:25 PM PST 24
Finished Jan 07 01:18:36 PM PST 24
Peak memory 198832 kb
Host smart-6162f5cf-dc67-42af-beee-b319d43625be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543577562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3543577562
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3708263000
Short name T790
Test name
Test status
Simulation time 124280384 ps
CPU time 5.82 seconds
Started Jan 07 01:16:25 PM PST 24
Finished Jan 07 01:16:33 PM PST 24
Peak memory 198656 kb
Host smart-120a67d2-6cf7-4e7c-a7a9-a5cf7b7cf9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708263000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3708263000
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1044057296
Short name T787
Test name
Test status
Simulation time 44324986 ps
CPU time 1.28 seconds
Started Jan 07 01:16:33 PM PST 24
Finished Jan 07 01:16:35 PM PST 24
Peak memory 197596 kb
Host smart-f0cf14de-9962-447a-adb0-764475a921a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044057296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1044057296
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1699903403
Short name T509
Test name
Test status
Simulation time 123124879516 ps
CPU time 1977.38 seconds
Started Jan 07 01:16:44 PM PST 24
Finished Jan 07 01:49:42 PM PST 24
Peak memory 206848 kb
Host smart-d84f91e4-f412-4960-bf8d-d81e72e828d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699903403 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1699903403
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.3026848119
Short name T615
Test name
Test status
Simulation time 143336007095 ps
CPU time 2151.74 seconds
Started Jan 07 01:16:25 PM PST 24
Finished Jan 07 01:52:20 PM PST 24
Peak memory 263420 kb
Host smart-a6c92d14-e609-4cd0-9f22-d00bbfb2aeb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3026848119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.3026848119
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.834351831
Short name T728
Test name
Test status
Simulation time 77726633 ps
CPU time 0.97 seconds
Started Jan 07 01:16:25 PM PST 24
Finished Jan 07 01:16:28 PM PST 24
Peak memory 196548 kb
Host smart-af7083e0-852a-465e-a945-4600262ad9af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834351831 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.834351831
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2557902404
Short name T637
Test name
Test status
Simulation time 7077607074 ps
CPU time 87.61 seconds
Started Jan 07 01:16:28 PM PST 24
Finished Jan 07 01:17:57 PM PST 24
Peak memory 198824 kb
Host smart-32095b18-169d-4850-8d96-3fa84793bb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557902404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2557902404
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3476975504
Short name T798
Test name
Test status
Simulation time 33119865 ps
CPU time 0.55 seconds
Started Jan 07 01:16:44 PM PST 24
Finished Jan 07 01:16:45 PM PST 24
Peak memory 192940 kb
Host smart-1f308bf6-1dd5-48f8-b4f7-69870cedd465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476975504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3476975504
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3291278276
Short name T251
Test name
Test status
Simulation time 1323726952 ps
CPU time 42.29 seconds
Started Jan 07 01:16:29 PM PST 24
Finished Jan 07 01:17:12 PM PST 24
Peak memory 221256 kb
Host smart-14fe9a15-076d-4f35-b1d1-057eb494c0ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291278276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3291278276
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3281653791
Short name T759
Test name
Test status
Simulation time 3407889750 ps
CPU time 43.14 seconds
Started Jan 07 01:16:29 PM PST 24
Finished Jan 07 01:17:13 PM PST 24
Peak memory 198856 kb
Host smart-b488067d-9984-44d8-898b-2d3764d6126b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281653791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3281653791
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3826191857
Short name T257
Test name
Test status
Simulation time 3873764629 ps
CPU time 41.12 seconds
Started Jan 07 01:16:27 PM PST 24
Finished Jan 07 01:17:10 PM PST 24
Peak memory 198792 kb
Host smart-8953db08-8693-4d0f-a41e-c1075f26ecf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826191857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3826191857
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3094355238
Short name T226
Test name
Test status
Simulation time 12538994947 ps
CPU time 140.98 seconds
Started Jan 07 01:16:33 PM PST 24
Finished Jan 07 01:18:55 PM PST 24
Peak memory 198768 kb
Host smart-7ee528c6-43f7-4932-8f79-58f640ba7016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094355238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3094355238
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3687808497
Short name T232
Test name
Test status
Simulation time 1056296334 ps
CPU time 18.61 seconds
Started Jan 07 01:16:33 PM PST 24
Finished Jan 07 01:16:52 PM PST 24
Peak memory 198740 kb
Host smart-dd4b80fb-0110-4e9c-b37f-d210ab2664a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687808497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3687808497
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.252081731
Short name T312
Test name
Test status
Simulation time 139574471 ps
CPU time 2.14 seconds
Started Jan 07 01:16:28 PM PST 24
Finished Jan 07 01:16:31 PM PST 24
Peak memory 198660 kb
Host smart-58a36c3a-1bdc-42ad-a256-ea80037193d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252081731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.252081731
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3316522726
Short name T756
Test name
Test status
Simulation time 338428820490 ps
CPU time 1190.43 seconds
Started Jan 07 01:16:26 PM PST 24
Finished Jan 07 01:36:19 PM PST 24
Peak memory 239760 kb
Host smart-2293cc93-6e9d-46eb-8c56-062e65d42dfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316522726 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3316522726
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.675972150
Short name T364
Test name
Test status
Simulation time 307643932999 ps
CPU time 1360.65 seconds
Started Jan 07 01:16:29 PM PST 24
Finished Jan 07 01:39:11 PM PST 24
Peak memory 264004 kb
Host smart-b815e3e8-b46c-413d-ad0a-3137f8b0e75e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675972150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.675972150
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3766807489
Short name T373
Test name
Test status
Simulation time 76149850 ps
CPU time 1.22 seconds
Started Jan 07 01:16:26 PM PST 24
Finished Jan 07 01:16:30 PM PST 24
Peak memory 197212 kb
Host smart-7d24a7ef-d0f5-4e63-9131-b119cd0a2674
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766807489 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3766807489
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.3453290701
Short name T574
Test name
Test status
Simulation time 29580843054 ps
CPU time 345.1 seconds
Started Jan 07 01:16:35 PM PST 24
Finished Jan 07 01:22:21 PM PST 24
Peak memory 198664 kb
Host smart-42e68b3c-1f90-47ad-8252-a3bc35bf8cec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453290701 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_sha_vectors.3453290701
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.4016029981
Short name T435
Test name
Test status
Simulation time 4870967632 ps
CPU time 63.36 seconds
Started Jan 07 01:16:22 PM PST 24
Finished Jan 07 01:17:28 PM PST 24
Peak memory 198656 kb
Host smart-5c283c2c-5df4-4a25-930e-9ef6a0a9c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016029981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4016029981
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.457028204
Short name T310
Test name
Test status
Simulation time 105533862 ps
CPU time 0.54 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:06 PM PST 24
Peak memory 193104 kb
Host smart-8436d70c-67e6-441f-bdf3-3bf2149dbbc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457028204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.457028204
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.559128892
Short name T583
Test name
Test status
Simulation time 279934903 ps
CPU time 8.02 seconds
Started Jan 07 01:14:00 PM PST 24
Finished Jan 07 01:14:08 PM PST 24
Peak memory 206924 kb
Host smart-f988faf8-bfb7-4afb-879c-c9589a3233c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559128892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.559128892
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1723730569
Short name T396
Test name
Test status
Simulation time 4765987245 ps
CPU time 41.31 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:14:45 PM PST 24
Peak memory 198856 kb
Host smart-74f9a9e5-7817-4f8a-aed7-a8f788e37b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723730569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1723730569
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2408150374
Short name T741
Test name
Test status
Simulation time 1280221295 ps
CPU time 16.8 seconds
Started Jan 07 01:14:04 PM PST 24
Finished Jan 07 01:14:22 PM PST 24
Peak memory 198836 kb
Host smart-15fc39dd-bfd6-4ca3-8759-9d1bd6f60e1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2408150374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2408150374
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.4030318592
Short name T423
Test name
Test status
Simulation time 3698154198 ps
CPU time 42.32 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:47 PM PST 24
Peak memory 198768 kb
Host smart-4b427ed0-3d1e-46a4-997f-e22b3fd672f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030318592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.4030318592
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3966833744
Short name T651
Test name
Test status
Simulation time 2144124995 ps
CPU time 36.88 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:41 PM PST 24
Peak memory 198672 kb
Host smart-903ebe3b-5bae-4994-af2f-c7884c1fa9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966833744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3966833744
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1673887177
Short name T710
Test name
Test status
Simulation time 1189483861 ps
CPU time 2.39 seconds
Started Jan 07 01:13:59 PM PST 24
Finished Jan 07 01:14:03 PM PST 24
Peak memory 198452 kb
Host smart-7e48e553-1190-4cef-921e-c8808ccfde16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673887177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1673887177
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.465061391
Short name T691
Test name
Test status
Simulation time 18580483052 ps
CPU time 199.73 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:17:21 PM PST 24
Peak memory 198812 kb
Host smart-68841a81-be66-44c0-ba9a-95a93f7b642d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465061391 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.465061391
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2796333260
Short name T309
Test name
Test status
Simulation time 43259417244 ps
CPU time 358.59 seconds
Started Jan 07 01:14:04 PM PST 24
Finished Jan 07 01:20:04 PM PST 24
Peak memory 215284 kb
Host smart-9194efb6-a124-4db8-9e9b-4944b72cd3d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796333260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2796333260
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2757832984
Short name T640
Test name
Test status
Simulation time 71311441 ps
CPU time 1.22 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:14:03 PM PST 24
Peak memory 197208 kb
Host smart-76a44420-12e5-49e6-bad7-d436a8adb0a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757832984 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2757832984
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2723665527
Short name T754
Test name
Test status
Simulation time 123922188149 ps
CPU time 437.73 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:21:23 PM PST 24
Peak memory 198816 kb
Host smart-fda5d45a-7b6a-4972-a0bf-4d16d72d2131
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723665527 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.2723665527
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2172066628
Short name T261
Test name
Test status
Simulation time 16758815993 ps
CPU time 23.16 seconds
Started Jan 07 01:14:04 PM PST 24
Finished Jan 07 01:14:28 PM PST 24
Peak memory 198864 kb
Host smart-f6fea2fa-280d-4ec1-b5d5-83b96bc21c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172066628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2172066628
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.3276002699
Short name T119
Test name
Test status
Simulation time 340961491013 ps
CPU time 3273.56 seconds
Started Jan 07 01:16:24 PM PST 24
Finished Jan 07 02:11:00 PM PST 24
Peak memory 260552 kb
Host smart-f465dbbf-fcd1-4ed7-9c0a-2bde1ef7209a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276002699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.3276002699
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.4025383028
Short name T553
Test name
Test status
Simulation time 326817407491 ps
CPU time 1200.54 seconds
Started Jan 07 01:16:46 PM PST 24
Finished Jan 07 01:36:47 PM PST 24
Peak memory 243960 kb
Host smart-e79cf392-da22-4ca2-992e-6c09d9ce7039
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4025383028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.4025383028
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.2012858263
Short name T552
Test name
Test status
Simulation time 533815178473 ps
CPU time 1778.55 seconds
Started Jan 07 01:16:55 PM PST 24
Finished Jan 07 01:46:35 PM PST 24
Peak memory 256260 kb
Host smart-363682a0-aed3-42ae-b59d-bda7844733f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012858263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.2012858263
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.3429281309
Short name T45
Test name
Test status
Simulation time 365116266656 ps
CPU time 4373.16 seconds
Started Jan 07 01:16:56 PM PST 24
Finished Jan 07 02:29:50 PM PST 24
Peak memory 262904 kb
Host smart-971d308a-60c1-4e52-974a-e5fab1f091b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3429281309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.3429281309
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.899191125
Short name T422
Test name
Test status
Simulation time 132024520325 ps
CPU time 503.46 seconds
Started Jan 07 01:17:00 PM PST 24
Finished Jan 07 01:25:26 PM PST 24
Peak memory 257248 kb
Host smart-fae7ce9d-b4c6-42d7-91bc-2b0c7e33a843
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=899191125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.899191125
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.917843019
Short name T549
Test name
Test status
Simulation time 182710269239 ps
CPU time 3602.39 seconds
Started Jan 07 01:16:55 PM PST 24
Finished Jan 07 02:16:58 PM PST 24
Peak memory 239996 kb
Host smart-3f3408d9-2e4c-4898-9d6f-0aeb4aa5c0ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917843019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.917843019
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.3566005828
Short name T378
Test name
Test status
Simulation time 85237411551 ps
CPU time 1216.96 seconds
Started Jan 07 01:16:55 PM PST 24
Finished Jan 07 01:37:13 PM PST 24
Peak memory 240308 kb
Host smart-1753cd61-14f2-4a45-a923-3a0540b02d10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566005828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.3566005828
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.2015932235
Short name T748
Test name
Test status
Simulation time 141588263265 ps
CPU time 1613.25 seconds
Started Jan 07 01:16:59 PM PST 24
Finished Jan 07 01:43:54 PM PST 24
Peak memory 241888 kb
Host smart-ae58fc4a-572d-45d5-9394-1cc6fd8e1b9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015932235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.2015932235
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.1044803377
Short name T210
Test name
Test status
Simulation time 19330532493 ps
CPU time 939.92 seconds
Started Jan 07 01:16:55 PM PST 24
Finished Jan 07 01:32:35 PM PST 24
Peak memory 247644 kb
Host smart-82a8b3b6-db4d-4616-93b1-b3b3cea25ed4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044803377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.1044803377
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1527941080
Short name T231
Test name
Test status
Simulation time 14797467 ps
CPU time 0.57 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:05 PM PST 24
Peak memory 193072 kb
Host smart-94036f15-bfa1-4d3b-8f9c-163e7c253f47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527941080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1527941080
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3488141215
Short name T356
Test name
Test status
Simulation time 3831645384 ps
CPU time 27.46 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:14:29 PM PST 24
Peak memory 215244 kb
Host smart-96e4672a-c0ec-4527-a5c3-afb38d0f05ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488141215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3488141215
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1156259114
Short name T516
Test name
Test status
Simulation time 8354609696 ps
CPU time 24.78 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:30 PM PST 24
Peak memory 198768 kb
Host smart-582252b8-f78d-412e-b290-8d86f89c1eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156259114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1156259114
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3804508812
Short name T506
Test name
Test status
Simulation time 3139321395 ps
CPU time 115.65 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:15:57 PM PST 24
Peak memory 198812 kb
Host smart-5214d903-7e3d-4ef3-a34f-834f141bbd14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804508812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3804508812
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3793971314
Short name T217
Test name
Test status
Simulation time 13211978260 ps
CPU time 104.23 seconds
Started Jan 07 01:14:05 PM PST 24
Finished Jan 07 01:15:50 PM PST 24
Peak memory 198936 kb
Host smart-a548b8fa-cb72-47e2-9317-87321ad43fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793971314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3793971314
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.4188134416
Short name T507
Test name
Test status
Simulation time 4793757207 ps
CPU time 43.38 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:14:46 PM PST 24
Peak memory 198828 kb
Host smart-88c21c5c-95eb-448a-af30-ee2d1a0635da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188134416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4188134416
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3168340105
Short name T538
Test name
Test status
Simulation time 923932175 ps
CPU time 4.62 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:14:07 PM PST 24
Peak memory 198608 kb
Host smart-68105987-ffd0-4f4f-baf1-d397c5a90669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168340105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3168340105
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.275613573
Short name T682
Test name
Test status
Simulation time 3129314934 ps
CPU time 143.29 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:16:27 PM PST 24
Peak memory 198696 kb
Host smart-469762d6-d101-4796-b9f6-7c80a7720268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275613573 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.275613573
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.3138747428
Short name T687
Test name
Test status
Simulation time 214564744927 ps
CPU time 873.49 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:28:35 PM PST 24
Peak memory 247504 kb
Host smart-80cb75ae-4e10-4129-a22e-8c93c8adf0af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138747428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3138747428
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.1230913050
Short name T761
Test name
Test status
Simulation time 506836745 ps
CPU time 1.19 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:14:04 PM PST 24
Peak memory 197148 kb
Host smart-00fccb58-ee6d-40b9-b031-9a2dfd7e87fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230913050 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.1230913050
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.4237704375
Short name T733
Test name
Test status
Simulation time 27589760088 ps
CPU time 354.32 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:19:59 PM PST 24
Peak memory 198828 kb
Host smart-709bf40f-a0b8-4e20-8f2c-db954a1cc19d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237704375 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.4237704375
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2988545079
Short name T181
Test name
Test status
Simulation time 17277612533 ps
CPU time 71.99 seconds
Started Jan 07 01:14:04 PM PST 24
Finished Jan 07 01:15:18 PM PST 24
Peak memory 198876 kb
Host smart-e49b2057-7383-4bc5-921c-6bdace737fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988545079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2988545079
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.955041210
Short name T103
Test name
Test status
Simulation time 234266067258 ps
CPU time 4999.75 seconds
Started Jan 07 01:16:59 PM PST 24
Finished Jan 07 02:40:20 PM PST 24
Peak memory 256180 kb
Host smart-b1b879c5-a8b4-48ca-8a79-7f0c4351de54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955041210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.955041210
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.2357503536
Short name T469
Test name
Test status
Simulation time 54569962832 ps
CPU time 257.57 seconds
Started Jan 07 01:17:01 PM PST 24
Finished Jan 07 01:21:20 PM PST 24
Peak memory 207128 kb
Host smart-1bd16119-9326-462c-9189-f204da0236a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357503536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.2357503536
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.2918120338
Short name T739
Test name
Test status
Simulation time 299632297088 ps
CPU time 1260.73 seconds
Started Jan 07 01:16:47 PM PST 24
Finished Jan 07 01:37:49 PM PST 24
Peak memory 214916 kb
Host smart-19a5cf62-1e04-452f-ae1b-75b86d87d349
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2918120338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.2918120338
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.2428679970
Short name T239
Test name
Test status
Simulation time 1067063342554 ps
CPU time 2202.82 seconds
Started Jan 07 01:16:55 PM PST 24
Finished Jan 07 01:53:38 PM PST 24
Peak memory 259072 kb
Host smart-89c3ba13-ac13-4e4a-8413-f04e16c8b76e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428679970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.2428679970
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.4104964426
Short name T618
Test name
Test status
Simulation time 54895193350 ps
CPU time 1324.79 seconds
Started Jan 07 01:16:47 PM PST 24
Finished Jan 07 01:38:53 PM PST 24
Peak memory 253120 kb
Host smart-b84fce00-9d5e-48e4-be31-d1db3c5acb3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104964426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.4104964426
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3093876228
Short name T60
Test name
Test status
Simulation time 154814271806 ps
CPU time 1895.51 seconds
Started Jan 07 01:16:55 PM PST 24
Finished Jan 07 01:48:31 PM PST 24
Peak memory 249640 kb
Host smart-45ee7a29-c789-4f77-82b5-85c0302befe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093876228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.3093876228
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.595010793
Short name T258
Test name
Test status
Simulation time 98903439262 ps
CPU time 1558.39 seconds
Started Jan 07 01:17:26 PM PST 24
Finished Jan 07 01:43:25 PM PST 24
Peak memory 244788 kb
Host smart-6e68a2b4-23c3-4a74-a53e-170b943f44a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=595010793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.595010793
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.1562093530
Short name T343
Test name
Test status
Simulation time 10570850852 ps
CPU time 494.11 seconds
Started Jan 07 01:17:00 PM PST 24
Finished Jan 07 01:25:16 PM PST 24
Peak memory 231744 kb
Host smart-c6c1ad0e-1f92-4419-9838-1749d231610c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562093530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.1562093530
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.3268317672
Short name T401
Test name
Test status
Simulation time 85947292230 ps
CPU time 2563.04 seconds
Started Jan 07 01:16:54 PM PST 24
Finished Jan 07 01:59:38 PM PST 24
Peak memory 239968 kb
Host smart-5afcfc07-62e0-4ef2-8da4-26931ac3ed10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268317672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.3268317672
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2987075080
Short name T684
Test name
Test status
Simulation time 54798946 ps
CPU time 0.54 seconds
Started Jan 07 01:14:05 PM PST 24
Finished Jan 07 01:14:07 PM PST 24
Peak memory 193144 kb
Host smart-8b6132ea-c742-4b18-bf99-2af590b54606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987075080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2987075080
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1258938053
Short name T246
Test name
Test status
Simulation time 726172312 ps
CPU time 21.77 seconds
Started Jan 07 01:14:00 PM PST 24
Finished Jan 07 01:14:23 PM PST 24
Peak memory 206880 kb
Host smart-44c91bec-3f09-4785-90d1-13eb5a85f347
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258938053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1258938053
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.401973522
Short name T663
Test name
Test status
Simulation time 134349992 ps
CPU time 3.1 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:14:06 PM PST 24
Peak memory 198724 kb
Host smart-690264de-a0ed-4601-9d7e-332e0f6781a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401973522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.401973522
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1220415608
Short name T223
Test name
Test status
Simulation time 2072358411 ps
CPU time 104.05 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:15:48 PM PST 24
Peak memory 198648 kb
Host smart-dc1482ad-58d3-4af3-88db-7d1c6d411816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220415608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1220415608
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2175139745
Short name T495
Test name
Test status
Simulation time 1734624117 ps
CPU time 26.96 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:14:30 PM PST 24
Peak memory 198680 kb
Host smart-64914f6a-5321-48fe-a750-0da44fdcb7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175139745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2175139745
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2195453951
Short name T493
Test name
Test status
Simulation time 1761887663 ps
CPU time 29.92 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:14:34 PM PST 24
Peak memory 198660 kb
Host smart-bc56f73c-a11d-4ffd-a2d3-aa1740761169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195453951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2195453951
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.463483359
Short name T170
Test name
Test status
Simulation time 152973206 ps
CPU time 3.04 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:14:06 PM PST 24
Peak memory 198712 kb
Host smart-d0980ea8-24b4-429b-a77a-761519595a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463483359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.463483359
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.120948650
Short name T367
Test name
Test status
Simulation time 80010137782 ps
CPU time 580.84 seconds
Started Jan 07 01:14:07 PM PST 24
Finished Jan 07 01:23:49 PM PST 24
Peak memory 214084 kb
Host smart-f055fac6-1bc7-4562-92c8-c446c204ab17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120948650 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.120948650
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2172272285
Short name T533
Test name
Test status
Simulation time 31670397 ps
CPU time 1.12 seconds
Started Jan 07 01:14:00 PM PST 24
Finished Jan 07 01:14:02 PM PST 24
Peak memory 196764 kb
Host smart-49d8fb14-2fbf-4c22-a6e0-ecc7eabea37e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172272285 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2172272285
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.4144383899
Short name T350
Test name
Test status
Simulation time 10661594713 ps
CPU time 404.75 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:20:46 PM PST 24
Peak memory 198728 kb
Host smart-d12fa01b-d963-4320-a082-36689135d978
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144383899 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.4144383899
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.4086825543
Short name T773
Test name
Test status
Simulation time 24558277945 ps
CPU time 66.15 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:15:09 PM PST 24
Peak memory 198684 kb
Host smart-8f9f8f4b-1c31-4fb5-9636-7547043860fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086825543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.4086825543
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.339395532
Short name T758
Test name
Test status
Simulation time 496632975438 ps
CPU time 2627.08 seconds
Started Jan 07 01:16:56 PM PST 24
Finished Jan 07 02:00:44 PM PST 24
Peak memory 256276 kb
Host smart-4cebf7f9-680f-48e6-adbe-9c4f6cd6fddc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339395532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.339395532
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.3844532615
Short name T405
Test name
Test status
Simulation time 57162721006 ps
CPU time 871.73 seconds
Started Jan 07 01:16:56 PM PST 24
Finished Jan 07 01:31:28 PM PST 24
Peak memory 225468 kb
Host smart-c8efbcf2-9bee-458c-bd1e-a4be0a6e4f8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3844532615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.3844532615
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.574414633
Short name T593
Test name
Test status
Simulation time 112953957733 ps
CPU time 1263.15 seconds
Started Jan 07 01:16:48 PM PST 24
Finished Jan 07 01:37:52 PM PST 24
Peak memory 248100 kb
Host smart-39a835c2-6aca-421c-951d-af4f556d766e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=574414633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.574414633
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.4289290222
Short name T460
Test name
Test status
Simulation time 41832261061 ps
CPU time 159.58 seconds
Started Jan 07 01:17:00 PM PST 24
Finished Jan 07 01:19:42 PM PST 24
Peak memory 214984 kb
Host smart-f7a9d26a-522c-4387-9c3d-58e65d488047
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4289290222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.4289290222
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.3033379940
Short name T276
Test name
Test status
Simulation time 4524526335 ps
CPU time 115.76 seconds
Started Jan 07 01:16:54 PM PST 24
Finished Jan 07 01:18:50 PM PST 24
Peak memory 214384 kb
Host smart-c08eb434-e306-43f2-b02a-1799e1c7fb22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033379940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.3033379940
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.2385390881
Short name T320
Test name
Test status
Simulation time 62384585095 ps
CPU time 2931 seconds
Started Jan 07 01:17:00 PM PST 24
Finished Jan 07 02:05:53 PM PST 24
Peak memory 231668 kb
Host smart-13066684-1093-4d22-b807-04e1f079b164
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385390881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.2385390881
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.420536324
Short name T494
Test name
Test status
Simulation time 71189212778 ps
CPU time 420.88 seconds
Started Jan 07 01:16:55 PM PST 24
Finished Jan 07 01:23:56 PM PST 24
Peak memory 214368 kb
Host smart-5fb184b9-e48a-4fd8-b7fd-218986ca265b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=420536324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.420536324
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.252402110
Short name T526
Test name
Test status
Simulation time 183190938919 ps
CPU time 1046.74 seconds
Started Jan 07 01:16:55 PM PST 24
Finished Jan 07 01:34:23 PM PST 24
Peak memory 241920 kb
Host smart-0bc9dbe2-84f3-41b5-95af-c441091bb4c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=252402110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.252402110
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.1885172569
Short name T123
Test name
Test status
Simulation time 233141318654 ps
CPU time 2725.91 seconds
Started Jan 07 01:16:54 PM PST 24
Finished Jan 07 02:02:21 PM PST 24
Peak memory 252176 kb
Host smart-72882635-b783-43bb-8fb0-6b5052d3fc41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885172569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.1885172569
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.1994369407
Short name T433
Test name
Test status
Simulation time 512806296401 ps
CPU time 3758.99 seconds
Started Jan 07 01:16:54 PM PST 24
Finished Jan 07 02:19:34 PM PST 24
Peak memory 250496 kb
Host smart-9045ff8d-6bc2-460b-8ebe-f4f7687946b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994369407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.1994369407
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.4091488345
Short name T535
Test name
Test status
Simulation time 13344573 ps
CPU time 0.55 seconds
Started Jan 07 01:14:04 PM PST 24
Finished Jan 07 01:14:07 PM PST 24
Peak memory 193136 kb
Host smart-c0160c86-6e84-49e9-b6d3-daf227505930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091488345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.4091488345
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1084793818
Short name T501
Test name
Test status
Simulation time 349979572 ps
CPU time 1.6 seconds
Started Jan 07 01:14:02 PM PST 24
Finished Jan 07 01:14:05 PM PST 24
Peak memory 198536 kb
Host smart-1ea2a6ed-e7b7-4037-928b-c26c7b4b225b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1084793818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1084793818
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2966123131
Short name T316
Test name
Test status
Simulation time 979665720 ps
CPU time 43.27 seconds
Started Jan 07 01:14:07 PM PST 24
Finished Jan 07 01:14:51 PM PST 24
Peak memory 198700 kb
Host smart-3afc1172-0c36-47d6-94a0-57f82e0e93d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966123131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2966123131
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3104339446
Short name T782
Test name
Test status
Simulation time 97333427 ps
CPU time 3.76 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:09 PM PST 24
Peak memory 198632 kb
Host smart-04f64f7a-30a0-439c-ab7e-e4d7989e88c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3104339446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3104339446
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2011180977
Short name T769
Test name
Test status
Simulation time 39892687129 ps
CPU time 184.85 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:17:07 PM PST 24
Peak memory 198788 kb
Host smart-52645eda-9745-497a-b763-e6d6ec2aabf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011180977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2011180977
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1384827076
Short name T286
Test name
Test status
Simulation time 14043953083 ps
CPU time 48.43 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:54 PM PST 24
Peak memory 198684 kb
Host smart-f289f458-ef9b-467c-976f-50285768cc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384827076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1384827076
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3111942539
Short name T540
Test name
Test status
Simulation time 465279287 ps
CPU time 2.83 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:14:05 PM PST 24
Peak memory 198452 kb
Host smart-42a4a217-0b09-4434-b4df-1336c95abe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111942539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3111942539
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3982992245
Short name T652
Test name
Test status
Simulation time 505284925381 ps
CPU time 1306.91 seconds
Started Jan 07 01:14:07 PM PST 24
Finished Jan 07 01:35:55 PM PST 24
Peak memory 230632 kb
Host smart-039316ac-f9be-4970-b4ff-c704606141e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982992245 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3982992245
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.819868578
Short name T304
Test name
Test status
Simulation time 213011059261 ps
CPU time 980.03 seconds
Started Jan 07 01:14:06 PM PST 24
Finished Jan 07 01:30:27 PM PST 24
Peak memory 257212 kb
Host smart-64a7cdff-8ace-4709-b028-6e93642b1e9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819868578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.819868578
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2791757548
Short name T812
Test name
Test status
Simulation time 44402089 ps
CPU time 0.9 seconds
Started Jan 07 01:14:04 PM PST 24
Finished Jan 07 01:14:06 PM PST 24
Peak memory 195788 kb
Host smart-bf63f9fc-3185-4b5a-85e0-d52b771cc51e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791757548 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2791757548
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3670672432
Short name T735
Test name
Test status
Simulation time 17206418598 ps
CPU time 385.1 seconds
Started Jan 07 01:14:08 PM PST 24
Finished Jan 07 01:20:34 PM PST 24
Peak memory 198804 kb
Host smart-9680bef4-86ea-4b26-80f1-971e696f459d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670672432 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.3670672432
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.4276040120
Short name T699
Test name
Test status
Simulation time 5823793077 ps
CPU time 58.47 seconds
Started Jan 07 01:14:06 PM PST 24
Finished Jan 07 01:15:06 PM PST 24
Peak memory 198840 kb
Host smart-4a154698-be17-4e0e-b1d4-094011afbce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276040120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.4276040120
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.209442238
Short name T294
Test name
Test status
Simulation time 30517417894 ps
CPU time 628.3 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 01:27:38 PM PST 24
Peak memory 248052 kb
Host smart-25702376-1dfd-40c8-880a-cc93d21565ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209442238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.209442238
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.1223140799
Short name T523
Test name
Test status
Simulation time 328128419468 ps
CPU time 1303.55 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:38:57 PM PST 24
Peak memory 244972 kb
Host smart-116a789f-9835-4f39-a98a-fcefd16da6f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223140799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.1223140799
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.2648301308
Short name T639
Test name
Test status
Simulation time 25405328777 ps
CPU time 241.01 seconds
Started Jan 07 01:17:17 PM PST 24
Finished Jan 07 01:21:19 PM PST 24
Peak memory 240916 kb
Host smart-d8615fe7-e652-45c8-80f5-1e6a161492b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648301308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.2648301308
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.3248206804
Short name T474
Test name
Test status
Simulation time 123753227255 ps
CPU time 1114.59 seconds
Started Jan 07 01:17:00 PM PST 24
Finished Jan 07 01:35:37 PM PST 24
Peak memory 225960 kb
Host smart-375b0228-984c-4505-b3e5-df4ff113a818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248206804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.3248206804
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.2786533650
Short name T632
Test name
Test status
Simulation time 1652858200315 ps
CPU time 5097.84 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 02:42:11 PM PST 24
Peak memory 256288 kb
Host smart-afe70a64-5d2e-420b-b1bd-1bdc0806b200
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786533650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.2786533650
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.1748685513
Short name T518
Test name
Test status
Simulation time 161159339319 ps
CPU time 508.05 seconds
Started Jan 07 01:17:01 PM PST 24
Finished Jan 07 01:25:31 PM PST 24
Peak memory 231712 kb
Host smart-eeda9e25-8ad2-4820-b965-746964e21ea5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748685513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.1748685513
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.2293973897
Short name T738
Test name
Test status
Simulation time 1340370167326 ps
CPU time 2095.89 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:52:10 PM PST 24
Peak memory 249040 kb
Host smart-8b29640d-7677-4604-927c-931c135624ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293973897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.2293973897
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.2631292665
Short name T686
Test name
Test status
Simulation time 180903956968 ps
CPU time 1607.19 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:43:58 PM PST 24
Peak memory 256824 kb
Host smart-e68ac522-d43a-48bb-bd01-75c1438cc91b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2631292665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.2631292665
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.738731181
Short name T702
Test name
Test status
Simulation time 14662443205 ps
CPU time 210.88 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:20:42 PM PST 24
Peak memory 207012 kb
Host smart-d5263cc4-cdcd-4db5-84a3-260e2af2d03e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738731181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.738731181
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1061878516
Short name T541
Test name
Test status
Simulation time 34286785 ps
CPU time 0.56 seconds
Started Jan 07 01:14:34 PM PST 24
Finished Jan 07 01:14:35 PM PST 24
Peak memory 193088 kb
Host smart-b77f6c6d-537b-427a-a574-a8981ce478a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061878516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1061878516
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.4222143816
Short name T690
Test name
Test status
Simulation time 6247002609 ps
CPU time 41.2 seconds
Started Jan 07 01:14:07 PM PST 24
Finished Jan 07 01:14:50 PM PST 24
Peak memory 230600 kb
Host smart-07ef3b61-47ce-4685-a1c1-1ed927aaefbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222143816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.4222143816
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4244543746
Short name T620
Test name
Test status
Simulation time 439696486 ps
CPU time 5.85 seconds
Started Jan 07 01:14:07 PM PST 24
Finished Jan 07 01:14:14 PM PST 24
Peak memory 198676 kb
Host smart-f06e79f8-3a40-46a2-8352-979042892656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244543746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4244543746
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1423177845
Short name T497
Test name
Test status
Simulation time 2135384330 ps
CPU time 109.57 seconds
Started Jan 07 01:14:01 PM PST 24
Finished Jan 07 01:15:52 PM PST 24
Peak memory 198680 kb
Host smart-97828db0-054e-4811-ad94-8a49a001cc84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423177845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1423177845
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.563976938
Short name T805
Test name
Test status
Simulation time 19015432085 ps
CPU time 222.89 seconds
Started Jan 07 01:14:35 PM PST 24
Finished Jan 07 01:18:19 PM PST 24
Peak memory 198872 kb
Host smart-d6188403-29cd-4894-860a-0b335fd31c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563976938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.563976938
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.456947028
Short name T715
Test name
Test status
Simulation time 935726545 ps
CPU time 24.42 seconds
Started Jan 07 01:14:03 PM PST 24
Finished Jan 07 01:14:30 PM PST 24
Peak memory 198652 kb
Host smart-f67cde24-cd2a-47de-942a-8a53aac426ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456947028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.456947028
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3213315410
Short name T167
Test name
Test status
Simulation time 110542856 ps
CPU time 1.2 seconds
Started Jan 07 01:14:08 PM PST 24
Finished Jan 07 01:14:10 PM PST 24
Peak memory 198116 kb
Host smart-f54b1988-84b7-4866-b32c-88a67e851f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213315410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3213315410
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2516621911
Short name T660
Test name
Test status
Simulation time 33949997039 ps
CPU time 407.75 seconds
Started Jan 07 01:14:44 PM PST 24
Finished Jan 07 01:21:33 PM PST 24
Peak memory 223468 kb
Host smart-6355dc85-98c3-4082-8ab4-4f0301beeadf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516621911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2516621911
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1239831237
Short name T636
Test name
Test status
Simulation time 548891456378 ps
CPU time 2191.42 seconds
Started Jan 07 01:14:34 PM PST 24
Finished Jan 07 01:51:07 PM PST 24
Peak memory 257124 kb
Host smart-2f26b603-7c36-4ae5-9e00-b4eb4459e3c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1239831237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1239831237
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2214075262
Short name T674
Test name
Test status
Simulation time 71650268 ps
CPU time 1.08 seconds
Started Jan 07 01:14:53 PM PST 24
Finished Jan 07 01:14:55 PM PST 24
Peak memory 196844 kb
Host smart-583798a7-63cf-4f09-a9b9-abefad51c311
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214075262 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2214075262
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.974849158
Short name T499
Test name
Test status
Simulation time 30352493052 ps
CPU time 406.7 seconds
Started Jan 07 01:14:46 PM PST 24
Finished Jan 07 01:21:35 PM PST 24
Peak memory 198744 kb
Host smart-e002c1e4-da07-43d5-9330-1c05c6cb212d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974849158 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.hmac_test_sha_vectors.974849158
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1045581688
Short name T555
Test name
Test status
Simulation time 5066576590 ps
CPU time 52.84 seconds
Started Jan 07 01:14:48 PM PST 24
Finished Jan 07 01:15:44 PM PST 24
Peak memory 198864 kb
Host smart-7d7ff792-ed3c-4a23-b257-4c81df42ec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045581688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1045581688
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.3955393843
Short name T453
Test name
Test status
Simulation time 57446292160 ps
CPU time 2639.48 seconds
Started Jan 07 01:17:00 PM PST 24
Finished Jan 07 02:01:01 PM PST 24
Peak memory 244916 kb
Host smart-9ad3c275-e374-4853-94e1-825e88d39273
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955393843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.3955393843
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.2149208150
Short name T631
Test name
Test status
Simulation time 32176865994 ps
CPU time 118.25 seconds
Started Jan 07 01:17:09 PM PST 24
Finished Jan 07 01:19:08 PM PST 24
Peak memory 215268 kb
Host smart-6cae91d9-77bc-4d52-926d-f8a12f2014a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149208150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.2149208150
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.3066872886
Short name T770
Test name
Test status
Simulation time 168162423262 ps
CPU time 3593.09 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 02:17:07 PM PST 24
Peak memory 264424 kb
Host smart-5529974d-89d6-4d5e-ac7c-50895c040abd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066872886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.3066872886
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.790908564
Short name T64
Test name
Test status
Simulation time 116748112368 ps
CPU time 1379.8 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:40:11 PM PST 24
Peak memory 214544 kb
Host smart-1b2b2f4d-280b-4266-92eb-c9a2d14d5961
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=790908564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.790908564
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.776167209
Short name T385
Test name
Test status
Simulation time 19236027411 ps
CPU time 993.07 seconds
Started Jan 07 01:17:12 PM PST 24
Finished Jan 07 01:33:46 PM PST 24
Peak memory 239868 kb
Host smart-74e5da62-7455-4482-855e-76ad80157830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776167209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.776167209
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.3225174287
Short name T449
Test name
Test status
Simulation time 214864647604 ps
CPU time 1468.78 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:41:41 PM PST 24
Peak memory 248004 kb
Host smart-3346d37e-e98d-4939-b897-f703226f462e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225174287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.3225174287
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.3168757392
Short name T568
Test name
Test status
Simulation time 77665382901 ps
CPU time 855.9 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 01:31:29 PM PST 24
Peak memory 241636 kb
Host smart-a1db4472-d478-4329-a137-c361b5ebe5d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168757392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.3168757392
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.3608670257
Short name T775
Test name
Test status
Simulation time 174536888352 ps
CPU time 3545.81 seconds
Started Jan 07 01:17:11 PM PST 24
Finished Jan 07 02:16:19 PM PST 24
Peak memory 264376 kb
Host smart-d1dd4d50-09b8-405e-868f-09f2ac24f04f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608670257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.3608670257
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.672562230
Short name T473
Test name
Test status
Simulation time 235908651419 ps
CPU time 1089.04 seconds
Started Jan 07 01:17:10 PM PST 24
Finished Jan 07 01:35:20 PM PST 24
Peak memory 215236 kb
Host smart-c2449e24-33ef-403d-9f3a-4061126b4ee5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672562230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.672562230
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.2469058937
Short name T596
Test name
Test status
Simulation time 675952926186 ps
CPU time 2221.58 seconds
Started Jan 07 01:17:01 PM PST 24
Finished Jan 07 01:54:05 PM PST 24
Peak memory 250112 kb
Host smart-58287ef0-b47d-4e35-b2e9-df361d9c81fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2469058937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.2469058937
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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