Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	43265040	1			T16	8		T17	8		T22	5
all_values[1]	43265040	1			T16	8		T17	8		T22	5
all_values[2]	43265040	1			T16	8		T17	8		T22	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139994

1

T16

20

T17

9

T22

4

auto[1]

129655126

1

T16

4

T17

15

T22

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94686032

1

T16

9

T17

14

T22

9

auto[1]

35109088

1

T16

15

T17

10

T22

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	59566	1			T16	2		T17	1		T22	3
all_values[0]	auto[0]	auto[1]	1355	1			T16	4		T67	4		T107	2
all_values[0]	auto[1]	auto[0]	43023426	1			T16	1		T17	2		T22	2
all_values[0]	auto[1]	auto[1]	180693	1			T16	1		T17	5		T67	2
all_values[1]	auto[0]	auto[0]	20271	1			T16	3		T17	3		T33	1
all_values[1]	auto[0]	auto[1]	16113	1			T16	4		T17	3		T33	1
all_values[1]	auto[1]	auto[0]	24812928	1			T17	1		T22	3		T33	1
all_values[1]	auto[1]	auto[1]	18415728	1			T16	1		T17	1		T22	2
all_values[2]	auto[0]	auto[0]	34364	1			T16	3		T17	2		T33	1
all_values[2]	auto[0]	auto[1]	8325	1			T16	4		T22	1		T33	3
all_values[2]	auto[1]	auto[0]	26735477	1			T17	5		T22	1		T67	4
all_values[2]	auto[1]	auto[1]	16486874	1			T16	1		T17	1		T22	3