Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21652992

1

T1

560

T4

1984

T5

96692

auto[1]

10571926

1

T1

2280

T2

1043

T4

4283

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10641883

1

T1

2278

T2

1043

T4

3784

auto[1]

21583035

1

T1

562

T4

2483

T5

103070

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18849813

1

T1

561

T2

1043

T5

81896

auto[1]

13375105

1

T1

2279

T4

6267

T5

85022

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	17269168	1			T1	1258		T2	47		T4	2180
fifo_depth[1]	1655316	1			T1	184		T2	21		T4	426
fifo_depth[2]	1535151	1			T1	160		T2	26		T4	438
fifo_depth[3]	1335153	1			T1	171		T2	19		T4	467
fifo_depth[4]	1305499	1			T1	168		T2	26		T4	480
fifo_depth[5]	1123375	1			T1	168		T2	21		T4	465
fifo_depth[6]	1159183	1			T1	191		T2	28		T4	446
fifo_depth[7]	991447	1			T1	173		T2	20		T4	417
fifo_depth[8]	1147714	1			T1	132		T2	26		T4	350
fifo_depth[9]	693074	1			T1	107		T2	19		T4	257
fifo_depth[10]	675779	1			T1	63		T2	26		T4	147
fifo_depth[11]	420258	1			T1	34		T2	19		T4	104
fifo_depth[12]	672421	1			T1	20		T2	26		T4	48
fifo_depth[13]	310729	1			T1	5		T2	19		T4	20
fifo_depth[14]	497525	1			T1	4		T2	26		T4	12
fifo_depth[15]	291114	1			T1	2		T2	19		T4	8
fifo_depth[16]	1142012	1			T2	655		T4	2		T5	11527

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14955750

1

T1

1582

T2

996

T4

4087

auto[1]

17269168

1

T1

1258

T2

47

T4

2180

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31082906

1

T1

2840

T2

388

T4

6265

auto[1]

1142012

1

T2

655

T4

2

T5

11527

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1148323

1

T5

7115

T6

667

T7

115

auto[0]

auto[0]

auto[0]

auto[1]

1154533

1

T2

996

T5

11333

T6

466

auto[0]

auto[0]

auto[1]

auto[0]

4072344

1

T1

352

T5

18767

T6

1499

auto[0]

auto[0]

auto[1]

auto[1]

1089620

1

T5

7348

T6

1087

T35

813

auto[0]

auto[1]

auto[0]

auto[0]

1835375

1

T4

1005

T5

11388

T6

857

auto[0]

auto[1]

auto[0]

auto[1]

1907252

1

T1

1230

T4

1497

T5

19241

auto[0]

auto[1]

auto[1]

auto[0]

1916336

1

T4

263

T5

16626

T6

1649

auto[0]

auto[1]

auto[1]

auto[1]

1831967

1

T4

1322

T5

16127

T6

935

auto[1]

auto[0]

auto[0]

auto[0]

831490

1

T5

1591

T6

3115

T7

807

auto[1]

auto[0]

auto[0]

auto[1]

790441

1

T2

47

T5

548

T6

1135

auto[1]

auto[0]

auto[1]

auto[0]

8922374

1

T1

208

T5

32254

T6

9216

auto[1]

auto[0]

auto[1]

auto[1]

840688

1

T1

1

T5

2940

T6

4377

auto[1]

auto[1]

auto[0]

auto[0]

1493086

1

T4

564

T5

5269

T6

3820

auto[1]

auto[1]

auto[0]

auto[1]

1481383

1

T1

1048

T4

718

T5

7363

auto[1]

auto[1]

auto[1]

auto[0]

1433664

1

T4

152

T5

3682

T6

6071

auto[1]

auto[1]

auto[1]

auto[1]

1476042

1

T1

1

T4

746

T5

5326

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1847458

1

T5

7988

T6

3782

T7

922

auto[0]

auto[0]

auto[0]

auto[1]

1802792

1

T2

388

T5

9814

T6

1601

auto[0]

auto[0]

auto[1]

auto[0]

12841461

1

T1

560

T5

50848

T6

10715

auto[0]

auto[0]

auto[1]

auto[1]

1796760

1

T1

1

T5

9318

T6

5464

auto[0]

auto[1]

auto[0]

auto[0]

3186937

1

T4

1568

T5

15244

T6

4677

auto[0]

auto[1]

auto[0]

auto[1]

3235286

1

T1

2278

T4

2215

T5

25383

auto[0]

auto[1]

auto[1]

auto[0]

3205309

1

T4

415

T5

17967

T6

7720

auto[0]

auto[1]

auto[1]

auto[1]

3166903

1

T1

1

T4

2067

T5

18829

auto[1]

auto[0]

auto[0]

auto[0]

132355

1

T5

718

T36

1

T38

656

auto[1]

auto[0]

auto[0]

auto[1]

142182

1

T2

655

T5

2067

T36

73

auto[1]

auto[0]

auto[1]

auto[0]

153257

1

T5

173

T8

1

T36

69

auto[1]

auto[0]

auto[1]

auto[1]

133548

1

T5

970

T36

36

T38

930

auto[1]

auto[1]

auto[0]

auto[0]

141524

1

T4

1

T5

1413

T37

1

auto[1]

auto[1]

auto[0]

auto[1]

153349

1

T5

1221

T35

1

T36

157

auto[1]

auto[1]

auto[1]

auto[0]

144691

1

T5

2341

T13

1

T37

2

auto[1]

auto[1]

auto[1]

auto[1]

141106

1

T4

1

T5

2624

T37

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	831490	1			T5	1591		T6	3115		T7	807
fifo_depth[0]	auto[0]	auto[0]	auto[1]	790441	1			T2	47		T5	548		T6	1135
fifo_depth[0]	auto[0]	auto[1]	auto[0]	8922374	1			T1	208		T5	32254		T6	9216
fifo_depth[0]	auto[0]	auto[1]	auto[1]	840688	1			T1	1		T5	2940		T6	4377
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1493086	1			T4	564		T5	5269		T6	3820
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1481383	1			T1	1048		T4	718		T5	7363
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1433664	1			T4	152		T5	3682		T6	6071
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1476042	1			T1	1		T4	746		T5	5326
fifo_depth[1]	auto[0]	auto[0]	auto[0]	82568	1			T5	293		T6	217		T7	47
fifo_depth[1]	auto[0]	auto[0]	auto[1]	79579	1			T2	21		T5	183		T6	56
fifo_depth[1]	auto[0]	auto[1]	auto[0]	701528	1			T1	35		T5	3218		T6	498
fifo_depth[1]	auto[0]	auto[1]	auto[1]	82141	1			T5	553		T6	296		T35	87
fifo_depth[1]	auto[1]	auto[0]	auto[0]	178205	1			T4	100		T5	932		T6	203
fifo_depth[1]	auto[1]	auto[0]	auto[1]	178828	1			T1	149		T4	165		T5	1345
fifo_depth[1]	auto[1]	auto[1]	auto[0]	177230	1			T4	25		T5	762		T6	419
fifo_depth[1]	auto[1]	auto[1]	auto[1]	175237	1			T4	136		T5	1119		T6	334
fifo_depth[2]	auto[0]	auto[0]	auto[0]	80028	1			T5	330		T6	138		T7	37
fifo_depth[2]	auto[0]	auto[0]	auto[1]	78532	1			T2	26		T5	250		T6	78
fifo_depth[2]	auto[0]	auto[1]	auto[0]	625971	1			T1	39		T5	3001		T6	356
fifo_depth[2]	auto[0]	auto[1]	auto[1]	78163	1			T5	623		T6	275		T35	78
fifo_depth[2]	auto[1]	auto[0]	auto[0]	168112	1			T4	106		T5	922		T6	315
fifo_depth[2]	auto[1]	auto[0]	auto[1]	169897	1			T1	121		T4	159		T5	1525
fifo_depth[2]	auto[1]	auto[1]	auto[0]	169730	1			T4	34		T5	758		T6	405
fifo_depth[2]	auto[1]	auto[1]	auto[1]	164718	1			T4	139		T5	1097		T6	259
fifo_depth[3]	auto[0]	auto[0]	auto[0]	70836	1			T5	304		T6	78		T7	20
fifo_depth[3]	auto[0]	auto[0]	auto[1]	70499	1			T2	19		T5	302		T6	39
fifo_depth[3]	auto[0]	auto[1]	auto[0]	510586	1			T1	40		T5	2477		T6	197
fifo_depth[3]	auto[0]	auto[1]	auto[1]	70859	1			T5	592		T6	172		T35	93
fifo_depth[3]	auto[1]	auto[0]	auto[0]	152720	1			T4	109		T5	884		T6	96
fifo_depth[3]	auto[1]	auto[0]	auto[1]	155401	1			T1	131		T4	175		T5	1657
fifo_depth[3]	auto[1]	auto[1]	auto[0]	155246	1			T4	34		T5	884		T6	245
fifo_depth[3]	auto[1]	auto[1]	auto[1]	149006	1			T4	149		T5	1139		T6	123
fifo_depth[4]	auto[0]	auto[0]	auto[0]	84419	1			T5	424		T6	102		T7	9
fifo_depth[4]	auto[0]	auto[0]	auto[1]	84574	1			T2	26		T5	581		T6	115
fifo_depth[4]	auto[0]	auto[1]	auto[0]	405853	1			T1	36		T5	1771		T6	196
fifo_depth[4]	auto[0]	auto[1]	auto[1]	80924	1			T5	611		T6	118		T35	100
fifo_depth[4]	auto[1]	auto[0]	auto[0]	161785	1			T4	120		T5	996		T6	154
fifo_depth[4]	auto[1]	auto[0]	auto[1]	163506	1			T1	132		T4	183		T5	1566
fifo_depth[4]	auto[1]	auto[1]	auto[0]	166954	1			T4	35		T5	836		T6	242
fifo_depth[4]	auto[1]	auto[1]	auto[1]	157484	1			T4	142		T5	1151		T6	78
fifo_depth[5]	auto[0]	auto[0]	auto[0]	69404	1			T5	364		T6	22		T7	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	69535	1			T2	21		T5	473		T6	33
fifo_depth[5]	auto[0]	auto[1]	auto[0]	333647	1			T1	38		T5	1458		T6	76
fifo_depth[5]	auto[0]	auto[1]	auto[1]	67705	1			T5	574		T6	71		T35	99
fifo_depth[5]	auto[1]	auto[0]	auto[0]	146118	1			T4	110		T5	968		T6	21
fifo_depth[5]	auto[1]	auto[0]	auto[1]	147278	1			T1	130		T4	160		T5	1501
fifo_depth[5]	auto[1]	auto[1]	auto[0]	149156	1			T4	29		T5	842		T6	100
fifo_depth[5]	auto[1]	auto[1]	auto[1]	140532	1			T4	166		T5	1131		T6	36
fifo_depth[6]	auto[0]	auto[0]	auto[0]	81108	1			T5	451		T6	29		T35	54
fifo_depth[6]	auto[0]	auto[0]	auto[1]	79842	1			T2	28		T5	682		T6	30
fifo_depth[6]	auto[0]	auto[1]	auto[0]	306423	1			T1	46		T5	1350		T6	72
fifo_depth[6]	auto[0]	auto[1]	auto[1]	75097	1			T5	561		T6	56		T35	83
fifo_depth[6]	auto[1]	auto[0]	auto[0]	152085	1			T4	106		T5	984		T6	30
fifo_depth[6]	auto[1]	auto[0]	auto[1]	155893	1			T1	145		T4	163		T5	1593
fifo_depth[6]	auto[1]	auto[1]	auto[0]	157966	1			T4	28		T5	785		T6	94
fifo_depth[6]	auto[1]	auto[1]	auto[1]	150769	1			T4	149		T5	1191		T6	38
fifo_depth[7]	auto[0]	auto[0]	auto[0]	67700	1			T5	477		T6	3		T35	48
fifo_depth[7]	auto[0]	auto[0]	auto[1]	68278	1			T2	20		T5	525		T6	18
fifo_depth[7]	auto[0]	auto[1]	auto[0]	245387	1			T1	35		T5	1058		T6	32
fifo_depth[7]	auto[0]	auto[1]	auto[1]	64986	1			T5	560		T6	21		T35	73
fifo_depth[7]	auto[1]	auto[0]	auto[0]	134683	1			T4	104		T5	863		T6	9
fifo_depth[7]	auto[1]	auto[0]	auto[1]	137944	1			T1	138		T4	148		T5	1518
fifo_depth[7]	auto[1]	auto[1]	auto[0]	140086	1			T4	29		T5	746		T6	40
fifo_depth[7]	auto[1]	auto[1]	auto[1]	132383	1			T4	136		T5	1189		T6	19
fifo_depth[8]	auto[0]	auto[0]	auto[0]	102793	1			T5	513		T6	70		T35	47
fifo_depth[8]	auto[0]	auto[0]	auto[1]	102037	1			T2	26		T5	869		T6	95
fifo_depth[8]	auto[0]	auto[1]	auto[0]	229690	1			T1	30		T5	1009		T6	55
fifo_depth[8]	auto[0]	auto[1]	auto[1]	97289	1			T5	559		T6	57		T35	68
fifo_depth[8]	auto[1]	auto[0]	auto[0]	148509	1			T4	88		T5	1050		T6	19
fifo_depth[8]	auto[1]	auto[0]	auto[1]	158337	1			T1	102		T4	121		T5	1402
fifo_depth[8]	auto[1]	auto[1]	auto[0]	159303	1			T4	25		T5	1357		T6	74
fifo_depth[8]	auto[1]	auto[1]	auto[1]	149756	1			T4	116		T5	1435		T6	33
fifo_depth[9]	auto[0]	auto[0]	auto[0]	54316	1			T5	362		T6	3		T35	42
fifo_depth[9]	auto[0]	auto[0]	auto[1]	54899	1			T2	19		T5	460		T6	2
fifo_depth[9]	auto[0]	auto[1]	auto[0]	140471	1			T1	24		T5	749		T6	4
fifo_depth[9]	auto[0]	auto[1]	auto[1]	50043	1			T5	458		T6	9		T35	53
fifo_depth[9]	auto[1]	auto[0]	auto[0]	96342	1			T4	71		T5	620		T6	2
fifo_depth[9]	auto[1]	auto[0]	auto[1]	98642	1			T1	83		T4	97		T5	1106
fifo_depth[9]	auto[1]	auto[1]	auto[0]	101642	1			T4	10		T5	741		T6	16
fifo_depth[9]	auto[1]	auto[1]	auto[1]	96719	1			T4	79		T5	940		T6	6
fifo_depth[10]	auto[0]	auto[0]	auto[0]	68294	1			T5	386		T6	3		T35	24
fifo_depth[10]	auto[0]	auto[0]	auto[1]	66692	1			T2	26		T5	681		T35	26
fifo_depth[10]	auto[0]	auto[1]	auto[0]	117221	1			T1	10		T5	676		T6	5
fifo_depth[10]	auto[0]	auto[1]	auto[1]	56146	1			T5	329		T6	8		T35	38
fifo_depth[10]	auto[1]	auto[0]	auto[0]	88150	1			T4	38		T5	614		T6	8
fifo_depth[10]	auto[1]	auto[0]	auto[1]	91744	1			T1	53		T4	64		T5	806
fifo_depth[10]	auto[1]	auto[1]	auto[0]	96116	1			T4	4		T5	1222		T6	5
fifo_depth[10]	auto[1]	auto[1]	auto[1]	91416	1			T4	41		T5	814		T6	8
fifo_depth[11]	auto[0]	auto[0]	auto[0]	39823	1			T5	356		T6	2		T35	15
fifo_depth[11]	auto[0]	auto[0]	auto[1]	41100	1			T2	19		T5	499		T35	14
fifo_depth[11]	auto[0]	auto[1]	auto[0]	70625	1			T1	12		T5	586		T6	3
fifo_depth[11]	auto[0]	auto[1]	auto[1]	37209	1			T5	225		T6	2		T35	16
fifo_depth[11]	auto[1]	auto[0]	auto[0]	55398	1			T4	25		T5	272		T12	3
fifo_depth[11]	auto[1]	auto[0]	auto[1]	59551	1			T1	22		T4	34		T5	711
fifo_depth[11]	auto[1]	auto[1]	auto[0]	59851	1			T4	6		T5	760		T6	9
fifo_depth[11]	auto[1]	auto[1]	auto[1]	56701	1			T4	39		T5	606		T13	18
fifo_depth[12]	auto[0]	auto[0]	auto[0]	81778	1			T5	631		T35	9		T36	1
fifo_depth[12]	auto[0]	auto[0]	auto[1]	78878	1			T2	26		T5	1281		T35	13
fifo_depth[12]	auto[0]	auto[1]	auto[0]	93353	1			T1	5		T5	377		T6	3
fifo_depth[12]	auto[0]	auto[1]	auto[1]	75005	1			T5	182		T6	2		T35	19
fifo_depth[12]	auto[1]	auto[0]	auto[0]	80831	1			T4	14		T5	323		T12	7
fifo_depth[12]	auto[1]	auto[0]	auto[1]	89104	1			T1	15		T4	15		T5	784
fifo_depth[12]	auto[1]	auto[1]	auto[0]	88275	1			T4	4		T5	1472		T13	13
fifo_depth[12]	auto[1]	auto[1]	auto[1]	85197	1			T4	15		T5	627		T6	1
fifo_depth[13]	auto[0]	auto[0]	auto[0]	33986	1			T5	548		T35	3		T36	2
fifo_depth[13]	auto[0]	auto[0]	auto[1]	37330	1			T2	19		T5	798		T35	7
fifo_depth[13]	auto[0]	auto[1]	auto[0]	41922	1			T1	1		T5	374		T8	32
fifo_depth[13]	auto[0]	auto[1]	auto[1]	33548	1			T5	148		T35	3		T36	86
fifo_depth[13]	auto[1]	auto[0]	auto[0]	38321	1			T4	5		T5	162		T13	2
fifo_depth[13]	auto[1]	auto[0]	auto[1]	42796	1			T1	4		T4	9		T5	578
fifo_depth[13]	auto[1]	auto[1]	auto[0]	43089	1			T5	1018		T13	6		T37	15
fifo_depth[13]	auto[1]	auto[1]	auto[1]	39737	1			T4	6		T5	398		T13	5
fifo_depth[14]	auto[0]	auto[0]	auto[0]	65582	1			T5	525		T35	1		T38	866
fifo_depth[14]	auto[0]	auto[0]	auto[1]	63413	1			T2	26		T5	1005		T35	2
fifo_depth[14]	auto[0]	auto[1]	auto[0]	62012	1			T1	1		T5	294		T6	2
fifo_depth[14]	auto[0]	auto[1]	auto[1]	53791	1			T5	221		T35	3		T36	62
fifo_depth[14]	auto[1]	auto[0]	auto[0]	58462	1			T4	5		T5	259		T12	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	64227	1			T1	3		T4	2		T5	973
fifo_depth[14]	auto[1]	auto[1]	auto[0]	65857	1			T5	1222		T13	4		T37	9
fifo_depth[14]	auto[1]	auto[1]	auto[1]	64181	1			T4	5		T5	386		T13	3
fifo_depth[15]	auto[0]	auto[0]	auto[0]	33333	1			T5	433		T36	1		T38	132
fifo_depth[15]	auto[0]	auto[0]	auto[1]	37163	1			T2	19		T5	677		T36	99
fifo_depth[15]	auto[0]	auto[1]	auto[0]	34398	1			T5	196		T8	1		T9	2
fifo_depth[15]	auto[0]	auto[1]	auto[1]	33166	1			T5	182		T36	61		T38	283
fifo_depth[15]	auto[1]	auto[0]	auto[0]	34130	1			T4	3		T5	126		T13	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	40755	1			T1	2		T4	2		T5	955
fifo_depth[15]	auto[1]	auto[1]	auto[0]	41144	1			T5	880		T13	2		T37	6
fifo_depth[15]	auto[1]	auto[1]	auto[1]	37025	1			T4	3		T5	280		T38	112
fifo_depth[16]	auto[0]	auto[0]	auto[0]	132355	1			T5	718		T36	1		T38	656
fifo_depth[16]	auto[0]	auto[0]	auto[1]	142182	1			T2	655		T5	2067		T36	73
fifo_depth[16]	auto[0]	auto[1]	auto[0]	153257	1			T5	173		T8	1		T36	69
fifo_depth[16]	auto[0]	auto[1]	auto[1]	133548	1			T5	970		T36	36		T38	930
fifo_depth[16]	auto[1]	auto[0]	auto[0]	141524	1			T4	1		T5	1413		T37	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	153349	1			T5	1221		T35	1		T36	157
fifo_depth[16]	auto[1]	auto[1]	auto[0]	144691	1			T5	2341		T13	1		T37	2
fifo_depth[16]	auto[1]	auto[1]	auto[1]	141106	1			T4	1		T5	2624		T37	1