Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	43265040	1			T16	8		T17	8		T22	5
all_pins[1]	43265040	1			T16	8		T17	8		T22	5
all_pins[2]	43265040	1			T16	8		T17	8		T22	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	94455577	1			T16	21		T17	17		T22	10
values[0x1]	35339543	1			T16	3		T17	7		T22	5
transitions[0x0=>0x1]	31042783	1			T16	3		T17	5		T22	3
transitions[0x1=>0x0]	31042805	1			T16	3		T17	6		T22	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	43080136	1			T16	7		T17	3		T22	5
all_pins[0]	values[0x1]	184904	1			T16	1		T17	5		T67	2
all_pins[0]	transitions[0x0=>0x1]	184674	1			T16	1		T17	4		T67	2
all_pins[0]	transitions[0x1=>0x0]	16486666	1			T16	1		T17	1		T22	3
all_pins[1]	values[0x0]	24597275	1			T16	7		T17	7		T22	3
all_pins[1]	values[0x1]	18667765	1			T16	1		T17	1		T22	2
all_pins[1]	transitions[0x0=>0x1]	18522904	1			T16	1		T22	2		T33	2
all_pins[1]	transitions[0x1=>0x0]	40043	1			T16	1		T17	4		T67	1
all_pins[2]	values[0x0]	26778166	1			T16	7		T17	7		T22	2
all_pins[2]	values[0x1]	16486874	1			T16	1		T17	1		T22	3
all_pins[2]	transitions[0x0=>0x1]	12335205	1			T16	1		T17	1		T22	1
all_pins[2]	transitions[0x1=>0x0]	14516096	1			T16	1		T17	1		T33	2