Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 4308 1 T16 7 T17 7 T22 4
all_values[1] 4308 1 T16 7 T17 7 T22 4
all_values[2] 4308 1 T16 7 T17 7 T22 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6222 1 T16 17 T17 10 T22 5
auto[1] 6702 1 T16 4 T17 11 T22 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4876 1 T16 5 T17 7 T22 4
auto[1] 8048 1 T16 16 T17 14 T22 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7385 1 T16 12 T17 11 T22 7
auto[1] 5539 1 T16 9 T17 10 T22 5


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 778 1 T16 1 T22 2 T33 4
all_values[0] auto[0] auto[0] auto[1] 421 1 T16 2 T17 1 T67 1
all_values[0] auto[0] auto[1] auto[0] 869 1 T22 1 T61 1 T107 1
all_values[0] auto[0] auto[1] auto[1] 410 1 T16 1 T17 1 T67 1
all_values[0] auto[1] auto[0] auto[1] 867 1 T16 3 T17 2 T22 1
all_values[0] auto[1] auto[1] auto[1] 963 1 T17 3 T67 1 T61 3
all_values[1] auto[0] auto[0] auto[0] 750 1 T16 1 T17 1 T33 1
all_values[1] auto[0] auto[0] auto[1] 428 1 T16 2 T17 2 T33 1
all_values[1] auto[0] auto[1] auto[0] 859 1 T16 1 T17 1 T22 1
all_values[1] auto[0] auto[1] auto[1] 405 1 T16 1 T22 1 T33 1
all_values[1] auto[1] auto[0] auto[1] 932 1 T16 2 T17 2 T22 1
all_values[1] auto[1] auto[1] auto[1] 934 1 T17 1 T22 1 T67 1
all_values[2] auto[0] auto[0] auto[0] 733 1 T16 1 T17 1 T67 2
all_values[2] auto[0] auto[0] auto[1] 427 1 T16 1 T33 2 T61 1
all_values[2] auto[0] auto[1] auto[0] 887 1 T16 1 T17 4 T67 2
all_values[2] auto[0] auto[1] auto[1] 418 1 T22 2 T67 1 T107 1
all_values[2] auto[1] auto[0] auto[1] 886 1 T16 4 T17 1 T22 1
all_values[2] auto[1] auto[1] auto[1] 957 1 T17 1 T22 1 T67 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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