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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.53 98.47 100.00 100.00 99.76 99.49 99.86


Total test records in report: 849
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T761 /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.1235299967 Jan 10 01:23:08 PM PST 24 Jan 10 02:00:03 PM PST 24 52468071847 ps
T762 /workspace/coverage/default/40.hmac_error.3503183677 Jan 10 01:22:25 PM PST 24 Jan 10 01:22:51 PM PST 24 170434436 ps
T763 /workspace/coverage/default/47.hmac_smoke.1421123671 Jan 10 01:23:32 PM PST 24 Jan 10 01:23:42 PM PST 24 484474942 ps
T764 /workspace/coverage/default/15.hmac_smoke.2047839941 Jan 10 01:21:37 PM PST 24 Jan 10 01:21:58 PM PST 24 103087806 ps
T765 /workspace/coverage/default/49.hmac_long_msg.3621198955 Jan 10 01:22:49 PM PST 24 Jan 10 01:23:47 PM PST 24 4670197605 ps
T766 /workspace/coverage/default/31.hmac_alert_test.4094114242 Jan 10 01:22:17 PM PST 24 Jan 10 01:22:41 PM PST 24 14656624 ps
T767 /workspace/coverage/default/25.hmac_alert_test.3661985318 Jan 10 01:21:54 PM PST 24 Jan 10 01:22:23 PM PST 24 33783225 ps
T768 /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.514976442 Jan 10 01:23:08 PM PST 24 Jan 10 02:26:51 PM PST 24 176578517637 ps
T769 /workspace/coverage/default/19.hmac_burst_wr.2222455423 Jan 10 01:21:40 PM PST 24 Jan 10 01:22:25 PM PST 24 5145798347 ps
T770 /workspace/coverage/default/49.hmac_back_pressure.1431583940 Jan 10 01:22:43 PM PST 24 Jan 10 01:23:08 PM PST 24 336798829 ps
T771 /workspace/coverage/default/3.hmac_burst_wr.1741037273 Jan 10 01:21:33 PM PST 24 Jan 10 01:22:21 PM PST 24 1036426470 ps
T772 /workspace/coverage/default/6.hmac_wipe_secret.1702477013 Jan 10 01:21:39 PM PST 24 Jan 10 01:22:44 PM PST 24 1107404325 ps
T773 /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.961485265 Jan 10 01:23:20 PM PST 24 Jan 10 01:35:14 PM PST 24 73066197063 ps
T52 /workspace/coverage/default/0.hmac_sec_cm.2091885952 Jan 10 01:21:29 PM PST 24 Jan 10 01:21:43 PM PST 24 454430787 ps
T774 /workspace/coverage/default/10.hmac_test_sha_vectors.1376554458 Jan 10 01:21:44 PM PST 24 Jan 10 01:29:28 PM PST 24 48397929817 ps
T775 /workspace/coverage/default/20.hmac_long_msg.133422160 Jan 10 01:21:43 PM PST 24 Jan 10 01:23:29 PM PST 24 1621129179 ps
T776 /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.3875080612 Jan 10 01:22:17 PM PST 24 Jan 10 02:01:45 PM PST 24 64259193269 ps
T777 /workspace/coverage/default/40.hmac_alert_test.3514247233 Jan 10 01:22:43 PM PST 24 Jan 10 01:23:03 PM PST 24 47072241 ps
T778 /workspace/coverage/default/30.hmac_stress_all.222197296 Jan 10 01:22:17 PM PST 24 Jan 10 01:35:34 PM PST 24 15929468088 ps
T779 /workspace/coverage/default/28.hmac_back_pressure.2152832690 Jan 10 01:22:23 PM PST 24 Jan 10 01:23:13 PM PST 24 3346930312 ps
T780 /workspace/coverage/default/32.hmac_back_pressure.3495961756 Jan 10 01:22:23 PM PST 24 Jan 10 01:23:22 PM PST 24 10936305219 ps
T781 /workspace/coverage/default/39.hmac_datapath_stress.3163489042 Jan 10 01:22:29 PM PST 24 Jan 10 01:24:33 PM PST 24 2208668425 ps
T782 /workspace/coverage/default/16.hmac_error.1316663531 Jan 10 01:21:36 PM PST 24 Jan 10 01:23:30 PM PST 24 7820576882 ps
T783 /workspace/coverage/default/34.hmac_wipe_secret.2413681315 Jan 10 01:23:08 PM PST 24 Jan 10 01:24:52 PM PST 24 5123277829 ps
T784 /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.4258559068 Jan 10 01:23:09 PM PST 24 Jan 10 01:43:19 PM PST 24 251442844701 ps
T785 /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.1434354932 Jan 10 01:22:58 PM PST 24 Jan 10 01:57:39 PM PST 24 221014284863 ps
T786 /workspace/coverage/default/37.hmac_stress_all.2418400501 Jan 10 01:22:30 PM PST 24 Jan 10 01:39:27 PM PST 24 306169145958 ps
T787 /workspace/coverage/default/45.hmac_smoke.4014511643 Jan 10 01:22:49 PM PST 24 Jan 10 01:23:11 PM PST 24 1768537887 ps
T788 /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.2709587461 Jan 10 01:23:20 PM PST 24 Jan 10 01:40:06 PM PST 24 281856369351 ps
T789 /workspace/coverage/default/7.hmac_long_msg.435673075 Jan 10 01:21:33 PM PST 24 Jan 10 01:23:09 PM PST 24 5089791756 ps
T790 /workspace/coverage/default/0.hmac_test_hmac_vectors.1127064697 Jan 10 01:21:10 PM PST 24 Jan 10 01:21:15 PM PST 24 94607055 ps
T791 /workspace/coverage/default/42.hmac_alert_test.1354540877 Jan 10 01:22:43 PM PST 24 Jan 10 01:23:04 PM PST 24 13817478 ps
T792 /workspace/coverage/default/49.hmac_error.1503769309 Jan 10 01:22:42 PM PST 24 Jan 10 01:24:15 PM PST 24 26438425703 ps
T793 /workspace/coverage/default/10.hmac_test_hmac_vectors.860464067 Jan 10 01:21:32 PM PST 24 Jan 10 01:21:52 PM PST 24 33461390 ps
T794 /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.1871973944 Jan 10 01:22:45 PM PST 24 Jan 10 01:43:47 PM PST 24 32356285788 ps
T795 /workspace/coverage/default/16.hmac_test_hmac_vectors.3207404271 Jan 10 01:21:41 PM PST 24 Jan 10 01:22:03 PM PST 24 142618108 ps
T796 /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.2301433566 Jan 10 01:22:56 PM PST 24 Jan 10 02:25:52 PM PST 24 92738180363 ps
T797 /workspace/coverage/default/21.hmac_test_hmac_vectors.845691510 Jan 10 01:21:51 PM PST 24 Jan 10 01:22:20 PM PST 24 139255536 ps
T798 /workspace/coverage/default/32.hmac_error.1783241595 Jan 10 01:22:46 PM PST 24 Jan 10 01:25:12 PM PST 24 2585236742 ps
T799 /workspace/coverage/default/27.hmac_long_msg.1090203408 Jan 10 01:21:51 PM PST 24 Jan 10 01:22:52 PM PST 24 26751719258 ps
T800 /workspace/coverage/default/6.hmac_test_hmac_vectors.4264179923 Jan 10 01:21:54 PM PST 24 Jan 10 01:22:24 PM PST 24 451929162 ps
T801 /workspace/coverage/default/16.hmac_test_sha_vectors.3058073460 Jan 10 01:21:41 PM PST 24 Jan 10 01:27:46 PM PST 24 7163680258 ps
T802 /workspace/coverage/default/25.hmac_smoke.4218773057 Jan 10 01:21:58 PM PST 24 Jan 10 01:22:31 PM PST 24 1031245853 ps
T803 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3529991463 Jan 10 12:59:31 PM PST 24 Jan 10 01:01:15 PM PST 24 12980872 ps
T804 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.100328795 Jan 10 12:59:51 PM PST 24 Jan 10 01:01:28 PM PST 24 124719906 ps
T805 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2260108568 Jan 10 01:00:08 PM PST 24 Jan 10 01:01:37 PM PST 24 39651940 ps
T806 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3135817638 Jan 10 12:59:57 PM PST 24 Jan 10 01:01:27 PM PST 24 39938005 ps
T807 /workspace/coverage/cover_reg_top/39.hmac_intr_test.744195862 Jan 10 01:00:08 PM PST 24 Jan 10 01:01:37 PM PST 24 53193919 ps
T808 /workspace/coverage/cover_reg_top/49.hmac_intr_test.453298703 Jan 10 01:00:01 PM PST 24 Jan 10 01:01:35 PM PST 24 34638034 ps
T104 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.230764809 Jan 10 12:59:54 PM PST 24 Jan 10 01:01:26 PM PST 24 113908665 ps
T82 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3358544905 Jan 10 12:59:55 PM PST 24 Jan 10 01:01:26 PM PST 24 11985152 ps
T103 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.89432811 Jan 10 12:59:49 PM PST 24 Jan 10 01:01:26 PM PST 24 131482110 ps
T809 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3775329479 Jan 10 12:59:32 PM PST 24 Jan 10 01:01:03 PM PST 24 30052118 ps
T810 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3463084524 Jan 10 12:59:58 PM PST 24 Jan 10 01:01:27 PM PST 24 28047875 ps
T106 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1319102148 Jan 10 12:59:56 PM PST 24 Jan 10 01:01:31 PM PST 24 297195699 ps
T811 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1298202241 Jan 10 12:59:47 PM PST 24 Jan 10 01:01:30 PM PST 24 12343450 ps
T99 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3027382241 Jan 10 12:59:47 PM PST 24 Jan 10 01:01:24 PM PST 24 15185315 ps
T812 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.726750131 Jan 10 12:59:53 PM PST 24 Jan 10 01:01:40 PM PST 24 580192208 ps
T813 /workspace/coverage/cover_reg_top/19.hmac_intr_test.50888488 Jan 10 12:59:49 PM PST 24 Jan 10 01:01:25 PM PST 24 27629053 ps
T814 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1474979890 Jan 10 12:59:59 PM PST 24 Jan 10 01:01:27 PM PST 24 12595693 ps
T815 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3808759362 Jan 10 12:59:51 PM PST 24 Jan 10 01:01:32 PM PST 24 51334538 ps
T816 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3599244630 Jan 10 12:59:46 PM PST 24 Jan 10 01:01:24 PM PST 24 85126320 ps
T83 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2582532488 Jan 10 12:59:47 PM PST 24 Jan 10 01:01:30 PM PST 24 21493142 ps
T817 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3642300073 Jan 10 12:59:31 PM PST 24 Jan 10 01:01:17 PM PST 24 171465050 ps
T818 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1042827656 Jan 10 12:59:54 PM PST 24 Jan 10 01:01:34 PM PST 24 86082784 ps
T819 /workspace/coverage/cover_reg_top/37.hmac_intr_test.834441612 Jan 10 01:00:00 PM PST 24 Jan 10 01:01:32 PM PST 24 38406657 ps
T820 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2603276120 Jan 10 12:59:34 PM PST 24 Jan 10 01:01:07 PM PST 24 125649790 ps
T821 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2337284176 Jan 10 01:00:09 PM PST 24 Jan 10 01:01:54 PM PST 24 14395737 ps
T822 /workspace/coverage/cover_reg_top/24.hmac_intr_test.615166783 Jan 10 12:59:55 PM PST 24 Jan 10 01:01:26 PM PST 24 13659814 ps
T823 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2390474245 Jan 10 12:59:54 PM PST 24 Jan 10 01:01:35 PM PST 24 71420374 ps
T824 /workspace/coverage/cover_reg_top/33.hmac_intr_test.4046293641 Jan 10 12:59:52 PM PST 24 Jan 10 01:01:33 PM PST 24 44610160 ps
T825 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2127576209 Jan 10 12:59:54 PM PST 24 Jan 10 01:01:37 PM PST 24 160939903 ps
T826 /workspace/coverage/cover_reg_top/12.hmac_intr_test.4035787163 Jan 10 12:59:47 PM PST 24 Jan 10 01:01:27 PM PST 24 15763814 ps
T827 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3094345659 Jan 10 12:59:30 PM PST 24 Jan 10 01:01:05 PM PST 24 252105412 ps
T828 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2793339707 Jan 10 12:59:53 PM PST 24 Jan 10 01:01:22 PM PST 24 49765642 ps
T829 /workspace/coverage/cover_reg_top/5.hmac_intr_test.434423920 Jan 10 12:59:46 PM PST 24 Jan 10 01:01:18 PM PST 24 35450184 ps
T830 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2228352170 Jan 10 01:00:12 PM PST 24 Jan 10 01:01:36 PM PST 24 14854500 ps
T831 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3511742862 Jan 10 12:59:55 PM PST 24 Jan 10 01:01:25 PM PST 24 16457028 ps
T832 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1664102987 Jan 10 12:59:58 PM PST 24 Jan 10 01:01:30 PM PST 24 40456235 ps
T833 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.351525148 Jan 10 01:00:08 PM PST 24 Jan 10 01:01:38 PM PST 24 51857505 ps
T834 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2116685999 Jan 10 12:59:47 PM PST 24 Jan 10 01:01:27 PM PST 24 146557243 ps
T835 /workspace/coverage/cover_reg_top/6.hmac_intr_test.155259776 Jan 10 12:59:43 PM PST 24 Jan 10 01:01:21 PM PST 24 116618907 ps
T836 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4031991710 Jan 10 12:59:46 PM PST 24 Jan 10 01:01:27 PM PST 24 53842547 ps
T837 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.347877000 Jan 10 12:59:54 PM PST 24 Jan 10 01:01:38 PM PST 24 46526430 ps
T838 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4139420231 Jan 10 12:59:49 PM PST 24 Jan 10 01:01:25 PM PST 24 249146703 ps
T84 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2145295440 Jan 10 12:59:29 PM PST 24 Jan 10 01:01:06 PM PST 24 594046798 ps
T839 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1515957151 Jan 10 01:00:02 PM PST 24 Jan 10 01:02:12 PM PST 24 14417032 ps
T840 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.789812303 Jan 10 12:59:35 PM PST 24 Jan 10 01:01:17 PM PST 24 73235704 ps
T841 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3077995704 Jan 10 12:59:59 PM PST 24 Jan 10 01:01:42 PM PST 24 57856248 ps
T842 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1659572569 Jan 10 12:59:34 PM PST 24 Jan 10 01:01:05 PM PST 24 20231130 ps
T843 /workspace/coverage/cover_reg_top/31.hmac_intr_test.374562421 Jan 10 01:00:08 PM PST 24 Jan 10 01:01:33 PM PST 24 44350529 ps
T844 /workspace/coverage/cover_reg_top/38.hmac_intr_test.555946694 Jan 10 12:59:56 PM PST 24 Jan 10 01:01:28 PM PST 24 14668592 ps
T105 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.721307235 Jan 10 12:59:43 PM PST 24 Jan 10 01:01:24 PM PST 24 59397437 ps
T845 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.702670062 Jan 10 12:59:43 PM PST 24 Jan 10 01:01:22 PM PST 24 101233077 ps
T85 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.57289754 Jan 10 12:59:32 PM PST 24 Jan 10 01:01:13 PM PST 24 78127969 ps
T846 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2551873595 Jan 10 01:00:11 PM PST 24 Jan 10 01:01:54 PM PST 24 34446163 ps
T847 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1165241885 Jan 10 12:59:52 PM PST 24 Jan 10 01:01:33 PM PST 24 118508531 ps
T848 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2704209528 Jan 10 12:59:49 PM PST 24 Jan 10 01:01:33 PM PST 24 388635678 ps
T849 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3644458950 Jan 10 12:59:27 PM PST 24 Jan 10 01:01:02 PM PST 24 12976727 ps

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.271584647
Short name T14
Test name
Test status
Simulation time 23879135 ps
CPU time 0.59 seconds
Started Jan 10 12:59:51 PM PST 24
Finished Jan 10 01:01:28 PM PST 24
Peak memory 194196 kb
Host smart-4959ad6d-0dd2-422c-acc6-55dfabc529e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271584647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.271584647
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.3504717196
Short name T5
Test name
Test status
Simulation time 439429761657 ps
CPU time 1546.29 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:48:50 PM PST 24
Peak memory 243964 kb
Host smart-85988acb-9e6e-4908-ab10-8c1a2c051af4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3504717196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.3504717196
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4098391133
Short name T15
Test name
Test status
Simulation time 405878724 ps
CPU time 1.91 seconds
Started Jan 10 12:59:31 PM PST 24
Finished Jan 10 01:01:04 PM PST 24
Peak memory 198636 kb
Host smart-4990e396-6551-4a27-9626-eb7e6228fd5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098391133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4098391133
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.880331721
Short name T61
Test name
Test status
Simulation time 48180824 ps
CPU time 0.62 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:01:24 PM PST 24
Peak memory 193204 kb
Host smart-d9a972cd-84d9-4d0f-bc6f-f23ef37dd00a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880331721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.880331721
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.777869982
Short name T65
Test name
Test status
Simulation time 98478112 ps
CPU time 2 seconds
Started Jan 10 12:59:46 PM PST 24
Finished Jan 10 01:01:21 PM PST 24
Peak memory 198860 kb
Host smart-59518574-2100-4929-8c38-92e115641213
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777869982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.777869982
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.1829453053
Short name T76
Test name
Test status
Simulation time 138129242471 ps
CPU time 5353.72 seconds
Started Jan 10 01:23:21 PM PST 24
Finished Jan 10 02:52:47 PM PST 24
Peak memory 271444 kb
Host smart-ecb472a9-6fd0-42e0-be06-90762e40f873
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829453053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.1829453053
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.851261752
Short name T20
Test name
Test status
Simulation time 64721620 ps
CPU time 1.48 seconds
Started Jan 10 12:59:52 PM PST 24
Finished Jan 10 01:01:34 PM PST 24
Peak memory 198780 kb
Host smart-199f58c4-c48f-4a25-a1df-4073220af22e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851261752 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.851261752
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2091885952
Short name T52
Test name
Test status
Simulation time 454430787 ps
CPU time 0.86 seconds
Started Jan 10 01:21:29 PM PST 24
Finished Jan 10 01:21:43 PM PST 24
Peak memory 216040 kb
Host smart-6c692d87-dff0-4e03-8c9a-d4333156e9bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091885952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2091885952
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2233375884
Short name T148
Test name
Test status
Simulation time 28521921 ps
CPU time 0.58 seconds
Started Jan 10 12:59:54 PM PST 24
Finished Jan 10 01:01:25 PM PST 24
Peak memory 193064 kb
Host smart-f294e615-057d-4684-839d-36049aa5b960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233375884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2233375884
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1266822154
Short name T117
Test name
Test status
Simulation time 83279263868 ps
CPU time 1032.72 seconds
Started Jan 10 01:22:41 PM PST 24
Finished Jan 10 01:40:15 PM PST 24
Peak memory 198708 kb
Host smart-d6b7c58a-0456-4512-ae65-e3de621e86e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266822154 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1266822154
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.2198926357
Short name T116
Test name
Test status
Simulation time 156548386407 ps
CPU time 2674.13 seconds
Started Jan 10 01:23:24 PM PST 24
Finished Jan 10 02:08:08 PM PST 24
Peak memory 228760 kb
Host smart-9541040e-a6cb-4a10-b6b5-513dc1c8623b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198926357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.2198926357
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3717840898
Short name T72
Test name
Test status
Simulation time 772839044 ps
CPU time 2.35 seconds
Started Jan 10 12:59:58 PM PST 24
Finished Jan 10 01:01:35 PM PST 24
Peak memory 198464 kb
Host smart-4330e070-11a4-45b4-8bcf-8e7e331948f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717840898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3717840898
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2101349834
Short name T11
Test name
Test status
Simulation time 42090915 ps
CPU time 0.56 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:21:55 PM PST 24
Peak memory 192976 kb
Host smart-07cd32c6-084b-4001-9299-b23caed8f7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101349834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2101349834
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_stress_all.434533154
Short name T38
Test name
Test status
Simulation time 29717181991 ps
CPU time 609.55 seconds
Started Jan 10 01:21:35 PM PST 24
Finished Jan 10 01:32:03 PM PST 24
Peak memory 224512 kb
Host smart-d7992c2e-adfd-480e-b0e6-5187ccfb40e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434533154 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.434533154
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.747723232
Short name T677
Test name
Test status
Simulation time 95154648786 ps
CPU time 4415.14 seconds
Started Jan 10 01:23:32 PM PST 24
Finished Jan 10 02:37:12 PM PST 24
Peak memory 264412 kb
Host smart-12e97022-fabf-4646-a341-2a70f15a9efd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747723232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.747723232
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.736072593
Short name T130
Test name
Test status
Simulation time 637975777555 ps
CPU time 4299.49 seconds
Started Jan 10 01:23:03 PM PST 24
Finished Jan 10 02:35:00 PM PST 24
Peak memory 260696 kb
Host smart-88d959b9-3c4c-4136-b7cb-e369b21e8e20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=736072593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.736072593
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3143986258
Short name T100
Test name
Test status
Simulation time 29052770 ps
CPU time 0.78 seconds
Started Jan 10 12:59:27 PM PST 24
Finished Jan 10 01:01:02 PM PST 24
Peak memory 192092 kb
Host smart-ecedc168-cd18-493e-87ba-302ecf9b140e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143986258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3143986258
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1754363689
Short name T71
Test name
Test status
Simulation time 213723994 ps
CPU time 1.13 seconds
Started Jan 10 12:59:31 PM PST 24
Finished Jan 10 01:01:05 PM PST 24
Peak memory 198044 kb
Host smart-ed92432c-99bb-4848-81d1-42c1a9a78f03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754363689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1754363689
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.2694134756
Short name T143
Test name
Test status
Simulation time 82934903102 ps
CPU time 645.81 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:34:14 PM PST 24
Peak memory 215228 kb
Host smart-184b8f61-1bea-4c4d-a3c2-17de0560f981
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694134756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.2694134756
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.3216057644
Short name T122
Test name
Test status
Simulation time 363991304934 ps
CPU time 4736.15 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 02:42:24 PM PST 24
Peak memory 256344 kb
Host smart-00173392-1257-4824-a66b-fc62a10e4433
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216057644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.hmac_stress_all_with_rand_reset.3216057644
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.1293050072
Short name T110
Test name
Test status
Simulation time 270272887798 ps
CPU time 1050.61 seconds
Started Jan 10 01:23:21 PM PST 24
Finished Jan 10 01:41:03 PM PST 24
Peak memory 215140 kb
Host smart-47c29714-af70-4794-9b70-4b5a0298c78f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293050072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.1293050072
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.1058766940
Short name T142
Test name
Test status
Simulation time 78037867669 ps
CPU time 2518.99 seconds
Started Jan 10 01:23:15 PM PST 24
Finished Jan 10 02:05:30 PM PST 24
Peak memory 256340 kb
Host smart-524a57ae-260f-45a1-a92e-f2dd034d40fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1058766940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.1058766940
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_stress_all.632790331
Short name T144
Test name
Test status
Simulation time 251400297554 ps
CPU time 1951.79 seconds
Started Jan 10 01:22:39 PM PST 24
Finished Jan 10 01:55:33 PM PST 24
Peak memory 214976 kb
Host smart-d4c03193-1f00-4b7e-a9b3-fd0d9318779c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632790331 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.632790331
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2145295440
Short name T84
Test name
Test status
Simulation time 594046798 ps
CPU time 5.52 seconds
Started Jan 10 12:59:29 PM PST 24
Finished Jan 10 01:01:06 PM PST 24
Peak memory 192332 kb
Host smart-287229a2-8c57-44fe-ac30-30667df60e4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145295440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2145295440
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1659572569
Short name T842
Test name
Test status
Simulation time 20231130 ps
CPU time 0.83 seconds
Started Jan 10 12:59:34 PM PST 24
Finished Jan 10 01:01:05 PM PST 24
Peak memory 198692 kb
Host smart-895c9bdc-e592-4379-ab4a-943f1ff1cc72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659572569 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1659572569
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3775329479
Short name T809
Test name
Test status
Simulation time 30052118 ps
CPU time 0.56 seconds
Started Jan 10 12:59:32 PM PST 24
Finished Jan 10 01:01:03 PM PST 24
Peak memory 193092 kb
Host smart-9fb5e2a9-0931-4205-ac45-ff3d924e7fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775329479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3775329479
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.939923665
Short name T28
Test name
Test status
Simulation time 111501646 ps
CPU time 2.14 seconds
Started Jan 10 12:59:27 PM PST 24
Finished Jan 10 01:01:04 PM PST 24
Peak memory 198728 kb
Host smart-e8e651b1-85a6-4c04-9411-0679bb2ff33d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939923665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.939923665
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1139725652
Short name T26
Test name
Test status
Simulation time 36842350 ps
CPU time 2.63 seconds
Started Jan 10 12:59:27 PM PST 24
Finished Jan 10 01:01:04 PM PST 24
Peak memory 198804 kb
Host smart-136b656a-4057-4524-b484-e2407fedca07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139725652 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1139725652
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3529991463
Short name T803
Test name
Test status
Simulation time 12980872 ps
CPU time 0.56 seconds
Started Jan 10 12:59:31 PM PST 24
Finished Jan 10 01:01:15 PM PST 24
Peak memory 193128 kb
Host smart-4c158e2d-1590-42cd-b7b8-234f1b8995cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529991463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3529991463
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3094345659
Short name T827
Test name
Test status
Simulation time 252105412 ps
CPU time 1.14 seconds
Started Jan 10 12:59:30 PM PST 24
Finished Jan 10 01:01:05 PM PST 24
Peak memory 192252 kb
Host smart-a3ed7247-c523-49a1-8522-2c5b023e4c34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094345659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3094345659
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1977616976
Short name T25
Test name
Test status
Simulation time 124496171 ps
CPU time 2.21 seconds
Started Jan 10 12:59:41 PM PST 24
Finished Jan 10 01:01:20 PM PST 24
Peak memory 198392 kb
Host smart-ea0f4231-3439-41c9-b2e3-c7e07fc9eeab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977616976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1977616976
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2390474245
Short name T823
Test name
Test status
Simulation time 71420374 ps
CPU time 1.62 seconds
Started Jan 10 12:59:54 PM PST 24
Finished Jan 10 01:01:35 PM PST 24
Peak memory 198572 kb
Host smart-9e75aa13-9ddc-446b-9930-26cefa0db6a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390474245 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2390474245
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2678935532
Short name T73
Test name
Test status
Simulation time 283154206 ps
CPU time 0.78 seconds
Started Jan 10 12:59:49 PM PST 24
Finished Jan 10 01:01:32 PM PST 24
Peak memory 192140 kb
Host smart-6364bd52-f30c-45f8-8732-d40efb7fe5ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678935532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2678935532
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1319102148
Short name T106
Test name
Test status
Simulation time 297195699 ps
CPU time 2.25 seconds
Started Jan 10 12:59:56 PM PST 24
Finished Jan 10 01:01:31 PM PST 24
Peak memory 198600 kb
Host smart-3d2ae9b9-3a80-49ab-bbaf-78d81cba82e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319102148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1319102148
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3358544905
Short name T82
Test name
Test status
Simulation time 11985152 ps
CPU time 0.64 seconds
Started Jan 10 12:59:55 PM PST 24
Finished Jan 10 01:01:26 PM PST 24
Peak memory 194016 kb
Host smart-ffadfc56-9dd8-4be5-aa6b-20871d8e109d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358544905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3358544905
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.4139420231
Short name T838
Test name
Test status
Simulation time 249146703 ps
CPU time 1.05 seconds
Started Jan 10 12:59:49 PM PST 24
Finished Jan 10 01:01:25 PM PST 24
Peak memory 196772 kb
Host smart-34c4df74-3ea0-4f4f-9d87-f89cb5995d4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139420231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.4139420231
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2704209528
Short name T848
Test name
Test status
Simulation time 388635678 ps
CPU time 1.62 seconds
Started Jan 10 12:59:49 PM PST 24
Finished Jan 10 01:01:33 PM PST 24
Peak memory 198304 kb
Host smart-5a611c33-b885-4ec8-ae64-44d3faadfe03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704209528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2704209528
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.351525148
Short name T833
Test name
Test status
Simulation time 51857505 ps
CPU time 1.5 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:01:38 PM PST 24
Peak memory 198808 kb
Host smart-7897ade5-96c7-4940-96db-dd98bbcc63a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351525148 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.351525148
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1142650031
Short name T18
Test name
Test status
Simulation time 51108018 ps
CPU time 0.6 seconds
Started Jan 10 12:59:49 PM PST 24
Finished Jan 10 01:01:25 PM PST 24
Peak memory 194128 kb
Host smart-d2c339e1-9266-4d3c-8b53-c52aa60b98db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142650031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1142650031
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.4035787163
Short name T826
Test name
Test status
Simulation time 15763814 ps
CPU time 0.58 seconds
Started Jan 10 12:59:47 PM PST 24
Finished Jan 10 01:01:27 PM PST 24
Peak memory 193228 kb
Host smart-8e704283-8c10-4349-bd64-7040fb99543f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035787163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.4035787163
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.100328795
Short name T804
Test name
Test status
Simulation time 124719906 ps
CPU time 1.36 seconds
Started Jan 10 12:59:51 PM PST 24
Finished Jan 10 01:01:28 PM PST 24
Peak memory 192312 kb
Host smart-e32ce525-eed7-4fb4-a894-1dcff64e2a71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100328795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.100328795
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.230764809
Short name T104
Test name
Test status
Simulation time 113908665 ps
CPU time 2.31 seconds
Started Jan 10 12:59:54 PM PST 24
Finished Jan 10 01:01:26 PM PST 24
Peak memory 198632 kb
Host smart-a9891afc-217f-460a-bc2a-7b3fb4338cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230764809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.230764809
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1664102987
Short name T832
Test name
Test status
Simulation time 40456235 ps
CPU time 0.8 seconds
Started Jan 10 12:59:58 PM PST 24
Finished Jan 10 01:01:30 PM PST 24
Peak memory 198432 kb
Host smart-efcebeec-e263-4611-8f4b-90f43089f439
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664102987 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1664102987
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1298202241
Short name T811
Test name
Test status
Simulation time 12343450 ps
CPU time 0.62 seconds
Started Jan 10 12:59:47 PM PST 24
Finished Jan 10 01:01:30 PM PST 24
Peak memory 194404 kb
Host smart-293462d7-f655-4c88-951e-9cdb6a05d6a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298202241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1298202241
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1007728182
Short name T22
Test name
Test status
Simulation time 10879678 ps
CPU time 0.55 seconds
Started Jan 10 12:59:51 PM PST 24
Finished Jan 10 01:01:28 PM PST 24
Peak memory 193240 kb
Host smart-19f4b9c7-953b-4a8c-8fca-228fec580eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007728182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1007728182
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.347877000
Short name T837
Test name
Test status
Simulation time 46526430 ps
CPU time 1.11 seconds
Started Jan 10 12:59:54 PM PST 24
Finished Jan 10 01:01:38 PM PST 24
Peak memory 192408 kb
Host smart-d41dd7c4-ff9a-4720-9a2b-93a550b2ad26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347877000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.347877000
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.702670062
Short name T845
Test name
Test status
Simulation time 101233077 ps
CPU time 1.88 seconds
Started Jan 10 12:59:43 PM PST 24
Finished Jan 10 01:01:22 PM PST 24
Peak memory 198328 kb
Host smart-76e8c54a-d288-411a-a45c-a620f7d0255f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702670062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.702670062
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3420321022
Short name T30
Test name
Test status
Simulation time 41885721 ps
CPU time 1.05 seconds
Started Jan 10 12:59:52 PM PST 24
Finished Jan 10 01:01:33 PM PST 24
Peak memory 198576 kb
Host smart-37fa05ca-dc69-48bd-9c6f-9785618e0a47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420321022 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3420321022
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1170398958
Short name T152
Test name
Test status
Simulation time 45551849 ps
CPU time 0.59 seconds
Started Jan 10 12:59:59 PM PST 24
Finished Jan 10 01:01:36 PM PST 24
Peak memory 193120 kb
Host smart-42bf14eb-1e6f-4793-9b85-9dcd1fd16779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170398958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1170398958
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1165241885
Short name T847
Test name
Test status
Simulation time 118508531 ps
CPU time 1.3 seconds
Started Jan 10 12:59:52 PM PST 24
Finished Jan 10 01:01:33 PM PST 24
Peak memory 192372 kb
Host smart-80b61ae5-f70e-49fa-87d0-54e89acc0279
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165241885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1165241885
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.417487851
Short name T70
Test name
Test status
Simulation time 73590301 ps
CPU time 1.64 seconds
Started Jan 10 12:59:55 PM PST 24
Finished Jan 10 01:01:34 PM PST 24
Peak memory 198388 kb
Host smart-c663f759-08ff-4e82-9aec-8ac913cbc04f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417487851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.417487851
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1031419709
Short name T146
Test name
Test status
Simulation time 21911889 ps
CPU time 0.71 seconds
Started Jan 10 12:59:53 PM PST 24
Finished Jan 10 01:01:21 PM PST 24
Peak memory 195208 kb
Host smart-b3b43489-9ac8-4f4b-a46e-fae6b7698fcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031419709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1031419709
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1042827656
Short name T818
Test name
Test status
Simulation time 86082784 ps
CPU time 0.63 seconds
Started Jan 10 12:59:54 PM PST 24
Finished Jan 10 01:01:34 PM PST 24
Peak memory 192992 kb
Host smart-7272cf92-2d83-4965-a514-7bc43684a7de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042827656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1042827656
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3808759362
Short name T815
Test name
Test status
Simulation time 51334538 ps
CPU time 0.77 seconds
Started Jan 10 12:59:51 PM PST 24
Finished Jan 10 01:01:32 PM PST 24
Peak memory 195468 kb
Host smart-3aaca9f1-7e02-48a4-8502-e47f30de0527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808759362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3808759362
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.726750131
Short name T812
Test name
Test status
Simulation time 580192208 ps
CPU time 3.17 seconds
Started Jan 10 12:59:53 PM PST 24
Finished Jan 10 01:01:40 PM PST 24
Peak memory 198796 kb
Host smart-68b45b95-77fa-468f-92d4-fdd06144637b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726750131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.726750131
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.89432811
Short name T103
Test name
Test status
Simulation time 131482110 ps
CPU time 1.82 seconds
Started Jan 10 12:59:49 PM PST 24
Finished Jan 10 01:01:26 PM PST 24
Peak memory 198392 kb
Host smart-984657a4-ee3c-4cbc-bbdf-dec3d6850a66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89432811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.89432811
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2793339707
Short name T828
Test name
Test status
Simulation time 49765642 ps
CPU time 1.3 seconds
Started Jan 10 12:59:53 PM PST 24
Finished Jan 10 01:01:22 PM PST 24
Peak memory 198748 kb
Host smart-0b4ca081-0ae6-4b8d-9703-aa6f47fbbcb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793339707 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2793339707
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2582532488
Short name T83
Test name
Test status
Simulation time 21493142 ps
CPU time 0.71 seconds
Started Jan 10 12:59:47 PM PST 24
Finished Jan 10 01:01:30 PM PST 24
Peak memory 195072 kb
Host smart-320d8133-73b6-4738-936d-520acaf9552a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582532488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2582532488
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2624088123
Short name T63
Test name
Test status
Simulation time 513030114 ps
CPU time 1.84 seconds
Started Jan 10 01:00:05 PM PST 24
Finished Jan 10 01:01:39 PM PST 24
Peak memory 198340 kb
Host smart-86c851fd-5a73-4895-a6cb-149ad4bc30b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624088123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2624088123
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1627152776
Short name T21
Test name
Test status
Simulation time 43110566 ps
CPU time 0.82 seconds
Started Jan 10 12:59:52 PM PST 24
Finished Jan 10 01:01:36 PM PST 24
Peak memory 198580 kb
Host smart-c57129e3-b939-4402-88f4-942b3139668c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627152776 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1627152776
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2112729562
Short name T102
Test name
Test status
Simulation time 71356853 ps
CPU time 0.66 seconds
Started Jan 10 12:59:58 PM PST 24
Finished Jan 10 01:01:27 PM PST 24
Peak memory 194348 kb
Host smart-8f8225ba-00f7-4cfc-858e-3a6055823a67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112729562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2112729562
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2228352170
Short name T830
Test name
Test status
Simulation time 14854500 ps
CPU time 0.59 seconds
Started Jan 10 01:00:12 PM PST 24
Finished Jan 10 01:01:36 PM PST 24
Peak memory 193280 kb
Host smart-fb319451-7f66-463d-bce8-cb686fdcc3ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228352170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2228352170
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3027382241
Short name T99
Test name
Test status
Simulation time 15185315 ps
CPU time 0.6 seconds
Started Jan 10 12:59:47 PM PST 24
Finished Jan 10 01:01:24 PM PST 24
Peak memory 194144 kb
Host smart-eed878a8-3d53-4ba3-a45c-d4eb50c17b2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027382241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3027382241
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3135817638
Short name T806
Test name
Test status
Simulation time 39938005 ps
CPU time 0.58 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:01:27 PM PST 24
Peak memory 192992 kb
Host smart-1fff93b1-4e7c-4dab-beac-6129fc82de32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135817638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3135817638
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2127576209
Short name T825
Test name
Test status
Simulation time 160939903 ps
CPU time 0.88 seconds
Started Jan 10 12:59:54 PM PST 24
Finished Jan 10 01:01:37 PM PST 24
Peak memory 195940 kb
Host smart-e2a3b004-1518-477d-a07c-34c39bc8b0f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127576209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2127576209
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1903861096
Short name T66
Test name
Test status
Simulation time 189317617 ps
CPU time 2.74 seconds
Started Jan 10 12:59:52 PM PST 24
Finished Jan 10 01:01:26 PM PST 24
Peak memory 198764 kb
Host smart-731920c7-9103-498c-9718-1151743bebe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903861096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1903861096
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.721307235
Short name T105
Test name
Test status
Simulation time 59397437 ps
CPU time 1.18 seconds
Started Jan 10 12:59:43 PM PST 24
Finished Jan 10 01:01:24 PM PST 24
Peak memory 198216 kb
Host smart-909b7ca6-e5a9-4d11-9212-d60d48d31753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721307235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.721307235
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.136585849
Short name T27
Test name
Test status
Simulation time 25921007 ps
CPU time 1.69 seconds
Started Jan 10 01:00:05 PM PST 24
Finished Jan 10 01:01:55 PM PST 24
Peak memory 198816 kb
Host smart-5e76630c-2bb8-4175-91c6-b50e79c92f1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136585849 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.136585849
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.50888488
Short name T813
Test name
Test status
Simulation time 27629053 ps
CPU time 0.6 seconds
Started Jan 10 12:59:49 PM PST 24
Finished Jan 10 01:01:25 PM PST 24
Peak memory 193116 kb
Host smart-2e478942-5e0e-419b-bdeb-797b81be8034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50888488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.50888488
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1922438880
Short name T68
Test name
Test status
Simulation time 761399941 ps
CPU time 3.56 seconds
Started Jan 10 12:59:28 PM PST 24
Finished Jan 10 01:01:05 PM PST 24
Peak memory 192324 kb
Host smart-8bf6831f-806a-42a7-a369-88a9b3e3778c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922438880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1922438880
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2603276120
Short name T820
Test name
Test status
Simulation time 125649790 ps
CPU time 0.59 seconds
Started Jan 10 12:59:34 PM PST 24
Finished Jan 10 01:01:07 PM PST 24
Peak memory 193836 kb
Host smart-de9f44ce-78f5-4a32-b17e-e0a485be0ce9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603276120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2603276120
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.171054146
Short name T29
Test name
Test status
Simulation time 240647367 ps
CPU time 0.95 seconds
Started Jan 10 12:59:26 PM PST 24
Finished Jan 10 01:00:59 PM PST 24
Peak memory 198688 kb
Host smart-03197e07-c69e-463d-af8c-4d6673fe0eab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171054146 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.171054146
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3644458950
Short name T849
Test name
Test status
Simulation time 12976727 ps
CPU time 0.58 seconds
Started Jan 10 12:59:27 PM PST 24
Finished Jan 10 01:01:02 PM PST 24
Peak memory 193236 kb
Host smart-a34e9120-bf37-4087-9c50-9c01d5167f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644458950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3644458950
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2260108568
Short name T805
Test name
Test status
Simulation time 39651940 ps
CPU time 0.57 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:01:37 PM PST 24
Peak memory 193204 kb
Host smart-e0683565-8710-444d-ac9c-3499e4036c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260108568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2260108568
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1515957151
Short name T839
Test name
Test status
Simulation time 14417032 ps
CPU time 0.6 seconds
Started Jan 10 01:00:02 PM PST 24
Finished Jan 10 01:02:12 PM PST 24
Peak memory 193292 kb
Host smart-8eb1d566-7f8b-4e71-8dfb-601ef5084348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515957151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1515957151
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2469180038
Short name T67
Test name
Test status
Simulation time 51178635 ps
CPU time 0.58 seconds
Started Jan 10 12:59:49 PM PST 24
Finished Jan 10 01:01:25 PM PST 24
Peak memory 193232 kb
Host smart-bb8bed21-bf41-4dbe-9de2-f78bbdcede70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469180038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2469180038
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.615166783
Short name T822
Test name
Test status
Simulation time 13659814 ps
CPU time 0.57 seconds
Started Jan 10 12:59:55 PM PST 24
Finished Jan 10 01:01:26 PM PST 24
Peak memory 193220 kb
Host smart-c8d2c035-ff0a-4e17-b5ec-78d59e815f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615166783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.615166783
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3077995704
Short name T841
Test name
Test status
Simulation time 57856248 ps
CPU time 0.59 seconds
Started Jan 10 12:59:59 PM PST 24
Finished Jan 10 01:01:42 PM PST 24
Peak memory 193160 kb
Host smart-0e327dab-10e3-43f8-bf0f-7226188c4110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077995704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3077995704
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1375178301
Short name T149
Test name
Test status
Simulation time 58349968 ps
CPU time 0.61 seconds
Started Jan 10 12:59:56 PM PST 24
Finished Jan 10 01:01:29 PM PST 24
Peak memory 193072 kb
Host smart-9b2a63a4-55d6-452e-97b1-340a9d9dde37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375178301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1375178301
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1812860430
Short name T147
Test name
Test status
Simulation time 17207025 ps
CPU time 0.56 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:01:29 PM PST 24
Peak memory 193232 kb
Host smart-db8c8ca4-a4b5-449f-a9c2-3d17a8dba254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812860430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1812860430
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3511742862
Short name T831
Test name
Test status
Simulation time 16457028 ps
CPU time 0.59 seconds
Started Jan 10 12:59:55 PM PST 24
Finished Jan 10 01:01:25 PM PST 24
Peak memory 193240 kb
Host smart-8473aeca-f020-45fa-906d-0a13d7a947f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511742862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3511742862
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1603723034
Short name T34
Test name
Test status
Simulation time 46400627 ps
CPU time 0.71 seconds
Started Jan 10 12:59:37 PM PST 24
Finished Jan 10 01:01:16 PM PST 24
Peak memory 194576 kb
Host smart-11035cba-ec1b-408c-854c-4a2f73ad558c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603723034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1603723034
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2116685999
Short name T834
Test name
Test status
Simulation time 146557243 ps
CPU time 1.31 seconds
Started Jan 10 12:59:47 PM PST 24
Finished Jan 10 01:01:27 PM PST 24
Peak memory 198696 kb
Host smart-1959da93-2d5a-41c1-97ca-68c3f894450a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116685999 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2116685999
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.57289754
Short name T85
Test name
Test status
Simulation time 78127969 ps
CPU time 0.71 seconds
Started Jan 10 12:59:32 PM PST 24
Finished Jan 10 01:01:13 PM PST 24
Peak memory 194744 kb
Host smart-7e6333a0-2641-480e-aedd-1d76164cffe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57289754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.57289754
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.684186620
Short name T107
Test name
Test status
Simulation time 47310651 ps
CPU time 0.57 seconds
Started Jan 10 12:59:34 PM PST 24
Finished Jan 10 01:01:05 PM PST 24
Peak memory 193072 kb
Host smart-00ade701-7bad-44b1-a84e-4b9246739357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684186620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.684186620
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.989603961
Short name T101
Test name
Test status
Simulation time 156143560 ps
CPU time 0.79 seconds
Started Jan 10 12:59:33 PM PST 24
Finished Jan 10 01:01:14 PM PST 24
Peak memory 195536 kb
Host smart-d6fe01d6-c67e-4e0d-a720-bf85559c7223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989603961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.989603961
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.62630192
Short name T24
Test name
Test status
Simulation time 72626678 ps
CPU time 1.06 seconds
Started Jan 10 12:59:28 PM PST 24
Finished Jan 10 01:01:02 PM PST 24
Peak memory 198512 kb
Host smart-4147798a-b6cd-4e29-94e9-6f2cf7b482af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62630192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.62630192
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2475836723
Short name T62
Test name
Test status
Simulation time 12163564 ps
CPU time 0.56 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:01:33 PM PST 24
Peak memory 193060 kb
Host smart-6dee04ed-ef6a-466c-8d67-4a8273a1ec2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475836723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2475836723
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.374562421
Short name T843
Test name
Test status
Simulation time 44350529 ps
CPU time 0.6 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:01:33 PM PST 24
Peak memory 193072 kb
Host smart-59bedf6a-5315-48e7-ab41-b7d02318bc9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374562421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.374562421
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3598818677
Short name T17
Test name
Test status
Simulation time 47981638 ps
CPU time 0.56 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:01:24 PM PST 24
Peak memory 193108 kb
Host smart-d685ab40-3fd1-4a77-a863-e1cb9eb78cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598818677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3598818677
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.4046293641
Short name T824
Test name
Test status
Simulation time 44610160 ps
CPU time 0.55 seconds
Started Jan 10 12:59:52 PM PST 24
Finished Jan 10 01:01:33 PM PST 24
Peak memory 193224 kb
Host smart-dbea057d-7d83-4f81-85fc-c6dad1df16f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046293641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.4046293641
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2551873595
Short name T846
Test name
Test status
Simulation time 34446163 ps
CPU time 0.6 seconds
Started Jan 10 01:00:11 PM PST 24
Finished Jan 10 01:01:54 PM PST 24
Peak memory 193220 kb
Host smart-3818274d-2224-4684-9c8d-789c417ecaee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551873595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2551873595
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.576670644
Short name T150
Test name
Test status
Simulation time 64747654 ps
CPU time 0.59 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:01:44 PM PST 24
Peak memory 193136 kb
Host smart-199ca05a-0c05-4a7e-b21a-1bbfc1ccfa94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576670644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.576670644
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2850311666
Short name T157
Test name
Test status
Simulation time 12630070 ps
CPU time 0.56 seconds
Started Jan 10 12:59:58 PM PST 24
Finished Jan 10 01:01:33 PM PST 24
Peak memory 193236 kb
Host smart-720002d2-5254-4784-9b90-97506ac99efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850311666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2850311666
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.834441612
Short name T819
Test name
Test status
Simulation time 38406657 ps
CPU time 0.57 seconds
Started Jan 10 01:00:00 PM PST 24
Finished Jan 10 01:01:32 PM PST 24
Peak memory 193240 kb
Host smart-019975b4-1dc2-4e76-945f-00e2d24b6dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834441612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.834441612
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.555946694
Short name T844
Test name
Test status
Simulation time 14668592 ps
CPU time 0.6 seconds
Started Jan 10 12:59:56 PM PST 24
Finished Jan 10 01:01:28 PM PST 24
Peak memory 193044 kb
Host smart-7c95983d-be07-46a6-9fe7-10bcf3e84c0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555946694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.555946694
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.744195862
Short name T807
Test name
Test status
Simulation time 53193919 ps
CPU time 0.57 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:01:37 PM PST 24
Peak memory 193280 kb
Host smart-78f7a552-7658-4f35-bf79-e001e5130c55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744195862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.744195862
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1214351812
Short name T32
Test name
Test status
Simulation time 65173704 ps
CPU time 0.7 seconds
Started Jan 10 12:59:40 PM PST 24
Finished Jan 10 01:01:13 PM PST 24
Peak memory 194460 kb
Host smart-f2205975-96d1-43d4-bc1b-62d45f207609
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214351812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1214351812
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3048129671
Short name T19
Test name
Test status
Simulation time 35293979 ps
CPU time 1.65 seconds
Started Jan 10 12:59:31 PM PST 24
Finished Jan 10 01:01:16 PM PST 24
Peak memory 198760 kb
Host smart-859bab15-640a-46e3-aeda-fc2747c95bed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048129671 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3048129671
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2500590283
Short name T33
Test name
Test status
Simulation time 15775563 ps
CPU time 0.56 seconds
Started Jan 10 12:59:47 PM PST 24
Finished Jan 10 01:01:30 PM PST 24
Peak memory 193132 kb
Host smart-dc962d9c-7766-4693-a8fa-f429ee26bbaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500590283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2500590283
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4031991710
Short name T836
Test name
Test status
Simulation time 53842547 ps
CPU time 0.78 seconds
Started Jan 10 12:59:46 PM PST 24
Finished Jan 10 01:01:27 PM PST 24
Peak memory 195620 kb
Host smart-2dd5ac46-bdbf-49f0-bec0-7fb064aa4a11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031991710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.4031991710
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1416663858
Short name T155
Test name
Test status
Simulation time 25535522 ps
CPU time 0.55 seconds
Started Jan 10 12:59:54 PM PST 24
Finished Jan 10 01:01:25 PM PST 24
Peak memory 193132 kb
Host smart-26762b34-1ca9-4639-aa42-3d4cee929a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416663858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1416663858
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3463084524
Short name T810
Test name
Test status
Simulation time 28047875 ps
CPU time 0.6 seconds
Started Jan 10 12:59:58 PM PST 24
Finished Jan 10 01:01:27 PM PST 24
Peak memory 193256 kb
Host smart-e1851b99-fb20-4bb2-8699-f1e6cc39d32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463084524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3463084524
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3451712432
Short name T16
Test name
Test status
Simulation time 23494786 ps
CPU time 0.58 seconds
Started Jan 10 12:59:53 PM PST 24
Finished Jan 10 01:01:24 PM PST 24
Peak memory 193220 kb
Host smart-7a6759eb-da36-4846-9dd1-c73aad74d156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451712432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3451712432
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2337284176
Short name T821
Test name
Test status
Simulation time 14395737 ps
CPU time 0.6 seconds
Started Jan 10 01:00:09 PM PST 24
Finished Jan 10 01:01:54 PM PST 24
Peak memory 193232 kb
Host smart-2d786737-a629-488d-b8f9-caed96452478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337284176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2337284176
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2082380171
Short name T151
Test name
Test status
Simulation time 22588046 ps
CPU time 0.58 seconds
Started Jan 10 12:59:54 PM PST 24
Finished Jan 10 01:01:31 PM PST 24
Peak memory 193204 kb
Host smart-dc520f50-11a4-487f-a260-596c7527483a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082380171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2082380171
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1474979890
Short name T814
Test name
Test status
Simulation time 12595693 ps
CPU time 0.56 seconds
Started Jan 10 12:59:59 PM PST 24
Finished Jan 10 01:01:27 PM PST 24
Peak memory 193212 kb
Host smart-582638ee-4d46-4c7e-9b12-af64cf77ad99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474979890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1474979890
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4058448665
Short name T153
Test name
Test status
Simulation time 39808424 ps
CPU time 0.56 seconds
Started Jan 10 01:00:01 PM PST 24
Finished Jan 10 01:01:44 PM PST 24
Peak memory 193212 kb
Host smart-0463bc47-84c5-48bc-9845-e390f3cbedfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058448665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4058448665
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1221548299
Short name T154
Test name
Test status
Simulation time 29038825 ps
CPU time 0.63 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:01:37 PM PST 24
Peak memory 193288 kb
Host smart-9f2f343a-fec0-48cd-95ed-977460a4a0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221548299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1221548299
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.453298703
Short name T808
Test name
Test status
Simulation time 34638034 ps
CPU time 0.56 seconds
Started Jan 10 01:00:01 PM PST 24
Finished Jan 10 01:01:35 PM PST 24
Peak memory 193284 kb
Host smart-05b05894-0ce8-4db8-9273-adf668eaf91d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453298703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.453298703
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.434423920
Short name T829
Test name
Test status
Simulation time 35450184 ps
CPU time 0.56 seconds
Started Jan 10 12:59:46 PM PST 24
Finished Jan 10 01:01:18 PM PST 24
Peak memory 193264 kb
Host smart-3c776f7e-09dd-41d4-8098-f97e381593a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434423920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.434423920
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1987529020
Short name T23
Test name
Test status
Simulation time 40272800 ps
CPU time 0.88 seconds
Started Jan 10 12:59:52 PM PST 24
Finished Jan 10 01:01:33 PM PST 24
Peak memory 195636 kb
Host smart-b764b9c1-08bd-4b73-aedb-ae88f48e4c24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987529020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1987529020
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3642300073
Short name T817
Test name
Test status
Simulation time 171465050 ps
CPU time 2.45 seconds
Started Jan 10 12:59:31 PM PST 24
Finished Jan 10 01:01:17 PM PST 24
Peak memory 198436 kb
Host smart-155a5eb5-5d0a-4beb-a090-ec5cac101148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642300073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3642300073
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.155259776
Short name T835
Test name
Test status
Simulation time 116618907 ps
CPU time 0.56 seconds
Started Jan 10 12:59:43 PM PST 24
Finished Jan 10 01:01:21 PM PST 24
Peak memory 193060 kb
Host smart-b3cd4316-799f-48c7-b85c-6d1aa1de8ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155259776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.155259776
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.789812303
Short name T840
Test name
Test status
Simulation time 73235704 ps
CPU time 1.15 seconds
Started Jan 10 12:59:35 PM PST 24
Finished Jan 10 01:01:17 PM PST 24
Peak memory 198236 kb
Host smart-a19e8387-dc80-4d4e-831e-88c731711395
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789812303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.789812303
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3599244630
Short name T816
Test name
Test status
Simulation time 85126320 ps
CPU time 0.75 seconds
Started Jan 10 12:59:46 PM PST 24
Finished Jan 10 01:01:24 PM PST 24
Peak memory 192180 kb
Host smart-e540bbae-7602-4ef0-a7d3-ca975ef126d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599244630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3599244630
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2292160115
Short name T156
Test name
Test status
Simulation time 27886424 ps
CPU time 0.61 seconds
Started Jan 10 12:59:33 PM PST 24
Finished Jan 10 01:01:14 PM PST 24
Peak memory 194388 kb
Host smart-40ab116c-8bb5-4ce8-8abe-ab1ffa645a5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292160115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2292160115
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1982423257
Short name T64
Test name
Test status
Simulation time 1211340295 ps
CPU time 3.24 seconds
Started Jan 10 12:59:37 PM PST 24
Finished Jan 10 01:01:19 PM PST 24
Peak memory 198736 kb
Host smart-55ac80c9-5e0f-466d-9c27-c5c3455e67cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982423257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1982423257
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3645099201
Short name T31
Test name
Test status
Simulation time 92856586 ps
CPU time 0.93 seconds
Started Jan 10 12:59:46 PM PST 24
Finished Jan 10 01:01:24 PM PST 24
Peak memory 198664 kb
Host smart-df64fd2c-2819-44e1-a997-640ec66db717
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645099201 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3645099201
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3096953748
Short name T424
Test name
Test status
Simulation time 34723890 ps
CPU time 0.57 seconds
Started Jan 10 01:21:08 PM PST 24
Finished Jan 10 01:21:13 PM PST 24
Peak memory 193132 kb
Host smart-7fc7ec60-3953-46fe-a13a-8b8f9c4d0b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096953748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3096953748
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.179661911
Short name T613
Test name
Test status
Simulation time 1053821730 ps
CPU time 35.86 seconds
Started Jan 10 01:21:27 PM PST 24
Finished Jan 10 01:22:08 PM PST 24
Peak memory 231348 kb
Host smart-8b53123d-4ba5-445a-9cda-775395156256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179661911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.179661911
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.310930220
Short name T219
Test name
Test status
Simulation time 570011466 ps
CPU time 7.69 seconds
Started Jan 10 01:21:12 PM PST 24
Finished Jan 10 01:21:23 PM PST 24
Peak memory 198800 kb
Host smart-0192de71-03a9-4fd4-a4d8-bd99519aa55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310930220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.310930220
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3156273108
Short name T405
Test name
Test status
Simulation time 9449504079 ps
CPU time 126.39 seconds
Started Jan 10 01:21:12 PM PST 24
Finished Jan 10 01:23:21 PM PST 24
Peak memory 198856 kb
Host smart-286eba85-1c0f-4dc0-a6a4-2b607955f54c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156273108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3156273108
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.938488369
Short name T598
Test name
Test status
Simulation time 60900603222 ps
CPU time 167.63 seconds
Started Jan 10 01:21:28 PM PST 24
Finished Jan 10 01:24:28 PM PST 24
Peak memory 198880 kb
Host smart-2de9c2af-4178-457f-9d3c-cfde2c594680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938488369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.938488369
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.494573616
Short name T431
Test name
Test status
Simulation time 5757730698 ps
CPU time 36.55 seconds
Started Jan 10 01:20:53 PM PST 24
Finished Jan 10 01:21:35 PM PST 24
Peak memory 198808 kb
Host smart-59f0c014-8a01-40e4-8307-01fe2a59c42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494573616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.494573616
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1842292111
Short name T527
Test name
Test status
Simulation time 1374316502 ps
CPU time 3.72 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:21:57 PM PST 24
Peak memory 198596 kb
Host smart-aca65b93-3283-4f45-b0ae-b0e4b130cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842292111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1842292111
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.528286993
Short name T376
Test name
Test status
Simulation time 37935334122 ps
CPU time 838.04 seconds
Started Jan 10 01:21:29 PM PST 24
Finished Jan 10 01:35:42 PM PST 24
Peak memory 240748 kb
Host smart-598c9e24-8657-45de-b419-0a2f88edf3a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528286993 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.528286993
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1527271439
Short name T284
Test name
Test status
Simulation time 10825764661 ps
CPU time 159.1 seconds
Started Jan 10 01:21:07 PM PST 24
Finished Jan 10 01:23:51 PM PST 24
Peak memory 215124 kb
Host smart-fc2711ff-fc80-4ba8-b4e2-b48c0b9911e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1527271439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1527271439
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1127064697
Short name T790
Test name
Test status
Simulation time 94607055 ps
CPU time 0.93 seconds
Started Jan 10 01:21:10 PM PST 24
Finished Jan 10 01:21:15 PM PST 24
Peak memory 197240 kb
Host smart-cb782e27-1b11-4953-90c6-fc27af1bb048
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127064697 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1127064697
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2862646474
Short name T215
Test name
Test status
Simulation time 14715508210 ps
CPU time 379.5 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:28:08 PM PST 24
Peak memory 198776 kb
Host smart-ae557f26-bd76-45b8-809c-385022c7ae3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862646474 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.2862646474
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3204336099
Short name T669
Test name
Test status
Simulation time 2172220167 ps
CPU time 33.67 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:22:27 PM PST 24
Peak memory 198936 kb
Host smart-5f31d7ff-5bbe-4ec1-a991-d579d2498c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204336099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3204336099
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3500433105
Short name T410
Test name
Test status
Simulation time 41480055 ps
CPU time 0.57 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:21:54 PM PST 24
Peak memory 193100 kb
Host smart-6591a97e-c8b5-4761-965b-8c105d5c4aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500433105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3500433105
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2021153320
Short name T592
Test name
Test status
Simulation time 470155390 ps
CPU time 16.95 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:22:10 PM PST 24
Peak memory 221368 kb
Host smart-5cfa0e89-611a-4ee7-985b-9a42e7b47c09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2021153320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2021153320
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1679264409
Short name T516
Test name
Test status
Simulation time 1532418178 ps
CPU time 33.54 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:34 PM PST 24
Peak memory 198772 kb
Host smart-d8372cda-229e-4fdc-b2ba-c58601656672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679264409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1679264409
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.67370275
Short name T198
Test name
Test status
Simulation time 3126770405 ps
CPU time 24.04 seconds
Started Jan 10 01:21:11 PM PST 24
Finished Jan 10 01:21:38 PM PST 24
Peak memory 198876 kb
Host smart-f7524a6d-bd86-4e9c-ae94-67aed4cc2731
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67370275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.67370275
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1284139576
Short name T250
Test name
Test status
Simulation time 2283575296 ps
CPU time 109.06 seconds
Started Jan 10 01:21:30 PM PST 24
Finished Jan 10 01:23:35 PM PST 24
Peak memory 198832 kb
Host smart-98b0ce13-d63a-4df2-805d-5c44cc7dc38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284139576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1284139576
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3693034790
Short name T88
Test name
Test status
Simulation time 1176030907 ps
CPU time 58.75 seconds
Started Jan 10 01:21:28 PM PST 24
Finished Jan 10 01:22:36 PM PST 24
Peak memory 198644 kb
Host smart-d4bc03f6-ea8f-4c3a-803b-0a0e2178ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693034790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3693034790
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3130679756
Short name T49
Test name
Test status
Simulation time 32613154 ps
CPU time 0.78 seconds
Started Jan 10 01:21:29 PM PST 24
Finished Jan 10 01:21:43 PM PST 24
Peak memory 215644 kb
Host smart-d76fd9ad-ae49-4f1a-97f7-39f79b4babf3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130679756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3130679756
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3529367724
Short name T438
Test name
Test status
Simulation time 6685424522 ps
CPU time 4.17 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:21:58 PM PST 24
Peak memory 198708 kb
Host smart-5f15f689-3812-42d7-a5cd-5e61ec46a549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529367724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3529367724
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1387469985
Short name T541
Test name
Test status
Simulation time 74816977 ps
CPU time 1.16 seconds
Started Jan 10 01:21:06 PM PST 24
Finished Jan 10 01:21:12 PM PST 24
Peak memory 197176 kb
Host smart-fef01c5c-84f6-4ba5-8c6f-46977177f8de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387469985 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1387469985
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2332635469
Short name T187
Test name
Test status
Simulation time 7893310544 ps
CPU time 382.37 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:28:16 PM PST 24
Peak memory 198828 kb
Host smart-a0e1239e-fcea-48ad-bb7d-2c7c927f468f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332635469 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.2332635469
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1247078649
Short name T536
Test name
Test status
Simulation time 3504206511 ps
CPU time 24.22 seconds
Started Jan 10 01:21:35 PM PST 24
Finished Jan 10 01:22:18 PM PST 24
Peak memory 198836 kb
Host smart-b0ae4d71-22b6-4338-acc4-b83acfa467dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247078649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1247078649
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.625724761
Short name T739
Test name
Test status
Simulation time 13435191 ps
CPU time 0.57 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:21:58 PM PST 24
Peak memory 193324 kb
Host smart-fece8921-e350-4495-95a9-9327abac1f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625724761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.625724761
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1341744128
Short name T407
Test name
Test status
Simulation time 113392021 ps
CPU time 2.36 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:21:59 PM PST 24
Peak memory 198684 kb
Host smart-0f0086c0-6992-49a8-9a04-968e37f1b922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341744128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1341744128
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2586895289
Short name T426
Test name
Test status
Simulation time 2288754939 ps
CPU time 19.08 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:22:18 PM PST 24
Peak memory 198784 kb
Host smart-052a3a93-ca26-4549-bd2b-8d68205fbd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586895289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2586895289
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3067232558
Short name T526
Test name
Test status
Simulation time 4043281975 ps
CPU time 104.45 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:23:38 PM PST 24
Peak memory 198832 kb
Host smart-cc2d8315-d45f-4fe2-af5f-764d9daf8756
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067232558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3067232558
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3350642244
Short name T715
Test name
Test status
Simulation time 1656864895 ps
CPU time 80.1 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:23:17 PM PST 24
Peak memory 198780 kb
Host smart-f57a2323-ce91-490b-b657-b4e8725640c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350642244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3350642244
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.4159428774
Short name T728
Test name
Test status
Simulation time 13261890670 ps
CPU time 46.06 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:22:45 PM PST 24
Peak memory 198924 kb
Host smart-ce7219a7-5b36-46f0-8632-a1b904e67834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159428774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.4159428774
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1794718451
Short name T197
Test name
Test status
Simulation time 67991610 ps
CPU time 0.93 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:22:00 PM PST 24
Peak memory 196528 kb
Host smart-7cbf2d5a-9403-4d09-beae-bd6fa7f47f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794718451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1794718451
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2769554054
Short name T497
Test name
Test status
Simulation time 241127722668 ps
CPU time 602.99 seconds
Started Jan 10 01:21:34 PM PST 24
Finished Jan 10 01:31:57 PM PST 24
Peak memory 198884 kb
Host smart-db591772-f1be-4bf2-8332-b29233e43fc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769554054 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2769554054
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.232313702
Short name T699
Test name
Test status
Simulation time 44673371496 ps
CPU time 387.54 seconds
Started Jan 10 01:21:34 PM PST 24
Finished Jan 10 01:28:21 PM PST 24
Peak memory 207120 kb
Host smart-c0a18f11-b599-49b4-9731-c572df9f5adc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232313702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.232313702
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.860464067
Short name T793
Test name
Test status
Simulation time 33461390 ps
CPU time 1.05 seconds
Started Jan 10 01:21:32 PM PST 24
Finished Jan 10 01:21:52 PM PST 24
Peak memory 197328 kb
Host smart-a575ee00-9fb5-49e3-aada-6de801996a45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860464067 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_hmac_vectors.860464067
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1376554458
Short name T774
Test name
Test status
Simulation time 48397929817 ps
CPU time 441.61 seconds
Started Jan 10 01:21:44 PM PST 24
Finished Jan 10 01:29:28 PM PST 24
Peak memory 198684 kb
Host smart-12f2dbb1-101e-43b1-a9a9-6a41c0916a38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376554458 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.1376554458
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2626660176
Short name T12
Test name
Test status
Simulation time 105758035 ps
CPU time 3.29 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:22:03 PM PST 24
Peak memory 198788 kb
Host smart-a4288a48-d20e-4409-a2e8-c7dd8ccc422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626660176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2626660176
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.1529353846
Short name T444
Test name
Test status
Simulation time 235728910595 ps
CPU time 2578.29 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 02:06:14 PM PST 24
Peak memory 256352 kb
Host smart-1ed6a2cf-9e6b-4885-a1f8-69b8277c0aec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529353846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.1529353846
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.3931245438
Short name T661
Test name
Test status
Simulation time 280510055688 ps
CPU time 1236.02 seconds
Started Jan 10 01:23:06 PM PST 24
Finished Jan 10 01:43:59 PM PST 24
Peak memory 224568 kb
Host smart-74db30b3-4d8f-44e6-9374-e3938572f11a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931245438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.3931245438
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.3515434722
Short name T522
Test name
Test status
Simulation time 318285523483 ps
CPU time 3051.69 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 02:14:20 PM PST 24
Peak memory 256828 kb
Host smart-d3ea2932-5a65-4610-a0f3-b5887c69f88c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515434722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.3515434722
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.1762510753
Short name T409
Test name
Test status
Simulation time 66537120622 ps
CPU time 628.38 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:33:56 PM PST 24
Peak memory 245000 kb
Host smart-8f1a0812-c8af-4201-a0e7-e56dd40d73d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762510753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.1762510753
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.3788445710
Short name T450
Test name
Test status
Simulation time 355546198956 ps
CPU time 790.73 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:36:28 PM PST 24
Peak memory 214864 kb
Host smart-cdbf6665-f5a4-4a79-b75b-12b476f3a77b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788445710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.3788445710
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.3836133056
Short name T126
Test name
Test status
Simulation time 995166642215 ps
CPU time 708.2 seconds
Started Jan 10 01:23:06 PM PST 24
Finished Jan 10 01:35:12 PM PST 24
Peak memory 239740 kb
Host smart-6fef8da7-136f-48b0-bea9-70c225944180
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836133056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.3836133056
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.4267863071
Short name T75
Test name
Test status
Simulation time 149116391235 ps
CPU time 1603.03 seconds
Started Jan 10 01:23:10 PM PST 24
Finished Jan 10 01:50:12 PM PST 24
Peak memory 236148 kb
Host smart-5e6cd43d-4baa-4cb5-b661-4666fd913079
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267863071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.4267863071
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.1320282987
Short name T140
Test name
Test status
Simulation time 509968258272 ps
CPU time 3686.61 seconds
Started Jan 10 01:23:11 PM PST 24
Finished Jan 10 02:24:56 PM PST 24
Peak memory 257820 kb
Host smart-9e6705db-abcb-443a-91bd-fbc255fbbf1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320282987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.1320282987
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2858268993
Short name T319
Test name
Test status
Simulation time 30121570 ps
CPU time 0.59 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:22:00 PM PST 24
Peak memory 193156 kb
Host smart-81328b96-1261-448e-bdad-538130726a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858268993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2858268993
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3986020580
Short name T259
Test name
Test status
Simulation time 935271846 ps
CPU time 17.62 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:22:15 PM PST 24
Peak memory 219208 kb
Host smart-3ba7ef6e-6259-4f35-9ed9-a47684ea17d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986020580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3986020580
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1038564436
Short name T359
Test name
Test status
Simulation time 6724396728 ps
CPU time 28.8 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:30 PM PST 24
Peak memory 198880 kb
Host smart-bfed30e7-bbbf-4c5f-ac43-87dc6c495656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038564436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1038564436
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1528130320
Short name T327
Test name
Test status
Simulation time 12371296814 ps
CPU time 135.62 seconds
Started Jan 10 01:21:44 PM PST 24
Finished Jan 10 01:24:23 PM PST 24
Peak memory 198760 kb
Host smart-bd263d3f-5634-4f27-ae0d-344a7c5e6aa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528130320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1528130320
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1747554937
Short name T542
Test name
Test status
Simulation time 1285545626 ps
CPU time 16.55 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:22:13 PM PST 24
Peak memory 198796 kb
Host smart-d05e75af-28d4-429d-9aad-19767a7f96c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747554937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1747554937
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2631314041
Short name T163
Test name
Test status
Simulation time 161315724 ps
CPU time 2.1 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:04 PM PST 24
Peak memory 198744 kb
Host smart-527a2e9c-4ca9-4569-955c-51a2d7da6476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631314041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2631314041
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2957271242
Short name T752
Test name
Test status
Simulation time 371947648 ps
CPU time 4.12 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:21:59 PM PST 24
Peak memory 198776 kb
Host smart-dbbe73c8-5399-409c-9eb4-a83880c9a39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957271242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2957271242
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3682374745
Short name T551
Test name
Test status
Simulation time 37773065452 ps
CPU time 850.36 seconds
Started Jan 10 01:21:43 PM PST 24
Finished Jan 10 01:36:16 PM PST 24
Peak memory 222248 kb
Host smart-bcba381e-b23e-449f-9aac-ba58b79c9a96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682374745 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3682374745
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.827030296
Short name T682
Test name
Test status
Simulation time 37418582367 ps
CPU time 276.2 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:26:36 PM PST 24
Peak memory 215340 kb
Host smart-574002f0-1ce8-45df-a957-bc5723af9ce0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=827030296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.827030296
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1180606701
Short name T483
Test name
Test status
Simulation time 39496061 ps
CPU time 0.89 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:05 PM PST 24
Peak memory 196796 kb
Host smart-f14d6792-01f6-44e8-accd-f5d5ca880b04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180606701 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1180606701
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2801905315
Short name T180
Test name
Test status
Simulation time 5108582374 ps
CPU time 21.94 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:22:19 PM PST 24
Peak memory 198896 kb
Host smart-478f26af-229c-4f4b-906e-928e83693edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801905315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2801905315
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.961485265
Short name T773
Test name
Test status
Simulation time 73066197063 ps
CPU time 701.33 seconds
Started Jan 10 01:23:20 PM PST 24
Finished Jan 10 01:35:14 PM PST 24
Peak memory 215324 kb
Host smart-ddc6bf27-8fe9-416e-969c-aab4fb828ddb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961485265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.961485265
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.1303284903
Short name T362
Test name
Test status
Simulation time 99654380559 ps
CPU time 1895.96 seconds
Started Jan 10 01:23:07 PM PST 24
Finished Jan 10 01:55:01 PM PST 24
Peak memory 250144 kb
Host smart-a373ad55-2fd2-4334-9c5a-38aee3d166ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1303284903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.1303284903
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.2269188342
Short name T78
Test name
Test status
Simulation time 539769950779 ps
CPU time 2540.4 seconds
Started Jan 10 01:23:12 PM PST 24
Finished Jan 10 02:05:50 PM PST 24
Peak memory 248072 kb
Host smart-c54f6231-9590-4446-8488-0a25b6e7692f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2269188342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.2269188342
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.2325827584
Short name T620
Test name
Test status
Simulation time 240388833173 ps
CPU time 765.99 seconds
Started Jan 10 01:23:13 PM PST 24
Finished Jan 10 01:36:16 PM PST 24
Peak memory 256296 kb
Host smart-9eb0e2de-10ca-40a0-9024-4e2d6f8661d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325827584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.2325827584
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.544479386
Short name T86
Test name
Test status
Simulation time 72209547209 ps
CPU time 2581.63 seconds
Started Jan 10 01:23:06 PM PST 24
Finished Jan 10 02:06:26 PM PST 24
Peak memory 254368 kb
Host smart-b9c0d614-5f56-4484-8926-c9310dc5ef53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544479386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.544479386
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.3203363984
Short name T665
Test name
Test status
Simulation time 60902575694 ps
CPU time 2726.12 seconds
Started Jan 10 01:23:30 PM PST 24
Finished Jan 10 02:09:02 PM PST 24
Peak memory 248072 kb
Host smart-31828b2b-749d-45c5-8584-fb3094b88280
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203363984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.3203363984
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.2584640762
Short name T111
Test name
Test status
Simulation time 183202463872 ps
CPU time 666.85 seconds
Started Jan 10 01:23:33 PM PST 24
Finished Jan 10 01:34:44 PM PST 24
Peak memory 241860 kb
Host smart-721d4533-83eb-4374-9491-e74493246ac4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584640762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.2584640762
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.4258559068
Short name T784
Test name
Test status
Simulation time 251442844701 ps
CPU time 1191.17 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:43:19 PM PST 24
Peak memory 256164 kb
Host smart-9cea080e-68b7-4dd5-af66-39d65cbadb24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4258559068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.4258559068
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.979116837
Short name T395
Test name
Test status
Simulation time 13764331 ps
CPU time 0.58 seconds
Started Jan 10 01:21:45 PM PST 24
Finished Jan 10 01:22:08 PM PST 24
Peak memory 194144 kb
Host smart-0e3a31f4-992a-4ff9-a2a0-cad1348b61e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979116837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.979116837
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1223977700
Short name T304
Test name
Test status
Simulation time 730460743 ps
CPU time 30.03 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:35 PM PST 24
Peak memory 229172 kb
Host smart-e0affcc0-7104-456d-a527-d569d0ab6d94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223977700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1223977700
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.4147148503
Short name T523
Test name
Test status
Simulation time 2662342932 ps
CPU time 58.26 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:23:08 PM PST 24
Peak memory 198816 kb
Host smart-0e29546b-3b83-438a-aa39-c53c090c52d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147148503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.4147148503
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1205080622
Short name T631
Test name
Test status
Simulation time 1456019581 ps
CPU time 36.5 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:22:37 PM PST 24
Peak memory 198820 kb
Host smart-4d776996-40fa-4722-8638-8e806d64f65d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1205080622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1205080622
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3065927289
Short name T572
Test name
Test status
Simulation time 4376367759 ps
CPU time 104.2 seconds
Started Jan 10 01:21:45 PM PST 24
Finished Jan 10 01:23:53 PM PST 24
Peak memory 198836 kb
Host smart-27de51f1-3ca4-4092-9589-d51cec669b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065927289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3065927289
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.365588560
Short name T519
Test name
Test status
Simulation time 384580023 ps
CPU time 6.76 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:22:05 PM PST 24
Peak memory 198808 kb
Host smart-41b913ce-defd-48b6-b2f1-fd9a1a933aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365588560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.365588560
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2897740825
Short name T585
Test name
Test status
Simulation time 256141284 ps
CPU time 3.03 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:22:14 PM PST 24
Peak memory 198700 kb
Host smart-f5e76922-0f27-4ec5-a150-92f34d1493e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897740825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2897740825
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1536085728
Short name T533
Test name
Test status
Simulation time 7926079157 ps
CPU time 33.62 seconds
Started Jan 10 01:21:44 PM PST 24
Finished Jan 10 01:22:41 PM PST 24
Peak memory 198856 kb
Host smart-03dc708d-c1b8-413e-a2b9-6a8be352e4da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536085728 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1536085728
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.1982472286
Short name T714
Test name
Test status
Simulation time 22664900650 ps
CPU time 746.85 seconds
Started Jan 10 01:21:43 PM PST 24
Finished Jan 10 01:34:33 PM PST 24
Peak memory 223536 kb
Host smart-41dc2809-16c2-4b9b-a319-b7199e4e16c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982472286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.1982472286
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1687651100
Short name T361
Test name
Test status
Simulation time 32401848 ps
CPU time 1.08 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:22:13 PM PST 24
Peak memory 197108 kb
Host smart-a1b474bf-cab7-41b8-83c1-f80bdeca9f0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687651100 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1687651100
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3483627421
Short name T192
Test name
Test status
Simulation time 15796060631 ps
CPU time 366.11 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:28:01 PM PST 24
Peak memory 198832 kb
Host smart-f6072cc2-4408-4b90-ad9e-885c5eff8ab4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483627421 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.3483627421
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2230401375
Short name T453
Test name
Test status
Simulation time 12364349488 ps
CPU time 48.59 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:22:58 PM PST 24
Peak memory 198804 kb
Host smart-47036f55-325d-49ea-be34-f6cc4b4bd9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230401375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2230401375
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.2779483561
Short name T616
Test name
Test status
Simulation time 45592342394 ps
CPU time 806.26 seconds
Started Jan 10 01:23:07 PM PST 24
Finished Jan 10 01:36:52 PM PST 24
Peak memory 215132 kb
Host smart-7150860e-25a4-482a-abe3-200bb5ca7595
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779483561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.2779483561
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.2338841073
Short name T195
Test name
Test status
Simulation time 63395885467 ps
CPU time 954.56 seconds
Started Jan 10 01:23:11 PM PST 24
Finished Jan 10 01:39:24 PM PST 24
Peak memory 248080 kb
Host smart-3123636a-9906-4430-87d0-4e47c466a8db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338841073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.2338841073
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.106722269
Short name T199
Test name
Test status
Simulation time 68641779802 ps
CPU time 645.54 seconds
Started Jan 10 01:23:35 PM PST 24
Finished Jan 10 01:34:24 PM PST 24
Peak memory 239896 kb
Host smart-b91af79f-04c8-4da3-9a35-5dd0c641e767
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106722269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.106722269
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.283881262
Short name T202
Test name
Test status
Simulation time 377750949655 ps
CPU time 1868.05 seconds
Started Jan 10 01:23:06 PM PST 24
Finished Jan 10 01:54:32 PM PST 24
Peak memory 248068 kb
Host smart-bdfea00f-3248-49f5-adde-aeb6536a7a5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283881262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.283881262
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.1997047351
Short name T115
Test name
Test status
Simulation time 56924863604 ps
CPU time 368.34 seconds
Started Jan 10 01:23:18 PM PST 24
Finished Jan 10 01:29:40 PM PST 24
Peak memory 214524 kb
Host smart-42e0cedc-a380-46ed-994d-d3e7bba16514
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1997047351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.1997047351
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.284386943
Short name T236
Test name
Test status
Simulation time 38495730832 ps
CPU time 970.85 seconds
Started Jan 10 01:23:32 PM PST 24
Finished Jan 10 01:39:47 PM PST 24
Peak memory 215284 kb
Host smart-55588c83-08de-442e-a053-b1078b2c9cc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284386943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.284386943
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.2311560014
Short name T486
Test name
Test status
Simulation time 58011220614 ps
CPU time 1126.68 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:42:14 PM PST 24
Peak memory 229776 kb
Host smart-cfb6adb0-6793-4d5f-be84-069998e7bce3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311560014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.2311560014
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.1774888084
Short name T96
Test name
Test status
Simulation time 140064917704 ps
CPU time 995.02 seconds
Started Jan 10 01:23:12 PM PST 24
Finished Jan 10 01:40:04 PM PST 24
Peak memory 239888 kb
Host smart-778335c1-5330-4244-b8b2-bce47aac83f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774888084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.1774888084
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.1126644666
Short name T447
Test name
Test status
Simulation time 27413903794 ps
CPU time 501.52 seconds
Started Jan 10 01:23:21 PM PST 24
Finished Jan 10 01:31:54 PM PST 24
Peak memory 215024 kb
Host smart-fd5f9e53-8341-47b8-bd99-48d81ba97917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126644666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.1126644666
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1404926075
Short name T277
Test name
Test status
Simulation time 95814313 ps
CPU time 0.59 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:15 PM PST 24
Peak memory 193100 kb
Host smart-f6f4c1a5-ff5e-4c61-9fe9-26d65aeb636c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404926075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1404926075
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1961364019
Short name T247
Test name
Test status
Simulation time 5789423735 ps
CPU time 48.15 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:53 PM PST 24
Peak memory 236856 kb
Host smart-59697d3b-9229-4e89-a366-6ae074d8dd0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961364019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1961364019
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3934375205
Short name T227
Test name
Test status
Simulation time 11949988258 ps
CPU time 38.98 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:22:49 PM PST 24
Peak memory 198896 kb
Host smart-91c6d181-016c-45c2-9615-cccd0f6666a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934375205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3934375205
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3743345301
Short name T543
Test name
Test status
Simulation time 11813978897 ps
CPU time 90.35 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:23:20 PM PST 24
Peak memory 198804 kb
Host smart-7785fe44-c2ce-4dfb-9fdf-36d405b76719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743345301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3743345301
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1063515863
Short name T193
Test name
Test status
Simulation time 27521931773 ps
CPU time 79.06 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:23:21 PM PST 24
Peak memory 198852 kb
Host smart-4097143a-ac6b-49a3-8eb0-28fd1fda48f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063515863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1063515863
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2684933427
Short name T494
Test name
Test status
Simulation time 42151950773 ps
CPU time 37.24 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:51 PM PST 24
Peak memory 198868 kb
Host smart-15446044-3d24-4529-9069-ee86a49335c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684933427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2684933427
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1797958903
Short name T93
Test name
Test status
Simulation time 941788829 ps
CPU time 3.16 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:22:14 PM PST 24
Peak memory 198736 kb
Host smart-7d5785f7-3343-45d8-b83c-ee2613e0db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797958903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1797958903
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1573654440
Short name T462
Test name
Test status
Simulation time 118821048647 ps
CPU time 469.46 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:29:47 PM PST 24
Peak memory 198824 kb
Host smart-947a12b5-67ba-4049-aa85-75d6945e6eab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573654440 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1573654440
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.4081205332
Short name T692
Test name
Test status
Simulation time 86426987994 ps
CPU time 906.89 seconds
Started Jan 10 01:21:45 PM PST 24
Finished Jan 10 01:37:16 PM PST 24
Peak memory 223508 kb
Host smart-54c4a6de-70d0-493e-9933-8e6d5adc16a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081205332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.4081205332
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1468773028
Short name T337
Test name
Test status
Simulation time 26767934 ps
CPU time 0.87 seconds
Started Jan 10 01:21:47 PM PST 24
Finished Jan 10 01:22:13 PM PST 24
Peak memory 195784 kb
Host smart-ad26a020-d895-4372-9d16-3d17c227bdd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468773028 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.1468773028
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1999047099
Short name T335
Test name
Test status
Simulation time 39946541689 ps
CPU time 407.53 seconds
Started Jan 10 01:21:48 PM PST 24
Finished Jan 10 01:29:01 PM PST 24
Peak memory 198804 kb
Host smart-12d62ecf-fe1e-4d04-b58a-53a51757681c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999047099 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.1999047099
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2365546210
Short name T175
Test name
Test status
Simulation time 5272396493 ps
CPU time 31.91 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:46 PM PST 24
Peak memory 197772 kb
Host smart-8014c47f-20e0-40d5-bd5f-2cdd4f3af98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365546210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2365546210
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.1521558047
Short name T288
Test name
Test status
Simulation time 79318238310 ps
CPU time 4050.83 seconds
Started Jan 10 01:23:18 PM PST 24
Finished Jan 10 02:31:03 PM PST 24
Peak memory 231752 kb
Host smart-1f866363-bec7-4584-b525-1bfcceca3829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521558047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.1521558047
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.92925692
Short name T98
Test name
Test status
Simulation time 289633735613 ps
CPU time 3784.29 seconds
Started Jan 10 01:23:19 PM PST 24
Finished Jan 10 02:26:37 PM PST 24
Peak memory 259264 kb
Host smart-e162ab57-60f6-47a4-963f-4c88b3bda370
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92925692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.92925692
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.2460666038
Short name T429
Test name
Test status
Simulation time 26576375250 ps
CPU time 1181.23 seconds
Started Jan 10 01:23:23 PM PST 24
Finished Jan 10 01:43:14 PM PST 24
Peak memory 215300 kb
Host smart-eef2cafc-0db1-4ff0-93f7-154b92904c93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460666038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.2460666038
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.2962133099
Short name T207
Test name
Test status
Simulation time 273549298166 ps
CPU time 964 seconds
Started Jan 10 01:23:34 PM PST 24
Finished Jan 10 01:39:42 PM PST 24
Peak memory 240936 kb
Host smart-70d3a460-52db-41e2-bf6b-e73059ddc7cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2962133099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.2962133099
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.3174879035
Short name T479
Test name
Test status
Simulation time 139454750089 ps
CPU time 2105.98 seconds
Started Jan 10 01:23:11 PM PST 24
Finished Jan 10 01:58:36 PM PST 24
Peak memory 231672 kb
Host smart-b2179270-5702-4b54-ae62-ec0898cccab7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3174879035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.3174879035
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.4139522084
Short name T394
Test name
Test status
Simulation time 68342512150 ps
CPU time 3519.56 seconds
Started Jan 10 01:23:10 PM PST 24
Finished Jan 10 02:22:09 PM PST 24
Peak memory 238820 kb
Host smart-8edd3f47-d24f-48bf-b2a9-925fbc4869e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139522084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.4139522084
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.2496399460
Short name T90
Test name
Test status
Simulation time 306853046943 ps
CPU time 1628.54 seconds
Started Jan 10 01:23:12 PM PST 24
Finished Jan 10 01:50:38 PM PST 24
Peak memory 244220 kb
Host smart-b3f7607f-9963-418f-ac06-5a455e25cdd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496399460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.2496399460
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.2783342075
Short name T309
Test name
Test status
Simulation time 85142113394 ps
CPU time 1135.4 seconds
Started Jan 10 01:23:14 PM PST 24
Finished Jan 10 01:42:26 PM PST 24
Peak memory 223588 kb
Host smart-4b83d30d-5549-4873-92a7-5bba438b0ad8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2783342075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.2783342075
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.3911714765
Short name T461
Test name
Test status
Simulation time 81178099796 ps
CPU time 714.12 seconds
Started Jan 10 01:23:07 PM PST 24
Finished Jan 10 01:35:18 PM PST 24
Peak memory 210072 kb
Host smart-feab0f17-82cb-461d-a1b3-39b338b68fc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3911714765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.3911714765
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.484316175
Short name T667
Test name
Test status
Simulation time 12561660547 ps
CPU time 23.82 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:38 PM PST 24
Peak memory 207004 kb
Host smart-e646126d-b595-4a34-890e-eac1b6054712
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484316175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.484316175
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3643327717
Short name T634
Test name
Test status
Simulation time 2515114910 ps
CPU time 10.75 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:25 PM PST 24
Peak memory 198784 kb
Host smart-ac80d4df-cb28-45df-9175-3e11f467f3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643327717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3643327717
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3278338383
Short name T343
Test name
Test status
Simulation time 2518902300 ps
CPU time 61.96 seconds
Started Jan 10 01:21:52 PM PST 24
Finished Jan 10 01:23:23 PM PST 24
Peak memory 198828 kb
Host smart-f8408779-99c7-4c94-bb9a-2feed71a96ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3278338383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3278338383
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.470727707
Short name T382
Test name
Test status
Simulation time 3642234023 ps
CPU time 70.61 seconds
Started Jan 10 01:21:50 PM PST 24
Finished Jan 10 01:23:29 PM PST 24
Peak memory 198832 kb
Host smart-c22bf929-75d9-4fa4-a981-b472d7ef503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470727707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.470727707
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3507161938
Short name T420
Test name
Test status
Simulation time 1024164916 ps
CPU time 25.09 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:29 PM PST 24
Peak memory 198760 kb
Host smart-512d8f4e-15da-4e6c-a67d-6273de23b675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507161938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3507161938
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.4186275178
Short name T268
Test name
Test status
Simulation time 176994203 ps
CPU time 4.2 seconds
Started Jan 10 01:21:50 PM PST 24
Finished Jan 10 01:22:23 PM PST 24
Peak memory 198664 kb
Host smart-41fcd43d-d2c1-4dfd-88f1-dce92a4aa9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186275178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4186275178
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.4009153794
Short name T464
Test name
Test status
Simulation time 667352379120 ps
CPU time 1405.34 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:45:25 PM PST 24
Peak memory 198716 kb
Host smart-c8773a7a-b374-48c8-bc55-ae51c9bf6b7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009153794 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.4009153794
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.858923281
Short name T112
Test name
Test status
Simulation time 68722858750 ps
CPU time 1259.74 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:43:02 PM PST 24
Peak memory 247612 kb
Host smart-ab36af08-51b7-417d-9861-79a2220a8b5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=858923281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.858923281
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2990556948
Short name T540
Test name
Test status
Simulation time 91494499 ps
CPU time 0.95 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:22:28 PM PST 24
Peak memory 196008 kb
Host smart-fa32177e-5cc6-40e6-ad63-05f97070c496
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990556948 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2990556948
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2339011190
Short name T275
Test name
Test status
Simulation time 8873083714 ps
CPU time 419.39 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:29:14 PM PST 24
Peak memory 198740 kb
Host smart-f99adb64-a59b-4156-88aa-4e1ed68fbd62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339011190 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.2339011190
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1393208294
Short name T675
Test name
Test status
Simulation time 3664956217 ps
CPU time 13.19 seconds
Started Jan 10 01:21:59 PM PST 24
Finished Jan 10 01:22:40 PM PST 24
Peak memory 198628 kb
Host smart-44600654-8bae-45bd-9bd9-423da9c708cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393208294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1393208294
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.826323753
Short name T114
Test name
Test status
Simulation time 41285495444 ps
CPU time 1735.41 seconds
Started Jan 10 01:23:24 PM PST 24
Finished Jan 10 01:52:29 PM PST 24
Peak memory 248124 kb
Host smart-f1833ae5-bae6-4007-9ece-58ae5d4ede08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826323753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.826323753
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.1621762573
Short name T404
Test name
Test status
Simulation time 150973995733 ps
CPU time 3833.2 seconds
Started Jan 10 01:23:07 PM PST 24
Finished Jan 10 02:27:18 PM PST 24
Peak memory 248052 kb
Host smart-3f62e34d-2084-4d40-a26f-2d1442fb0916
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621762573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.1621762573
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.1135701756
Short name T401
Test name
Test status
Simulation time 37479655463 ps
CPU time 488.12 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:31:36 PM PST 24
Peak memory 237720 kb
Host smart-07024db5-09a7-41d1-a26a-304a730bafd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135701756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.1135701756
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.405562368
Short name T738
Test name
Test status
Simulation time 464075390505 ps
CPU time 2396.39 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 02:03:24 PM PST 24
Peak memory 248100 kb
Host smart-f3a2326b-556e-485b-8f13-934916dd3554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405562368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.405562368
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.2588897592
Short name T399
Test name
Test status
Simulation time 200085825098 ps
CPU time 2950.96 seconds
Started Jan 10 01:23:11 PM PST 24
Finished Jan 10 02:12:40 PM PST 24
Peak memory 258016 kb
Host smart-6b17a9be-e0e1-4530-bf3b-d0f3bbcb5afd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588897592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.2588897592
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.514976442
Short name T768
Test name
Test status
Simulation time 176578517637 ps
CPU time 3805.02 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 02:26:51 PM PST 24
Peak memory 244484 kb
Host smart-a612ba89-45c3-4256-9414-e789506552ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514976442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.514976442
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.470894851
Short name T563
Test name
Test status
Simulation time 7423206313 ps
CPU time 377.27 seconds
Started Jan 10 01:23:11 PM PST 24
Finished Jan 10 01:29:46 PM PST 24
Peak memory 214816 kb
Host smart-879a2867-ac58-422d-b700-fc5551820284
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470894851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.470894851
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.561853413
Short name T347
Test name
Test status
Simulation time 113707728215 ps
CPU time 1565.79 seconds
Started Jan 10 01:23:22 PM PST 24
Finished Jan 10 01:49:39 PM PST 24
Peak memory 247592 kb
Host smart-505a6866-06a0-406a-8dcf-9db76c1f675d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561853413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.561853413
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.3488400008
Short name T296
Test name
Test status
Simulation time 88260461611 ps
CPU time 1112.67 seconds
Started Jan 10 01:23:19 PM PST 24
Finished Jan 10 01:42:04 PM PST 24
Peak memory 228340 kb
Host smart-0faba5fe-d750-4d66-b77e-2f9c74c72519
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488400008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.3488400008
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.3996216089
Short name T276
Test name
Test status
Simulation time 47202802521 ps
CPU time 238.74 seconds
Started Jan 10 01:23:32 PM PST 24
Finished Jan 10 01:27:35 PM PST 24
Peak memory 223488 kb
Host smart-794748d6-553f-494c-a168-11405ea4bdfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3996216089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.3996216089
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1367571609
Short name T253
Test name
Test status
Simulation time 39449032 ps
CPU time 0.56 seconds
Started Jan 10 01:21:47 PM PST 24
Finished Jan 10 01:22:13 PM PST 24
Peak memory 193124 kb
Host smart-d203a739-82ac-49ae-9457-8f23e00ab29a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367571609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1367571609
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2695987646
Short name T666
Test name
Test status
Simulation time 110168838 ps
CPU time 5.35 seconds
Started Jan 10 01:22:07 PM PST 24
Finished Jan 10 01:22:38 PM PST 24
Peak memory 216228 kb
Host smart-ab59273d-77c2-4e0c-bffe-86c35d1e2ca0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695987646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2695987646
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.642305519
Short name T509
Test name
Test status
Simulation time 7258742239 ps
CPU time 31.45 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:22:26 PM PST 24
Peak memory 198824 kb
Host smart-73b2f6af-66ca-469a-9870-40084f213856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642305519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.642305519
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2970428536
Short name T379
Test name
Test status
Simulation time 1636196219 ps
CPU time 40.75 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:22:35 PM PST 24
Peak memory 198648 kb
Host smart-1f88e053-d931-484d-b457-2ff0121fef57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970428536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2970428536
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1084702113
Short name T506
Test name
Test status
Simulation time 49349596813 ps
CPU time 79.63 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:23:18 PM PST 24
Peak memory 198796 kb
Host smart-09f398af-0461-4daa-ad3a-74a6e842e738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084702113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1084702113
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2146385728
Short name T113
Test name
Test status
Simulation time 42531135960 ps
CPU time 65.36 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:23:00 PM PST 24
Peak memory 198796 kb
Host smart-480e78ee-f3db-4c40-93e7-5e13891d6882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146385728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2146385728
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2047839941
Short name T764
Test name
Test status
Simulation time 103087806 ps
CPU time 0.98 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:21:58 PM PST 24
Peak memory 197228 kb
Host smart-e3d2402d-252c-4d29-9c7e-66b81c1a36fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047839941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2047839941
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.287425134
Short name T560
Test name
Test status
Simulation time 243867477954 ps
CPU time 1029.74 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:39:13 PM PST 24
Peak memory 210904 kb
Host smart-99249ef8-9670-4517-8c42-076872499c7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287425134 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.287425134
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.2695196669
Short name T203
Test name
Test status
Simulation time 22937860818 ps
CPU time 151.24 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:24:36 PM PST 24
Peak memory 215344 kb
Host smart-ee598bbb-f842-4129-ac10-09ed3f26b17b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695196669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.2695196669
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.640209971
Short name T332
Test name
Test status
Simulation time 199632405 ps
CPU time 1.11 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:21:55 PM PST 24
Peak memory 197228 kb
Host smart-62f546dd-d478-4204-8317-1f1ee4e78cd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640209971 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.640209971
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1860680989
Short name T341
Test name
Test status
Simulation time 26891881954 ps
CPU time 418.29 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:28:54 PM PST 24
Peak memory 198828 kb
Host smart-f76ca0dd-5ced-4ed3-8539-7cd47509829d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860680989 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_sha_vectors.1860680989
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1903789606
Short name T604
Test name
Test status
Simulation time 479006475 ps
CPU time 5.86 seconds
Started Jan 10 01:21:35 PM PST 24
Finished Jan 10 01:21:59 PM PST 24
Peak memory 198800 kb
Host smart-b21fe898-4eb8-43a7-a8d2-9832790898d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903789606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1903789606
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.1216661260
Short name T423
Test name
Test status
Simulation time 39192436539 ps
CPU time 331.57 seconds
Started Jan 10 01:23:34 PM PST 24
Finished Jan 10 01:29:09 PM PST 24
Peak memory 236852 kb
Host smart-a2f2bc7d-8c1e-4e78-ad74-cbfc574116de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216661260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.1216661260
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.828854211
Short name T127
Test name
Test status
Simulation time 307065943280 ps
CPU time 3181.8 seconds
Started Jan 10 01:23:18 PM PST 24
Finished Jan 10 02:16:34 PM PST 24
Peak memory 248084 kb
Host smart-44678319-a751-4301-a932-145a8b142ffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828854211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.828854211
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.460057226
Short name T134
Test name
Test status
Simulation time 728233322372 ps
CPU time 2762.82 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 02:09:30 PM PST 24
Peak memory 256312 kb
Host smart-1f647a1e-a57d-4b87-b462-2212c38b2e92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460057226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.460057226
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.1688597380
Short name T702
Test name
Test status
Simulation time 90394042294 ps
CPU time 4109.26 seconds
Started Jan 10 01:23:13 PM PST 24
Finished Jan 10 02:32:00 PM PST 24
Peak memory 259048 kb
Host smart-65e9f48a-13f8-4d2b-ae16-ef5aba7a8d73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688597380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.1688597380
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.1817935686
Short name T408
Test name
Test status
Simulation time 76487051054 ps
CPU time 318.49 seconds
Started Jan 10 01:23:21 PM PST 24
Finished Jan 10 01:28:51 PM PST 24
Peak memory 247976 kb
Host smart-6ad578ef-9d9d-4298-9428-58bb10923a8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817935686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.1817935686
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.1878843144
Short name T718
Test name
Test status
Simulation time 90903680367 ps
CPU time 4228.07 seconds
Started Jan 10 01:23:21 PM PST 24
Finished Jan 10 02:34:01 PM PST 24
Peak memory 250168 kb
Host smart-76db6520-18bb-4759-9a9c-89de6184733f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878843144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.1878843144
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.3274868719
Short name T591
Test name
Test status
Simulation time 299674152720 ps
CPU time 3258.12 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 02:17:45 PM PST 24
Peak memory 256304 kb
Host smart-480aed9f-49a6-4fda-a334-0f83473f7ad0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274868719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.3274868719
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.2737145223
Short name T108
Test name
Test status
Simulation time 452231421553 ps
CPU time 671.15 seconds
Started Jan 10 01:23:36 PM PST 24
Finished Jan 10 01:34:52 PM PST 24
Peak memory 215212 kb
Host smart-85486cc1-29d1-4e10-9be9-c8094643242e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737145223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.2737145223
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.1058974663
Short name T586
Test name
Test status
Simulation time 300211013475 ps
CPU time 4593.91 seconds
Started Jan 10 01:23:23 PM PST 24
Finished Jan 10 02:40:08 PM PST 24
Peak memory 272708 kb
Host smart-5104b4d3-c98d-4e49-9e41-52b5d1dfe40e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1058974663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.1058974663
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.999821866
Short name T673
Test name
Test status
Simulation time 122448887502 ps
CPU time 1198.52 seconds
Started Jan 10 01:23:31 PM PST 24
Finished Jan 10 01:43:35 PM PST 24
Peak memory 231148 kb
Host smart-2748428a-7856-48cb-a4e9-cb68b1ea59d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999821866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.999821866
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.459405671
Short name T294
Test name
Test status
Simulation time 76041377 ps
CPU time 0.63 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:05 PM PST 24
Peak memory 193140 kb
Host smart-eed1f44a-ecbd-4973-98f2-f1952278ac97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459405671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.459405671
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.4006446195
Short name T45
Test name
Test status
Simulation time 2098356184 ps
CPU time 15.45 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:20 PM PST 24
Peak memory 206972 kb
Host smart-28443987-3933-4ce9-b3c5-f007e71d3bd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006446195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4006446195
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2652272420
Short name T639
Test name
Test status
Simulation time 2081458874 ps
CPU time 45.45 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:49 PM PST 24
Peak memory 198580 kb
Host smart-7f7c8d82-f0cc-42e6-9fb6-631ef595b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652272420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2652272420
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2752046020
Short name T577
Test name
Test status
Simulation time 2604615232 ps
CPU time 58.35 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:22:55 PM PST 24
Peak memory 198900 kb
Host smart-5339127a-4803-4f02-8ed1-3460d12ac9d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752046020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2752046020
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1316663531
Short name T782
Test name
Test status
Simulation time 7820576882 ps
CPU time 95.53 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:23:30 PM PST 24
Peak memory 198852 kb
Host smart-61b5e973-1df3-49bd-8c11-dd7c95b4cf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316663531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1316663531
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3153058629
Short name T184
Test name
Test status
Simulation time 12462675173 ps
CPU time 52.96 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:55 PM PST 24
Peak memory 198844 kb
Host smart-38b1a2ec-29aa-4167-b21b-f6865eb6ac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153058629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3153058629
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2812357175
Short name T372
Test name
Test status
Simulation time 1293400592 ps
CPU time 3.51 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:05 PM PST 24
Peak memory 198788 kb
Host smart-e94edebd-c385-447b-a782-75b2d45fc976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812357175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2812357175
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1673547935
Short name T729
Test name
Test status
Simulation time 282130039747 ps
CPU time 1088.63 seconds
Started Jan 10 01:21:43 PM PST 24
Finished Jan 10 01:40:14 PM PST 24
Peak memory 198856 kb
Host smart-a48f3114-d4a2-4860-9d03-549be293cd87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673547935 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1673547935
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.3770080497
Short name T686
Test name
Test status
Simulation time 181363562811 ps
CPU time 5266.53 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 02:49:50 PM PST 24
Peak memory 257308 kb
Host smart-48a68667-e025-4e83-935b-acb56a80bb21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770080497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.3770080497
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3207404271
Short name T795
Test name
Test status
Simulation time 142618108 ps
CPU time 0.85 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:03 PM PST 24
Peak memory 195640 kb
Host smart-6bd9c0b4-658f-482c-b950-683225ab86ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207404271 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3207404271
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3058073460
Short name T801
Test name
Test status
Simulation time 7163680258 ps
CPU time 343.96 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:27:46 PM PST 24
Peak memory 198856 kb
Host smart-9224eaa2-ed7d-40fe-b587-9f81de17f7e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058073460 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.3058073460
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2360731043
Short name T710
Test name
Test status
Simulation time 3109098484 ps
CPU time 37.33 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:41 PM PST 24
Peak memory 198824 kb
Host smart-c944e1ff-0a4b-4cc2-b77e-227aa92e4cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360731043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2360731043
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.3081776601
Short name T217
Test name
Test status
Simulation time 76098890974 ps
CPU time 706.59 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:35:15 PM PST 24
Peak memory 247420 kb
Host smart-2c5fc15f-758a-4d66-9531-c1d6def73ae9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081776601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.3081776601
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.1881008737
Short name T291
Test name
Test status
Simulation time 85908885926 ps
CPU time 1205.2 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:43:33 PM PST 24
Peak memory 218888 kb
Host smart-da829935-a3fa-4b3d-af21-4e44906387ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881008737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.1881008737
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.47456127
Short name T307
Test name
Test status
Simulation time 30555573938 ps
CPU time 539.94 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:32:27 PM PST 24
Peak memory 244016 kb
Host smart-9e918975-64cb-45f6-87c5-fd8f6e897bfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47456127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.47456127
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.1235299967
Short name T761
Test name
Test status
Simulation time 52468071847 ps
CPU time 2196.59 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 02:00:03 PM PST 24
Peak memory 245560 kb
Host smart-dac1b8c7-b6f0-47b4-a0cd-1f89af480fe3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235299967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.1235299967
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.782459021
Short name T281
Test name
Test status
Simulation time 27082073124 ps
CPU time 514.1 seconds
Started Jan 10 01:23:22 PM PST 24
Finished Jan 10 01:32:07 PM PST 24
Peak memory 248092 kb
Host smart-30a30fd4-d852-41bf-a82c-1289255c9f52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=782459021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.782459021
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.427480661
Short name T69
Test name
Test status
Simulation time 8210851717 ps
CPU time 122.38 seconds
Started Jan 10 01:23:05 PM PST 24
Finished Jan 10 01:25:25 PM PST 24
Peak memory 214768 kb
Host smart-d7fbed8a-c6e6-4fae-aa90-b9af8c6156be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=427480661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.427480661
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.2293253294
Short name T432
Test name
Test status
Simulation time 51581307492 ps
CPU time 1805.6 seconds
Started Jan 10 01:23:30 PM PST 24
Finished Jan 10 01:53:42 PM PST 24
Peak memory 240228 kb
Host smart-df651a01-c6b7-45d8-bd22-84af3ea4790c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293253294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.2293253294
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.1383241730
Short name T79
Test name
Test status
Simulation time 137369400230 ps
CPU time 1517.43 seconds
Started Jan 10 01:23:17 PM PST 24
Finished Jan 10 01:48:49 PM PST 24
Peak memory 243564 kb
Host smart-16cd34b0-f76f-408d-a6ff-d88be89eb0ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383241730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.1383241730
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.887110729
Short name T687
Test name
Test status
Simulation time 93060461127 ps
CPU time 416.77 seconds
Started Jan 10 01:23:22 PM PST 24
Finished Jan 10 01:30:30 PM PST 24
Peak memory 214716 kb
Host smart-bd9d2fe3-ffa3-49b6-b1a6-ded2854c13a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887110729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.887110729
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.4216519565
Short name T602
Test name
Test status
Simulation time 50047738 ps
CPU time 0.57 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 01:22:23 PM PST 24
Peak memory 193884 kb
Host smart-57d8315f-ffd9-44dc-b5ed-d6006e925c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216519565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4216519565
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1846752965
Short name T753
Test name
Test status
Simulation time 744702065 ps
CPU time 22.2 seconds
Started Jan 10 01:21:48 PM PST 24
Finished Jan 10 01:22:35 PM PST 24
Peak memory 215084 kb
Host smart-2db5bf29-653c-4186-85ae-919e367bcb0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846752965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1846752965
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1746627019
Short name T406
Test name
Test status
Simulation time 1135917416 ps
CPU time 20.06 seconds
Started Jan 10 01:21:43 PM PST 24
Finished Jan 10 01:22:26 PM PST 24
Peak memory 198776 kb
Host smart-879d6924-c68b-4229-9f77-b64424cbf10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746627019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1746627019
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1118367194
Short name T425
Test name
Test status
Simulation time 2168744151 ps
CPU time 53.18 seconds
Started Jan 10 01:21:43 PM PST 24
Finished Jan 10 01:22:59 PM PST 24
Peak memory 198816 kb
Host smart-3e6daa07-0483-49cd-b682-97f7d13cfbc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118367194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1118367194
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2203758766
Short name T411
Test name
Test status
Simulation time 1834481102 ps
CPU time 23.58 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:22:34 PM PST 24
Peak memory 198720 kb
Host smart-d647e577-239e-4565-b547-6382479ec54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203758766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2203758766
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.190562422
Short name T696
Test name
Test status
Simulation time 7087289622 ps
CPU time 92.95 seconds
Started Jan 10 01:21:47 PM PST 24
Finished Jan 10 01:23:45 PM PST 24
Peak memory 198784 kb
Host smart-8053983d-ab15-4d27-9caf-c371ccfd825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190562422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.190562422
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1656010249
Short name T396
Test name
Test status
Simulation time 229003068 ps
CPU time 1.12 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:05 PM PST 24
Peak memory 197012 kb
Host smart-6a502000-ca06-431b-9bb8-2c4a8fcd45ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656010249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1656010249
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3045629223
Short name T317
Test name
Test status
Simulation time 30571899486 ps
CPU time 691.31 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 01:33:54 PM PST 24
Peak memory 206900 kb
Host smart-0ffcaef5-7eaf-439d-b093-63a0c9a17072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045629223 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3045629223
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.1788154565
Short name T397
Test name
Test status
Simulation time 36593664688 ps
CPU time 259.69 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:26:38 PM PST 24
Peak memory 231608 kb
Host smart-48d41a6b-c3e2-4ff0-aac2-fafc969851f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788154565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.1788154565
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1288381584
Short name T388
Test name
Test status
Simulation time 186176016 ps
CPU time 0.92 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 01:22:24 PM PST 24
Peak memory 196344 kb
Host smart-6a8363c1-3717-41e9-9d27-68352b340f7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288381584 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1288381584
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2115078556
Short name T366
Test name
Test status
Simulation time 36432251990 ps
CPU time 378.59 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 01:28:41 PM PST 24
Peak memory 198368 kb
Host smart-a631f3df-abcc-499a-a687-9ab56072e3f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115078556 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_sha_vectors.2115078556
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1871199584
Short name T55
Test name
Test status
Simulation time 5511568150 ps
CPU time 26.06 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:41 PM PST 24
Peak memory 197740 kb
Host smart-1593a35f-1383-4456-afbd-700a151e541e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871199584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1871199584
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.3648856462
Short name T302
Test name
Test status
Simulation time 61802236273 ps
CPU time 1109.01 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:41:57 PM PST 24
Peak memory 248120 kb
Host smart-3a94dff8-f4d6-428c-8737-df2bd7fb3052
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648856462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.3648856462
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.2709587461
Short name T788
Test name
Test status
Simulation time 281856369351 ps
CPU time 993.35 seconds
Started Jan 10 01:23:20 PM PST 24
Finished Jan 10 01:40:06 PM PST 24
Peak memory 239984 kb
Host smart-bcb86091-f0fc-4df9-bc3c-74936075f549
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709587461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.2709587461
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.1667139077
Short name T170
Test name
Test status
Simulation time 25758611812 ps
CPU time 366.22 seconds
Started Jan 10 01:23:34 PM PST 24
Finished Jan 10 01:29:44 PM PST 24
Peak memory 225568 kb
Host smart-15e58852-20c6-415c-94a1-02ee9b7dbb1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667139077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.1667139077
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.2194860975
Short name T120
Test name
Test status
Simulation time 79033756595 ps
CPU time 628.71 seconds
Started Jan 10 01:23:06 PM PST 24
Finished Jan 10 01:33:52 PM PST 24
Peak memory 208344 kb
Host smart-7d575194-6b2b-42c4-91ed-9878098eb7b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194860975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.2194860975
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.417704806
Short name T712
Test name
Test status
Simulation time 100681984947 ps
CPU time 1244.85 seconds
Started Jan 10 01:23:33 PM PST 24
Finished Jan 10 01:44:22 PM PST 24
Peak memory 223596 kb
Host smart-7c45b3b4-9569-42a1-adff-30d10c3b0086
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417704806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.417704806
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.34415702
Short name T643
Test name
Test status
Simulation time 41314849466 ps
CPU time 461.56 seconds
Started Jan 10 01:23:31 PM PST 24
Finished Jan 10 01:31:18 PM PST 24
Peak memory 214372 kb
Host smart-281c2ea4-a2c6-4925-863a-125da4ccdee9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34415702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.34415702
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.351813574
Short name T7
Test name
Test status
Simulation time 55664833455 ps
CPU time 266.87 seconds
Started Jan 10 01:23:07 PM PST 24
Finished Jan 10 01:27:51 PM PST 24
Peak memory 215276 kb
Host smart-fd4fcba5-61e0-433d-8717-ed78e791a12f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351813574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.351813574
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.1211936050
Short name T121
Test name
Test status
Simulation time 52545482950 ps
CPU time 414.54 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:30:21 PM PST 24
Peak memory 235536 kb
Host smart-909725f5-30cf-4ad6-a68c-06bed7f842ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211936050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.1211936050
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.1565191808
Short name T573
Test name
Test status
Simulation time 463939723091 ps
CPU time 1450.2 seconds
Started Jan 10 01:23:21 PM PST 24
Finished Jan 10 01:47:43 PM PST 24
Peak memory 246896 kb
Host smart-5a76f7cc-2326-4377-a74a-148cc70088c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565191808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.1565191808
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.2376849223
Short name T123
Test name
Test status
Simulation time 74795974807 ps
CPU time 647.12 seconds
Started Jan 10 01:23:17 PM PST 24
Finished Jan 10 01:34:18 PM PST 24
Peak memory 247220 kb
Host smart-ab9543bf-e5a0-4bae-856d-bbe0f8fcbf1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376849223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.2376849223
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2380175466
Short name T213
Test name
Test status
Simulation time 50372206 ps
CPU time 0.59 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:22:10 PM PST 24
Peak memory 193028 kb
Host smart-a6e1035e-01cf-445c-a0b0-ec76aae746e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380175466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2380175466
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.842525576
Short name T283
Test name
Test status
Simulation time 1292538801 ps
CPU time 19.42 seconds
Started Jan 10 01:21:59 PM PST 24
Finished Jan 10 01:22:46 PM PST 24
Peak memory 229524 kb
Host smart-22caf5a5-a4d9-4d33-9b14-9bec32bb882a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842525576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.842525576
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3421379660
Short name T689
Test name
Test status
Simulation time 12946416647 ps
CPU time 48.26 seconds
Started Jan 10 01:21:50 PM PST 24
Finished Jan 10 01:23:07 PM PST 24
Peak memory 198812 kb
Host smart-a33ba412-ce1d-4f07-8fa9-f0090eeb0768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421379660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3421379660
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3618045091
Short name T720
Test name
Test status
Simulation time 4141540185 ps
CPU time 57.76 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:23:16 PM PST 24
Peak memory 198800 kb
Host smart-b56c58e7-7fd5-47f7-9aa1-98669bc9b261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618045091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3618045091
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.137616920
Short name T649
Test name
Test status
Simulation time 511439836 ps
CPU time 13.41 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:22:40 PM PST 24
Peak memory 198676 kb
Host smart-7e855912-1d21-4d16-9e46-757b670bfdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137616920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.137616920
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.4243368757
Short name T204
Test name
Test status
Simulation time 4048530988 ps
CPU time 32.42 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:22:29 PM PST 24
Peak memory 198780 kb
Host smart-22065d3a-a729-4887-93df-bc2e6e360748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243368757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4243368757
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1348276695
Short name T627
Test name
Test status
Simulation time 320305851 ps
CPU time 3.12 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:17 PM PST 24
Peak memory 198644 kb
Host smart-cea3ab43-1add-40bb-aba0-820802e5d163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348276695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1348276695
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1367015553
Short name T59
Test name
Test status
Simulation time 372988036545 ps
CPU time 1055.12 seconds
Started Jan 10 01:21:45 PM PST 24
Finished Jan 10 01:39:44 PM PST 24
Peak memory 198724 kb
Host smart-148915e4-470e-4394-ae94-a6959e730422
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367015553 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1367015553
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.3690888963
Short name T441
Test name
Test status
Simulation time 68249911499 ps
CPU time 283.52 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:26:54 PM PST 24
Peak memory 215200 kb
Host smart-daa8ca21-af7c-45d9-8f01-60eeafb4b68a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3690888963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.3690888963
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3789458118
Short name T230
Test name
Test status
Simulation time 214050714 ps
CPU time 1.09 seconds
Started Jan 10 01:21:59 PM PST 24
Finished Jan 10 01:22:28 PM PST 24
Peak memory 196844 kb
Host smart-3ca0cb53-e3e1-48d0-80a6-f96f9ed4da96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789458118 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3789458118
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1298160652
Short name T260
Test name
Test status
Simulation time 49946068073 ps
CPU time 383.23 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:28:50 PM PST 24
Peak memory 198764 kb
Host smart-8cdcb6e7-d0f6-4584-8019-2c794e38e08e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298160652 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.1298160652
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2809281394
Short name T178
Test name
Test status
Simulation time 5913474509 ps
CPU time 23.34 seconds
Started Jan 10 01:21:59 PM PST 24
Finished Jan 10 01:22:50 PM PST 24
Peak memory 198800 kb
Host smart-ea7ca9e5-69e9-41e4-ae35-8ed13bbf6bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809281394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2809281394
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.2299102803
Short name T208
Test name
Test status
Simulation time 142541166391 ps
CPU time 1034.91 seconds
Started Jan 10 01:23:20 PM PST 24
Finished Jan 10 01:40:47 PM PST 24
Peak memory 240376 kb
Host smart-529aa4f7-c6c3-4039-b6cb-f433fdee317f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299102803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.2299102803
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.3296438045
Short name T94
Test name
Test status
Simulation time 163526380024 ps
CPU time 5376.89 seconds
Started Jan 10 01:23:35 PM PST 24
Finished Jan 10 02:53:16 PM PST 24
Peak memory 272716 kb
Host smart-0fb2b588-9f80-4d82-ad3c-b05ec672c517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296438045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.3296438045
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.1602715895
Short name T133
Test name
Test status
Simulation time 106766577313 ps
CPU time 2649.46 seconds
Started Jan 10 01:23:23 PM PST 24
Finished Jan 10 02:07:43 PM PST 24
Peak memory 258232 kb
Host smart-044f1d68-1076-41de-b1e3-9c8df0846ca4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1602715895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.hmac_stress_all_with_rand_reset.1602715895
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.3482969151
Short name T704
Test name
Test status
Simulation time 355422763107 ps
CPU time 3897.29 seconds
Started Jan 10 01:23:23 PM PST 24
Finished Jan 10 02:28:31 PM PST 24
Peak memory 263508 kb
Host smart-7c2f4dc8-9ede-444b-a519-dd75b047c529
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3482969151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.3482969151
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.3537197877
Short name T647
Test name
Test status
Simulation time 423136403807 ps
CPU time 1243.15 seconds
Started Jan 10 01:23:35 PM PST 24
Finished Jan 10 01:44:23 PM PST 24
Peak memory 252976 kb
Host smart-397f74ef-6653-44ab-87a2-aace9bc843a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537197877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.3537197877
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.907177334
Short name T353
Test name
Test status
Simulation time 251447032156 ps
CPU time 867.59 seconds
Started Jan 10 01:23:35 PM PST 24
Finished Jan 10 01:38:06 PM PST 24
Peak memory 229192 kb
Host smart-d4507a24-2b6f-4953-8516-613d8fcfef0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907177334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.907177334
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.2759300621
Short name T322
Test name
Test status
Simulation time 597486665115 ps
CPU time 2331.15 seconds
Started Jan 10 01:23:14 PM PST 24
Finished Jan 10 02:02:22 PM PST 24
Peak memory 262068 kb
Host smart-ad331a76-3f31-436a-a0af-c6974fa42b54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2759300621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.2759300621
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.828902536
Short name T757
Test name
Test status
Simulation time 37918736649 ps
CPU time 734.62 seconds
Started Jan 10 01:23:37 PM PST 24
Finished Jan 10 01:35:58 PM PST 24
Peak memory 244048 kb
Host smart-02e833eb-8e7a-44db-af34-206600f7017e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828902536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.828902536
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.3909776343
Short name T583
Test name
Test status
Simulation time 14588259024 ps
CPU time 166.46 seconds
Started Jan 10 01:23:39 PM PST 24
Finished Jan 10 01:26:32 PM PST 24
Peak memory 215352 kb
Host smart-0e6318f4-810f-475f-a97f-79cf34b4d8e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909776343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.3909776343
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3667402454
Short name T252
Test name
Test status
Simulation time 13455461 ps
CPU time 0.56 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:21:56 PM PST 24
Peak memory 193144 kb
Host smart-808e1c91-fa2b-4185-9268-d1ed5eef9cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667402454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3667402454
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3786526486
Short name T553
Test name
Test status
Simulation time 894478930 ps
CPU time 24.48 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:22:24 PM PST 24
Peak memory 214600 kb
Host smart-c828b0d5-c7be-482c-af49-b5608ef4f165
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3786526486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3786526486
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2222455423
Short name T769
Test name
Test status
Simulation time 5145798347 ps
CPU time 25.18 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:22:25 PM PST 24
Peak memory 198844 kb
Host smart-20a1b1f7-9ade-4bf4-8735-ea22a4862337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222455423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2222455423
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2594377076
Short name T520
Test name
Test status
Simulation time 14113779594 ps
CPU time 143.17 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:24:20 PM PST 24
Peak memory 198804 kb
Host smart-431d0fa4-242a-4276-b973-5285efb5f512
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594377076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2594377076
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3995444637
Short name T10
Test name
Test status
Simulation time 10466765724 ps
CPU time 128.95 seconds
Started Jan 10 01:21:35 PM PST 24
Finished Jan 10 01:24:03 PM PST 24
Peak memory 198964 kb
Host smart-0c85c024-b012-471d-a2df-8d73feefb2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995444637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3995444637
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4010888036
Short name T314
Test name
Test status
Simulation time 12769325139 ps
CPU time 55.4 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:22:50 PM PST 24
Peak memory 198944 kb
Host smart-83dba6f2-5cc6-45ef-a182-12de3aab7256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010888036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4010888036
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2251322893
Short name T320
Test name
Test status
Simulation time 263722699 ps
CPU time 3.55 seconds
Started Jan 10 01:21:53 PM PST 24
Finished Jan 10 01:22:25 PM PST 24
Peak memory 198496 kb
Host smart-68e66bde-e97d-4d93-84a8-d72d9e9685f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251322893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2251322893
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3742582113
Short name T125
Test name
Test status
Simulation time 88758094114 ps
CPU time 488.93 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:30:12 PM PST 24
Peak memory 230948 kb
Host smart-92782467-f166-4666-9f0d-90b8f5805272
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742582113 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3742582113
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.2108540781
Short name T576
Test name
Test status
Simulation time 117907295498 ps
CPU time 466.97 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:29:42 PM PST 24
Peak memory 223704 kb
Host smart-f62e24dd-14fa-466a-8a78-de199c80fbca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108540781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.2108540781
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1540748610
Short name T209
Test name
Test status
Simulation time 28889401 ps
CPU time 0.88 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:21:55 PM PST 24
Peak memory 195896 kb
Host smart-38656f03-4674-4770-bff9-b5bb8bf3b0b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540748610 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1540748610
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2991906157
Short name T440
Test name
Test status
Simulation time 55053799338 ps
CPU time 353.08 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:27:48 PM PST 24
Peak memory 198800 kb
Host smart-6f551851-480d-45ed-b68d-7672cc108c68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991906157 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.2991906157
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1204202149
Short name T352
Test name
Test status
Simulation time 9980519820 ps
CPU time 21.21 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:22:20 PM PST 24
Peak memory 198820 kb
Host smart-d5588a9a-742d-4fbd-a124-fdf9abb8aa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204202149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1204202149
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.2565361442
Short name T662
Test name
Test status
Simulation time 34848996528 ps
CPU time 504.73 seconds
Started Jan 10 01:23:23 PM PST 24
Finished Jan 10 01:31:58 PM PST 24
Peak memory 215084 kb
Host smart-961af00a-5650-44d0-b765-3a7a7e4dce48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2565361442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.2565361442
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.913484245
Short name T128
Test name
Test status
Simulation time 82875401973 ps
CPU time 2095.22 seconds
Started Jan 10 01:23:23 PM PST 24
Finished Jan 10 01:58:29 PM PST 24
Peak memory 227044 kb
Host smart-4362fa85-bc64-4eca-8e98-8183f544f3e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=913484245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.913484245
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.2872708345
Short name T471
Test name
Test status
Simulation time 165587802224 ps
CPU time 1143.85 seconds
Started Jan 10 01:23:34 PM PST 24
Finished Jan 10 01:42:42 PM PST 24
Peak memory 231716 kb
Host smart-5a06b89c-55a3-4ad0-8bf1-5f588b25c32b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872708345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.2872708345
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.2880131789
Short name T97
Test name
Test status
Simulation time 310861458160 ps
CPU time 1067.33 seconds
Started Jan 10 01:23:13 PM PST 24
Finished Jan 10 01:41:17 PM PST 24
Peak memory 231592 kb
Host smart-0261e683-5428-4e24-9cb0-00a199e929f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880131789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.2880131789
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.788689545
Short name T477
Test name
Test status
Simulation time 396558231 ps
CPU time 8.19 seconds
Started Jan 10 01:23:17 PM PST 24
Finished Jan 10 01:23:39 PM PST 24
Peak memory 198880 kb
Host smart-d0edfdbc-0861-4ca9-8c49-6232bb3a5675
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=788689545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.788689545
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.3256727614
Short name T735
Test name
Test status
Simulation time 41022491170 ps
CPU time 1387.06 seconds
Started Jan 10 01:23:29 PM PST 24
Finished Jan 10 01:46:42 PM PST 24
Peak memory 209304 kb
Host smart-f394a411-7b8e-4a05-91cf-78bb228cb4d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256727614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.3256727614
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.46397884
Short name T40
Test name
Test status
Simulation time 84254512527 ps
CPU time 3695.27 seconds
Started Jan 10 01:23:38 PM PST 24
Finished Jan 10 02:25:20 PM PST 24
Peak memory 256180 kb
Host smart-349bfd61-e924-4424-98c3-f9d75b23d800
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46397884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.46397884
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.2234163530
Short name T54
Test name
Test status
Simulation time 321970788093 ps
CPU time 3653 seconds
Started Jan 10 01:23:34 PM PST 24
Finished Jan 10 02:24:31 PM PST 24
Peak memory 225976 kb
Host smart-5f27d443-053b-40af-864b-f92676f3f2ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2234163530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.2234163530
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.3037889012
Short name T243
Test name
Test status
Simulation time 41245926838 ps
CPU time 737.45 seconds
Started Jan 10 01:23:34 PM PST 24
Finished Jan 10 01:35:55 PM PST 24
Peak memory 230056 kb
Host smart-23b587f7-1d95-4a42-9456-c7a46548ae22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037889012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.3037889012
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.4122063024
Short name T458
Test name
Test status
Simulation time 16322245 ps
CPU time 0.57 seconds
Started Jan 10 01:21:29 PM PST 24
Finished Jan 10 01:21:44 PM PST 24
Peak memory 193332 kb
Host smart-23949b63-61eb-4ad3-b9d9-058f0bb57f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122063024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4122063024
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.462908100
Short name T44
Test name
Test status
Simulation time 7650459724 ps
CPU time 48.64 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:22:37 PM PST 24
Peak memory 231632 kb
Host smart-2389e86f-3ab8-42b3-a057-017a25682b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462908100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.462908100
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2500045132
Short name T505
Test name
Test status
Simulation time 1808942897 ps
CPU time 31.41 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:22:25 PM PST 24
Peak memory 198848 kb
Host smart-5158209a-6ffa-4900-b413-2c013626c432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500045132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2500045132
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1216861373
Short name T37
Test name
Test status
Simulation time 1836054598 ps
CPU time 75.73 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:23:09 PM PST 24
Peak memory 198756 kb
Host smart-96abd1d5-e7fc-466e-b734-34a0dc6aa266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216861373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1216861373
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1896564283
Short name T1
Test name
Test status
Simulation time 1912632479 ps
CPU time 31.07 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:22:19 PM PST 24
Peak memory 198792 kb
Host smart-1bcd57ca-ec89-4c54-a5db-a9d81ec4c88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896564283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1896564283
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3720129313
Short name T201
Test name
Test status
Simulation time 986213442 ps
CPU time 6.21 seconds
Started Jan 10 01:21:30 PM PST 24
Finished Jan 10 01:21:53 PM PST 24
Peak memory 198784 kb
Host smart-71c86cf9-8af7-4623-9601-f26f7c230a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720129313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3720129313
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1180218129
Short name T48
Test name
Test status
Simulation time 339617343 ps
CPU time 0.97 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:21:49 PM PST 24
Peak memory 217056 kb
Host smart-322368d8-9b8b-4835-a1a6-761b166e7d9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180218129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1180218129
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.694728237
Short name T188
Test name
Test status
Simulation time 2081173308 ps
CPU time 3.48 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:21:54 PM PST 24
Peak memory 198848 kb
Host smart-9b81dcba-b43b-4afb-b7f8-e98288f520ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694728237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.694728237
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2820439134
Short name T224
Test name
Test status
Simulation time 29355258267 ps
CPU time 88.18 seconds
Started Jan 10 01:21:35 PM PST 24
Finished Jan 10 01:23:22 PM PST 24
Peak memory 198828 kb
Host smart-ba2a7626-f705-45ef-9fed-80fcc3c37f76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820439134 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2820439134
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.700025990
Short name T357
Test name
Test status
Simulation time 344632497341 ps
CPU time 3814.24 seconds
Started Jan 10 01:21:30 PM PST 24
Finished Jan 10 02:25:22 PM PST 24
Peak memory 264520 kb
Host smart-3ac0e692-1784-4095-b448-587a4c91a25c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700025990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.700025990
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2831299863
Short name T449
Test name
Test status
Simulation time 328133912 ps
CPU time 0.87 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:21:49 PM PST 24
Peak memory 195912 kb
Host smart-9dec410d-4d75-472f-a443-0c81156def5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831299863 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2831299863
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.883783509
Short name T39
Test name
Test status
Simulation time 12454246042 ps
CPU time 364.41 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:27:52 PM PST 24
Peak memory 198688 kb
Host smart-bc6fbd9a-6b6d-4f6c-a54f-21ff01d0fd24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883783509 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.hmac_test_sha_vectors.883783509
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2667097777
Short name T257
Test name
Test status
Simulation time 2024089685 ps
CPU time 39.45 seconds
Started Jan 10 01:21:05 PM PST 24
Finished Jan 10 01:21:49 PM PST 24
Peak memory 198824 kb
Host smart-836641fa-9fc7-4012-8de4-d67468baa2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667097777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2667097777
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1290449807
Short name T470
Test name
Test status
Simulation time 12448243 ps
CPU time 0.56 seconds
Started Jan 10 01:21:50 PM PST 24
Finished Jan 10 01:22:19 PM PST 24
Peak memory 193072 kb
Host smart-75cc2495-4e0a-46e5-ab7e-2a9e4e51129a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290449807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1290449807
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4128881963
Short name T566
Test name
Test status
Simulation time 232146488 ps
CPU time 1.92 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:06 PM PST 24
Peak memory 214812 kb
Host smart-01883df0-8914-4983-a963-3bdcb1ec69e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4128881963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4128881963
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.159571430
Short name T345
Test name
Test status
Simulation time 3041060150 ps
CPU time 40.17 seconds
Started Jan 10 01:21:59 PM PST 24
Finished Jan 10 01:23:07 PM PST 24
Peak memory 198876 kb
Host smart-340929c2-9702-447e-b684-8b96d2f3d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159571430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.159571430
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3819278831
Short name T377
Test name
Test status
Simulation time 311715908 ps
CPU time 3.77 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:18 PM PST 24
Peak memory 198792 kb
Host smart-6d8be838-7eaa-4812-a5f1-f536265ddc21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819278831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3819278831
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2996892810
Short name T456
Test name
Test status
Simulation time 5944828926 ps
CPU time 14.52 seconds
Started Jan 10 01:21:51 PM PST 24
Finished Jan 10 01:22:34 PM PST 24
Peak memory 198868 kb
Host smart-0271edad-1f20-4036-a4b9-42117a55befc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996892810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2996892810
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.133422160
Short name T775
Test name
Test status
Simulation time 1621129179 ps
CPU time 83.73 seconds
Started Jan 10 01:21:43 PM PST 24
Finished Jan 10 01:23:29 PM PST 24
Peak memory 198776 kb
Host smart-bfeb4633-d55b-465b-b81f-bc808067f9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133422160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.133422160
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1956560606
Short name T599
Test name
Test status
Simulation time 39594825 ps
CPU time 1.17 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:05 PM PST 24
Peak memory 197880 kb
Host smart-0c4c01b6-567c-45a1-9c21-da441b5c6dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956560606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1956560606
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1845952522
Short name T171
Test name
Test status
Simulation time 208931744880 ps
CPU time 1216.1 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 01:42:40 PM PST 24
Peak memory 207056 kb
Host smart-351805c0-735d-4f9c-9cfe-a076817cb336
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845952522 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1845952522
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.1594804740
Short name T418
Test name
Test status
Simulation time 57715005217 ps
CPU time 746.55 seconds
Started Jan 10 01:21:51 PM PST 24
Finished Jan 10 01:34:46 PM PST 24
Peak memory 223488 kb
Host smart-7274ddcb-a555-428c-a517-3424002e484e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594804740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.1594804740
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1197586227
Short name T650
Test name
Test status
Simulation time 240321705 ps
CPU time 1.1 seconds
Started Jan 10 01:21:50 PM PST 24
Finished Jan 10 01:22:20 PM PST 24
Peak memory 197540 kb
Host smart-407f4374-7228-4bb4-9092-5a8c4b551e7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197586227 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1197586227
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1518483152
Short name T747
Test name
Test status
Simulation time 30364233181 ps
CPU time 358.7 seconds
Started Jan 10 01:21:56 PM PST 24
Finished Jan 10 01:28:25 PM PST 24
Peak memory 198668 kb
Host smart-de60c830-7ea0-4ab4-bdb2-3993f4293088
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518483152 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.1518483152
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2632054853
Short name T168
Test name
Test status
Simulation time 10646913580 ps
CPU time 32.8 seconds
Started Jan 10 01:21:48 PM PST 24
Finished Jan 10 01:22:46 PM PST 24
Peak memory 198888 kb
Host smart-c7333958-382f-4860-a39f-7020ad6e7b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632054853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2632054853
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3771540345
Short name T176
Test name
Test status
Simulation time 14072506 ps
CPU time 0.55 seconds
Started Jan 10 01:21:50 PM PST 24
Finished Jan 10 01:22:19 PM PST 24
Peak memory 193152 kb
Host smart-cd31015a-5291-4ca1-b0d0-77a107040344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771540345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3771540345
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2949053144
Short name T336
Test name
Test status
Simulation time 5247534171 ps
CPU time 39.27 seconds
Started Jan 10 01:21:55 PM PST 24
Finished Jan 10 01:23:05 PM PST 24
Peak memory 207040 kb
Host smart-a4165cb4-6da2-4cb9-8f88-0ff303336356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949053144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2949053144
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.321798186
Short name T564
Test name
Test status
Simulation time 2992246737 ps
CPU time 35.56 seconds
Started Jan 10 01:21:52 PM PST 24
Finished Jan 10 01:22:57 PM PST 24
Peak memory 198868 kb
Host smart-fc3dc6a6-8b72-4bc4-b74f-ebbb790a8c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321798186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.321798186
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3169834057
Short name T672
Test name
Test status
Simulation time 1920359019 ps
CPU time 100.67 seconds
Started Jan 10 01:21:50 PM PST 24
Finished Jan 10 01:23:59 PM PST 24
Peak memory 198640 kb
Host smart-5838339d-0c66-4d80-a983-75e23b31c3d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169834057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3169834057
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2882220024
Short name T676
Test name
Test status
Simulation time 6953880447 ps
CPU time 83.62 seconds
Started Jan 10 01:21:50 PM PST 24
Finished Jan 10 01:23:42 PM PST 24
Peak memory 198752 kb
Host smart-b1169772-0f32-4750-9cd9-9c5443bcabb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882220024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2882220024
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3079460413
Short name T270
Test name
Test status
Simulation time 1381541595 ps
CPU time 73.21 seconds
Started Jan 10 01:21:52 PM PST 24
Finished Jan 10 01:23:34 PM PST 24
Peak memory 198788 kb
Host smart-e18e2137-a3c2-4c28-91a4-8c737dc2d3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079460413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3079460413
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.221251054
Short name T269
Test name
Test status
Simulation time 108229815 ps
CPU time 1.47 seconds
Started Jan 10 01:21:55 PM PST 24
Finished Jan 10 01:22:27 PM PST 24
Peak memory 198516 kb
Host smart-d24587b1-06fe-4cb2-9b8a-60d890b63a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221251054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.221251054
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.4281758246
Short name T36
Test name
Test status
Simulation time 14234979565 ps
CPU time 122.88 seconds
Started Jan 10 01:21:55 PM PST 24
Finished Jan 10 01:24:28 PM PST 24
Peak memory 208068 kb
Host smart-9823cbdc-41bd-418f-8958-4c8fb889ffe9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281758246 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.4281758246
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.34507376
Short name T623
Test name
Test status
Simulation time 52952815223 ps
CPU time 695.45 seconds
Started Jan 10 01:21:52 PM PST 24
Finished Jan 10 01:33:57 PM PST 24
Peak memory 241756 kb
Host smart-03fa20a7-c462-4c25-817d-30605bed72ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34507376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.34507376
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.845691510
Short name T797
Test name
Test status
Simulation time 139255536 ps
CPU time 1.16 seconds
Started Jan 10 01:21:51 PM PST 24
Finished Jan 10 01:22:20 PM PST 24
Peak memory 196400 kb
Host smart-48c70812-5ac9-4c11-8520-c06c7c4674fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845691510 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.845691510
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3962567151
Short name T756
Test name
Test status
Simulation time 10243227548 ps
CPU time 370.88 seconds
Started Jan 10 01:21:53 PM PST 24
Finished Jan 10 01:28:33 PM PST 24
Peak memory 198784 kb
Host smart-79e19d6a-5b87-49b1-9081-4f414c3ea5c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962567151 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.3962567151
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2920012975
Short name T221
Test name
Test status
Simulation time 5343789761 ps
CPU time 61.06 seconds
Started Jan 10 01:21:57 PM PST 24
Finished Jan 10 01:23:27 PM PST 24
Peak memory 198948 kb
Host smart-2fbccbfc-14f2-4995-ac98-9c0349a20cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920012975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2920012975
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3077586441
Short name T239
Test name
Test status
Simulation time 13728078 ps
CPU time 0.56 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:22:27 PM PST 24
Peak memory 193144 kb
Host smart-146a4494-0be2-4d77-b49a-fd57f3aa5777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077586441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3077586441
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2361453411
Short name T457
Test name
Test status
Simulation time 3716233502 ps
CPU time 32.43 seconds
Started Jan 10 01:21:53 PM PST 24
Finished Jan 10 01:22:54 PM PST 24
Peak memory 207024 kb
Host smart-d8904d02-ba5d-423e-a732-326b28b1832c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2361453411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2361453411
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2914421817
Short name T528
Test name
Test status
Simulation time 1212671514 ps
CPU time 5.87 seconds
Started Jan 10 01:21:51 PM PST 24
Finished Jan 10 01:22:25 PM PST 24
Peak memory 198572 kb
Host smart-0689aed7-5e12-405b-9c89-115b7ca6ed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914421817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2914421817
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3397029958
Short name T182
Test name
Test status
Simulation time 2736392797 ps
CPU time 33.26 seconds
Started Jan 10 01:21:57 PM PST 24
Finished Jan 10 01:22:59 PM PST 24
Peak memory 198860 kb
Host smart-6a96b859-418b-4546-8758-47f94cce17d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397029958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3397029958
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.4066060382
Short name T737
Test name
Test status
Simulation time 13640481991 ps
CPU time 51.7 seconds
Started Jan 10 01:22:07 PM PST 24
Finished Jan 10 01:23:25 PM PST 24
Peak memory 198840 kb
Host smart-9fc9215f-2cff-4296-8c23-4fb4df128be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066060382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4066060382
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3300749275
Short name T285
Test name
Test status
Simulation time 4540798963 ps
CPU time 57.01 seconds
Started Jan 10 01:21:50 PM PST 24
Finished Jan 10 01:23:16 PM PST 24
Peak memory 198944 kb
Host smart-a2969013-b510-45e7-a06e-5b1a5642b593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300749275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3300749275
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3694309433
Short name T455
Test name
Test status
Simulation time 2575056753 ps
CPU time 4.13 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 01:22:28 PM PST 24
Peak memory 198832 kb
Host smart-6886f4a0-de93-4963-8280-c3334f65e7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694309433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3694309433
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.23406576
Short name T706
Test name
Test status
Simulation time 81245234107 ps
CPU time 1351.69 seconds
Started Jan 10 01:21:55 PM PST 24
Finished Jan 10 01:44:56 PM PST 24
Peak memory 231672 kb
Host smart-0f053c5f-0f00-4e30-9a82-928a0c514143
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23406576 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.23406576
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.3153849902
Short name T609
Test name
Test status
Simulation time 35153621087 ps
CPU time 1654 seconds
Started Jan 10 01:22:06 PM PST 24
Finished Jan 10 01:50:06 PM PST 24
Peak memory 239896 kb
Host smart-cac05115-9558-4b83-a6bb-0394ff8d6cb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3153849902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.3153849902
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2752695824
Short name T158
Test name
Test status
Simulation time 56406295 ps
CPU time 1.14 seconds
Started Jan 10 01:22:00 PM PST 24
Finished Jan 10 01:22:28 PM PST 24
Peak memory 197424 kb
Host smart-92a3353b-0fab-47a9-831c-80d385953233
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752695824 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2752695824
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3836179202
Short name T693
Test name
Test status
Simulation time 88454781694 ps
CPU time 356.36 seconds
Started Jan 10 01:21:50 PM PST 24
Finished Jan 10 01:28:15 PM PST 24
Peak memory 198832 kb
Host smart-0ce07f6c-2aef-42fa-90cb-78a8abd0d342
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836179202 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.3836179202
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.446430557
Short name T595
Test name
Test status
Simulation time 899413942 ps
CPU time 27.6 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 01:22:51 PM PST 24
Peak memory 198788 kb
Host smart-833b11db-ba57-4f9e-8e16-71930ec7e4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446430557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.446430557
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2963048342
Short name T556
Test name
Test status
Simulation time 47901055 ps
CPU time 0.61 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 01:22:25 PM PST 24
Peak memory 193172 kb
Host smart-8a772099-bd51-4363-8dde-66b87acaddbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963048342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2963048342
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3365110413
Short name T223
Test name
Test status
Simulation time 13174470151 ps
CPU time 31.91 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:22:58 PM PST 24
Peak memory 215216 kb
Host smart-2e78f4ef-84da-46c8-93c4-f7b5199fcdbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365110413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3365110413
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2087122638
Short name T365
Test name
Test status
Simulation time 1060341252 ps
CPU time 45.56 seconds
Started Jan 10 01:21:59 PM PST 24
Finished Jan 10 01:23:13 PM PST 24
Peak memory 198772 kb
Host smart-263f21e6-b36c-4639-8475-07dda5020f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087122638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2087122638
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.29655943
Short name T730
Test name
Test status
Simulation time 23314614717 ps
CPU time 106.55 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:24:13 PM PST 24
Peak memory 198756 kb
Host smart-bb1cf0fc-6b22-432f-aad5-633112f4a6ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29655943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.29655943
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.266189167
Short name T612
Test name
Test status
Simulation time 32413553536 ps
CPU time 124.06 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:24:30 PM PST 24
Peak memory 198712 kb
Host smart-87443f56-cb1a-4bbb-87d9-818c008c75bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266189167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.266189167
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3084495197
Short name T141
Test name
Test status
Simulation time 790026979 ps
CPU time 19.77 seconds
Started Jan 10 01:21:57 PM PST 24
Finished Jan 10 01:22:46 PM PST 24
Peak memory 198780 kb
Host smart-21f772cd-512f-4fe7-9c55-9a1e49e0b569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084495197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3084495197
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.359688204
Short name T723
Test name
Test status
Simulation time 1226381957 ps
CPU time 1.91 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:16 PM PST 24
Peak memory 198632 kb
Host smart-1226d8fa-6421-4969-b60a-d58b748b1bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359688204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.359688204
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.785012111
Short name T387
Test name
Test status
Simulation time 363199978273 ps
CPU time 2220.25 seconds
Started Jan 10 01:21:55 PM PST 24
Finished Jan 10 01:59:25 PM PST 24
Peak memory 239852 kb
Host smart-381e7e56-684a-4de0-8ad3-5b4168c231e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785012111 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.785012111
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1134022001
Short name T280
Test name
Test status
Simulation time 50512462 ps
CPU time 0.84 seconds
Started Jan 10 01:21:59 PM PST 24
Finished Jan 10 01:22:28 PM PST 24
Peak memory 196020 kb
Host smart-0e09d3a3-c953-4965-a4d0-c1f0bd892088
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134022001 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1134022001
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.26957703
Short name T53
Test name
Test status
Simulation time 47676464887 ps
CPU time 376 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:28:43 PM PST 24
Peak memory 197932 kb
Host smart-ddbadf82-1918-4a7c-9a5d-7a15fe033e6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26957703 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.hmac_test_sha_vectors.26957703
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1179301639
Short name T655
Test name
Test status
Simulation time 2259300344 ps
CPU time 39.18 seconds
Started Jan 10 01:21:55 PM PST 24
Finished Jan 10 01:23:03 PM PST 24
Peak memory 198868 kb
Host smart-7870a159-b346-4cdf-89e2-afbdf0db3886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179301639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1179301639
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1351478447
Short name T393
Test name
Test status
Simulation time 13721885 ps
CPU time 0.57 seconds
Started Jan 10 01:22:00 PM PST 24
Finished Jan 10 01:22:28 PM PST 24
Peak memory 193124 kb
Host smart-5ce43588-f9e6-4737-96f8-d1f9dd815f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351478447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1351478447
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2429823495
Short name T487
Test name
Test status
Simulation time 1434367663 ps
CPU time 42.55 seconds
Started Jan 10 01:22:09 PM PST 24
Finished Jan 10 01:23:17 PM PST 24
Peak memory 227232 kb
Host smart-32b98a78-78ed-4938-8e4c-d8baa1a88f7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429823495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2429823495
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2775319254
Short name T390
Test name
Test status
Simulation time 2570394221 ps
CPU time 55.56 seconds
Started Jan 10 01:22:05 PM PST 24
Finished Jan 10 01:23:27 PM PST 24
Peak memory 198844 kb
Host smart-83bb6386-56d4-43b9-b249-d34c4c5abcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775319254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2775319254
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1383829090
Short name T254
Test name
Test status
Simulation time 8045708831 ps
CPU time 67.27 seconds
Started Jan 10 01:22:09 PM PST 24
Finished Jan 10 01:23:42 PM PST 24
Peak memory 198780 kb
Host smart-8445fe47-8690-42db-837c-b4c5cc4cf6ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383829090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1383829090
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1020487187
Short name T415
Test name
Test status
Simulation time 15105612201 ps
CPU time 67.33 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:23:34 PM PST 24
Peak memory 198868 kb
Host smart-6a1ed011-5ff4-4616-9db0-15d7ec673a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020487187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1020487187
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2003524538
Short name T301
Test name
Test status
Simulation time 270173976 ps
CPU time 14.19 seconds
Started Jan 10 01:22:09 PM PST 24
Finished Jan 10 01:22:49 PM PST 24
Peak memory 198792 kb
Host smart-917e3b57-f513-441e-8428-76309e568a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003524538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2003524538
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.601502531
Short name T244
Test name
Test status
Simulation time 822267133 ps
CPU time 3.12 seconds
Started Jan 10 01:21:52 PM PST 24
Finished Jan 10 01:22:25 PM PST 24
Peak memory 198720 kb
Host smart-bb98f42c-e9fd-47f9-bea8-5221c9f3e683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601502531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.601502531
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1415589438
Short name T544
Test name
Test status
Simulation time 182120713674 ps
CPU time 1079.06 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:40:26 PM PST 24
Peak memory 198748 kb
Host smart-41c3c4b5-ef32-46eb-90aa-b271f57b1176
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415589438 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1415589438
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.2893552034
Short name T530
Test name
Test status
Simulation time 81556797862 ps
CPU time 1444.59 seconds
Started Jan 10 01:22:00 PM PST 24
Finished Jan 10 01:46:32 PM PST 24
Peak memory 231668 kb
Host smart-520aae22-f2e3-4c0b-92c8-1beff7a53584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893552034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.2893552034
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.904216002
Short name T386
Test name
Test status
Simulation time 125716312 ps
CPU time 1.14 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:22:28 PM PST 24
Peak memory 196956 kb
Host smart-f8b3f049-6283-4664-94ec-c2064e741229
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904216002 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_hmac_vectors.904216002
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2055205833
Short name T579
Test name
Test status
Simulation time 51926226839 ps
CPU time 378.76 seconds
Started Jan 10 01:22:10 PM PST 24
Finished Jan 10 01:28:54 PM PST 24
Peak memory 198800 kb
Host smart-77e4cf87-72f8-4e9e-abeb-36a48a1291f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055205833 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.2055205833
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1652841608
Short name T231
Test name
Test status
Simulation time 1117524919 ps
CPU time 12.48 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:22:39 PM PST 24
Peak memory 198592 kb
Host smart-9b268613-1bd9-40ea-97b9-930ba8fa100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652841608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1652841608
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3661985318
Short name T767
Test name
Test status
Simulation time 33783225 ps
CPU time 0.55 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 01:22:23 PM PST 24
Peak memory 193176 kb
Host smart-90bf66a0-7092-426f-b79d-2a71d570a57b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661985318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3661985318
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.300443440
Short name T488
Test name
Test status
Simulation time 439078946 ps
CPU time 16.2 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:22:43 PM PST 24
Peak memory 231568 kb
Host smart-f4a06922-395f-49aa-9390-4f71c5136dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300443440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.300443440
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2109978140
Short name T167
Test name
Test status
Simulation time 3169832905 ps
CPU time 28.07 seconds
Started Jan 10 01:22:05 PM PST 24
Finished Jan 10 01:23:00 PM PST 24
Peak memory 198860 kb
Host smart-f51d36bd-7c38-4472-a235-b3d3c0e6f5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109978140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2109978140
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.4230757959
Short name T58
Test name
Test status
Simulation time 1144682622 ps
CPU time 58.82 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:23:26 PM PST 24
Peak memory 198816 kb
Host smart-dfa85160-e321-47e0-9d96-71ab9c51b9c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4230757959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.4230757959
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3787792436
Short name T568
Test name
Test status
Simulation time 34102635555 ps
CPU time 132.06 seconds
Started Jan 10 01:22:00 PM PST 24
Finished Jan 10 01:24:40 PM PST 24
Peak memory 198828 kb
Host smart-df1bdbea-0811-42ce-b083-dfbbb61c70ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787792436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3787792436
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.40718264
Short name T574
Test name
Test status
Simulation time 1673382487 ps
CPU time 69.95 seconds
Started Jan 10 01:21:56 PM PST 24
Finished Jan 10 01:23:36 PM PST 24
Peak memory 198740 kb
Host smart-7f415dce-2916-478f-9cf0-41a5a17607ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40718264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.40718264
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.4218773057
Short name T802
Test name
Test status
Simulation time 1031245853 ps
CPU time 3.83 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:22:31 PM PST 24
Peak memory 198720 kb
Host smart-f364bc62-50c4-4245-b55c-b1552d117a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218773057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.4218773057
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2114205184
Short name T678
Test name
Test status
Simulation time 16803604463 ps
CPU time 370.73 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:28:38 PM PST 24
Peak memory 214940 kb
Host smart-8bd2a9e2-49c5-40a6-8cb8-3535831e173b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114205184 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2114205184
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.3531416205
Short name T746
Test name
Test status
Simulation time 41915437499 ps
CPU time 746.21 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:34:52 PM PST 24
Peak memory 215208 kb
Host smart-6b2eac1f-e0c0-464e-a6ee-e5d2290fbb8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531416205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.3531416205
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1866248096
Short name T608
Test name
Test status
Simulation time 123349596 ps
CPU time 1.14 seconds
Started Jan 10 01:21:58 PM PST 24
Finished Jan 10 01:22:27 PM PST 24
Peak memory 196352 kb
Host smart-fa011757-f69d-412d-968c-cccbad73948c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866248096 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1866248096
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3049978022
Short name T559
Test name
Test status
Simulation time 9224491179 ps
CPU time 438.5 seconds
Started Jan 10 01:21:53 PM PST 24
Finished Jan 10 01:29:41 PM PST 24
Peak memory 198844 kb
Host smart-caeff427-e734-4887-977e-b4811af8e2fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049978022 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.3049978022
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3899427342
Short name T436
Test name
Test status
Simulation time 3066758460 ps
CPU time 52.38 seconds
Started Jan 10 01:21:52 PM PST 24
Finished Jan 10 01:23:14 PM PST 24
Peak memory 198824 kb
Host smart-84ecd07b-1bdf-40d5-b901-fe9f7a46258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899427342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3899427342
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1822710749
Short name T318
Test name
Test status
Simulation time 22743689 ps
CPU time 0.57 seconds
Started Jan 10 01:21:52 PM PST 24
Finished Jan 10 01:22:22 PM PST 24
Peak memory 193184 kb
Host smart-92ada24e-348b-4ebd-9e5f-c614f9c5c654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822710749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1822710749
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2883535071
Short name T664
Test name
Test status
Simulation time 2145061463 ps
CPU time 34.94 seconds
Started Jan 10 01:22:09 PM PST 24
Finished Jan 10 01:23:10 PM PST 24
Peak memory 228308 kb
Host smart-02818357-b0c1-425b-90ba-e29f10400ce1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883535071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2883535071
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.555818596
Short name T580
Test name
Test status
Simulation time 14822795100 ps
CPU time 44.66 seconds
Started Jan 10 01:22:02 PM PST 24
Finished Jan 10 01:23:14 PM PST 24
Peak memory 198900 kb
Host smart-d5fd78f5-640e-4614-a4fc-7b9087d6b66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555818596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.555818596
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1226083303
Short name T237
Test name
Test status
Simulation time 1910300446 ps
CPU time 95.21 seconds
Started Jan 10 01:22:09 PM PST 24
Finished Jan 10 01:24:10 PM PST 24
Peak memory 198664 kb
Host smart-ca73f49e-e18c-45af-822d-2120d9e8d75e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226083303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1226083303
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.162170544
Short name T348
Test name
Test status
Simulation time 2106450023 ps
CPU time 25.66 seconds
Started Jan 10 01:21:57 PM PST 24
Finished Jan 10 01:22:52 PM PST 24
Peak memory 198796 kb
Host smart-092fd0cf-f464-4908-82ee-ff3807d149e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162170544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.162170544
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2228141129
Short name T289
Test name
Test status
Simulation time 1191403167 ps
CPU time 58.62 seconds
Started Jan 10 01:22:09 PM PST 24
Finished Jan 10 01:23:33 PM PST 24
Peak memory 198828 kb
Host smart-6734d4da-e695-4a16-b2be-edb38d5cd8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228141129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2228141129
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2658669709
Short name T169
Test name
Test status
Simulation time 99640577 ps
CPU time 0.94 seconds
Started Jan 10 01:22:00 PM PST 24
Finished Jan 10 01:22:29 PM PST 24
Peak memory 197516 kb
Host smart-3c4383ab-85d2-42aa-ab09-17dec74a0daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658669709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2658669709
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3168714475
Short name T266
Test name
Test status
Simulation time 23490501493 ps
CPU time 1137.42 seconds
Started Jan 10 01:22:02 PM PST 24
Finished Jan 10 01:41:27 PM PST 24
Peak memory 198900 kb
Host smart-7b6059bd-d064-409d-9518-53d3fd229830
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168714475 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3168714475
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.823842870
Short name T255
Test name
Test status
Simulation time 91835128503 ps
CPU time 1574.87 seconds
Started Jan 10 01:22:02 PM PST 24
Finished Jan 10 01:48:44 PM PST 24
Peak memory 264464 kb
Host smart-01f37c8a-6f8e-4170-a18a-fc44ac447817
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823842870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.823842870
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1883072241
Short name T694
Test name
Test status
Simulation time 125620470 ps
CPU time 1.21 seconds
Started Jan 10 01:22:02 PM PST 24
Finished Jan 10 01:22:30 PM PST 24
Peak memory 197752 kb
Host smart-672f9c91-906c-44f3-991e-7b42984a15f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883072241 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1883072241
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.927608145
Short name T380
Test name
Test status
Simulation time 53179375093 ps
CPU time 436.04 seconds
Started Jan 10 01:22:09 PM PST 24
Finished Jan 10 01:29:51 PM PST 24
Peak memory 198816 kb
Host smart-b0db1308-a9ff-43c7-9766-929e594580eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927608145 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.hmac_test_sha_vectors.927608145
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.410956365
Short name T565
Test name
Test status
Simulation time 1177483454 ps
CPU time 15.11 seconds
Started Jan 10 01:22:09 PM PST 24
Finished Jan 10 01:22:50 PM PST 24
Peak memory 198760 kb
Host smart-7250e71a-29d3-407d-beb8-de9ecf76edf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410956365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.410956365
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.731762409
Short name T338
Test name
Test status
Simulation time 38092929 ps
CPU time 0.54 seconds
Started Jan 10 01:22:14 PM PST 24
Finished Jan 10 01:22:39 PM PST 24
Peak memory 193108 kb
Host smart-8229c5a7-02c7-4eab-9d73-55870433b2e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731762409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.731762409
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3504930251
Short name T292
Test name
Test status
Simulation time 3129884346 ps
CPU time 53.42 seconds
Started Jan 10 01:21:55 PM PST 24
Finished Jan 10 01:23:18 PM PST 24
Peak memory 224644 kb
Host smart-90e88440-75fe-47d1-a0c5-cbb7217c3db7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3504930251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3504930251
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3234366740
Short name T264
Test name
Test status
Simulation time 2113082524 ps
CPU time 29.77 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:23:11 PM PST 24
Peak memory 198728 kb
Host smart-923b01c1-b44d-413b-a05c-c862343c67af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234366740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3234366740
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.375664500
Short name T690
Test name
Test status
Simulation time 1544557184 ps
CPU time 40.82 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:23:22 PM PST 24
Peak memory 198796 kb
Host smart-0a59e831-49e3-4d53-b503-dfd008900f5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375664500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.375664500
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2163992926
Short name T496
Test name
Test status
Simulation time 3905781544 ps
CPU time 17.43 seconds
Started Jan 10 01:22:21 PM PST 24
Finished Jan 10 01:23:02 PM PST 24
Peak memory 198324 kb
Host smart-73eb5f7d-dddf-4661-9a24-b969a971c46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163992926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2163992926
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1090203408
Short name T799
Test name
Test status
Simulation time 26751719258 ps
CPU time 32.57 seconds
Started Jan 10 01:21:51 PM PST 24
Finished Jan 10 01:22:52 PM PST 24
Peak memory 198756 kb
Host smart-8d7ba7e4-9d0f-4c99-8400-57ea906fd3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090203408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1090203408
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3449533361
Short name T419
Test name
Test status
Simulation time 1677008459 ps
CPU time 1.83 seconds
Started Jan 10 01:21:57 PM PST 24
Finished Jan 10 01:22:28 PM PST 24
Peak memory 198612 kb
Host smart-388b0a4a-b24a-4015-bea5-8b59531e50a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449533361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3449533361
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1617634373
Short name T331
Test name
Test status
Simulation time 66097390527 ps
CPU time 236.57 seconds
Started Jan 10 01:22:14 PM PST 24
Finished Jan 10 01:26:35 PM PST 24
Peak memory 198780 kb
Host smart-0eff11c4-b400-455f-bd63-c1b3c70d39a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617634373 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1617634373
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.200240571
Short name T77
Test name
Test status
Simulation time 45453811770 ps
CPU time 669.1 seconds
Started Jan 10 01:22:21 PM PST 24
Finished Jan 10 01:33:53 PM PST 24
Peak memory 239840 kb
Host smart-f2b4f687-7f8b-445e-8e1e-b78de8f9107e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=200240571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.200240571
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3927567932
Short name T513
Test name
Test status
Simulation time 65362904 ps
CPU time 1.09 seconds
Started Jan 10 01:22:20 PM PST 24
Finished Jan 10 01:22:45 PM PST 24
Peak memory 197616 kb
Host smart-950d17fa-fe6d-4125-8ca5-08826709226b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927567932 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3927567932
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1607373855
Short name T654
Test name
Test status
Simulation time 114578445264 ps
CPU time 434.87 seconds
Started Jan 10 01:22:09 PM PST 24
Finished Jan 10 01:29:50 PM PST 24
Peak memory 198772 kb
Host smart-b5660db2-569e-4fa0-9d12-e6c687a66fa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607373855 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.1607373855
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1539182138
Short name T354
Test name
Test status
Simulation time 1749842881 ps
CPU time 29.21 seconds
Started Jan 10 01:22:24 PM PST 24
Finished Jan 10 01:23:15 PM PST 24
Peak memory 198740 kb
Host smart-4c86444f-f913-42b9-a9e1-fc0d6159a602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539182138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1539182138
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3486266964
Short name T745
Test name
Test status
Simulation time 26794877 ps
CPU time 0.55 seconds
Started Jan 10 01:22:15 PM PST 24
Finished Jan 10 01:22:41 PM PST 24
Peak memory 193132 kb
Host smart-123a97bc-8f1c-4214-b270-174dd253839e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486266964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3486266964
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2152832690
Short name T779
Test name
Test status
Simulation time 3346930312 ps
CPU time 27.16 seconds
Started Jan 10 01:22:23 PM PST 24
Finished Jan 10 01:23:13 PM PST 24
Peak memory 221404 kb
Host smart-36b4be25-1645-49b7-a732-2e44b0bef6f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152832690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2152832690
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3635893027
Short name T587
Test name
Test status
Simulation time 5121811956 ps
CPU time 57.01 seconds
Started Jan 10 01:22:21 PM PST 24
Finished Jan 10 01:23:42 PM PST 24
Peak memory 198848 kb
Host smart-93c20ae2-7f1f-4b64-a187-c08b51d096d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635893027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3635893027
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.4239739133
Short name T724
Test name
Test status
Simulation time 1270642609 ps
CPU time 59.75 seconds
Started Jan 10 01:22:16 PM PST 24
Finished Jan 10 01:23:41 PM PST 24
Peak memory 198772 kb
Host smart-d2d739b3-4f30-4e2a-9136-68ad02eae7b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239739133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4239739133
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3735613389
Short name T74
Test name
Test status
Simulation time 139306539252 ps
CPU time 173.74 seconds
Started Jan 10 01:22:20 PM PST 24
Finished Jan 10 01:25:37 PM PST 24
Peak memory 198892 kb
Host smart-7117ec8d-5fd2-40bc-af37-03f1eb4257a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735613389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3735613389
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.741361243
Short name T546
Test name
Test status
Simulation time 3169931098 ps
CPU time 79.62 seconds
Started Jan 10 01:22:18 PM PST 24
Finished Jan 10 01:24:00 PM PST 24
Peak memory 198840 kb
Host smart-13681c6e-8a09-49ce-b2de-83ca45caffd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741361243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.741361243
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3561100290
Short name T374
Test name
Test status
Simulation time 236396162 ps
CPU time 2.77 seconds
Started Jan 10 01:22:18 PM PST 24
Finished Jan 10 01:22:45 PM PST 24
Peak memory 198492 kb
Host smart-89a0c70b-2fc3-448d-9fa7-4b595c1c2a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561100290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3561100290
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2661157292
Short name T434
Test name
Test status
Simulation time 71682896157 ps
CPU time 790.18 seconds
Started Jan 10 01:22:16 PM PST 24
Finished Jan 10 01:35:51 PM PST 24
Peak memory 224472 kb
Host smart-614729e2-1840-4846-a64e-d3a2e40e5abc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661157292 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2661157292
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.789448492
Short name T137
Test name
Test status
Simulation time 251198436891 ps
CPU time 2596.98 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 02:05:58 PM PST 24
Peak memory 256964 kb
Host smart-7dae10fe-5564-4cad-a140-36a04bea586c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789448492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.789448492
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.4001285781
Short name T261
Test name
Test status
Simulation time 42087415 ps
CPU time 0.93 seconds
Started Jan 10 01:22:19 PM PST 24
Finished Jan 10 01:22:44 PM PST 24
Peak memory 196392 kb
Host smart-22fa5891-0a12-4e52-866b-f78fd1da9c35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001285781 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.4001285781
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2782637850
Short name T212
Test name
Test status
Simulation time 74279401282 ps
CPU time 412.73 seconds
Started Jan 10 01:22:16 PM PST 24
Finished Jan 10 01:29:34 PM PST 24
Peak memory 198748 kb
Host smart-5dc30086-f121-4a22-a921-249dbf78429a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782637850 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.2782637850
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2947484152
Short name T179
Test name
Test status
Simulation time 5669419508 ps
CPU time 66.46 seconds
Started Jan 10 01:22:16 PM PST 24
Finished Jan 10 01:23:47 PM PST 24
Peak memory 198744 kb
Host smart-49e26c13-5026-48a9-b817-bf8f3f9ec501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947484152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2947484152
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4167603481
Short name T691
Test name
Test status
Simulation time 149085173 ps
CPU time 0.57 seconds
Started Jan 10 01:22:19 PM PST 24
Finished Jan 10 01:22:44 PM PST 24
Peak memory 193200 kb
Host smart-72684208-3a4b-453d-89e7-59c6401be940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167603481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4167603481
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2011502639
Short name T657
Test name
Test status
Simulation time 382580039 ps
CPU time 3.05 seconds
Started Jan 10 01:22:21 PM PST 24
Finished Jan 10 01:22:47 PM PST 24
Peak memory 198804 kb
Host smart-f3e8ad70-73e8-45cf-8f50-a4bba89d0dec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011502639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2011502639
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3164318933
Short name T733
Test name
Test status
Simulation time 7053299904 ps
CPU time 23.28 seconds
Started Jan 10 01:22:21 PM PST 24
Finished Jan 10 01:23:07 PM PST 24
Peak memory 198864 kb
Host smart-f43c7eda-154c-47e2-87df-ee7cd04c6c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164318933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3164318933
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.944918824
Short name T707
Test name
Test status
Simulation time 743219793 ps
CPU time 9.05 seconds
Started Jan 10 01:22:15 PM PST 24
Finished Jan 10 01:22:50 PM PST 24
Peak memory 198816 kb
Host smart-916a07e9-c448-4d4b-8f47-219e1206d3ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944918824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.944918824
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1750459603
Short name T731
Test name
Test status
Simulation time 847660906 ps
CPU time 38.28 seconds
Started Jan 10 01:22:15 PM PST 24
Finished Jan 10 01:23:19 PM PST 24
Peak memory 198784 kb
Host smart-1fe985c8-ad1d-4124-abdf-fc89df7cadaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750459603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1750459603
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4102915300
Short name T367
Test name
Test status
Simulation time 3169964644 ps
CPU time 40.68 seconds
Started Jan 10 01:22:19 PM PST 24
Finished Jan 10 01:23:24 PM PST 24
Peak memory 198812 kb
Host smart-e268a10c-8154-41c5-9e4e-a4ba74ca0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102915300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4102915300
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.566344992
Short name T754
Test name
Test status
Simulation time 100443926 ps
CPU time 1.87 seconds
Started Jan 10 01:22:16 PM PST 24
Finished Jan 10 01:22:43 PM PST 24
Peak memory 198184 kb
Host smart-4f717c02-0a01-4da0-9f26-20ec74baa732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566344992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.566344992
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2256307861
Short name T437
Test name
Test status
Simulation time 22213324325 ps
CPU time 95.7 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:24:16 PM PST 24
Peak memory 198804 kb
Host smart-4cee0ab5-44a7-46ec-be30-58dfd1b312e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256307861 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2256307861
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.3875080612
Short name T776
Test name
Test status
Simulation time 64259193269 ps
CPU time 2343.54 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 02:01:45 PM PST 24
Peak memory 244340 kb
Host smart-8b1346a6-9669-4f30-978c-3200c4a65fe9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875080612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.3875080612
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2573805130
Short name T346
Test name
Test status
Simulation time 80737335 ps
CPU time 1.03 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:22:42 PM PST 24
Peak memory 195980 kb
Host smart-baa3572d-f152-429a-8071-06d82d6e898d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573805130 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2573805130
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2750546665
Short name T749
Test name
Test status
Simulation time 88459266658 ps
CPU time 496.84 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:30:58 PM PST 24
Peak memory 198844 kb
Host smart-b13cc5d0-1cee-4028-8d3f-d0823eb9ae8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750546665 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.2750546665
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3301935076
Short name T200
Test name
Test status
Simulation time 25938704828 ps
CPU time 63.93 seconds
Started Jan 10 01:22:20 PM PST 24
Finished Jan 10 01:23:48 PM PST 24
Peak memory 198868 kb
Host smart-873dd941-560f-4106-b84f-1d3ef01513d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301935076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3301935076
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3701446511
Short name T459
Test name
Test status
Simulation time 16092602 ps
CPU time 0.57 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:21:58 PM PST 24
Peak memory 193192 kb
Host smart-b0289555-9416-4571-b415-43160e400519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701446511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3701446511
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3417537907
Short name T734
Test name
Test status
Simulation time 730009043 ps
CPU time 25.18 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:22:14 PM PST 24
Peak memory 228488 kb
Host smart-6881d089-e4df-4592-acd9-ba616618da5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417537907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3417537907
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1741037273
Short name T771
Test name
Test status
Simulation time 1036426470 ps
CPU time 27.2 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:22:21 PM PST 24
Peak memory 198704 kb
Host smart-6c6504b7-750d-4302-be64-6521df1ea36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741037273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1741037273
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2531949000
Short name T13
Test name
Test status
Simulation time 752975828 ps
CPU time 20.4 seconds
Started Jan 10 01:21:30 PM PST 24
Finished Jan 10 01:22:08 PM PST 24
Peak memory 198760 kb
Host smart-bc275521-67ec-41dd-9cf9-55f0be82b944
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531949000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2531949000
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3903886573
Short name T160
Test name
Test status
Simulation time 16155416029 ps
CPU time 13.24 seconds
Started Jan 10 01:21:34 PM PST 24
Finished Jan 10 01:22:07 PM PST 24
Peak memory 198740 kb
Host smart-5b5d8394-fd23-4d1f-8a62-ea1b79563c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903886573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3903886573
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.4277094511
Short name T448
Test name
Test status
Simulation time 15606924534 ps
CPU time 65.92 seconds
Started Jan 10 01:21:34 PM PST 24
Finished Jan 10 01:22:59 PM PST 24
Peak memory 198836 kb
Host smart-0d792c76-5037-4a6c-ad97-60716f4033f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277094511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.4277094511
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2484274246
Short name T51
Test name
Test status
Simulation time 337716077 ps
CPU time 0.96 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:21:56 PM PST 24
Peak memory 217092 kb
Host smart-2dd69381-daf3-4d8a-9372-ea42c6dc0f03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484274246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2484274246
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.716182207
Short name T368
Test name
Test status
Simulation time 72145133 ps
CPU time 1.41 seconds
Started Jan 10 01:21:29 PM PST 24
Finished Jan 10 01:21:44 PM PST 24
Peak memory 198856 kb
Host smart-568afab5-68c7-412a-aa83-e77675bcfed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716182207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.716182207
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3862162274
Short name T454
Test name
Test status
Simulation time 355013929979 ps
CPU time 1073.5 seconds
Started Jan 10 01:21:28 PM PST 24
Finished Jan 10 01:39:35 PM PST 24
Peak memory 231576 kb
Host smart-1707ba24-80e4-4bf0-9c26-0dd81292ac9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862162274 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3862162274
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1641462978
Short name T601
Test name
Test status
Simulation time 737195189253 ps
CPU time 495.15 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:30:10 PM PST 24
Peak memory 225732 kb
Host smart-68c80610-dda6-49b4-a92c-c8d9e740d8b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1641462978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1641462978
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.4168317820
Short name T725
Test name
Test status
Simulation time 226408550 ps
CPU time 1.08 seconds
Started Jan 10 01:21:11 PM PST 24
Finished Jan 10 01:21:15 PM PST 24
Peak memory 197060 kb
Host smart-5e333f97-8f54-4354-a26f-bac350e350c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168317820 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.4168317820
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1743669142
Short name T700
Test name
Test status
Simulation time 25916721329 ps
CPU time 410.87 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:28:48 PM PST 24
Peak memory 198820 kb
Host smart-baf1f6f4-e35d-425a-a18d-0e054bce07cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743669142 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.1743669142
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2275970551
Short name T600
Test name
Test status
Simulation time 54095489403 ps
CPU time 55.75 seconds
Started Jan 10 01:21:32 PM PST 24
Finished Jan 10 01:22:48 PM PST 24
Peak memory 198824 kb
Host smart-945d7e78-37fe-4323-bb15-77b4bf551939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275970551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2275970551
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1053366317
Short name T47
Test name
Test status
Simulation time 14384777 ps
CPU time 0.6 seconds
Started Jan 10 01:22:20 PM PST 24
Finished Jan 10 01:22:44 PM PST 24
Peak memory 194056 kb
Host smart-a6b94b36-342d-4ea5-a3b7-a3c065d4c565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053366317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1053366317
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2343272027
Short name T711
Test name
Test status
Simulation time 1040640366 ps
CPU time 32.46 seconds
Started Jan 10 01:22:22 PM PST 24
Finished Jan 10 01:23:17 PM PST 24
Peak memory 215236 kb
Host smart-08fda587-2672-4b8f-9627-cf3f19645bc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2343272027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2343272027
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3664985963
Short name T340
Test name
Test status
Simulation time 2065007817 ps
CPU time 38.03 seconds
Started Jan 10 01:22:19 PM PST 24
Finished Jan 10 01:23:21 PM PST 24
Peak memory 198720 kb
Host smart-d9396022-65ab-405a-b686-72b15fbd3445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664985963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3664985963
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2709218306
Short name T656
Test name
Test status
Simulation time 1945343441 ps
CPU time 96.72 seconds
Started Jan 10 01:22:23 PM PST 24
Finished Jan 10 01:24:22 PM PST 24
Peak memory 198828 kb
Host smart-ae4cee48-06cb-4353-b73b-729609140079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709218306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2709218306
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1680339177
Short name T226
Test name
Test status
Simulation time 11521512716 ps
CPU time 35.12 seconds
Started Jan 10 01:22:15 PM PST 24
Finished Jan 10 01:23:16 PM PST 24
Peak memory 198716 kb
Host smart-92d711a1-529e-4dcd-8634-1ab994cf9a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680339177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1680339177
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1685394360
Short name T554
Test name
Test status
Simulation time 1226849123 ps
CPU time 59.2 seconds
Started Jan 10 01:22:19 PM PST 24
Finished Jan 10 01:23:42 PM PST 24
Peak memory 198712 kb
Host smart-08eb9bd6-f733-4efe-88d3-c2bff04a577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685394360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1685394360
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2999747017
Short name T644
Test name
Test status
Simulation time 28394929 ps
CPU time 0.81 seconds
Started Jan 10 01:22:15 PM PST 24
Finished Jan 10 01:22:41 PM PST 24
Peak memory 195872 kb
Host smart-79de5677-31df-4497-8505-65112ba3e4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999747017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2999747017
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.222197296
Short name T778
Test name
Test status
Simulation time 15929468088 ps
CPU time 772.94 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:35:34 PM PST 24
Peak memory 224488 kb
Host smart-4b2c2b6e-3785-4ec5-adc1-d2a5ab27d14f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222197296 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.222197296
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.3281787152
Short name T95
Test name
Test status
Simulation time 492501189176 ps
CPU time 1845.1 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:53:26 PM PST 24
Peak memory 261560 kb
Host smart-19ed934a-a075-41ae-93d7-32dd8bf390f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3281787152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.3281787152
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2840124701
Short name T225
Test name
Test status
Simulation time 103149114 ps
CPU time 0.95 seconds
Started Jan 10 01:22:22 PM PST 24
Finished Jan 10 01:22:46 PM PST 24
Peak memory 196208 kb
Host smart-d35c46f8-1286-42df-b87b-64fbe770faa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840124701 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2840124701
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1555990953
Short name T9
Test name
Test status
Simulation time 33771668665 ps
CPU time 401.62 seconds
Started Jan 10 01:22:19 PM PST 24
Finished Jan 10 01:29:24 PM PST 24
Peak memory 198804 kb
Host smart-869127d5-5a36-4bb4-bc0d-b735a7232f8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555990953 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.1555990953
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.4051205531
Short name T709
Test name
Test status
Simulation time 2970580905 ps
CPU time 48.61 seconds
Started Jan 10 01:22:07 PM PST 24
Finished Jan 10 01:23:22 PM PST 24
Peak memory 198804 kb
Host smart-54b56f59-870f-4944-a920-bd76b62e9389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051205531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.4051205531
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.4094114242
Short name T766
Test name
Test status
Simulation time 14656624 ps
CPU time 0.6 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:22:41 PM PST 24
Peak memory 194208 kb
Host smart-7df38077-3dba-4331-94a4-57091790f327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094114242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4094114242
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.4222709666
Short name T351
Test name
Test status
Simulation time 1368092166 ps
CPU time 11 seconds
Started Jan 10 01:22:16 PM PST 24
Finished Jan 10 01:22:52 PM PST 24
Peak memory 206884 kb
Host smart-178a3d18-7446-4bf7-adb9-293a0bbd9ab8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222709666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.4222709666
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.204005879
Short name T645
Test name
Test status
Simulation time 472816282 ps
CPU time 5.78 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:22:47 PM PST 24
Peak memory 198788 kb
Host smart-5a02231f-8ce8-43be-843e-eec5be5ca5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204005879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.204005879
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3166891479
Short name T373
Test name
Test status
Simulation time 6049055885 ps
CPU time 59.45 seconds
Started Jan 10 01:22:16 PM PST 24
Finished Jan 10 01:23:40 PM PST 24
Peak memory 198792 kb
Host smart-ba52ca69-ee4e-4c63-9152-f1bb5d23c73a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166891479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3166891479
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1864165694
Short name T624
Test name
Test status
Simulation time 8514238344 ps
CPU time 101.38 seconds
Started Jan 10 01:22:18 PM PST 24
Finished Jan 10 01:24:24 PM PST 24
Peak memory 198800 kb
Host smart-33a95641-50d1-4cd2-9348-5e63bc525d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864165694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1864165694
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3244095060
Short name T422
Test name
Test status
Simulation time 67519823694 ps
CPU time 120.72 seconds
Started Jan 10 01:22:21 PM PST 24
Finished Jan 10 01:24:45 PM PST 24
Peak memory 198840 kb
Host smart-7dd46fac-bb42-4695-8d28-166b20b8739b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244095060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3244095060
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4096624898
Short name T507
Test name
Test status
Simulation time 1240795922 ps
CPU time 3.69 seconds
Started Jan 10 01:22:19 PM PST 24
Finished Jan 10 01:22:47 PM PST 24
Peak memory 198780 kb
Host smart-e4856366-3ff3-4ace-841f-79ae508ff043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096624898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4096624898
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2920007450
Short name T428
Test name
Test status
Simulation time 30773461455 ps
CPU time 487.76 seconds
Started Jan 10 01:22:19 PM PST 24
Finished Jan 10 01:30:51 PM PST 24
Peak memory 223452 kb
Host smart-46223ee0-76cf-42b0-b508-f0fa82cae98a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920007450 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2920007450
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.3136489429
Short name T659
Test name
Test status
Simulation time 265081984932 ps
CPU time 2328.92 seconds
Started Jan 10 01:22:21 PM PST 24
Finished Jan 10 02:01:33 PM PST 24
Peak memory 248144 kb
Host smart-4799c885-0932-45df-a8f4-8f13823570c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3136489429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.3136489429
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3048132653
Short name T166
Test name
Test status
Simulation time 104759090 ps
CPU time 0.93 seconds
Started Jan 10 01:22:22 PM PST 24
Finished Jan 10 01:22:46 PM PST 24
Peak memory 196520 kb
Host smart-1478eba9-09a7-454b-8422-1a0a054efc93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048132653 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3048132653
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.861320425
Short name T492
Test name
Test status
Simulation time 13965792940 ps
CPU time 405.8 seconds
Started Jan 10 01:22:28 PM PST 24
Finished Jan 10 01:29:35 PM PST 24
Peak memory 198692 kb
Host smart-97e481a3-5e6a-4fa8-ad52-e4115dd097d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861320425 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.hmac_test_sha_vectors.861320425
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1473756902
Short name T324
Test name
Test status
Simulation time 1555401855 ps
CPU time 31.91 seconds
Started Jan 10 01:22:18 PM PST 24
Finished Jan 10 01:23:13 PM PST 24
Peak memory 198876 kb
Host smart-ca72d736-46db-4033-82e2-42d5a068e291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473756902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1473756902
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1019069596
Short name T316
Test name
Test status
Simulation time 30297861 ps
CPU time 0.58 seconds
Started Jan 10 01:22:30 PM PST 24
Finished Jan 10 01:22:51 PM PST 24
Peak memory 193104 kb
Host smart-c2dfd253-4112-4b67-ac03-6dae8bf5de7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019069596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1019069596
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3495961756
Short name T780
Test name
Test status
Simulation time 10936305219 ps
CPU time 36.9 seconds
Started Jan 10 01:22:23 PM PST 24
Finished Jan 10 01:23:22 PM PST 24
Peak memory 210036 kb
Host smart-786fb7ea-ee6e-43ff-bd77-b7832bbe2def
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3495961756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3495961756
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.435055912
Short name T480
Test name
Test status
Simulation time 2716348313 ps
CPU time 40.12 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:23:55 PM PST 24
Peak memory 198864 kb
Host smart-9ba9adb7-24af-422d-ab52-4b0e24f8e0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435055912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.435055912
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.636157774
Short name T191
Test name
Test status
Simulation time 3354860828 ps
CPU time 57.4 seconds
Started Jan 10 01:22:20 PM PST 24
Finished Jan 10 01:23:41 PM PST 24
Peak memory 198956 kb
Host smart-65527b57-fc45-46bf-b734-e0e1fa4142b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=636157774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.636157774
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1783241595
Short name T798
Test name
Test status
Simulation time 2585236742 ps
CPU time 127.76 seconds
Started Jan 10 01:22:46 PM PST 24
Finished Jan 10 01:25:12 PM PST 24
Peak memory 198820 kb
Host smart-27a7446b-2f59-435b-8a23-0a0be6a2fd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783241595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1783241595
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2319098481
Short name T60
Test name
Test status
Simulation time 11584901424 ps
CPU time 95.77 seconds
Started Jan 10 01:22:22 PM PST 24
Finished Jan 10 01:24:20 PM PST 24
Peak memory 198872 kb
Host smart-dd21d06e-6e9e-471b-a762-9c042b1c159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319098481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2319098481
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3882694475
Short name T545
Test name
Test status
Simulation time 2042562561 ps
CPU time 3.23 seconds
Started Jan 10 01:22:20 PM PST 24
Finished Jan 10 01:22:47 PM PST 24
Peak memory 198792 kb
Host smart-f3b960fb-f34e-4175-9f81-e72252806025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882694475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3882694475
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.52078930
Short name T569
Test name
Test status
Simulation time 66152028315 ps
CPU time 859.07 seconds
Started Jan 10 01:22:47 PM PST 24
Finished Jan 10 01:37:25 PM PST 24
Peak memory 239856 kb
Host smart-1021f53d-37f9-472c-a8f2-9e42606de46a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52078930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.52078930
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3817034785
Short name T265
Test name
Test status
Simulation time 107122298 ps
CPU time 1.12 seconds
Started Jan 10 01:22:23 PM PST 24
Finished Jan 10 01:22:47 PM PST 24
Peak memory 197192 kb
Host smart-be7975ad-3f70-4a14-bf5f-18206b5ae294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817034785 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3817034785
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3261066898
Short name T271
Test name
Test status
Simulation time 52991611644 ps
CPU time 343.69 seconds
Started Jan 10 01:22:23 PM PST 24
Finished Jan 10 01:28:29 PM PST 24
Peak memory 198812 kb
Host smart-e74d4bc5-ba24-41c1-acae-5af676891b6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261066898 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.3261066898
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2843993274
Short name T517
Test name
Test status
Simulation time 7805209454 ps
CPU time 47.09 seconds
Started Jan 10 01:22:25 PM PST 24
Finished Jan 10 01:23:34 PM PST 24
Peak memory 198876 kb
Host smart-c8a39af0-6bad-441e-b9b8-428e0c63691b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843993274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2843993274
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.50286225
Short name T350
Test name
Test status
Simulation time 13711845 ps
CPU time 0.55 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:23:20 PM PST 24
Peak memory 193128 kb
Host smart-a8b3fa94-3cf5-4a90-99c4-15909fb5f4a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50286225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.50286225
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4135336835
Short name T378
Test name
Test status
Simulation time 967164849 ps
CPU time 26.7 seconds
Started Jan 10 01:23:03 PM PST 24
Finished Jan 10 01:23:48 PM PST 24
Peak memory 225976 kb
Host smart-975cdbf2-fbcf-46fd-989a-64cfbb0844d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135336835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4135336835
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2514968354
Short name T233
Test name
Test status
Simulation time 6903841401 ps
CPU time 12.05 seconds
Started Jan 10 01:22:46 PM PST 24
Finished Jan 10 01:23:17 PM PST 24
Peak memory 198772 kb
Host smart-4752cf0f-18a3-455c-a39a-ec848bd99fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514968354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2514968354
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.197074787
Short name T41
Test name
Test status
Simulation time 5133268586 ps
CPU time 76.5 seconds
Started Jan 10 01:22:46 PM PST 24
Finished Jan 10 01:24:22 PM PST 24
Peak memory 198840 kb
Host smart-fa5a201e-7d5c-4860-a35d-fe78abced562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=197074787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.197074787
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2007271400
Short name T708
Test name
Test status
Simulation time 3871968920 ps
CPU time 58.21 seconds
Started Jan 10 01:22:34 PM PST 24
Finished Jan 10 01:23:51 PM PST 24
Peak memory 198872 kb
Host smart-7817402e-baa0-44b7-9612-c362ffb5b2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007271400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2007271400
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1422033040
Short name T500
Test name
Test status
Simulation time 5042286383 ps
CPU time 65.09 seconds
Started Jan 10 01:22:26 PM PST 24
Finished Jan 10 01:23:52 PM PST 24
Peak memory 198916 kb
Host smart-7a050726-3a97-45cd-951d-6c3718038a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422033040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1422033040
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.874799339
Short name T555
Test name
Test status
Simulation time 173324308 ps
CPU time 1.34 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:23:04 PM PST 24
Peak memory 198628 kb
Host smart-a58a43cb-03a5-4ce9-b962-9879c130bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874799339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.874799339
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1325155023
Short name T482
Test name
Test status
Simulation time 7633077369 ps
CPU time 331.77 seconds
Started Jan 10 01:22:46 PM PST 24
Finished Jan 10 01:28:36 PM PST 24
Peak memory 215224 kb
Host smart-93c41673-8935-44f2-9c42-26b9ec487419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325155023 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1325155023
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.511566485
Short name T642
Test name
Test status
Simulation time 33220695069 ps
CPU time 164.29 seconds
Started Jan 10 01:22:49 PM PST 24
Finished Jan 10 01:25:51 PM PST 24
Peak memory 225600 kb
Host smart-b6e91098-524d-4fc4-bf9b-3347763d5850
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=511566485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.511566485
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1842173186
Short name T539
Test name
Test status
Simulation time 27960090 ps
CPU time 0.89 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:23:20 PM PST 24
Peak memory 195900 kb
Host smart-ff0a175a-5ea9-4be2-8518-5c6d6611a806
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842173186 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1842173186
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.620124004
Short name T641
Test name
Test status
Simulation time 195583891518 ps
CPU time 482.17 seconds
Started Jan 10 01:22:33 PM PST 24
Finished Jan 10 01:30:54 PM PST 24
Peak memory 198840 kb
Host smart-6cf94b19-216d-41c6-9b93-4943deef630a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620124004 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.hmac_test_sha_vectors.620124004
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1460983990
Short name T165
Test name
Test status
Simulation time 7844461558 ps
CPU time 25.22 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:23:44 PM PST 24
Peak memory 198928 kb
Host smart-be8805e2-8913-4eb7-893e-4494295d95d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460983990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1460983990
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3449491868
Short name T498
Test name
Test status
Simulation time 11478558 ps
CPU time 0.54 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:23:28 PM PST 24
Peak memory 193164 kb
Host smart-d0876922-9931-4381-ba75-55db0cdbbe9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449491868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3449491868
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4054349729
Short name T532
Test name
Test status
Simulation time 1829665842 ps
CPU time 14.32 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 01:23:30 PM PST 24
Peak memory 198804 kb
Host smart-35c3a120-b1d2-4184-b562-a801806873c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054349729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4054349729
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1697441961
Short name T633
Test name
Test status
Simulation time 1389482895 ps
CPU time 24.08 seconds
Started Jan 10 01:22:47 PM PST 24
Finished Jan 10 01:23:30 PM PST 24
Peak memory 198768 kb
Host smart-860cb30a-c11a-4e5d-a040-b076ad54f1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697441961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1697441961
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2574730685
Short name T529
Test name
Test status
Simulation time 8131519883 ps
CPU time 113.38 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:25:12 PM PST 24
Peak memory 198836 kb
Host smart-854be48e-b61a-4f1e-9bf9-802fff226fbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574730685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2574730685
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3599632224
Short name T162
Test name
Test status
Simulation time 3226528514 ps
CPU time 157.26 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:25:52 PM PST 24
Peak memory 198868 kb
Host smart-1b34dae9-8e91-4569-91c8-92f17885d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599632224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3599632224
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4020265415
Short name T605
Test name
Test status
Simulation time 1958166599 ps
CPU time 13.9 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 01:23:30 PM PST 24
Peak memory 198768 kb
Host smart-583fae62-cc4d-4a9b-96e7-b6eec87edf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020265415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4020265415
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.4105823719
Short name T570
Test name
Test status
Simulation time 2191774281 ps
CPU time 1.61 seconds
Started Jan 10 01:22:47 PM PST 24
Finished Jan 10 01:23:07 PM PST 24
Peak memory 198548 kb
Host smart-eeb57697-4657-4d02-8bd6-04730d8a9f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105823719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.4105823719
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3096617223
Short name T680
Test name
Test status
Simulation time 10358137300 ps
CPU time 470.77 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:31:18 PM PST 24
Peak memory 198820 kb
Host smart-f3e6779e-1de5-4791-b01a-c81d9d87d601
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096617223 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3096617223
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.1115646878
Short name T274
Test name
Test status
Simulation time 37070625996 ps
CPU time 918.05 seconds
Started Jan 10 01:23:17 PM PST 24
Finished Jan 10 01:38:49 PM PST 24
Peak memory 215340 kb
Host smart-f107b1c9-a000-40e3-81a6-1aec7aa6961a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115646878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.1115646878
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.643527746
Short name T549
Test name
Test status
Simulation time 109049306 ps
CPU time 0.92 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:23:28 PM PST 24
Peak memory 195932 kb
Host smart-f679b91d-b59d-472c-bb89-a7530ef6dace
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643527746 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.643527746
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.234588751
Short name T241
Test name
Test status
Simulation time 45924152295 ps
CPU time 482.33 seconds
Started Jan 10 01:23:04 PM PST 24
Finished Jan 10 01:31:24 PM PST 24
Peak memory 198820 kb
Host smart-97e73a36-a367-446a-a013-9f8b73146963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234588751 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.hmac_test_sha_vectors.234588751
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2413681315
Short name T783
Test name
Test status
Simulation time 5123277829 ps
CPU time 85.24 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:24:52 PM PST 24
Peak memory 198904 kb
Host smart-79ff8285-ebc1-4d77-8cab-acf956de3620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413681315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2413681315
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1507620088
Short name T282
Test name
Test status
Simulation time 19889156 ps
CPU time 0.6 seconds
Started Jan 10 01:22:18 PM PST 24
Finished Jan 10 01:22:41 PM PST 24
Peak memory 193088 kb
Host smart-f1f771c2-2a6a-413a-93ae-3f233985dcdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507620088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1507620088
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.339294549
Short name T504
Test name
Test status
Simulation time 809792809 ps
CPU time 26.19 seconds
Started Jan 10 01:23:32 PM PST 24
Finished Jan 10 01:24:03 PM PST 24
Peak memory 215116 kb
Host smart-f9cf5c6f-b6f9-40a0-80c0-a824d392fec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339294549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.339294549
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.4036482132
Short name T413
Test name
Test status
Simulation time 1251664815 ps
CPU time 17.2 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:23:44 PM PST 24
Peak memory 198680 kb
Host smart-57c1a3a6-5dd7-4fc3-a487-1eac59992ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036482132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.4036482132
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.996770345
Short name T118
Test name
Test status
Simulation time 6218608833 ps
CPU time 76.32 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:24:43 PM PST 24
Peak memory 199028 kb
Host smart-01a50716-03c4-4820-8c8d-dfd8983e25a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996770345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.996770345
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3317916816
Short name T495
Test name
Test status
Simulation time 8536987776 ps
CPU time 136.4 seconds
Started Jan 10 01:23:07 PM PST 24
Finished Jan 10 01:25:41 PM PST 24
Peak memory 198800 kb
Host smart-8509742e-d62a-42f4-bb8b-b95f601eebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317916816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3317916816
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.815569446
Short name T750
Test name
Test status
Simulation time 392434122 ps
CPU time 5.18 seconds
Started Jan 10 01:23:39 PM PST 24
Finished Jan 10 01:23:52 PM PST 24
Peak memory 198700 kb
Host smart-d37d188b-e3f2-4316-8ef5-f4d862c85f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815569446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.815569446
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.527008245
Short name T558
Test name
Test status
Simulation time 63252690 ps
CPU time 0.75 seconds
Started Jan 10 01:23:10 PM PST 24
Finished Jan 10 01:23:29 PM PST 24
Peak memory 194732 kb
Host smart-779cb02b-c74f-41b8-9a76-0ee36d482046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527008245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.527008245
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.808807848
Short name T658
Test name
Test status
Simulation time 61157469734 ps
CPU time 2358.87 seconds
Started Jan 10 01:22:16 PM PST 24
Finished Jan 10 02:02:00 PM PST 24
Peak memory 198808 kb
Host smart-3484315a-c59f-475c-96a2-8b023eaf75f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808807848 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.808807848
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.1346192825
Short name T398
Test name
Test status
Simulation time 72870693292 ps
CPU time 1352.08 seconds
Started Jan 10 01:22:18 PM PST 24
Finished Jan 10 01:45:15 PM PST 24
Peak memory 248140 kb
Host smart-be4c6003-fbd2-4f83-b922-0be4fc76c9b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346192825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.1346192825
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1031130858
Short name T210
Test name
Test status
Simulation time 27317953 ps
CPU time 0.92 seconds
Started Jan 10 01:22:19 PM PST 24
Finished Jan 10 01:22:44 PM PST 24
Peak memory 197060 kb
Host smart-358e4f71-9c3a-46c0-b48d-2229a937f2fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031130858 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1031130858
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.174841681
Short name T515
Test name
Test status
Simulation time 8743692665 ps
CPU time 428.48 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:29:49 PM PST 24
Peak memory 198772 kb
Host smart-1e7a14a4-8e90-4cfc-b454-f72807dc827d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174841681 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.hmac_test_sha_vectors.174841681
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.4226596652
Short name T333
Test name
Test status
Simulation time 8149902857 ps
CPU time 58.54 seconds
Started Jan 10 01:23:07 PM PST 24
Finished Jan 10 01:24:24 PM PST 24
Peak memory 198804 kb
Host smart-e31e154a-a62c-4a87-8017-99706585f8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226596652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4226596652
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4271630340
Short name T3
Test name
Test status
Simulation time 14526113 ps
CPU time 0.61 seconds
Started Jan 10 01:22:25 PM PST 24
Finished Jan 10 01:22:47 PM PST 24
Peak memory 193148 kb
Host smart-9a06f8e0-cf71-4446-aab9-da3aa317b684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271630340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4271630340
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3017625644
Short name T521
Test name
Test status
Simulation time 512278833 ps
CPU time 8.5 seconds
Started Jan 10 01:22:24 PM PST 24
Finished Jan 10 01:22:54 PM PST 24
Peak memory 206844 kb
Host smart-37541122-6194-42fe-9f76-0e6bf8aab756
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017625644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3017625644
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1906075830
Short name T625
Test name
Test status
Simulation time 10998030868 ps
CPU time 32.7 seconds
Started Jan 10 01:22:14 PM PST 24
Finished Jan 10 01:23:12 PM PST 24
Peak memory 198792 kb
Host smart-b27ec3a5-8545-4cdf-8a11-d90e1f407938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906075830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1906075830
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2440570849
Short name T760
Test name
Test status
Simulation time 1217713404 ps
CPU time 14.96 seconds
Started Jan 10 01:22:17 PM PST 24
Finished Jan 10 01:22:56 PM PST 24
Peak memory 198892 kb
Host smart-6d3dd5be-cf95-4b74-950d-222f2dabbb3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440570849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2440570849
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1988593332
Short name T287
Test name
Test status
Simulation time 3764754476 ps
CPU time 42.89 seconds
Started Jan 10 01:22:19 PM PST 24
Finished Jan 10 01:23:26 PM PST 24
Peak memory 198904 kb
Host smart-4c2737a1-08ba-4fc1-92ae-6549b83c227f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988593332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1988593332
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2757397592
Short name T172
Test name
Test status
Simulation time 4018735754 ps
CPU time 66.89 seconds
Started Jan 10 01:22:16 PM PST 24
Finished Jan 10 01:23:50 PM PST 24
Peak memory 198900 kb
Host smart-bc6539b5-6bb2-4f62-855f-9bc924e40311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757397592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2757397592
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2430573999
Short name T330
Test name
Test status
Simulation time 146292875 ps
CPU time 3.14 seconds
Started Jan 10 01:22:29 PM PST 24
Finished Jan 10 01:22:53 PM PST 24
Peak memory 198632 kb
Host smart-a74d8b9e-512c-417c-aa07-b6967741bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430573999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2430573999
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1649958516
Short name T671
Test name
Test status
Simulation time 57872433795 ps
CPU time 934.94 seconds
Started Jan 10 01:22:40 PM PST 24
Finished Jan 10 01:38:37 PM PST 24
Peak memory 215264 kb
Host smart-89176391-51ea-45c7-8994-6ce2aaf67419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649958516 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1649958516
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.1182366600
Short name T621
Test name
Test status
Simulation time 486747194169 ps
CPU time 1010.61 seconds
Started Jan 10 01:22:29 PM PST 24
Finished Jan 10 01:39:41 PM PST 24
Peak memory 255596 kb
Host smart-295ea943-390a-461d-9025-8cf4a36e4e33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182366600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.1182366600
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1389715682
Short name T273
Test name
Test status
Simulation time 89154736 ps
CPU time 0.88 seconds
Started Jan 10 01:22:25 PM PST 24
Finished Jan 10 01:22:47 PM PST 24
Peak memory 195916 kb
Host smart-90360b56-3e6e-4d0c-9081-1f9f8314ea92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389715682 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1389715682
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.616178838
Short name T701
Test name
Test status
Simulation time 79774982679 ps
CPU time 439.07 seconds
Started Jan 10 01:22:48 PM PST 24
Finished Jan 10 01:30:25 PM PST 24
Peak memory 198752 kb
Host smart-b0b7f763-f239-425f-ab7f-470d913634c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616178838 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_sha_vectors.616178838
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.85544364
Short name T161
Test name
Test status
Simulation time 3415293321 ps
CPU time 32.27 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:23:49 PM PST 24
Peak memory 198796 kb
Host smart-85a54f13-96bc-4f5d-b95b-cb7bb97d415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85544364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.85544364
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1397673944
Short name T312
Test name
Test status
Simulation time 15464718 ps
CPU time 0.58 seconds
Started Jan 10 01:22:49 PM PST 24
Finished Jan 10 01:23:08 PM PST 24
Peak memory 193940 kb
Host smart-616c30dd-cb7b-4285-befa-4037a19d80d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397673944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1397673944
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3003931823
Short name T355
Test name
Test status
Simulation time 955651459 ps
CPU time 14.87 seconds
Started Jan 10 01:22:27 PM PST 24
Finished Jan 10 01:23:02 PM PST 24
Peak memory 208080 kb
Host smart-38618680-8584-4b77-b8d5-60f5a04c6744
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003931823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3003931823
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3666724373
Short name T2
Test name
Test status
Simulation time 124191025 ps
CPU time 2.49 seconds
Started Jan 10 01:22:31 PM PST 24
Finished Jan 10 01:22:54 PM PST 24
Peak memory 198676 kb
Host smart-4a8932e7-1e6f-4f75-bb75-79ff1299aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666724373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3666724373
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.250179691
Short name T615
Test name
Test status
Simulation time 908597423 ps
CPU time 45.38 seconds
Started Jan 10 01:22:41 PM PST 24
Finished Jan 10 01:23:48 PM PST 24
Peak memory 198816 kb
Host smart-cf12c2df-7e08-4f73-97cd-640961044def
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250179691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.250179691
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.365970638
Short name T263
Test name
Test status
Simulation time 14785297650 ps
CPU time 178.29 seconds
Started Jan 10 01:22:28 PM PST 24
Finished Jan 10 01:25:47 PM PST 24
Peak memory 198872 kb
Host smart-36f3e54b-1fd5-47c7-8f7e-bab700f916e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365970638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.365970638
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3812244437
Short name T637
Test name
Test status
Simulation time 60080225 ps
CPU time 3.26 seconds
Started Jan 10 01:22:49 PM PST 24
Finished Jan 10 01:23:10 PM PST 24
Peak memory 198136 kb
Host smart-9b8ca0d0-998c-4cb3-99d7-fcf69fd12d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812244437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3812244437
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3580404664
Short name T663
Test name
Test status
Simulation time 567477447 ps
CPU time 4.4 seconds
Started Jan 10 01:22:32 PM PST 24
Finished Jan 10 01:22:57 PM PST 24
Peak memory 198556 kb
Host smart-45406112-a950-442a-9769-c392db7f0ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580404664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3580404664
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2418400501
Short name T786
Test name
Test status
Simulation time 306169145958 ps
CPU time 995.94 seconds
Started Jan 10 01:22:30 PM PST 24
Finished Jan 10 01:39:27 PM PST 24
Peak memory 239904 kb
Host smart-d5fb8a33-03a8-43a2-b773-ed42d9e73ce5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418400501 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2418400501
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.2006858305
Short name T525
Test name
Test status
Simulation time 323969773122 ps
CPU time 1456.45 seconds
Started Jan 10 01:22:16 PM PST 24
Finished Jan 10 01:46:57 PM PST 24
Peak memory 264336 kb
Host smart-f3ff0720-7e64-432e-99bc-5eee30ae3bee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006858305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all_with_rand_reset.2006858305
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2688985494
Short name T547
Test name
Test status
Simulation time 114815129 ps
CPU time 0.88 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:23:04 PM PST 24
Peak memory 195884 kb
Host smart-5b2735dd-c8f8-48e7-a7ac-2c9a06594560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688985494 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.2688985494
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1552890371
Short name T567
Test name
Test status
Simulation time 68752135997 ps
CPU time 437.46 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:30:21 PM PST 24
Peak memory 198748 kb
Host smart-24cb9b6b-fc14-4bdd-93c8-3533920bc539
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552890371 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.1552890371
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2354276270
Short name T369
Test name
Test status
Simulation time 5827998572 ps
CPU time 77.94 seconds
Started Jan 10 01:22:32 PM PST 24
Finished Jan 10 01:24:10 PM PST 24
Peak memory 198844 kb
Host smart-a26869db-8fd7-4fd6-8f70-47b820ca0107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354276270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2354276270
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3930833032
Short name T460
Test name
Test status
Simulation time 12571097 ps
CPU time 0.59 seconds
Started Jan 10 01:22:41 PM PST 24
Finished Jan 10 01:23:03 PM PST 24
Peak memory 193140 kb
Host smart-06ad85ee-f469-403e-ae2b-2eb626b2afc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930833032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3930833032
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1457581468
Short name T356
Test name
Test status
Simulation time 6007461018 ps
CPU time 41.64 seconds
Started Jan 10 01:22:30 PM PST 24
Finished Jan 10 01:23:32 PM PST 24
Peak memory 226372 kb
Host smart-717ff00a-60d4-4e54-ad11-37be4686f0ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1457581468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1457581468
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3710820185
Short name T611
Test name
Test status
Simulation time 2926282288 ps
CPU time 26.96 seconds
Started Jan 10 01:22:35 PM PST 24
Finished Jan 10 01:23:20 PM PST 24
Peak memory 198884 kb
Host smart-41a36876-a058-4c39-b0d9-81ad0d6374e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710820185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3710820185
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4242904727
Short name T222
Test name
Test status
Simulation time 641179116 ps
CPU time 8.12 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:23:25 PM PST 24
Peak memory 198524 kb
Host smart-949172a2-1629-4d03-a29b-25b8fb4d13b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4242904727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4242904727
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3036142955
Short name T89
Test name
Test status
Simulation time 4048829275 ps
CPU time 23.45 seconds
Started Jan 10 01:22:27 PM PST 24
Finished Jan 10 01:23:11 PM PST 24
Peak memory 198856 kb
Host smart-50072b29-7f1e-47a8-94af-8f7a5a2c7d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036142955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3036142955
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3575368863
Short name T674
Test name
Test status
Simulation time 3999643221 ps
CPU time 40.62 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 01:23:56 PM PST 24
Peak memory 198744 kb
Host smart-c810bf24-2697-4070-b4fb-62c8399348fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575368863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3575368863
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1413909654
Short name T742
Test name
Test status
Simulation time 271544614 ps
CPU time 1.33 seconds
Started Jan 10 01:22:41 PM PST 24
Finished Jan 10 01:23:04 PM PST 24
Peak memory 198032 kb
Host smart-7febff7e-bef6-477f-a25b-44b9ecaec40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413909654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1413909654
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3589224060
Short name T485
Test name
Test status
Simulation time 28115488322 ps
CPU time 337.52 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:28:41 PM PST 24
Peak memory 207068 kb
Host smart-9980b7ac-44a8-4c21-876a-c1ffb4cc6bbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589224060 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3589224060
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.314993521
Short name T384
Test name
Test status
Simulation time 142325639014 ps
CPU time 2967.03 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 02:12:45 PM PST 24
Peak memory 248080 kb
Host smart-a408677e-7d9c-4fb0-b46c-580340addc39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=314993521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.314993521
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3886254424
Short name T389
Test name
Test status
Simulation time 128784586 ps
CPU time 0.96 seconds
Started Jan 10 01:22:27 PM PST 24
Finished Jan 10 01:22:48 PM PST 24
Peak memory 197228 kb
Host smart-77e49f37-b5b0-45bf-b88d-96e42096cf0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886254424 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3886254424
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2127233660
Short name T759
Test name
Test status
Simulation time 18674331151 ps
CPU time 388.74 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 01:29:44 PM PST 24
Peak memory 198768 kb
Host smart-86dfcc67-9221-481f-aef1-57759172d0c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127233660 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.2127233660
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1598578985
Short name T670
Test name
Test status
Simulation time 62396781943 ps
CPU time 53.19 seconds
Started Jan 10 01:22:29 PM PST 24
Finished Jan 10 01:23:43 PM PST 24
Peak memory 198800 kb
Host smart-5eb0ef07-fb90-48f6-8872-d5400b0083a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598578985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1598578985
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.916694210
Short name T278
Test name
Test status
Simulation time 56572683 ps
CPU time 0.55 seconds
Started Jan 10 01:22:57 PM PST 24
Finished Jan 10 01:23:13 PM PST 24
Peak memory 193052 kb
Host smart-9fd2bcd4-2787-4178-bc73-310fccea84f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916694210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.916694210
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3893022946
Short name T594
Test name
Test status
Simulation time 1661543472 ps
CPU time 25.96 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:23:43 PM PST 24
Peak memory 220340 kb
Host smart-51ce9b10-926a-4ad3-81be-d8c934de71b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893022946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3893022946
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.548693782
Short name T416
Test name
Test status
Simulation time 1158191619 ps
CPU time 25.2 seconds
Started Jan 10 01:22:45 PM PST 24
Finished Jan 10 01:23:30 PM PST 24
Peak memory 198688 kb
Host smart-5a6fc20a-68c1-4df3-b5b2-803d2a1c84d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548693782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.548693782
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3163489042
Short name T781
Test name
Test status
Simulation time 2208668425 ps
CPU time 103.88 seconds
Started Jan 10 01:22:29 PM PST 24
Finished Jan 10 01:24:33 PM PST 24
Peak memory 198696 kb
Host smart-a3e17f30-fcb0-4a9b-b7f0-f140bbc7dcc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163489042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3163489042
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1376596356
Short name T619
Test name
Test status
Simulation time 3066119634 ps
CPU time 20.1 seconds
Started Jan 10 01:22:27 PM PST 24
Finished Jan 10 01:23:09 PM PST 24
Peak memory 198884 kb
Host smart-e5a185de-29d7-4e73-bc86-58c393429991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376596356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1376596356
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3640404970
Short name T588
Test name
Test status
Simulation time 14087781344 ps
CPU time 84.01 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:24:27 PM PST 24
Peak memory 198812 kb
Host smart-253998ea-667b-4518-b400-22742ced6f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640404970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3640404970
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3257587676
Short name T173
Test name
Test status
Simulation time 285169034 ps
CPU time 3.45 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:23:07 PM PST 24
Peak memory 198744 kb
Host smart-8cbdfbe2-4825-427d-9097-1c9320f8a6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257587676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3257587676
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.2007866387
Short name T475
Test name
Test status
Simulation time 404970760964 ps
CPU time 1796.13 seconds
Started Jan 10 01:22:31 PM PST 24
Finished Jan 10 01:52:48 PM PST 24
Peak memory 249268 kb
Host smart-9c33e876-a14d-4345-a106-1d7e20317cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2007866387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.2007866387
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.66336327
Short name T684
Test name
Test status
Simulation time 42584451 ps
CPU time 0.96 seconds
Started Jan 10 01:22:29 PM PST 24
Finished Jan 10 01:22:50 PM PST 24
Peak memory 196512 kb
Host smart-23e517b9-1536-4f23-8ff7-eaef9e089ca4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66336327 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.hmac_test_hmac_vectors.66336327
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.973724746
Short name T697
Test name
Test status
Simulation time 48572028126 ps
CPU time 377.29 seconds
Started Jan 10 01:22:27 PM PST 24
Finished Jan 10 01:29:05 PM PST 24
Peak memory 198840 kb
Host smart-46e418cb-b1a4-4730-a98c-2817498c07c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973724746 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.hmac_test_sha_vectors.973724746
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2016219041
Short name T717
Test name
Test status
Simulation time 4094840825 ps
CPU time 50.77 seconds
Started Jan 10 01:22:46 PM PST 24
Finished Jan 10 01:23:56 PM PST 24
Peak memory 198852 kb
Host smart-6b5e377f-a0e8-4619-b41b-476085a685e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016219041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2016219041
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1633694859
Short name T499
Test name
Test status
Simulation time 15130123 ps
CPU time 0.62 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:05 PM PST 24
Peak memory 193168 kb
Host smart-64c9c9a4-f1de-47e9-b9b6-38683645640f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633694859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1633694859
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.578972325
Short name T42
Test name
Test status
Simulation time 3044184054 ps
CPU time 28.91 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:22:24 PM PST 24
Peak memory 215256 kb
Host smart-a217838d-a211-487e-94f9-812da3706045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578972325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.578972325
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2349591011
Short name T537
Test name
Test status
Simulation time 1199838273 ps
CPU time 28.75 seconds
Started Jan 10 01:21:35 PM PST 24
Finished Jan 10 01:22:22 PM PST 24
Peak memory 198852 kb
Host smart-7359c3e9-e8a7-454b-908a-370f4fe169e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349591011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2349591011
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2110610325
Short name T234
Test name
Test status
Simulation time 1040842576 ps
CPU time 13.56 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:22:11 PM PST 24
Peak memory 198796 kb
Host smart-e4cc9c3e-a59b-43d6-a028-cf576137d87e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110610325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2110610325
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.201289582
Short name T490
Test name
Test status
Simulation time 5790923278 ps
CPU time 85.9 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:23:23 PM PST 24
Peak memory 198716 kb
Host smart-6bf76068-f52a-499f-9801-7be11c949feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201289582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.201289582
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3449760363
Short name T439
Test name
Test status
Simulation time 3436083367 ps
CPU time 58.81 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:22:53 PM PST 24
Peak memory 198584 kb
Host smart-198849a3-7311-4317-8798-36aa64e3e2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449760363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3449760363
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3025272503
Short name T50
Test name
Test status
Simulation time 59686101 ps
CPU time 0.93 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:21:59 PM PST 24
Peak memory 217048 kb
Host smart-9cf0f868-af28-44f7-b4e5-b10b26fa3d51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025272503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3025272503
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1303632238
Short name T651
Test name
Test status
Simulation time 2839874880 ps
CPU time 4.57 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:22:00 PM PST 24
Peak memory 198872 kb
Host smart-451e6913-0dc9-4a2c-88a3-63b107fe0623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303632238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1303632238
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3665493696
Short name T524
Test name
Test status
Simulation time 21723465021 ps
CPU time 1016.09 seconds
Started Jan 10 01:21:47 PM PST 24
Finished Jan 10 01:39:08 PM PST 24
Peak memory 227288 kb
Host smart-b01a771a-ffbf-45b3-9fb4-791ba50cf6c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665493696 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3665493696
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2047531476
Short name T445
Test name
Test status
Simulation time 38725773609 ps
CPU time 2005.22 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:55:23 PM PST 24
Peak memory 239896 kb
Host smart-4e69de8e-dbc5-4806-b919-f56fd4353c4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2047531476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2047531476
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.780265913
Short name T190
Test name
Test status
Simulation time 91296225 ps
CPU time 0.9 seconds
Started Jan 10 01:21:47 PM PST 24
Finished Jan 10 01:22:13 PM PST 24
Peak memory 195944 kb
Host smart-e3cd8f25-697b-4b12-8282-3446de304a4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780265913 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.780265913
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.415206019
Short name T421
Test name
Test status
Simulation time 5029489403 ps
CPU time 43.16 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:22:40 PM PST 24
Peak memory 198884 kb
Host smart-6de99cf8-c000-4622-b33e-60ee5401301b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415206019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.415206019
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3514247233
Short name T777
Test name
Test status
Simulation time 47072241 ps
CPU time 0.57 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:23:03 PM PST 24
Peak memory 193064 kb
Host smart-cc48f55c-2a7f-4089-8033-0d552a20a003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514247233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3514247233
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.4043114006
Short name T590
Test name
Test status
Simulation time 988730502 ps
CPU time 28.49 seconds
Started Jan 10 01:22:25 PM PST 24
Finished Jan 10 01:23:15 PM PST 24
Peak memory 216520 kb
Host smart-d80291b8-15d8-4455-8167-70028bfb9eeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043114006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.4043114006
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3530355393
Short name T597
Test name
Test status
Simulation time 13421294837 ps
CPU time 37.74 seconds
Started Jan 10 01:22:41 PM PST 24
Finished Jan 10 01:23:40 PM PST 24
Peak memory 198852 kb
Host smart-55761807-2baf-4447-88a5-5826232b2ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530355393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3530355393
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3600212231
Short name T427
Test name
Test status
Simulation time 1956180005 ps
CPU time 48.32 seconds
Started Jan 10 01:22:57 PM PST 24
Finished Jan 10 01:24:03 PM PST 24
Peak memory 198616 kb
Host smart-ba4d5148-78d9-4fed-ad4b-cb4daadda29e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3600212231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3600212231
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3503183677
Short name T762
Test name
Test status
Simulation time 170434436 ps
CPU time 4.44 seconds
Started Jan 10 01:22:25 PM PST 24
Finished Jan 10 01:22:51 PM PST 24
Peak memory 197860 kb
Host smart-4f99e7dc-1a6d-432d-8f29-a674e0e94bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503183677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3503183677
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3322092007
Short name T228
Test name
Test status
Simulation time 11468574551 ps
CPU time 49.34 seconds
Started Jan 10 01:22:57 PM PST 24
Finished Jan 10 01:24:02 PM PST 24
Peak memory 198804 kb
Host smart-8ded6072-e344-4617-b394-24f81b91b4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322092007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3322092007
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2570140631
Short name T211
Test name
Test status
Simulation time 29448620 ps
CPU time 0.59 seconds
Started Jan 10 01:22:45 PM PST 24
Finished Jan 10 01:23:04 PM PST 24
Peak memory 193416 kb
Host smart-724fcf4f-4cfa-479e-8aba-f2495f3be801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570140631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2570140631
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.113420835
Short name T468
Test name
Test status
Simulation time 26026945249 ps
CPU time 447.6 seconds
Started Jan 10 01:22:29 PM PST 24
Finished Jan 10 01:30:17 PM PST 24
Peak memory 230296 kb
Host smart-8de40837-6b47-46b9-a753-35589a1cb66d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113420835 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.113420835
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3451943579
Short name T240
Test name
Test status
Simulation time 163364794 ps
CPU time 1.04 seconds
Started Jan 10 01:22:31 PM PST 24
Finished Jan 10 01:22:52 PM PST 24
Peak memory 196976 kb
Host smart-d9743b33-b91f-4726-8ce9-48f9b24de468
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451943579 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3451943579
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1928445801
Short name T249
Test name
Test status
Simulation time 15328809339 ps
CPU time 364.03 seconds
Started Jan 10 01:22:56 PM PST 24
Finished Jan 10 01:29:17 PM PST 24
Peak memory 198776 kb
Host smart-f0b99ce5-9b6b-4b24-a81a-77698d3f17e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928445801 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.1928445801
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1436264774
Short name T35
Test name
Test status
Simulation time 4738552915 ps
CPU time 47.5 seconds
Started Jan 10 01:22:29 PM PST 24
Finished Jan 10 01:23:38 PM PST 24
Peak memory 198868 kb
Host smart-2fbad673-b423-471d-bae2-60d887b65247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436264774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1436264774
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.349089970
Short name T721
Test name
Test status
Simulation time 121590172 ps
CPU time 0.58 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:23:16 PM PST 24
Peak memory 193104 kb
Host smart-2cbc773f-b37f-4740-aa37-4a09cbbaa424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349089970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.349089970
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2970309087
Short name T360
Test name
Test status
Simulation time 1128928400 ps
CPU time 33.02 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:23:48 PM PST 24
Peak memory 207736 kb
Host smart-7d81674a-9fc3-4d54-b786-03d111269005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970309087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2970309087
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1961049968
Short name T467
Test name
Test status
Simulation time 593598093 ps
CPU time 27.44 seconds
Started Jan 10 01:22:24 PM PST 24
Finished Jan 10 01:23:14 PM PST 24
Peak memory 198800 kb
Host smart-405527dc-b893-454d-97de-2c598c0e39b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961049968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1961049968
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1413508968
Short name T46
Test name
Test status
Simulation time 3058975633 ps
CPU time 74.38 seconds
Started Jan 10 01:22:27 PM PST 24
Finished Jan 10 01:24:03 PM PST 24
Peak memory 198872 kb
Host smart-434c9ba7-0944-43ac-ace2-990e5225fc53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413508968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1413508968
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2481762518
Short name T614
Test name
Test status
Simulation time 5043061938 ps
CPU time 81.8 seconds
Started Jan 10 01:22:30 PM PST 24
Finished Jan 10 01:24:12 PM PST 24
Peak memory 198836 kb
Host smart-956ef669-3694-4708-8747-e4dfa46f8aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481762518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2481762518
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.251602324
Short name T648
Test name
Test status
Simulation time 2581471523 ps
CPU time 8.31 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:23:26 PM PST 24
Peak memory 198852 kb
Host smart-90af7d1e-3635-4eec-b988-e3bb49aaa6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251602324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.251602324
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2514104179
Short name T218
Test name
Test status
Simulation time 575330659 ps
CPU time 3.77 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:23:08 PM PST 24
Peak memory 198708 kb
Host smart-4620203a-07be-436b-9eb0-5eb6459bd9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514104179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2514104179
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1037711809
Short name T473
Test name
Test status
Simulation time 5692377689 ps
CPU time 266.37 seconds
Started Jan 10 01:22:40 PM PST 24
Finished Jan 10 01:27:28 PM PST 24
Peak memory 198892 kb
Host smart-04d48e22-faf8-4922-a94d-5f2211efe21a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037711809 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1037711809
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.1871973944
Short name T794
Test name
Test status
Simulation time 32356285788 ps
CPU time 1242.72 seconds
Started Jan 10 01:22:45 PM PST 24
Finished Jan 10 01:43:47 PM PST 24
Peak memory 247964 kb
Host smart-937e1ad5-0512-48f8-8c18-cb5ba58fdbaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1871973944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.1871973944
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3959108766
Short name T391
Test name
Test status
Simulation time 84258480 ps
CPU time 0.96 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:23:05 PM PST 24
Peak memory 196892 kb
Host smart-19998702-2dba-47bd-9aa9-f5766d07e53a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959108766 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3959108766
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1245334624
Short name T478
Test name
Test status
Simulation time 41427907296 ps
CPU time 349.82 seconds
Started Jan 10 01:22:31 PM PST 24
Finished Jan 10 01:28:41 PM PST 24
Peak memory 198736 kb
Host smart-56cea23b-7fbc-45c0-aff5-ef1cfdf1d3af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245334624 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.1245334624
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1660130472
Short name T618
Test name
Test status
Simulation time 1317785801 ps
CPU time 44.72 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:24:03 PM PST 24
Peak memory 198732 kb
Host smart-68c08374-94d6-46e7-a652-6a91b1debe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660130472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1660130472
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1354540877
Short name T791
Test name
Test status
Simulation time 13817478 ps
CPU time 0.55 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:23:04 PM PST 24
Peak memory 193068 kb
Host smart-af628770-1287-4065-9b5a-d8a493142a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354540877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1354540877
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1265721964
Short name T205
Test name
Test status
Simulation time 5449310119 ps
CPU time 41.01 seconds
Started Jan 10 01:22:25 PM PST 24
Finished Jan 10 01:23:27 PM PST 24
Peak memory 214320 kb
Host smart-768e4505-e77e-4d52-88e4-94af86cfd8b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265721964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1265721964
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3381684429
Short name T339
Test name
Test status
Simulation time 97793517 ps
CPU time 1.69 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:23:16 PM PST 24
Peak memory 198700 kb
Host smart-fabf3550-e43a-4206-a47a-4a2b4db3a53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381684429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3381684429
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2202781835
Short name T603
Test name
Test status
Simulation time 3964309185 ps
CPU time 48.22 seconds
Started Jan 10 01:22:29 PM PST 24
Finished Jan 10 01:23:38 PM PST 24
Peak memory 198852 kb
Host smart-bf9981d5-6f2a-4ef3-b1cb-5caa1001b502
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202781835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2202781835
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1518639449
Short name T589
Test name
Test status
Simulation time 9886036904 ps
CPU time 129.46 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:25:25 PM PST 24
Peak memory 198880 kb
Host smart-9aebdd18-56ee-47ed-9c38-21e7985afc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518639449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1518639449
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3888077823
Short name T311
Test name
Test status
Simulation time 3763582811 ps
CPU time 49.05 seconds
Started Jan 10 01:22:50 PM PST 24
Finished Jan 10 01:23:57 PM PST 24
Peak memory 198788 kb
Host smart-2eca73dc-e8fc-4696-823e-c540ea08c6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888077823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3888077823
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3270936088
Short name T298
Test name
Test status
Simulation time 109689643 ps
CPU time 1.41 seconds
Started Jan 10 01:22:56 PM PST 24
Finished Jan 10 01:23:14 PM PST 24
Peak memory 196952 kb
Host smart-8cc7277d-456b-445e-9723-a99728c30a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270936088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3270936088
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1003019027
Short name T698
Test name
Test status
Simulation time 300396936529 ps
CPU time 890.83 seconds
Started Jan 10 01:22:25 PM PST 24
Finished Jan 10 01:37:37 PM PST 24
Peak memory 223468 kb
Host smart-eb95fe54-1a04-42f8-9657-d0bc2592049e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003019027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1003019027
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.1923912054
Short name T313
Test name
Test status
Simulation time 141542392924 ps
CPU time 613.7 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:33:17 PM PST 24
Peak memory 208332 kb
Host smart-f0595dfc-6b1e-4011-9866-0b0cf50d4d3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1923912054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.1923912054
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3945711752
Short name T185
Test name
Test status
Simulation time 105887557 ps
CPU time 0.89 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:23:20 PM PST 24
Peak memory 196772 kb
Host smart-8e4b584f-0083-416a-a6c2-6b13f73e2584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945711752 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3945711752
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1337808382
Short name T512
Test name
Test status
Simulation time 63579015951 ps
CPU time 474.48 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:31:12 PM PST 24
Peak memory 198808 kb
Host smart-1c2c17b7-1c18-4342-ae25-a16c81e3ba94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337808382 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.1337808382
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3645011253
Short name T262
Test name
Test status
Simulation time 1716633635 ps
CPU time 62.53 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 01:24:18 PM PST 24
Peak memory 198720 kb
Host smart-05ef6c6e-08b4-483f-90a5-d29b214aeb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645011253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3645011253
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2774053884
Short name T548
Test name
Test status
Simulation time 11198488 ps
CPU time 0.55 seconds
Started Jan 10 01:22:32 PM PST 24
Finished Jan 10 01:22:53 PM PST 24
Peak memory 193076 kb
Host smart-a018732a-2ef2-4f7e-aec3-5b50f05f8807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774053884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2774053884
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2912649173
Short name T342
Test name
Test status
Simulation time 3507774928 ps
CPU time 21.37 seconds
Started Jan 10 01:22:49 PM PST 24
Finished Jan 10 01:23:28 PM PST 24
Peak memory 208004 kb
Host smart-119050ae-eb6c-4be5-a765-43d90da78e09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912649173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2912649173
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.340989429
Short name T510
Test name
Test status
Simulation time 1065433527 ps
CPU time 13.91 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:23:33 PM PST 24
Peak memory 198712 kb
Host smart-51a09e85-57d9-45cf-a647-83154733de06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340989429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.340989429
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.717545261
Short name T538
Test name
Test status
Simulation time 1733343275 ps
CPU time 45.94 seconds
Started Jan 10 01:22:48 PM PST 24
Finished Jan 10 01:23:52 PM PST 24
Peak memory 198676 kb
Host smart-40c46ac6-3808-4239-ab29-307eb9162a2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=717545261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.717545261
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.707753315
Short name T501
Test name
Test status
Simulation time 304162612 ps
CPU time 14.67 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:23:18 PM PST 24
Peak memory 198768 kb
Host smart-448f2e74-2fa3-46ed-a211-c96c13a466dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707753315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.707753315
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3831989990
Short name T511
Test name
Test status
Simulation time 2114850703 ps
CPU time 37.4 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 01:23:53 PM PST 24
Peak memory 198824 kb
Host smart-da09349d-51e5-42ae-89f8-a88dbb2b9e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831989990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3831989990
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2658866107
Short name T216
Test name
Test status
Simulation time 131374998 ps
CPU time 1.76 seconds
Started Jan 10 01:22:23 PM PST 24
Finished Jan 10 01:22:47 PM PST 24
Peak memory 198828 kb
Host smart-ebc6e4de-caa2-4737-93cc-931142392b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658866107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2658866107
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3529785084
Short name T584
Test name
Test status
Simulation time 162280282499 ps
CPU time 845.51 seconds
Started Jan 10 01:22:29 PM PST 24
Finished Jan 10 01:36:56 PM PST 24
Peak memory 214492 kb
Host smart-1fb1bc42-70fa-4140-b82e-37507df1fc3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529785084 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3529785084
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.2478448704
Short name T465
Test name
Test status
Simulation time 352691878916 ps
CPU time 1422.3 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:46:46 PM PST 24
Peak memory 240880 kb
Host smart-16a9e51b-5c14-4538-83dd-0c09391bfe0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478448704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.2478448704
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.277780145
Short name T571
Test name
Test status
Simulation time 46451971 ps
CPU time 0.84 seconds
Started Jan 10 01:22:45 PM PST 24
Finished Jan 10 01:23:05 PM PST 24
Peak memory 196724 kb
Host smart-e3f88096-c2ec-41c8-bf02-4dfc0f7395b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277780145 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.277780145
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.4132915774
Short name T472
Test name
Test status
Simulation time 24153532936 ps
CPU time 397.42 seconds
Started Jan 10 01:22:42 PM PST 24
Finished Jan 10 01:29:40 PM PST 24
Peak memory 198820 kb
Host smart-78dfa1b1-17e2-42d1-ae7f-9880f948a393
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132915774 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.4132915774
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.147328042
Short name T518
Test name
Test status
Simulation time 864090583 ps
CPU time 36.59 seconds
Started Jan 10 01:22:49 PM PST 24
Finished Jan 10 01:23:44 PM PST 24
Peak memory 198684 kb
Host smart-e5305cea-ecc5-4deb-91c9-27239edbc511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147328042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.147328042
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2699610434
Short name T653
Test name
Test status
Simulation time 14589108 ps
CPU time 0.56 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:23:15 PM PST 24
Peak memory 193144 kb
Host smart-67c6c0da-3dc2-4fcb-a8d3-21d63332d0e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699610434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2699610434
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3910139508
Short name T235
Test name
Test status
Simulation time 4805240419 ps
CPU time 39.52 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 01:23:55 PM PST 24
Peak memory 218340 kb
Host smart-b80a9edf-750e-438c-8c6e-4f3ff373a789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910139508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3910139508
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.417908445
Short name T375
Test name
Test status
Simulation time 1542321380 ps
CPU time 20.29 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:23:38 PM PST 24
Peak memory 198712 kb
Host smart-f1bba510-bfda-4cc4-8a22-0300a120e250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417908445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.417908445
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1036421704
Short name T695
Test name
Test status
Simulation time 1445516253 ps
CPU time 20.39 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:23:37 PM PST 24
Peak memory 198648 kb
Host smart-6ac46c2f-0235-439f-bec6-96a058477919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1036421704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1036421704
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2587375507
Short name T430
Test name
Test status
Simulation time 7182420254 ps
CPU time 79.86 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:24:35 PM PST 24
Peak memory 198696 kb
Host smart-03278856-3bd4-43f1-9d9a-789724317ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587375507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2587375507
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.784300484
Short name T290
Test name
Test status
Simulation time 1029601916 ps
CPU time 26.35 seconds
Started Jan 10 01:22:31 PM PST 24
Finished Jan 10 01:23:18 PM PST 24
Peak memory 198728 kb
Host smart-aad80764-9ac8-454a-9338-8b1cfd186aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784300484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.784300484
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.477570174
Short name T740
Test name
Test status
Simulation time 187178375 ps
CPU time 3.87 seconds
Started Jan 10 01:23:03 PM PST 24
Finished Jan 10 01:23:25 PM PST 24
Peak memory 198632 kb
Host smart-76029473-4c2e-41a6-8e4c-0bcca334f979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477570174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.477570174
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3307920121
Short name T242
Test name
Test status
Simulation time 183443252689 ps
CPU time 594.02 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:32:57 PM PST 24
Peak memory 239264 kb
Host smart-bece12af-afff-4ae9-8651-77ddddd55165
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307920121 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3307920121
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.777088170
Short name T681
Test name
Test status
Simulation time 189182798900 ps
CPU time 1038.08 seconds
Started Jan 10 01:22:45 PM PST 24
Finished Jan 10 01:40:23 PM PST 24
Peak memory 247360 kb
Host smart-5f99ff18-e56e-4c7f-8a92-27bbe459067e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777088170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.777088170
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3634711717
Short name T186
Test name
Test status
Simulation time 30980083 ps
CPU time 1.09 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:23:20 PM PST 24
Peak memory 197384 kb
Host smart-926ca68f-1e7a-442c-9a80-d36eea76226a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634711717 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3634711717
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.567199079
Short name T194
Test name
Test status
Simulation time 55065793247 ps
CPU time 384.67 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:29:43 PM PST 24
Peak memory 198748 kb
Host smart-7a52f614-ad12-490c-8da8-a94aaf3b6777
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567199079 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.hmac_test_sha_vectors.567199079
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.709723854
Short name T297
Test name
Test status
Simulation time 28955114003 ps
CPU time 86.99 seconds
Started Jan 10 01:22:35 PM PST 24
Finished Jan 10 01:24:24 PM PST 24
Peak memory 198888 kb
Host smart-dfa0ccae-a4ac-4196-968f-bc64e0ae6109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709723854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.709723854
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3086765047
Short name T91
Test name
Test status
Simulation time 12971987 ps
CPU time 0.56 seconds
Started Jan 10 01:23:11 PM PST 24
Finished Jan 10 01:23:30 PM PST 24
Peak memory 193132 kb
Host smart-bcd55650-4633-4ef9-92e8-c57d1f1bf390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086765047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3086765047
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.4101722103
Short name T626
Test name
Test status
Simulation time 944724705 ps
CPU time 6.97 seconds
Started Jan 10 01:22:42 PM PST 24
Finished Jan 10 01:23:10 PM PST 24
Peak memory 214876 kb
Host smart-d8cca929-e795-42b4-9a4a-636e919184db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101722103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.4101722103
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2210658596
Short name T508
Test name
Test status
Simulation time 3377483901 ps
CPU time 38.32 seconds
Started Jan 10 01:22:56 PM PST 24
Finished Jan 10 01:23:51 PM PST 24
Peak memory 198920 kb
Host smart-e3dde2ae-54f3-4941-8c81-93552113e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210658596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2210658596
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.4267451620
Short name T334
Test name
Test status
Simulation time 9376064682 ps
CPU time 119.38 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:25:18 PM PST 24
Peak memory 198896 kb
Host smart-d9938339-4451-49fb-8784-6fd06822ddc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267451620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.4267451620
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1368622643
Short name T306
Test name
Test status
Simulation time 184300927660 ps
CPU time 171.79 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:26:11 PM PST 24
Peak memory 198800 kb
Host smart-cc15ab52-5fea-4a0a-9679-f3e321da80fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368622643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1368622643
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2010681243
Short name T630
Test name
Test status
Simulation time 3326186954 ps
CPU time 21.32 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:23:24 PM PST 24
Peak memory 198820 kb
Host smart-c5a31441-6816-412c-bc29-343dae7f5a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010681243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2010681243
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.4014511643
Short name T787
Test name
Test status
Simulation time 1768537887 ps
CPU time 4.11 seconds
Started Jan 10 01:22:49 PM PST 24
Finished Jan 10 01:23:11 PM PST 24
Peak memory 198332 kb
Host smart-f06a250b-7d93-45bc-8906-a5228fbd350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014511643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.4014511643
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3080229237
Short name T258
Test name
Test status
Simulation time 58296675817 ps
CPU time 889.27 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:38:16 PM PST 24
Peak memory 239836 kb
Host smart-87dae578-a40e-407f-a628-beb9bd6123fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080229237 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3080229237
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.155929536
Short name T617
Test name
Test status
Simulation time 48658969815 ps
CPU time 707.71 seconds
Started Jan 10 01:23:13 PM PST 24
Finished Jan 10 01:35:18 PM PST 24
Peak memory 215312 kb
Host smart-f8090f52-fff5-4c18-8871-bd025272141c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155929536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.155929536
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2995172398
Short name T363
Test name
Test status
Simulation time 217064569 ps
CPU time 1.24 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:23:29 PM PST 24
Peak memory 198720 kb
Host smart-8b482566-1010-4dda-8f27-8326de58f60b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995172398 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2995172398
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2232146938
Short name T272
Test name
Test status
Simulation time 7740387306 ps
CPU time 374 seconds
Started Jan 10 01:23:21 PM PST 24
Finished Jan 10 01:29:46 PM PST 24
Peak memory 198700 kb
Host smart-c003e769-c23f-4f89-af8e-e6d547d9c1fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232146938 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.2232146938
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1753574708
Short name T491
Test name
Test status
Simulation time 2163736255 ps
CPU time 70.44 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:24:38 PM PST 24
Peak memory 198848 kb
Host smart-bf635624-4619-4986-be47-21d6f0a7f193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753574708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1753574708
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.18938181
Short name T267
Test name
Test status
Simulation time 28992808 ps
CPU time 0.62 seconds
Started Jan 10 01:23:31 PM PST 24
Finished Jan 10 01:23:37 PM PST 24
Peak memory 193056 kb
Host smart-f807675e-3271-4445-9985-1759f625185c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18938181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.18938181
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1730593893
Short name T628
Test name
Test status
Simulation time 515937859 ps
CPU time 13.69 seconds
Started Jan 10 01:23:25 PM PST 24
Finished Jan 10 01:23:48 PM PST 24
Peak memory 207000 kb
Host smart-62035674-0917-48e0-bcf1-53a6f9f73471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730593893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1730593893
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.157685182
Short name T719
Test name
Test status
Simulation time 1895199505 ps
CPU time 33.4 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:24:00 PM PST 24
Peak memory 198712 kb
Host smart-708b3ef5-995b-4d46-8ed7-a2e388b68ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157685182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.157685182
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2257469383
Short name T159
Test name
Test status
Simulation time 874566044 ps
CPU time 22.88 seconds
Started Jan 10 01:23:30 PM PST 24
Finished Jan 10 01:23:59 PM PST 24
Peak memory 198760 kb
Host smart-d921ba60-4b1d-433f-a1e1-52589d3b0a07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257469383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2257469383
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3731018061
Short name T685
Test name
Test status
Simulation time 109256479477 ps
CPU time 123.43 seconds
Started Jan 10 01:23:21 PM PST 24
Finished Jan 10 01:25:36 PM PST 24
Peak memory 198572 kb
Host smart-5e6dc833-ef02-4430-954f-e20ae81037c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731018061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3731018061
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2446488870
Short name T206
Test name
Test status
Simulation time 115725756 ps
CPU time 6.23 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:23:34 PM PST 24
Peak memory 198816 kb
Host smart-331ce709-b38f-4633-8ca5-27296563bcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446488870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2446488870
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.4037273550
Short name T668
Test name
Test status
Simulation time 21719427 ps
CPU time 0.85 seconds
Started Jan 10 01:23:21 PM PST 24
Finished Jan 10 01:23:33 PM PST 24
Peak memory 195888 kb
Host smart-6809cf18-e69d-4e76-8ff7-d2468c13cca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037273550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.4037273550
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3826822189
Short name T138
Test name
Test status
Simulation time 63482003948 ps
CPU time 773.56 seconds
Started Jan 10 01:23:22 PM PST 24
Finished Jan 10 01:36:26 PM PST 24
Peak memory 198840 kb
Host smart-0aae8348-9e4e-4efa-b26b-3178b626f302
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826822189 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3826822189
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.1449354849
Short name T246
Test name
Test status
Simulation time 66156024666 ps
CPU time 976.03 seconds
Started Jan 10 01:23:18 PM PST 24
Finished Jan 10 01:39:48 PM PST 24
Peak memory 239288 kb
Host smart-aded6ef2-5aff-4bda-8d94-dbe95a4bc183
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449354849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.1449354849
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3008721400
Short name T535
Test name
Test status
Simulation time 54414587 ps
CPU time 0.86 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:23:28 PM PST 24
Peak memory 196572 kb
Host smart-a5fd54c7-8155-4f34-bf31-2fe913d0238d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008721400 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3008721400
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.16815488
Short name T503
Test name
Test status
Simulation time 29912535957 ps
CPU time 355.66 seconds
Started Jan 10 01:23:06 PM PST 24
Finished Jan 10 01:29:20 PM PST 24
Peak memory 198680 kb
Host smart-8f609021-4c6c-46f2-a178-e6c4bf6d3bbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16815488 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.hmac_test_sha_vectors.16815488
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1716398775
Short name T412
Test name
Test status
Simulation time 5469427743 ps
CPU time 70.76 seconds
Started Jan 10 01:23:10 PM PST 24
Finished Jan 10 01:24:39 PM PST 24
Peak memory 198840 kb
Host smart-f893379d-acd1-4bb7-9a21-29c98df73843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716398775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1716398775
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2911334565
Short name T596
Test name
Test status
Simulation time 98100054 ps
CPU time 0.57 seconds
Started Jan 10 01:23:38 PM PST 24
Finished Jan 10 01:23:46 PM PST 24
Peak memory 193232 kb
Host smart-75fefe37-d0f6-4a83-9e22-2bb2b2c6f983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911334565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2911334565
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2803641556
Short name T370
Test name
Test status
Simulation time 1900816024 ps
CPU time 13 seconds
Started Jan 10 01:23:30 PM PST 24
Finished Jan 10 01:23:49 PM PST 24
Peak memory 214940 kb
Host smart-d0d7eb8d-46fc-4cf7-8c34-d19d447a76d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803641556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2803641556
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2022773171
Short name T502
Test name
Test status
Simulation time 6541138821 ps
CPU time 22.88 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:23:50 PM PST 24
Peak memory 198780 kb
Host smart-d43ad00c-39b0-498d-8a30-9adc1d33b24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022773171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2022773171
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.4003991308
Short name T481
Test name
Test status
Simulation time 2175962492 ps
CPU time 112.78 seconds
Started Jan 10 01:23:31 PM PST 24
Finished Jan 10 01:25:29 PM PST 24
Peak memory 198832 kb
Host smart-31c2b24d-ee4b-41fb-823b-3af5611b93f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003991308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.4003991308
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.4291652373
Short name T189
Test name
Test status
Simulation time 4042985307 ps
CPU time 98.61 seconds
Started Jan 10 01:23:34 PM PST 24
Finished Jan 10 01:25:16 PM PST 24
Peak memory 198828 kb
Host smart-388b3a8e-c040-4256-b965-6f55cf844c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291652373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4291652373
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1243202980
Short name T92
Test name
Test status
Simulation time 2186206473 ps
CPU time 37.26 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:24:04 PM PST 24
Peak memory 198660 kb
Host smart-4dca877f-8b5f-48ae-b190-51368f9b3226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243202980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1243202980
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1421123671
Short name T763
Test name
Test status
Simulation time 484474942 ps
CPU time 4.98 seconds
Started Jan 10 01:23:32 PM PST 24
Finished Jan 10 01:23:42 PM PST 24
Peak memory 198772 kb
Host smart-fedfeeac-3a96-4f11-88e3-82a6d85e90d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421123671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1421123671
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.592872923
Short name T463
Test name
Test status
Simulation time 71431580548 ps
CPU time 953.19 seconds
Started Jan 10 01:23:39 PM PST 24
Finished Jan 10 01:39:40 PM PST 24
Peak memory 198840 kb
Host smart-90d3fd64-ab86-405a-ba60-173287884294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592872923 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.592872923
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.4076827861
Short name T484
Test name
Test status
Simulation time 245149354881 ps
CPU time 2098.16 seconds
Started Jan 10 01:23:36 PM PST 24
Finished Jan 10 01:58:40 PM PST 24
Peak memory 244440 kb
Host smart-ebb94031-a440-49be-9ef6-694b1e06a216
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4076827861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.4076827861
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2183654093
Short name T466
Test name
Test status
Simulation time 70807016 ps
CPU time 0.9 seconds
Started Jan 10 01:23:45 PM PST 24
Finished Jan 10 01:23:56 PM PST 24
Peak memory 195632 kb
Host smart-7e7bc1f5-7c76-4227-8743-6467df0124f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183654093 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2183654093
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3173644829
Short name T392
Test name
Test status
Simulation time 16068511576 ps
CPU time 382.92 seconds
Started Jan 10 01:23:34 PM PST 24
Finished Jan 10 01:30:01 PM PST 24
Peak memory 198860 kb
Host smart-538c1a36-be28-407c-97a4-cc9b0899a323
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173644829 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.3173644829
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1381990323
Short name T443
Test name
Test status
Simulation time 1463069896 ps
CPU time 6.89 seconds
Started Jan 10 01:23:33 PM PST 24
Finished Jan 10 01:23:44 PM PST 24
Peak memory 198808 kb
Host smart-d4d44973-a3f4-4896-837a-569f30bb6a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381990323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1381990323
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3359888191
Short name T299
Test name
Test status
Simulation time 16132683 ps
CPU time 0.58 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:23:17 PM PST 24
Peak memory 194200 kb
Host smart-3f5dfca8-ffd7-4e0d-ac41-af742cca89a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359888191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3359888191
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3588429499
Short name T716
Test name
Test status
Simulation time 224193269 ps
CPU time 2.01 seconds
Started Jan 10 01:23:16 PM PST 24
Finished Jan 10 01:23:33 PM PST 24
Peak memory 198760 kb
Host smart-f9d16f28-e9b1-4dca-b0fe-62a217dd1e40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588429499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3588429499
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3266549859
Short name T531
Test name
Test status
Simulation time 457842720 ps
CPU time 20.13 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:23:24 PM PST 24
Peak memory 198772 kb
Host smart-167171cd-f826-438c-9527-b00225676ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266549859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3266549859
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.284662997
Short name T744
Test name
Test status
Simulation time 1950320016 ps
CPU time 102.3 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:24:46 PM PST 24
Peak memory 198756 kb
Host smart-ccb83a8d-1e5c-4955-916b-2b57ecaf6137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284662997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.284662997
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3345866686
Short name T646
Test name
Test status
Simulation time 3077748114 ps
CPU time 133.42 seconds
Started Jan 10 01:22:49 PM PST 24
Finished Jan 10 01:25:20 PM PST 24
Peak memory 198772 kb
Host smart-839d4f90-239b-492e-9b5a-59204447c58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345866686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3345866686
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2599412927
Short name T232
Test name
Test status
Simulation time 2225750775 ps
CPU time 6.7 seconds
Started Jan 10 01:23:37 PM PST 24
Finished Jan 10 01:23:50 PM PST 24
Peak memory 198884 kb
Host smart-a372b324-0d86-4b2d-b33c-b6f239c30fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599412927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2599412927
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1732849333
Short name T181
Test name
Test status
Simulation time 746695892 ps
CPU time 0.98 seconds
Started Jan 10 01:23:38 PM PST 24
Finished Jan 10 01:23:45 PM PST 24
Peak memory 197500 kb
Host smart-dc445fef-0096-48fa-b4e0-2a81c57669c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732849333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1732849333
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1897028071
Short name T214
Test name
Test status
Simulation time 23532339926 ps
CPU time 1027.18 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 01:40:24 PM PST 24
Peak memory 236688 kb
Host smart-5442d246-cbfe-4491-a273-dfa663e92d13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897028071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1897028071
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.1029438849
Short name T489
Test name
Test status
Simulation time 119094915717 ps
CPU time 2272.14 seconds
Started Jan 10 01:22:49 PM PST 24
Finished Jan 10 02:00:59 PM PST 24
Peak memory 256228 kb
Host smart-a9e12306-b7df-4cc2-9665-54fd74770cfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1029438849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.1029438849
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1305144123
Short name T743
Test name
Test status
Simulation time 33389365 ps
CPU time 1.05 seconds
Started Jan 10 01:22:30 PM PST 24
Finished Jan 10 01:22:52 PM PST 24
Peak memory 197300 kb
Host smart-e61dd40f-ac3b-43df-baae-5e6c20329eeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305144123 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1305144123
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2392603107
Short name T640
Test name
Test status
Simulation time 64850663636 ps
CPU time 406.96 seconds
Started Jan 10 01:22:45 PM PST 24
Finished Jan 10 01:29:51 PM PST 24
Peak memory 198748 kb
Host smart-6e5c8009-ee8f-4134-a4ab-358e69f90440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392603107 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.2392603107
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3728575894
Short name T732
Test name
Test status
Simulation time 772545638 ps
CPU time 10.07 seconds
Started Jan 10 01:22:42 PM PST 24
Finished Jan 10 01:23:13 PM PST 24
Peak memory 198764 kb
Host smart-cd0d774c-e93e-4ca3-857c-007f0e54c38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728575894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3728575894
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.969284240
Short name T514
Test name
Test status
Simulation time 26660260 ps
CPU time 0.55 seconds
Started Jan 10 01:23:03 PM PST 24
Finished Jan 10 01:23:22 PM PST 24
Peak memory 192736 kb
Host smart-8290d178-e606-4f65-878f-faf0a344cc7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969284240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.969284240
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1431583940
Short name T770
Test name
Test status
Simulation time 336798829 ps
CPU time 5.27 seconds
Started Jan 10 01:22:43 PM PST 24
Finished Jan 10 01:23:08 PM PST 24
Peak memory 206952 kb
Host smart-b716943e-2158-47ab-85bf-5d47ba29c611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1431583940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1431583940
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3940194348
Short name T652
Test name
Test status
Simulation time 11648373622 ps
CPU time 52.09 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 01:24:08 PM PST 24
Peak memory 198824 kb
Host smart-ec9cd25a-8482-493a-b515-ae058f3f793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940194348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3940194348
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2437559629
Short name T4
Test name
Test status
Simulation time 4240339601 ps
CPU time 35.97 seconds
Started Jan 10 01:22:29 PM PST 24
Finished Jan 10 01:23:26 PM PST 24
Peak memory 198668 kb
Host smart-e2661729-1248-421d-9bfc-9c0ed574f2ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437559629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2437559629
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1503769309
Short name T792
Test name
Test status
Simulation time 26438425703 ps
CPU time 72.51 seconds
Started Jan 10 01:22:42 PM PST 24
Finished Jan 10 01:24:15 PM PST 24
Peak memory 198940 kb
Host smart-b91d1423-f039-406f-b009-f243a6c22966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503769309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1503769309
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3621198955
Short name T765
Test name
Test status
Simulation time 4670197605 ps
CPU time 39.63 seconds
Started Jan 10 01:22:49 PM PST 24
Finished Jan 10 01:23:47 PM PST 24
Peak memory 198776 kb
Host smart-da8884f2-949d-4573-91e6-d1adfb88caa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621198955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3621198955
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1601693753
Short name T683
Test name
Test status
Simulation time 243784623 ps
CPU time 1.34 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:23:05 PM PST 24
Peak memory 198520 kb
Host smart-f89cc4b0-6a75-4317-8c96-0f2ec3cb9414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601693753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1601693753
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.818922015
Short name T741
Test name
Test status
Simulation time 83511373447 ps
CPU time 2023.35 seconds
Started Jan 10 01:22:46 PM PST 24
Finished Jan 10 01:56:48 PM PST 24
Peak memory 228576 kb
Host smart-856d5473-d436-446b-9b86-f3a1fdf40938
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818922015 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.818922015
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.618014978
Short name T435
Test name
Test status
Simulation time 667091435932 ps
CPU time 3424.88 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 02:20:24 PM PST 24
Peak memory 256272 kb
Host smart-15caa9dd-2092-4da0-a3cf-5452ec697074
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618014978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.618014978
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1812013540
Short name T433
Test name
Test status
Simulation time 447253513 ps
CPU time 0.9 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:23:27 PM PST 24
Peak memory 195956 kb
Host smart-9c759f61-7439-4e0f-864d-d624d972be37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812013540 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1812013540
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2256183697
Short name T349
Test name
Test status
Simulation time 18630455414 ps
CPU time 397.57 seconds
Started Jan 10 01:23:04 PM PST 24
Finished Jan 10 01:29:59 PM PST 24
Peak memory 198848 kb
Host smart-65cb5b19-482d-42c4-bc47-a070b170f680
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256183697 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_sha_vectors.2256183697
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2774443425
Short name T174
Test name
Test status
Simulation time 9948005227 ps
CPU time 27.76 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:23:32 PM PST 24
Peak memory 198788 kb
Host smart-f6b3ee18-d64e-453a-9eb8-a5a71a9248fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774443425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2774443425
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1936307622
Short name T323
Test name
Test status
Simulation time 39818984 ps
CPU time 0.56 seconds
Started Jan 10 01:21:43 PM PST 24
Finished Jan 10 01:22:06 PM PST 24
Peak memory 193196 kb
Host smart-71bd82db-42fd-473c-8934-8736d5460da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936307622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1936307622
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2203798041
Short name T561
Test name
Test status
Simulation time 10994526942 ps
CPU time 21.1 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:23 PM PST 24
Peak memory 215108 kb
Host smart-6de06a89-7c76-4a0c-8ea2-58e40e9d5804
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203798041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2203798041
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2540338551
Short name T87
Test name
Test status
Simulation time 2309902502 ps
CPU time 16.1 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:18 PM PST 24
Peak memory 198796 kb
Host smart-71bf5b44-440d-433d-9465-485292e2e211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540338551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2540338551
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3883323436
Short name T238
Test name
Test status
Simulation time 6137913032 ps
CPU time 81.18 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:23:20 PM PST 24
Peak memory 198784 kb
Host smart-258e2be6-00ee-4c07-8938-54c9c8b9b246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883323436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3883323436
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.151400832
Short name T229
Test name
Test status
Simulation time 7728508741 ps
CPU time 57.1 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:22:55 PM PST 24
Peak memory 198692 kb
Host smart-965cee83-a601-4d47-866c-7af9c2d2bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151400832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.151400832
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3540885207
Short name T303
Test name
Test status
Simulation time 1613238402 ps
CPU time 44.51 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:46 PM PST 24
Peak memory 198768 kb
Host smart-2570d5db-5fe1-46c4-9169-20b8f4dcf0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540885207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3540885207
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.728434315
Short name T329
Test name
Test status
Simulation time 162949818 ps
CPU time 2.39 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:07 PM PST 24
Peak memory 198792 kb
Host smart-70902ef3-e14a-4f09-a3c0-56a522c518af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728434315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.728434315
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4014338705
Short name T638
Test name
Test status
Simulation time 1540694013 ps
CPU time 71.79 seconds
Started Jan 10 01:21:43 PM PST 24
Finished Jan 10 01:23:17 PM PST 24
Peak memory 198784 kb
Host smart-b30c2ad2-f1fc-4464-98f8-3244923b8d41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014338705 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4014338705
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.4051665629
Short name T358
Test name
Test status
Simulation time 39862143116 ps
CPU time 123.17 seconds
Started Jan 10 01:22:04 PM PST 24
Finished Jan 10 01:24:33 PM PST 24
Peak memory 208068 kb
Host smart-ca9dc1ff-4483-46ce-98dc-bb30e2726560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051665629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.4051665629
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1737711607
Short name T610
Test name
Test status
Simulation time 260805708 ps
CPU time 1.22 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:22:00 PM PST 24
Peak memory 197104 kb
Host smart-19a7caa6-28db-4e7e-ac68-188e254f16ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737711607 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.1737711607
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2791849243
Short name T57
Test name
Test status
Simulation time 7351219489 ps
CPU time 356.99 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:27:58 PM PST 24
Peak memory 198740 kb
Host smart-b648e84e-92a8-4de7-b506-3d46bd73899d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791849243 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.2791849243
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3150798153
Short name T129
Test name
Test status
Simulation time 10788466874 ps
CPU time 46.08 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:51 PM PST 24
Peak memory 198944 kb
Host smart-7b2b819c-af60-405d-81fb-fdaab61bc10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150798153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3150798153
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.1257714617
Short name T136
Test name
Test status
Simulation time 675211542435 ps
CPU time 4365.56 seconds
Started Jan 10 01:23:03 PM PST 24
Finished Jan 10 02:36:07 PM PST 24
Peak memory 264340 kb
Host smart-bb44f6cb-f509-4dd5-94c0-a3cd395b26fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257714617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.1257714617
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.3979998380
Short name T80
Test name
Test status
Simulation time 197042709256 ps
CPU time 1437.3 seconds
Started Jan 10 01:22:45 PM PST 24
Finished Jan 10 01:47:02 PM PST 24
Peak memory 248148 kb
Host smart-882e08be-78f5-4567-a1db-590b87a78067
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979998380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.3979998380
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.1282428067
Short name T139
Test name
Test status
Simulation time 74587965035 ps
CPU time 1204.2 seconds
Started Jan 10 01:23:04 PM PST 24
Finished Jan 10 01:43:26 PM PST 24
Peak memory 244028 kb
Host smart-33624bec-2886-4aab-b928-77b46b26fe6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1282428067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.1282428067
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.2246497068
Short name T371
Test name
Test status
Simulation time 147965495596 ps
CPU time 1572.94 seconds
Started Jan 10 01:22:57 PM PST 24
Finished Jan 10 01:49:26 PM PST 24
Peak memory 223496 kb
Host smart-3c48c4ca-1585-45c4-89c9-508ade6831c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2246497068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.2246497068
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.1466394905
Short name T474
Test name
Test status
Simulation time 149963221639 ps
CPU time 3876.44 seconds
Started Jan 10 01:22:57 PM PST 24
Finished Jan 10 02:27:50 PM PST 24
Peak memory 258236 kb
Host smart-702978ce-1bbd-40de-88e0-88dc4ef1f2b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466394905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.1466394905
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.1440832776
Short name T295
Test name
Test status
Simulation time 39597152235 ps
CPU time 1111.29 seconds
Started Jan 10 01:22:46 PM PST 24
Finished Jan 10 01:41:36 PM PST 24
Peak memory 247192 kb
Host smart-5cc7e550-9d0d-4bf0-a2b2-78c23bd7fcec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1440832776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.1440832776
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.617161893
Short name T43
Test name
Test status
Simulation time 44866318676 ps
CPU time 2319.28 seconds
Started Jan 10 01:23:02 PM PST 24
Finished Jan 10 02:02:00 PM PST 24
Peak memory 246344 kb
Host smart-94841b5a-79f3-4830-9bbb-96ea877cf505
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617161893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.617161893
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.2114707930
Short name T446
Test name
Test status
Simulation time 12410280052 ps
CPU time 463.38 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:31:03 PM PST 24
Peak memory 239072 kb
Host smart-59a7e446-6f1f-4c78-98ea-c28cfbbae08e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114707930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.2114707930
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.3976793168
Short name T606
Test name
Test status
Simulation time 263256284113 ps
CPU time 1053.73 seconds
Started Jan 10 01:22:48 PM PST 24
Finished Jan 10 01:40:40 PM PST 24
Peak memory 240496 kb
Host smart-f7963343-cbb3-44ce-94aa-2ace06468b98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976793168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.3976793168
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.327707187
Short name T131
Test name
Test status
Simulation time 290422203421 ps
CPU time 3028.98 seconds
Started Jan 10 01:22:57 PM PST 24
Finished Jan 10 02:13:44 PM PST 24
Peak memory 251192 kb
Host smart-d41be4b3-f2c0-42b8-a0ad-2b99ec4ac291
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=327707187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.327707187
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1325835585
Short name T251
Test name
Test status
Simulation time 33378568 ps
CPU time 0.54 seconds
Started Jan 10 01:21:53 PM PST 24
Finished Jan 10 01:22:23 PM PST 24
Peak memory 193052 kb
Host smart-f5c42cce-2439-4dc8-8887-13c541ca18e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325835585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1325835585
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.691101372
Short name T736
Test name
Test status
Simulation time 5088803585 ps
CPU time 34.6 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:53 PM PST 24
Peak memory 216288 kb
Host smart-9b7b7e82-1e83-4ad7-abff-a82ce3e4a277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691101372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.691101372
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2277110877
Short name T552
Test name
Test status
Simulation time 229866178 ps
CPU time 0.57 seconds
Started Jan 10 01:21:47 PM PST 24
Finished Jan 10 01:22:12 PM PST 24
Peak memory 193296 kb
Host smart-184b802b-ca70-4782-ac56-92a0e9edcb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277110877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2277110877
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.939173138
Short name T660
Test name
Test status
Simulation time 473829878 ps
CPU time 22.93 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:22:21 PM PST 24
Peak memory 198608 kb
Host smart-9ecb18da-1b23-4e4f-bdd0-f3514b0ec066
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939173138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.939173138
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2838841320
Short name T364
Test name
Test status
Simulation time 17952720178 ps
CPU time 234.86 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:26:05 PM PST 24
Peak memory 198864 kb
Host smart-4f48f791-0f11-461a-98d8-a591efbbcee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838841320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2838841320
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.4090134155
Short name T256
Test name
Test status
Simulation time 8272197487 ps
CPU time 14.96 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:22:26 PM PST 24
Peak memory 198896 kb
Host smart-4bb2aa95-b349-422d-8d5b-1e3121df3b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090134155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4090134155
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3085070924
Short name T310
Test name
Test status
Simulation time 789516152 ps
CPU time 3.69 seconds
Started Jan 10 01:21:45 PM PST 24
Finished Jan 10 01:22:12 PM PST 24
Peak memory 198680 kb
Host smart-2217e56b-417f-4b2b-9875-6c4f2f0f1bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085070924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3085070924
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1871081049
Short name T722
Test name
Test status
Simulation time 71630546064 ps
CPU time 638.12 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:32:56 PM PST 24
Peak memory 239772 kb
Host smart-c279f217-0593-4230-bedc-9924cc7e8210
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871081049 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1871081049
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.3125563128
Short name T688
Test name
Test status
Simulation time 557473290831 ps
CPU time 5439.82 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 02:53:04 PM PST 24
Peak memory 244708 kb
Host smart-ba3927b7-edd9-4e8e-804c-3f62d177dd17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125563128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3125563128
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.4264179923
Short name T800
Test name
Test status
Simulation time 451929162 ps
CPU time 0.96 seconds
Started Jan 10 01:21:54 PM PST 24
Finished Jan 10 01:22:24 PM PST 24
Peak memory 195628 kb
Host smart-3c4f4087-befe-49a3-a854-8a0c0790349e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264179923 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.4264179923
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3720828360
Short name T751
Test name
Test status
Simulation time 36135677494 ps
CPU time 340.72 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:27:59 PM PST 24
Peak memory 198744 kb
Host smart-a6c5489d-4e5a-4a07-afc0-4506d9df48d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720828360 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.3720828360
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1702477013
Short name T772
Test name
Test status
Simulation time 1107404325 ps
CPU time 45.25 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:22:44 PM PST 24
Peak memory 198824 kb
Host smart-3807eeb6-3e0d-4c67-86cb-22e262109dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702477013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1702477013
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.1551166815
Short name T109
Test name
Test status
Simulation time 195432815354 ps
CPU time 636.58 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:33:55 PM PST 24
Peak memory 246860 kb
Host smart-b1a52fbf-f13c-4e47-907b-3f1e81669915
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1551166815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.1551166815
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.2553783637
Short name T726
Test name
Test status
Simulation time 178889164450 ps
CPU time 3427.65 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 02:20:11 PM PST 24
Peak memory 256056 kb
Host smart-b08df0f0-7195-4ee6-9034-99c275289c4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553783637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.2553783637
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.2591557632
Short name T119
Test name
Test status
Simulation time 86665455148 ps
CPU time 1566.39 seconds
Started Jan 10 01:22:44 PM PST 24
Finished Jan 10 01:49:10 PM PST 24
Peak memory 256232 kb
Host smart-a6f8febf-a283-46fa-bf3c-f844a0fdf50d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591557632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.2591557632
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.3407731772
Short name T381
Test name
Test status
Simulation time 23059747523 ps
CPU time 246.48 seconds
Started Jan 10 01:23:02 PM PST 24
Finished Jan 10 01:27:26 PM PST 24
Peak memory 207040 kb
Host smart-f728ad75-8cf9-4f56-b4be-152e83d55196
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407731772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.3407731772
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.1834332307
Short name T476
Test name
Test status
Simulation time 82750873986 ps
CPU time 1107.51 seconds
Started Jan 10 01:23:01 PM PST 24
Finished Jan 10 01:41:47 PM PST 24
Peak memory 207120 kb
Host smart-f89810ee-cd98-4e6d-8953-5d38000c400a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1834332307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.1834332307
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.3611526179
Short name T414
Test name
Test status
Simulation time 34731777258 ps
CPU time 1729.34 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:52:08 PM PST 24
Peak memory 245868 kb
Host smart-b755eb59-ca1d-49a6-a223-a77908488d8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611526179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.3611526179
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3165942724
Short name T135
Test name
Test status
Simulation time 243578266750 ps
CPU time 2662.38 seconds
Started Jan 10 01:23:04 PM PST 24
Finished Jan 10 02:07:44 PM PST 24
Peak memory 239920 kb
Host smart-3f8a9e5a-a78f-4b0d-9002-6e810da45d95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165942724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.3165942724
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.3909057483
Short name T755
Test name
Test status
Simulation time 285290423269 ps
CPU time 1111.74 seconds
Started Jan 10 01:23:03 PM PST 24
Finished Jan 10 01:41:53 PM PST 24
Peak memory 255372 kb
Host smart-7f999b3a-8c6b-44ba-b35c-383b63cd5ad5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909057483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.3909057483
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.3912238567
Short name T177
Test name
Test status
Simulation time 17813088454 ps
CPU time 888.79 seconds
Started Jan 10 01:22:59 PM PST 24
Finished Jan 10 01:38:04 PM PST 24
Peak memory 215344 kb
Host smart-c904a5f2-03d3-496b-8301-3b63dfde6ae1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912238567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.3912238567
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.2323151970
Short name T582
Test name
Test status
Simulation time 50511191287 ps
CPU time 691.2 seconds
Started Jan 10 01:22:53 PM PST 24
Finished Jan 10 01:34:42 PM PST 24
Peak memory 215160 kb
Host smart-39c37678-fac8-4d64-917d-415b913401b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323151970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.2323151970
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2384055571
Short name T403
Test name
Test status
Simulation time 14109263 ps
CPU time 0.56 seconds
Started Jan 10 01:21:29 PM PST 24
Finished Jan 10 01:21:45 PM PST 24
Peak memory 193184 kb
Host smart-b202006a-025b-43d7-863d-bcd557c9fc8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384055571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2384055571
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1380342864
Short name T632
Test name
Test status
Simulation time 1123761524 ps
CPU time 6.28 seconds
Started Jan 10 01:21:29 PM PST 24
Finished Jan 10 01:21:51 PM PST 24
Peak memory 198732 kb
Host smart-09d46298-7863-498c-b540-81faa6a1bbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380342864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1380342864
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1396234424
Short name T705
Test name
Test status
Simulation time 6577061771 ps
CPU time 58.02 seconds
Started Jan 10 01:21:08 PM PST 24
Finished Jan 10 01:22:10 PM PST 24
Peak memory 198716 kb
Host smart-342bff75-8c6e-4804-a0d7-1d6c5872cb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396234424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1396234424
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.4218077518
Short name T321
Test name
Test status
Simulation time 1657196621 ps
CPU time 43.88 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:22:38 PM PST 24
Peak memory 198772 kb
Host smart-55a32e4b-a4d0-4f00-9089-1ac80875f2bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4218077518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.4218077518
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2303388258
Short name T402
Test name
Test status
Simulation time 2244287313 ps
CPU time 104.91 seconds
Started Jan 10 01:21:38 PM PST 24
Finished Jan 10 01:23:42 PM PST 24
Peak memory 198784 kb
Host smart-36dede7f-92e7-4308-8780-efe209660d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303388258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2303388258
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.435673075
Short name T789
Test name
Test status
Simulation time 5089791756 ps
CPU time 75.93 seconds
Started Jan 10 01:21:33 PM PST 24
Finished Jan 10 01:23:09 PM PST 24
Peak memory 198796 kb
Host smart-35a1d584-cb63-456a-b649-bf50482df6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435673075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.435673075
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.4084691517
Short name T293
Test name
Test status
Simulation time 123634593 ps
CPU time 1.66 seconds
Started Jan 10 01:21:49 PM PST 24
Finished Jan 10 01:22:16 PM PST 24
Peak memory 198588 kb
Host smart-99c5250f-2057-4e2c-9a7e-77e9d0ad3d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084691517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.4084691517
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1439490225
Short name T385
Test name
Test status
Simulation time 87054614800 ps
CPU time 2175.47 seconds
Started Jan 10 01:21:30 PM PST 24
Finished Jan 10 01:58:02 PM PST 24
Peak memory 214908 kb
Host smart-f8acb0dc-c1fe-4594-b112-29badefbc3d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439490225 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1439490225
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2744825304
Short name T636
Test name
Test status
Simulation time 22934175321 ps
CPU time 90.41 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:23:19 PM PST 24
Peak memory 198936 kb
Host smart-5317a905-7b07-4561-b35f-f217e550375e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744825304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2744825304
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2602674825
Short name T417
Test name
Test status
Simulation time 457507222 ps
CPU time 0.96 seconds
Started Jan 10 01:21:30 PM PST 24
Finished Jan 10 01:21:47 PM PST 24
Peak memory 196520 kb
Host smart-b341bdbc-d9c4-4b40-881f-829b115043d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602674825 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2602674825
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2945856037
Short name T279
Test name
Test status
Simulation time 113855659216 ps
CPU time 444.88 seconds
Started Jan 10 01:21:07 PM PST 24
Finished Jan 10 01:28:36 PM PST 24
Peak memory 198756 kb
Host smart-b652388c-ea15-4a0c-95de-e6ccb4ed6734
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945856037 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.2945856037
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2360314765
Short name T575
Test name
Test status
Simulation time 3205276803 ps
CPU time 67.04 seconds
Started Jan 10 01:21:31 PM PST 24
Finished Jan 10 01:22:55 PM PST 24
Peak memory 198748 kb
Host smart-dc1c1126-e6b5-4383-b022-77679b99edbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360314765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2360314765
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.32644661
Short name T220
Test name
Test status
Simulation time 63556465442 ps
CPU time 354.66 seconds
Started Jan 10 01:23:03 PM PST 24
Finished Jan 10 01:29:15 PM PST 24
Peak memory 240984 kb
Host smart-fbc86ec2-28e7-413f-930f-50b7e152cac4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32644661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.32644661
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.2003019404
Short name T452
Test name
Test status
Simulation time 281277425907 ps
CPU time 3113.53 seconds
Started Jan 10 01:22:56 PM PST 24
Finished Jan 10 02:15:09 PM PST 24
Peak memory 246364 kb
Host smart-c54a3551-18c5-429f-8cde-db44db1c901a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003019404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.2003019404
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.1739634965
Short name T6
Test name
Test status
Simulation time 94456526147 ps
CPU time 900.63 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:38:18 PM PST 24
Peak memory 241924 kb
Host smart-15b28355-e368-491e-9ae6-38730cbf84fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739634965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.1739634965
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.286398752
Short name T383
Test name
Test status
Simulation time 139329042671 ps
CPU time 1016.54 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:40:25 PM PST 24
Peak memory 245676 kb
Host smart-58871c60-d924-40cf-b85e-518c56adea88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286398752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.286398752
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.2391909688
Short name T703
Test name
Test status
Simulation time 81414339742 ps
CPU time 1144.76 seconds
Started Jan 10 01:22:56 PM PST 24
Finished Jan 10 01:42:19 PM PST 24
Peak memory 248104 kb
Host smart-258f997d-d5d5-4b25-a671-86fe76c14af2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391909688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.2391909688
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.3876461061
Short name T124
Test name
Test status
Simulation time 166748030120 ps
CPU time 1217.34 seconds
Started Jan 10 01:23:03 PM PST 24
Finished Jan 10 01:43:39 PM PST 24
Peak memory 215376 kb
Host smart-2b73aa53-1189-4479-af33-29e3d8d9681a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876461061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.3876461061
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.800358144
Short name T326
Test name
Test status
Simulation time 50832357 ps
CPU time 0.55 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:04 PM PST 24
Peak memory 193200 kb
Host smart-12b80bb7-eb93-488e-b545-0ff68fb2e36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800358144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.800358144
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.18036034
Short name T493
Test name
Test status
Simulation time 1762900406 ps
CPU time 30.3 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:22:25 PM PST 24
Peak memory 231100 kb
Host smart-887489ab-295a-42cb-ba1e-321c6542958f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18036034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.18036034
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2605329369
Short name T679
Test name
Test status
Simulation time 2558629279 ps
CPU time 21.48 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:22:16 PM PST 24
Peak memory 198784 kb
Host smart-6d27fa57-01ea-44e6-b546-835c118d466c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605329369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2605329369
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1375484468
Short name T315
Test name
Test status
Simulation time 638089083 ps
CPU time 2.37 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:21:57 PM PST 24
Peak memory 198476 kb
Host smart-ce776906-bcce-4da5-a7de-6195ad58d79c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375484468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1375484468
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.142840822
Short name T758
Test name
Test status
Simulation time 50862478715 ps
CPU time 199.94 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:25:15 PM PST 24
Peak memory 198868 kb
Host smart-00594af2-cade-4a7f-9912-d14cdaa2ed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142840822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.142840822
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2399466125
Short name T344
Test name
Test status
Simulation time 1976274215 ps
CPU time 103.09 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:23:41 PM PST 24
Peak memory 198800 kb
Host smart-a852a74c-1e45-426b-99c2-196c233f80b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399466125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2399466125
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1331390298
Short name T56
Test name
Test status
Simulation time 604593192 ps
CPU time 3.6 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:22:01 PM PST 24
Peak memory 198612 kb
Host smart-35e1c259-d7ac-4273-9126-06a490616cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331390298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1331390298
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3521507050
Short name T245
Test name
Test status
Simulation time 26232491939 ps
CPU time 227.37 seconds
Started Jan 10 01:21:46 PM PST 24
Finished Jan 10 01:25:59 PM PST 24
Peak memory 225408 kb
Host smart-267ba3a9-c067-4db7-8223-b0cd501d6453
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521507050 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3521507050
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2652266232
Short name T578
Test name
Test status
Simulation time 109443787784 ps
CPU time 1016.32 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:38:53 PM PST 24
Peak memory 255596 kb
Host smart-9c7f024e-9d71-4dab-ad1f-76de99a92e86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2652266232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2652266232
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2912103764
Short name T607
Test name
Test status
Simulation time 100105007 ps
CPU time 0.9 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:05 PM PST 24
Peak memory 196016 kb
Host smart-2851dd18-6d6f-4250-9c68-7084ed2a679a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912103764 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2912103764
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1601184453
Short name T8
Test name
Test status
Simulation time 17832878915 ps
CPU time 398.68 seconds
Started Jan 10 01:21:36 PM PST 24
Finished Jan 10 01:28:33 PM PST 24
Peak memory 198668 kb
Host smart-a09ab693-d543-4cbf-8660-4f745517959f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601184453 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.1601184453
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1542187930
Short name T534
Test name
Test status
Simulation time 20799523120 ps
CPU time 26.25 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:22:20 PM PST 24
Peak memory 198872 kb
Host smart-6cb0084c-7285-4506-904c-0dcd18a64d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542187930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1542187930
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.2139871841
Short name T145
Test name
Test status
Simulation time 450502330907 ps
CPU time 1200.08 seconds
Started Jan 10 01:22:56 PM PST 24
Finished Jan 10 01:43:13 PM PST 24
Peak memory 223516 kb
Host smart-d17af3f4-56e1-4b68-8886-419cacb20f97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139871841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.2139871841
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.603259287
Short name T622
Test name
Test status
Simulation time 39806325731 ps
CPU time 778.27 seconds
Started Jan 10 01:22:57 PM PST 24
Finished Jan 10 01:36:11 PM PST 24
Peak memory 247724 kb
Host smart-dcc48df6-aafc-486e-b2c8-6ebcd7410683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603259287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.603259287
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.1997662401
Short name T325
Test name
Test status
Simulation time 74173791587 ps
CPU time 922.68 seconds
Started Jan 10 01:22:57 PM PST 24
Finished Jan 10 01:38:36 PM PST 24
Peak memory 214696 kb
Host smart-29612a2e-ec27-4821-8395-e2541bf9d51c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1997662401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.1997662401
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.50798393
Short name T442
Test name
Test status
Simulation time 39260211404 ps
CPU time 523.39 seconds
Started Jan 10 01:22:57 PM PST 24
Finished Jan 10 01:31:58 PM PST 24
Peak memory 215360 kb
Host smart-43003b76-a3a7-437b-8d62-74347621a167
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50798393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.50798393
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.879719446
Short name T196
Test name
Test status
Simulation time 12922687521 ps
CPU time 42.28 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:24:10 PM PST 24
Peak memory 198864 kb
Host smart-d09b338c-4915-4a23-ba3d-c1b310e4144a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879719446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.879719446
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.1268904253
Short name T727
Test name
Test status
Simulation time 560810545107 ps
CPU time 1224.91 seconds
Started Jan 10 01:23:10 PM PST 24
Finished Jan 10 01:43:53 PM PST 24
Peak memory 223204 kb
Host smart-5845c421-607e-4125-af2c-afe3b7470154
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268904253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.1268904253
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.4055288889
Short name T164
Test name
Test status
Simulation time 38027085525 ps
CPU time 161.98 seconds
Started Jan 10 01:23:03 PM PST 24
Finished Jan 10 01:26:02 PM PST 24
Peak memory 231408 kb
Host smart-0a58d844-5254-4dbf-821b-0d6b917cfbb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055288889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.4055288889
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.523403773
Short name T183
Test name
Test status
Simulation time 58027200311 ps
CPU time 787.24 seconds
Started Jan 10 01:22:57 PM PST 24
Finished Jan 10 01:36:20 PM PST 24
Peak memory 223516 kb
Host smart-2898cfa2-1fcb-48a7-811a-935dd4a4c744
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=523403773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.523403773
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.1321927727
Short name T81
Test name
Test status
Simulation time 370518604293 ps
CPU time 3396.69 seconds
Started Jan 10 01:23:04 PM PST 24
Finished Jan 10 02:19:59 PM PST 24
Peak memory 256328 kb
Host smart-0e51ee4f-6b0a-4e41-ac1b-2edd1413112a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1321927727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.1321927727
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.10855418
Short name T562
Test name
Test status
Simulation time 115485770245 ps
CPU time 1073.98 seconds
Started Jan 10 01:23:00 PM PST 24
Finished Jan 10 01:41:12 PM PST 24
Peak memory 239852 kb
Host smart-9e0c3a91-4967-4723-a67c-5ef09dad8eb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10855418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.10855418
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4290324449
Short name T593
Test name
Test status
Simulation time 35757967 ps
CPU time 0.57 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:04 PM PST 24
Peak memory 193272 kb
Host smart-a13f7f0b-6031-4ab9-a580-3047d1c74f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290324449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4290324449
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1468193443
Short name T305
Test name
Test status
Simulation time 513987764 ps
CPU time 8.93 seconds
Started Jan 10 01:21:40 PM PST 24
Finished Jan 10 01:22:08 PM PST 24
Peak memory 207012 kb
Host smart-6764f067-cac8-4f06-b11c-3ed2850a0406
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468193443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1468193443
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2753424705
Short name T286
Test name
Test status
Simulation time 4776707349 ps
CPU time 15.12 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:17 PM PST 24
Peak memory 198876 kb
Host smart-d955713c-7ef7-4e9c-a7bf-6755cac4220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753424705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2753424705
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1220625418
Short name T748
Test name
Test status
Simulation time 3048121148 ps
CPU time 154.87 seconds
Started Jan 10 01:21:43 PM PST 24
Finished Jan 10 01:24:40 PM PST 24
Peak memory 198760 kb
Host smart-675044e1-53e4-4d49-9500-ee9b3482710c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220625418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1220625418
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1819324049
Short name T581
Test name
Test status
Simulation time 7469900880 ps
CPU time 93.47 seconds
Started Jan 10 01:21:43 PM PST 24
Finished Jan 10 01:23:39 PM PST 24
Peak memory 198824 kb
Host smart-77f9b5d7-980a-49dd-800d-dc9d22f917c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819324049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1819324049
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3187552196
Short name T328
Test name
Test status
Simulation time 7316518820 ps
CPU time 91.91 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:23:36 PM PST 24
Peak memory 198816 kb
Host smart-f75e6ae9-2cc5-4131-9bc1-c914a1f4ee3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187552196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3187552196
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1419038310
Short name T451
Test name
Test status
Simulation time 2112428836 ps
CPU time 4.14 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:22:09 PM PST 24
Peak memory 198776 kb
Host smart-fdacd30e-92c2-4b21-809a-29b3cc7ef2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419038310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1419038310
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1233536905
Short name T713
Test name
Test status
Simulation time 91503055161 ps
CPU time 583.02 seconds
Started Jan 10 01:21:39 PM PST 24
Finished Jan 10 01:31:41 PM PST 24
Peak memory 222816 kb
Host smart-b111c700-5c7d-412c-9a2c-d0b290d87f03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233536905 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1233536905
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.564902660
Short name T300
Test name
Test status
Simulation time 25787854713 ps
CPU time 366.72 seconds
Started Jan 10 01:21:42 PM PST 24
Finished Jan 10 01:28:10 PM PST 24
Peak memory 221020 kb
Host smart-fb68864d-fe05-4201-8027-0dcb3a1c13d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564902660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.564902660
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2289275875
Short name T308
Test name
Test status
Simulation time 202595775 ps
CPU time 1.12 seconds
Started Jan 10 01:21:37 PM PST 24
Finished Jan 10 01:21:56 PM PST 24
Peak memory 197200 kb
Host smart-b620cd76-8756-47f0-8f45-e6010f60a3d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289275875 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2289275875
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.668559641
Short name T557
Test name
Test status
Simulation time 1780773896 ps
CPU time 29.17 seconds
Started Jan 10 01:21:41 PM PST 24
Finished Jan 10 01:22:33 PM PST 24
Peak memory 198848 kb
Host smart-a407c0d9-3225-482d-8529-a9c6a631fe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668559641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.668559641
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.766220262
Short name T550
Test name
Test status
Simulation time 273499840404 ps
CPU time 680.42 seconds
Started Jan 10 01:23:10 PM PST 24
Finished Jan 10 01:34:49 PM PST 24
Peak memory 223452 kb
Host smart-f06e53cf-1471-443c-afeb-5b0afebe4828
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=766220262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.766220262
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.273467606
Short name T400
Test name
Test status
Simulation time 40279664415 ps
CPU time 725.64 seconds
Started Jan 10 01:23:10 PM PST 24
Finished Jan 10 01:35:34 PM PST 24
Peak memory 231424 kb
Host smart-fcf637c4-3c1d-4425-a476-1fb6fe04a8e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273467606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.273467606
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.3682972348
Short name T469
Test name
Test status
Simulation time 38964586766 ps
CPU time 546.11 seconds
Started Jan 10 01:23:08 PM PST 24
Finished Jan 10 01:32:32 PM PST 24
Peak memory 239896 kb
Host smart-6f96a703-909a-4dc4-93bf-2695ef8b6d72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682972348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.3682972348
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.2667236921
Short name T629
Test name
Test status
Simulation time 618553946263 ps
CPU time 1142.4 seconds
Started Jan 10 01:23:03 PM PST 24
Finished Jan 10 01:42:23 PM PST 24
Peak memory 247064 kb
Host smart-f5317521-972f-403a-8f14-4d711aaa0e83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667236921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.2667236921
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.4106981558
Short name T248
Test name
Test status
Simulation time 41251220332 ps
CPU time 638.32 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:33:53 PM PST 24
Peak memory 224548 kb
Host smart-77463411-86e7-4789-bdca-c6338fb55438
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106981558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.4106981558
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.1434354932
Short name T785
Test name
Test status
Simulation time 221014284863 ps
CPU time 2063.8 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:57:39 PM PST 24
Peak memory 259892 kb
Host smart-e62e4123-0162-48be-9069-9c56831fc497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434354932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.1434354932
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1798453793
Short name T132
Test name
Test status
Simulation time 28170495164 ps
CPU time 1347.53 seconds
Started Jan 10 01:22:58 PM PST 24
Finished Jan 10 01:45:43 PM PST 24
Peak memory 215388 kb
Host smart-72e8178b-fa61-42aa-b422-012a38149fbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1798453793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.1798453793
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.3491472483
Short name T635
Test name
Test status
Simulation time 131840852986 ps
CPU time 175.28 seconds
Started Jan 10 01:23:04 PM PST 24
Finished Jan 10 01:26:17 PM PST 24
Peak memory 229980 kb
Host smart-e1d5d0ea-968a-4f8c-b2c8-4172cce3e026
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491472483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.3491472483
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.2301433566
Short name T796
Test name
Test status
Simulation time 92738180363 ps
CPU time 3759.51 seconds
Started Jan 10 01:22:56 PM PST 24
Finished Jan 10 02:25:52 PM PST 24
Peak memory 255900 kb
Host smart-53e6b078-d52a-43ac-823d-558dc49185de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301433566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.2301433566
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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