Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13406509	1			T1	13450		T3	30		T4	35
all_values[1]	13406509	1			T1	13450		T3	30		T4	35
all_values[2]	13406509	1			T1	13450		T3	30		T4	35

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106118

1

T1

312

T10

95

T8

245

auto[1]

40113409

1

T1

40038

T3

90

T4

105

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28607917

1

T1

29323

T3

69

T4

80

auto[1]

11611610

1

T1

11027

T3

21

T4

25

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38006	1			T10	47		T5	18		T20	2085
all_values[0]	auto[0]	auto[1]	454	1			T10	5		T5	11		T20	4
all_values[0]	auto[1]	auto[0]	13323377	1			T1	13399		T3	26		T4	31
all_values[0]	auto[1]	auto[1]	44672	1			T1	51		T3	4		T4	4
all_values[1]	auto[0]	auto[0]	25051	1			T1	53		T10	9		T5	20
all_values[1]	auto[0]	auto[1]	13339	1			T1	259		T10	14		T5	13
all_values[1]	auto[1]	auto[0]	7303513	1			T1	2421		T3	13		T4	14
all_values[1]	auto[1]	auto[1]	6064606	1			T1	10717		T3	17		T4	21
all_values[2]	auto[0]	auto[0]	23096	1			T10	18		T8	245		T12	14
all_values[2]	auto[0]	auto[1]	6172	1			T10	2		T5	16		T101	723
all_values[2]	auto[1]	auto[0]	7894874	1			T1	13450		T3	30		T4	35
all_values[2]	auto[1]	auto[1]	5482367	1			T10	116657		T26	28220		T27	11659