Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6468177

1

T1

6408

T3

25

T4

30

auto[1]

2514088

1

T1

6937

T10

18369

T11

29

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2586482

1

T1

7190

T10

18144

T11

26

auto[1]

6395783

1

T1

6155

T3

25

T4

30

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5786432

1

T1

7072

T10

128293

T11

17

auto[1]

3195833

1

T1

6273

T3

25

T4

30

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5625333	1			T1	12043		T3	21		T4	24
fifo_depth[1]	443112	1			T1	698		T3	3		T4	3
fifo_depth[2]	380885	1			T1	386		T3	1		T4	2
fifo_depth[3]	315929	1			T1	155		T4	1		T10	1410
fifo_depth[4]	294300	1			T1	47		T10	1015		T11	3
fifo_depth[5]	254106	1			T1	13		T10	292		T11	3
fifo_depth[6]	254235	1			T1	3		T10	322		T11	4
fifo_depth[7]	218037	1			T10	94		T11	1		T8	1064
fifo_depth[8]	243812	1			T10	273		T11	2		T8	823
fifo_depth[9]	146966	1			T10	31		T8	644		T9	455
fifo_depth[10]	141071	1			T10	18		T8	423		T9	302
fifo_depth[11]	86137	1			T10	3		T8	263		T9	164
fifo_depth[12]	136561	1			T10	6		T8	135		T9	97
fifo_depth[13]	61197	1			T10	1		T8	47		T9	53
fifo_depth[14]	99515	1			T8	26		T9	21		T5	11472
fifo_depth[15]	57915	1			T8	8		T9	7		T5	5672
fifo_depth[16]	223154	1			T9	6		T5	20929		T20	9

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3356932

1

T1

1302

T3

4

T4

6

auto[1]

5625333

1

T1

12043

T3

21

T4

24

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8759111

1

T1

13345

T3

25

T4

30

auto[1]

223154

1

T9

6

T5

20929

T20

9

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

244389

1

T1

107

T10

1066

T8

981

auto[0]

auto[0]

auto[0]

auto[1]

230610

1

T1

275

T10

346

T8

1888

auto[0]

auto[0]

auto[1]

auto[0]

1021916

1

T1

91

T10

8067

T8

728

auto[0]

auto[0]

auto[1]

auto[1]

225305

1

T1

222

T10

469

T8

2092

auto[0]

auto[1]

auto[0]

auto[0]

415872

1

T1

230

T10

1037

T8

1026

auto[0]

auto[1]

auto[0]

auto[1]

403150

1

T1

99

T10

727

T11

16

auto[0]

auto[1]

auto[1]

auto[0]

427302

1

T1

183

T3

4

T4

6

auto[0]

auto[1]

auto[1]

auto[1]

388388

1

T1

95

T10

1215

T11

5

auto[1]

auto[0]

auto[0]

auto[0]

260285

1

T1

1007

T10

4119

T8

616

auto[1]

auto[0]

auto[0]

auto[1]

241696

1

T1

2477

T10

1942

T11

7

auto[1]

auto[0]

auto[1]

auto[0]

3305545

1

T1

897

T10

108736

T11

10

auto[1]

auto[0]

auto[1]

auto[1]

256686

1

T1

1996

T10

3548

T8

1162

auto[1]

auto[1]

auto[0]

auto[0]

392923

1

T1

2106

T10

5159

T11

2

auto[1]

auto[1]

auto[0]

auto[1]

397557

1

T1

889

T10

3748

T11

1

auto[1]

auto[1]

auto[1]

auto[0]

399945

1

T1

1787

T3

21

T4

24

auto[1]

auto[1]

auto[1]

auto[1]

370696

1

T1

884

T10

6374

T8

498

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

475714

1

T1

1114

T10

5185

T8

1597

auto[0]

auto[0]

auto[0]

auto[1]

447307

1

T1

2752

T10

2288

T11

7

auto[0]

auto[0]

auto[1]

auto[0]

4295326

1

T1

988

T10

116803

T11

10

auto[0]

auto[0]

auto[1]

auto[1]

451285

1

T1

2218

T10

4017

T8

3254

auto[0]

auto[1]

auto[0]

auto[0]

781286

1

T1

2336

T10

6196

T11

2

auto[0]

auto[1]

auto[0]

auto[1]

777681

1

T1

988

T10

4475

T11

17

auto[0]

auto[1]

auto[1]

auto[0]

797607

1

T1

1970

T3

25

T4

30

auto[0]

auto[1]

auto[1]

auto[1]

732905

1

T1

979

T10

7589

T11

5

auto[1]

auto[0]

auto[0]

auto[0]

28960

1

T9

1

T5

2242

T23

2

auto[1]

auto[0]

auto[0]

auto[1]

24999

1

T9

1

T5

1615

T28

1

auto[1]

auto[0]

auto[1]

auto[0]

32135

1

T5

1667

T18

1

T23

1

auto[1]

auto[0]

auto[1]

auto[1]

30706

1

T5

3433

T137

1

T32

1

auto[1]

auto[1]

auto[0]

auto[0]

27509

1

T5

2176

T20

2

T19

1

auto[1]

auto[1]

auto[0]

auto[1]

23026

1

T5

1859

T20

1

T103

1

auto[1]

auto[1]

auto[1]

auto[0]

29640

1

T5

3792

T20

5

T28

1

auto[1]

auto[1]

auto[1]

auto[1]

26179

1

T9

4

T5

4145

T20

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	260285	1			T1	1007		T10	4119		T8	616
fifo_depth[0]	auto[0]	auto[0]	auto[1]	241696	1			T1	2477		T10	1942		T11	7
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3305545	1			T1	897		T10	108736		T11	10
fifo_depth[0]	auto[0]	auto[1]	auto[1]	256686	1			T1	1996		T10	3548		T8	1162
fifo_depth[0]	auto[1]	auto[0]	auto[0]	392923	1			T1	2106		T10	5159		T11	2
fifo_depth[0]	auto[1]	auto[0]	auto[1]	397557	1			T1	889		T10	3748		T11	1
fifo_depth[0]	auto[1]	auto[1]	auto[0]	399945	1			T1	1787		T3	21		T4	24
fifo_depth[0]	auto[1]	auto[1]	auto[1]	370696	1			T1	884		T10	6374		T8	498
fifo_depth[1]	auto[0]	auto[0]	auto[0]	21434	1			T1	54		T10	239		T8	115
fifo_depth[1]	auto[0]	auto[0]	auto[1]	20076	1			T1	154		T10	69		T8	223
fifo_depth[1]	auto[0]	auto[1]	auto[0]	210311	1			T1	51		T10	4780		T8	75
fifo_depth[1]	auto[0]	auto[1]	auto[1]	21026	1			T1	125		T10	147		T8	240
fifo_depth[1]	auto[1]	auto[0]	auto[0]	43152	1			T1	114		T10	364		T8	118
fifo_depth[1]	auto[1]	auto[0]	auto[1]	43192	1			T1	56		T10	221		T11	3
fifo_depth[1]	auto[1]	auto[1]	auto[0]	43914	1			T1	101		T3	3		T4	3
fifo_depth[1]	auto[1]	auto[1]	auto[1]	40007	1			T1	43		T10	398		T11	1
fifo_depth[2]	auto[0]	auto[0]	auto[0]	19018	1			T1	34		T10	351		T8	101
fifo_depth[2]	auto[0]	auto[0]	auto[1]	18958	1			T1	78		T10	69		T8	212
fifo_depth[2]	auto[0]	auto[1]	auto[0]	168367	1			T1	24		T10	2086		T8	78
fifo_depth[2]	auto[0]	auto[1]	auto[1]	18554	1			T1	50		T10	133		T8	230
fifo_depth[2]	auto[1]	auto[0]	auto[0]	39737	1			T1	85		T10	278		T8	110
fifo_depth[2]	auto[1]	auto[0]	auto[1]	39945	1			T1	26		T10	148		T11	4
fifo_depth[2]	auto[1]	auto[1]	auto[0]	39515	1			T1	57		T3	1		T4	2
fifo_depth[2]	auto[1]	auto[1]	auto[1]	36791	1			T1	32		T10	293		T8	98
fifo_depth[3]	auto[0]	auto[0]	auto[0]	15568	1			T1	12		T10	98		T8	107
fifo_depth[3]	auto[0]	auto[0]	auto[1]	16001	1			T1	30		T10	37		T8	199
fifo_depth[3]	auto[0]	auto[1]	auto[0]	129966	1			T1	9		T10	787		T8	90
fifo_depth[3]	auto[0]	auto[1]	auto[1]	15221	1			T1	33		T10	59		T8	255
fifo_depth[3]	auto[1]	auto[0]	auto[0]	35567	1			T1	25		T10	133		T8	115
fifo_depth[3]	auto[1]	auto[0]	auto[1]	35860	1			T1	13		T10	102		T11	3
fifo_depth[3]	auto[1]	auto[1]	auto[0]	35404	1			T1	18		T4	1		T10	43
fifo_depth[3]	auto[1]	auto[1]	auto[1]	32342	1			T1	15		T10	151		T11	1
fifo_depth[4]	auto[0]	auto[0]	auto[0]	18098	1			T1	5		T10	206		T8	114
fifo_depth[4]	auto[0]	auto[0]	auto[1]	17321	1			T1	9		T10	95		T8	216
fifo_depth[4]	auto[0]	auto[1]	auto[0]	99104	1			T1	7		T10	272		T8	78
fifo_depth[4]	auto[0]	auto[1]	auto[1]	17098	1			T1	11		T10	56		T8	230
fifo_depth[4]	auto[1]	auto[0]	auto[0]	36576	1			T1	4		T10	119		T8	111
fifo_depth[4]	auto[1]	auto[0]	auto[1]	35750	1			T1	2		T10	95		T11	1
fifo_depth[4]	auto[1]	auto[1]	auto[0]	36869	1			T1	6		T10	23		T11	1
fifo_depth[4]	auto[1]	auto[1]	auto[1]	33484	1			T1	3		T10	149		T11	1
fifo_depth[5]	auto[0]	auto[0]	auto[0]	14589	1			T1	2		T10	33		T8	102
fifo_depth[5]	auto[0]	auto[0]	auto[1]	14459	1			T1	1		T10	17		T8	211
fifo_depth[5]	auto[0]	auto[1]	auto[0]	80852	1			T10	80		T8	81		T9	122
fifo_depth[5]	auto[0]	auto[1]	auto[1]	13798	1			T1	3		T10	23		T8	239
fifo_depth[5]	auto[1]	auto[0]	auto[0]	33263	1			T1	2		T10	23		T8	120
fifo_depth[5]	auto[1]	auto[0]	auto[1]	33135	1			T1	2		T10	40		T11	2
fifo_depth[5]	auto[1]	auto[1]	auto[0]	33236	1			T1	1		T10	14		T11	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	30774	1			T1	2		T10	62		T8	93
fifo_depth[6]	auto[0]	auto[0]	auto[0]	16461	1			T10	69		T8	107		T9	179
fifo_depth[6]	auto[0]	auto[0]	auto[1]	15855	1			T1	3		T10	26		T8	221
fifo_depth[6]	auto[0]	auto[1]	auto[0]	72244	1			T10	28		T8	75		T9	119
fifo_depth[6]	auto[0]	auto[1]	auto[1]	16192	1			T10	19		T8	212		T9	36
fifo_depth[6]	auto[1]	auto[0]	auto[0]	34865	1			T10	51		T8	122		T9	213
fifo_depth[6]	auto[1]	auto[0]	auto[1]	33134	1			T10	39		T11	1		T8	208
fifo_depth[6]	auto[1]	auto[1]	auto[0]	34164	1			T10	18		T11	1		T8	83
fifo_depth[6]	auto[1]	auto[1]	auto[1]	31320	1			T10	72		T11	2		T8	96
fifo_depth[7]	auto[0]	auto[0]	auto[0]	13748	1			T10	12		T8	112		T9	147
fifo_depth[7]	auto[0]	auto[0]	auto[1]	13603	1			T10	9		T8	181		T9	29
fifo_depth[7]	auto[0]	auto[1]	auto[0]	56818	1			T10	9		T8	73		T9	112
fifo_depth[7]	auto[0]	auto[1]	auto[1]	13537	1			T10	11		T8	204		T9	43
fifo_depth[7]	auto[1]	auto[0]	auto[0]	31205	1			T10	6		T8	100		T9	193
fifo_depth[7]	auto[1]	auto[0]	auto[1]	30352	1			T10	13		T8	206		T9	29
fifo_depth[7]	auto[1]	auto[1]	auto[0]	30903	1			T10	9		T11	1		T8	91
fifo_depth[7]	auto[1]	auto[1]	auto[1]	27871	1			T10	25		T8	97		T9	66
fifo_depth[8]	auto[0]	auto[0]	auto[0]	20840	1			T10	44		T8	81		T9	118
fifo_depth[8]	auto[0]	auto[0]	auto[1]	17218	1			T10	22		T8	142		T9	27
fifo_depth[8]	auto[0]	auto[1]	auto[0]	50464	1			T10	24		T8	50		T9	90
fifo_depth[8]	auto[0]	auto[1]	auto[1]	18069	1			T10	14		T8	184		T9	36
fifo_depth[8]	auto[1]	auto[0]	auto[0]	32931	1			T10	57		T8	78		T9	165
fifo_depth[8]	auto[1]	auto[0]	auto[1]	35942	1			T10	61		T11	2		T8	141
fifo_depth[8]	auto[1]	auto[1]	auto[0]	37104	1			T10	3		T8	71		T9	72
fifo_depth[8]	auto[1]	auto[1]	auto[1]	31244	1			T10	48		T8	76		T9	45
fifo_depth[9]	auto[0]	auto[0]	auto[0]	10606	1			T10	9		T8	59		T9	95
fifo_depth[9]	auto[0]	auto[0]	auto[1]	10905	1			T10	1		T8	117		T9	22
fifo_depth[9]	auto[0]	auto[1]	auto[0]	30961	1			T10	1		T8	53		T9	69
fifo_depth[9]	auto[0]	auto[1]	auto[1]	9837	1			T10	6		T8	115		T9	20
fifo_depth[9]	auto[1]	auto[0]	auto[0]	21708	1			T8	71		T9	140		T5	1012
fifo_depth[9]	auto[1]	auto[0]	auto[1]	21161	1			T10	4		T8	126		T9	14
fifo_depth[9]	auto[1]	auto[1]	auto[0]	21979	1			T10	4		T8	54		T9	53
fifo_depth[9]	auto[1]	auto[1]	auto[1]	19809	1			T10	6		T8	49		T9	42
fifo_depth[10]	auto[0]	auto[0]	auto[0]	14421	1			T10	5		T8	38		T9	65
fifo_depth[10]	auto[0]	auto[0]	auto[1]	12919	1			T10	1		T8	82		T9	12
fifo_depth[10]	auto[0]	auto[1]	auto[0]	25084	1			T8	34		T9	51		T14	5
fifo_depth[10]	auto[0]	auto[1]	auto[1]	10897	1			T10	1		T8	84		T9	14
fifo_depth[10]	auto[1]	auto[0]	auto[0]	19181	1			T10	3		T8	36		T9	70
fifo_depth[10]	auto[1]	auto[0]	auto[1]	19129	1			T10	2		T8	89		T9	17
fifo_depth[10]	auto[1]	auto[1]	auto[0]	21021	1			T8	19		T9	34		T14	1
fifo_depth[10]	auto[1]	auto[1]	auto[1]	18419	1			T10	6		T8	41		T9	39
fifo_depth[11]	auto[0]	auto[0]	auto[0]	8728	1			T8	21		T9	40		T5	1098
fifo_depth[11]	auto[0]	auto[0]	auto[1]	8523	1			T8	51		T9	4		T5	528
fifo_depth[11]	auto[0]	auto[1]	auto[0]	15080	1			T8	20		T9	19		T5	1169
fifo_depth[11]	auto[0]	auto[1]	auto[1]	6594	1			T8	54		T9	14		T5	831
fifo_depth[11]	auto[1]	auto[0]	auto[0]	11962	1			T8	25		T9	50		T5	827
fifo_depth[11]	auto[1]	auto[0]	auto[1]	11735	1			T10	2		T8	48		T9	3
fifo_depth[11]	auto[1]	auto[1]	auto[0]	12264	1			T8	22		T9	13		T5	1030
fifo_depth[11]	auto[1]	auto[1]	auto[1]	11251	1			T10	1		T8	22		T9	21
fifo_depth[12]	auto[0]	auto[0]	auto[0]	16092	1			T8	14		T9	14		T5	2118
fifo_depth[12]	auto[0]	auto[0]	auto[1]	13931	1			T8	18		T9	3		T5	1151
fifo_depth[12]	auto[0]	auto[1]	auto[0]	19931	1			T8	13		T9	13		T5	1733
fifo_depth[12]	auto[0]	auto[1]	auto[1]	12628	1			T8	30		T9	6		T5	1698
fifo_depth[12]	auto[1]	auto[0]	auto[0]	17316	1			T10	3		T8	14		T9	30
fifo_depth[12]	auto[1]	auto[0]	auto[1]	17353	1			T8	33		T9	4		T5	953
fifo_depth[12]	auto[1]	auto[1]	auto[0]	19422	1			T8	4		T9	14		T5	2502
fifo_depth[12]	auto[1]	auto[1]	auto[1]	19888	1			T10	3		T8	9		T9	13
fifo_depth[13]	auto[0]	auto[0]	auto[0]	7443	1			T8	7		T9	7		T5	1216
fifo_depth[13]	auto[0]	auto[0]	auto[1]	7377	1			T8	8		T9	2		T5	354
fifo_depth[13]	auto[0]	auto[1]	auto[0]	8853	1			T8	4		T9	7		T5	883
fifo_depth[13]	auto[0]	auto[1]	auto[1]	6134	1			T8	7		T9	5		T5	753
fifo_depth[13]	auto[1]	auto[0]	auto[0]	7887	1			T8	4		T9	14		T5	676
fifo_depth[13]	auto[1]	auto[0]	auto[1]	7103	1			T8	10		T9	4		T5	456
fifo_depth[13]	auto[1]	auto[1]	auto[0]	8255	1			T8	1		T9	4		T5	910
fifo_depth[13]	auto[1]	auto[1]	auto[1]	8145	1			T10	1		T8	6		T9	10
fifo_depth[14]	auto[0]	auto[0]	auto[0]	11998	1			T8	2		T9	3		T5	1809
fifo_depth[14]	auto[0]	auto[0]	auto[1]	11783	1			T8	4		T9	1		T5	1026
fifo_depth[14]	auto[0]	auto[1]	auto[0]	13627	1			T8	3		T5	1686		T18	1
fifo_depth[14]	auto[0]	auto[1]	auto[1]	9434	1			T8	5		T9	2		T5	1421
fifo_depth[14]	auto[1]	auto[0]	auto[0]	14377	1			T8	2		T9	9		T5	1455
fifo_depth[14]	auto[1]	auto[0]	auto[1]	10153	1			T8	5		T9	1		T5	799
fifo_depth[14]	auto[1]	auto[1]	auto[0]	14322	1			T8	2		T5	1623		T20	16
fifo_depth[14]	auto[1]	auto[1]	auto[1]	13821	1			T8	3		T9	5		T5	1653
fifo_depth[15]	auto[0]	auto[0]	auto[0]	6385	1			T8	1		T9	1		T5	973
fifo_depth[15]	auto[0]	auto[0]	auto[1]	6682	1			T8	3		T5	351		T31	2
fifo_depth[15]	auto[0]	auto[1]	auto[0]	8119	1			T8	1		T9	1		T5	986
fifo_depth[15]	auto[0]	auto[1]	auto[1]	5580	1			T8	3		T5	501		T28	2
fifo_depth[15]	auto[1]	auto[0]	auto[0]	8636	1			T5	862		T20	2		T101	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	6180	1			T5	595		T20	3		T38	3
fifo_depth[15]	auto[1]	auto[1]	auto[0]	9290	1			T5	854		T20	6		T124	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	7043	1			T9	5		T5	550		T20	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	28960	1			T9	1		T5	2242		T23	2
fifo_depth[16]	auto[0]	auto[0]	auto[1]	24999	1			T9	1		T5	1615		T28	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	32135	1			T5	1667		T18	1		T23	1
fifo_depth[16]	auto[0]	auto[1]	auto[1]	30706	1			T5	3433		T137	1		T32	1
fifo_depth[16]	auto[1]	auto[0]	auto[0]	27509	1			T5	2176		T20	2		T19	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	23026	1			T5	1859		T20	1		T103	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	29640	1			T5	3792		T20	5		T28	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	26179	1			T9	4		T5	4145		T20	1