Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13406509	1			T1	13450		T3	30		T4	35
all_pins[1]	13406509	1			T1	13450		T3	30		T4	35
all_pins[2]	13406509	1			T1	13450		T3	30		T4	35

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	28561313	1			T1	29505		T3	69		T4	79
values[0x1]	11658214	1			T1	10845		T3	21		T4	26
transitions[0x0=>0x1]	10169557	1			T1	10817		T3	19		T4	24
transitions[0x1=>0x0]	10169572	1			T1	10817		T3	19		T4	24

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13360841	1			T1	13397		T3	26		T4	31
all_pins[0]	values[0x1]	45668	1			T1	53		T3	4		T4	4
all_pins[0]	transitions[0x0=>0x1]	45596	1			T1	53		T3	4		T4	4
all_pins[0]	transitions[0x1=>0x0]	5482310	1			T10	116657		T26	28220		T27	11659
all_pins[1]	values[0x0]	7276330	1			T1	2658		T3	13		T4	13
all_pins[1]	values[0x1]	6130179	1			T1	10792		T3	17		T4	22
all_pins[1]	transitions[0x0=>0x1]	6094538	1			T1	10764		T3	15		T4	20
all_pins[1]	transitions[0x1=>0x0]	10027	1			T1	25		T3	2		T4	2
all_pins[2]	values[0x0]	7924142	1			T1	13450		T3	30		T4	35
all_pins[2]	values[0x1]	5482367	1			T10	116657		T26	28220		T27	11659
all_pins[2]	transitions[0x0=>0x1]	4029423	1			T10	79404		T26	22330		T27	9741
all_pins[2]	transitions[0x1=>0x0]	4677235	1			T1	10792		T3	17		T4	22