Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 957 1 T10 10 T5 55 T41 14
all_values[1] 957 1 T10 10 T5 55 T41 14
all_values[2] 957 1 T10 10 T5 55 T41 14


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1437 1 T10 17 T5 72 T41 22
auto[1] 1434 1 T10 13 T5 93 T41 20


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1027 1 T10 14 T5 57 T41 9
auto[1] 1844 1 T10 16 T5 108 T41 33


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1586 1 T10 19 T5 88 T41 21
auto[1] 1285 1 T10 11 T5 77 T41 21


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 180 1 T10 4 T5 10 T41 2
all_values[0] auto[0] auto[0] auto[1] 106 1 T10 1 T5 6 T41 2
all_values[0] auto[0] auto[1] auto[0] 145 1 T10 1 T5 7 T108 2
all_values[0] auto[0] auto[1] auto[1] 93 1 T5 7 T41 2 T108 2
all_values[0] auto[1] auto[0] auto[1] 214 1 T10 1 T5 7 T41 4
all_values[0] auto[1] auto[1] auto[1] 219 1 T10 3 T5 18 T41 4
all_values[1] auto[0] auto[0] auto[0] 185 1 T10 4 T5 8 T41 3
all_values[1] auto[0] auto[0] auto[1] 84 1 T5 5 T41 1 T108 3
all_values[1] auto[0] auto[1] auto[0] 167 1 T10 2 T5 10 T41 1
all_values[1] auto[0] auto[1] auto[1] 97 1 T10 2 T5 4 T41 3
all_values[1] auto[1] auto[0] auto[1] 206 1 T10 2 T5 12 T41 4
all_values[1] auto[1] auto[1] auto[1] 218 1 T5 16 T41 2 T108 7
all_values[2] auto[0] auto[0] auto[0] 161 1 T10 1 T5 6 T41 3
all_values[2] auto[0] auto[0] auto[1] 85 1 T10 2 T5 6 T108 4
all_values[2] auto[0] auto[1] auto[0] 189 1 T10 2 T5 16 T108 4
all_values[2] auto[0] auto[1] auto[1] 94 1 T5 3 T41 4 T108 1
all_values[2] auto[1] auto[0] auto[1] 216 1 T10 2 T5 12 T41 3
all_values[2] auto[1] auto[1] auto[1] 212 1 T10 3 T5 12 T41 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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