Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.38 99.55 98.55 100.00 100.00 98.47 99.49 99.59


Total test records in report: 720
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T532 /workspace/coverage/default/4.hmac_long_msg.1978163102 Feb 18 01:45:41 PM PST 24 Feb 18 01:46:17 PM PST 24 8850094010 ps
T533 /workspace/coverage/default/18.hmac_alert_test.1414039038 Feb 18 01:46:26 PM PST 24 Feb 18 01:46:29 PM PST 24 12665616 ps
T534 /workspace/coverage/default/43.hmac_stress_all.2425687314 Feb 18 01:47:59 PM PST 24 Feb 18 01:54:17 PM PST 24 14444806595 ps
T535 /workspace/coverage/default/47.hmac_alert_test.3248934744 Feb 18 01:48:10 PM PST 24 Feb 18 01:48:14 PM PST 24 38503361 ps
T536 /workspace/coverage/default/42.hmac_smoke.1491519460 Feb 18 01:47:57 PM PST 24 Feb 18 01:48:06 PM PST 24 355499346 ps
T537 /workspace/coverage/default/25.hmac_wipe_secret.678834044 Feb 18 01:46:48 PM PST 24 Feb 18 01:48:07 PM PST 24 37766340441 ps
T538 /workspace/coverage/default/15.hmac_stress_all.664868527 Feb 18 01:46:07 PM PST 24 Feb 18 02:02:22 PM PST 24 20479201636 ps
T539 /workspace/coverage/default/24.hmac_alert_test.3392421132 Feb 18 01:46:40 PM PST 24 Feb 18 01:46:43 PM PST 24 16504559 ps
T540 /workspace/coverage/default/41.hmac_test_sha_vectors.198465484 Feb 18 01:47:51 PM PST 24 Feb 18 01:54:55 PM PST 24 124146461072 ps
T541 /workspace/coverage/default/40.hmac_test_sha_vectors.2004554921 Feb 18 01:47:40 PM PST 24 Feb 18 01:55:18 PM PST 24 17453869494 ps
T542 /workspace/coverage/default/49.hmac_datapath_stress.2220945082 Feb 18 01:48:25 PM PST 24 Feb 18 01:50:23 PM PST 24 9601368969 ps
T543 /workspace/coverage/default/3.hmac_alert_test.4183756547 Feb 18 01:45:31 PM PST 24 Feb 18 01:45:35 PM PST 24 17752842 ps
T544 /workspace/coverage/default/43.hmac_test_sha_vectors.2209382082 Feb 18 01:48:05 PM PST 24 Feb 18 01:55:03 PM PST 24 104768122546 ps
T545 /workspace/coverage/default/6.hmac_wipe_secret.1119467699 Feb 18 01:45:33 PM PST 24 Feb 18 01:45:44 PM PST 24 119353431 ps
T546 /workspace/coverage/default/37.hmac_stress_all.976535475 Feb 18 01:47:32 PM PST 24 Feb 18 01:47:48 PM PST 24 6356623536 ps
T547 /workspace/coverage/default/1.hmac_test_hmac_vectors.4245744721 Feb 18 01:45:23 PM PST 24 Feb 18 01:45:32 PM PST 24 105148020 ps
T548 /workspace/coverage/default/2.hmac_wipe_secret.1190847773 Feb 18 01:45:35 PM PST 24 Feb 18 01:45:42 PM PST 24 263941223 ps
T549 /workspace/coverage/default/0.hmac_datapath_stress.414974679 Feb 18 01:45:19 PM PST 24 Feb 18 01:47:37 PM PST 24 5209948446 ps
T550 /workspace/coverage/default/45.hmac_error.894540149 Feb 18 01:48:03 PM PST 24 Feb 18 01:49:09 PM PST 24 4540086379 ps
T551 /workspace/coverage/default/47.hmac_test_hmac_vectors.3064527490 Feb 18 01:48:10 PM PST 24 Feb 18 01:48:16 PM PST 24 109580568 ps
T552 /workspace/coverage/default/11.hmac_error.3478976647 Feb 18 01:45:38 PM PST 24 Feb 18 01:46:08 PM PST 24 1382375774 ps
T553 /workspace/coverage/default/29.hmac_error.433011537 Feb 18 01:47:01 PM PST 24 Feb 18 01:47:38 PM PST 24 2946746498 ps
T554 /workspace/coverage/default/29.hmac_wipe_secret.338215547 Feb 18 01:47:04 PM PST 24 Feb 18 01:48:11 PM PST 24 4996498018 ps
T123 /workspace/coverage/default/18.hmac_burst_wr.3087184278 Feb 18 01:46:29 PM PST 24 Feb 18 01:47:07 PM PST 24 8365719384 ps
T555 /workspace/coverage/default/9.hmac_error.1779592505 Feb 18 01:45:41 PM PST 24 Feb 18 01:46:25 PM PST 24 15889886541 ps
T556 /workspace/coverage/default/12.hmac_burst_wr.416627819 Feb 18 01:45:52 PM PST 24 Feb 18 01:46:37 PM PST 24 34875264169 ps
T557 /workspace/coverage/default/18.hmac_wipe_secret.747002286 Feb 18 01:46:23 PM PST 24 Feb 18 01:46:50 PM PST 24 1948182501 ps
T558 /workspace/coverage/default/14.hmac_datapath_stress.3058373961 Feb 18 01:45:53 PM PST 24 Feb 18 01:46:54 PM PST 24 6735074167 ps
T559 /workspace/coverage/default/43.hmac_burst_wr.2486067981 Feb 18 01:47:59 PM PST 24 Feb 18 01:49:03 PM PST 24 1200136819 ps
T560 /workspace/coverage/default/22.hmac_test_sha_vectors.2259332756 Feb 18 01:46:34 PM PST 24 Feb 18 01:52:34 PM PST 24 14615855188 ps
T561 /workspace/coverage/default/41.hmac_back_pressure.3591245852 Feb 18 01:47:51 PM PST 24 Feb 18 01:48:11 PM PST 24 330588288 ps
T562 /workspace/coverage/default/37.hmac_test_sha_vectors.3102963736 Feb 18 01:47:32 PM PST 24 Feb 18 01:55:34 PM PST 24 114148058531 ps
T563 /workspace/coverage/default/36.hmac_smoke.2916090884 Feb 18 01:47:28 PM PST 24 Feb 18 01:47:34 PM PST 24 1506600617 ps
T564 /workspace/coverage/default/6.hmac_test_hmac_vectors.263381721 Feb 18 01:45:42 PM PST 24 Feb 18 01:45:48 PM PST 24 48421792 ps
T565 /workspace/coverage/default/30.hmac_back_pressure.831407049 Feb 18 01:47:03 PM PST 24 Feb 18 01:47:11 PM PST 24 146691617 ps
T566 /workspace/coverage/default/47.hmac_test_sha_vectors.2118322061 Feb 18 01:48:09 PM PST 24 Feb 18 01:54:04 PM PST 24 14840597360 ps
T567 /workspace/coverage/default/42.hmac_alert_test.2310503760 Feb 18 01:47:58 PM PST 24 Feb 18 01:48:05 PM PST 24 73772424 ps
T568 /workspace/coverage/default/18.hmac_test_sha_vectors.2972736164 Feb 18 01:46:22 PM PST 24 Feb 18 01:51:52 PM PST 24 46863883278 ps
T63 /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.3938079557 Feb 18 01:48:05 PM PST 24 Feb 18 02:39:51 PM PST 24 331023475065 ps
T569 /workspace/coverage/default/23.hmac_error.2473484128 Feb 18 01:46:38 PM PST 24 Feb 18 01:47:24 PM PST 24 11740408501 ps
T570 /workspace/coverage/default/19.hmac_back_pressure.3737824424 Feb 18 01:46:29 PM PST 24 Feb 18 01:46:51 PM PST 24 1561601190 ps
T571 /workspace/coverage/default/33.hmac_test_sha_vectors.3772712757 Feb 18 01:47:19 PM PST 24 Feb 18 01:54:09 PM PST 24 15980478979 ps
T572 /workspace/coverage/default/29.hmac_datapath_stress.4260621241 Feb 18 01:47:04 PM PST 24 Feb 18 01:47:28 PM PST 24 770219139 ps
T573 /workspace/coverage/default/36.hmac_wipe_secret.2553560029 Feb 18 01:47:29 PM PST 24 Feb 18 01:47:37 PM PST 24 563676522 ps
T574 /workspace/coverage/default/7.hmac_stress_all.280370305 Feb 18 01:45:44 PM PST 24 Feb 18 01:59:05 PM PST 24 234928266604 ps
T575 /workspace/coverage/default/33.hmac_smoke.1410689223 Feb 18 01:47:15 PM PST 24 Feb 18 01:47:24 PM PST 24 346753590 ps
T576 /workspace/coverage/default/44.hmac_back_pressure.3919436473 Feb 18 01:48:02 PM PST 24 Feb 18 01:48:30 PM PST 24 2470924635 ps
T577 /workspace/coverage/default/32.hmac_datapath_stress.2798427501 Feb 18 01:47:18 PM PST 24 Feb 18 01:47:55 PM PST 24 1090055002 ps
T578 /workspace/coverage/default/12.hmac_test_hmac_vectors.964826385 Feb 18 01:45:50 PM PST 24 Feb 18 01:45:53 PM PST 24 62942323 ps
T579 /workspace/coverage/default/19.hmac_alert_test.1421602248 Feb 18 01:46:27 PM PST 24 Feb 18 01:46:30 PM PST 24 24457239 ps
T580 /workspace/coverage/default/26.hmac_back_pressure.3110876596 Feb 18 01:46:49 PM PST 24 Feb 18 01:47:23 PM PST 24 972492834 ps
T581 /workspace/coverage/default/9.hmac_smoke.2632284559 Feb 18 01:45:36 PM PST 24 Feb 18 01:45:43 PM PST 24 65399277 ps
T582 /workspace/coverage/default/11.hmac_test_sha_vectors.2001005590 Feb 18 01:45:47 PM PST 24 Feb 18 01:52:01 PM PST 24 30863258961 ps
T583 /workspace/coverage/default/9.hmac_test_sha_vectors.1912419332 Feb 18 01:45:37 PM PST 24 Feb 18 01:53:45 PM PST 24 120028630747 ps
T584 /workspace/coverage/default/34.hmac_smoke.3029624134 Feb 18 01:47:18 PM PST 24 Feb 18 01:47:24 PM PST 24 74135824 ps
T585 /workspace/coverage/default/47.hmac_error.1611284379 Feb 18 01:48:12 PM PST 24 Feb 18 01:51:53 PM PST 24 65644653404 ps
T586 /workspace/coverage/default/14.hmac_test_sha_vectors.3845800731 Feb 18 01:46:01 PM PST 24 Feb 18 01:53:21 PM PST 24 104818057181 ps
T587 /workspace/coverage/default/13.hmac_datapath_stress.4014622086 Feb 18 01:45:51 PM PST 24 Feb 18 01:48:21 PM PST 24 11338100516 ps
T588 /workspace/coverage/default/37.hmac_test_hmac_vectors.1963447156 Feb 18 01:47:35 PM PST 24 Feb 18 01:47:38 PM PST 24 31340324 ps
T589 /workspace/coverage/default/8.hmac_wipe_secret.2057328257 Feb 18 01:45:41 PM PST 24 Feb 18 01:46:36 PM PST 24 2584338019 ps
T590 /workspace/coverage/default/30.hmac_datapath_stress.1621945382 Feb 18 01:47:00 PM PST 24 Feb 18 01:47:57 PM PST 24 20355827053 ps
T64 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.988410467 Feb 18 12:46:42 PM PST 24 Feb 18 12:46:52 PM PST 24 84534919 ps
T591 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3376797496 Feb 18 12:46:39 PM PST 24 Feb 18 12:46:49 PM PST 24 73743012 ps
T592 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3673959821 Feb 18 12:46:35 PM PST 24 Feb 18 12:46:45 PM PST 24 12761227 ps
T593 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2750634112 Feb 18 12:46:34 PM PST 24 Feb 18 12:46:46 PM PST 24 55146108 ps
T594 /workspace/coverage/cover_reg_top/33.hmac_intr_test.861047305 Feb 18 12:47:04 PM PST 24 Feb 18 12:47:08 PM PST 24 20948638 ps
T84 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3671667122 Feb 18 12:46:35 PM PST 24 Feb 18 12:46:46 PM PST 24 35800805 ps
T56 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3077915593 Feb 18 12:46:37 PM PST 24 Feb 18 12:46:50 PM PST 24 120087361 ps
T595 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2619743062 Feb 18 12:46:43 PM PST 24 Feb 18 12:46:51 PM PST 24 12140886 ps
T596 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3884650183 Feb 18 12:46:47 PM PST 24 Feb 18 12:46:56 PM PST 24 312339115 ps
T597 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1965480190 Feb 18 12:46:44 PM PST 24 Feb 18 12:46:54 PM PST 24 41700334 ps
T94 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3279231269 Feb 18 12:46:34 PM PST 24 Feb 18 12:46:54 PM PST 24 3333880216 ps
T598 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1858911264 Feb 18 12:46:43 PM PST 24 Feb 18 12:46:53 PM PST 24 81420457 ps
T599 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1626260023 Feb 18 12:46:45 PM PST 24 Feb 18 12:46:53 PM PST 24 42581819 ps
T600 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2644587189 Feb 18 12:46:33 PM PST 24 Feb 18 12:46:43 PM PST 24 17437326 ps
T601 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2458950942 Feb 18 12:46:53 PM PST 24 Feb 18 12:46:58 PM PST 24 101486112 ps
T602 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1969380750 Feb 18 12:46:34 PM PST 24 Feb 18 12:46:43 PM PST 24 13015766 ps
T57 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.774549568 Feb 18 12:46:40 PM PST 24 Feb 18 12:46:51 PM PST 24 157123562 ps
T85 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1190879687 Feb 18 12:46:35 PM PST 24 Feb 18 12:46:46 PM PST 24 14484725 ps
T603 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2036000526 Feb 18 12:46:56 PM PST 24 Feb 18 12:47:00 PM PST 24 81031905 ps
T604 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2038278917 Feb 18 12:46:35 PM PST 24 Feb 18 12:46:46 PM PST 24 49926390 ps
T86 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1427697988 Feb 18 12:46:34 PM PST 24 Feb 18 12:46:45 PM PST 24 89409253 ps
T87 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.69625467 Feb 18 12:46:42 PM PST 24 Feb 18 12:46:52 PM PST 24 247064356 ps
T605 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.717391537 Feb 18 12:47:00 PM PST 24 Feb 18 12:47:06 PM PST 24 401300491 ps
T606 /workspace/coverage/cover_reg_top/22.hmac_intr_test.870290175 Feb 18 12:46:58 PM PST 24 Feb 18 12:47:02 PM PST 24 12079303 ps
T607 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1509520062 Feb 18 12:46:36 PM PST 24 Feb 18 12:46:47 PM PST 24 20052023 ps
T58 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.621950898 Feb 18 12:46:53 PM PST 24 Feb 18 12:47:00 PM PST 24 156505946 ps
T608 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.450418183 Feb 18 12:46:34 PM PST 24 Feb 18 12:46:45 PM PST 24 227677924 ps
T609 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1849913802 Feb 18 12:46:33 PM PST 24 Feb 18 12:46:44 PM PST 24 210720327 ps
T610 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2640246177 Feb 18 12:46:37 PM PST 24 Feb 18 12:46:53 PM PST 24 273036570 ps
T611 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3727153356 Feb 18 12:46:34 PM PST 24 Feb 18 12:46:44 PM PST 24 72816049 ps
T131 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2680987877 Feb 18 12:46:49 PM PST 24 Feb 18 12:46:58 PM PST 24 110640437 ps
T612 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2282846734 Feb 18 12:46:49 PM PST 24 Feb 18 12:47:00 PM PST 24 62203829 ps
T129 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1868394887 Feb 18 12:46:53 PM PST 24 Feb 18 12:47:00 PM PST 24 265395754 ps
T613 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1384483765 Feb 18 12:46:35 PM PST 24 Feb 18 12:46:47 PM PST 24 210123327 ps
T614 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3912742167 Feb 18 12:46:36 PM PST 24 Feb 18 12:46:49 PM PST 24 329645461 ps
T88 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2380111704 Feb 18 12:46:42 PM PST 24 Feb 18 12:46:51 PM PST 24 35348677 ps
T615 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2546313375 Feb 18 12:46:39 PM PST 24 Feb 18 12:46:49 PM PST 24 13458056 ps
T616 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1824713521 Feb 18 12:46:36 PM PST 24 Feb 18 12:46:48 PM PST 24 26428054 ps
T617 /workspace/coverage/cover_reg_top/7.hmac_intr_test.66322300 Feb 18 12:46:41 PM PST 24 Feb 18 12:46:50 PM PST 24 39250438 ps
T618 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.591617489 Feb 18 12:46:49 PM PST 24 Feb 18 12:54:45 PM PST 24 155588885341 ps
T89 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2176053465 Feb 18 12:46:33 PM PST 24 Feb 18 12:46:44 PM PST 24 231927589 ps
T619 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1060275738 Feb 18 12:46:36 PM PST 24 Feb 18 12:46:49 PM PST 24 106573296 ps
T620 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.445688170 Feb 18 12:46:56 PM PST 24 Feb 18 12:47:00 PM PST 24 92499131 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3435442068 Feb 18 12:46:36 PM PST 24 Feb 18 12:46:51 PM PST 24 361293454 ps
T135 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3303879807 Feb 18 12:46:43 PM PST 24 Feb 18 12:46:53 PM PST 24 110900042 ps
T621 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3854282053 Feb 18 12:47:05 PM PST 24 Feb 18 12:47:10 PM PST 24 11680522 ps
T622 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1005069484 Feb 18 12:46:38 PM PST 24 Feb 18 12:46:49 PM PST 24 44745393 ps
T623 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2870876316 Feb 18 12:46:58 PM PST 24 Feb 18 12:47:06 PM PST 24 318538100 ps
T624 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1598021502 Feb 18 12:47:04 PM PST 24 Feb 18 12:47:08 PM PST 24 12276292 ps
T625 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2105918472 Feb 18 12:46:39 PM PST 24 Feb 18 12:46:49 PM PST 24 38209461 ps
T626 /workspace/coverage/cover_reg_top/6.hmac_intr_test.123861941 Feb 18 12:46:48 PM PST 24 Feb 18 12:46:56 PM PST 24 48797867 ps
T627 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.448022736 Feb 18 12:46:52 PM PST 24 Feb 18 12:46:58 PM PST 24 91199780 ps
T91 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3565154506 Feb 18 12:46:43 PM PST 24 Feb 18 12:46:52 PM PST 24 45596319 ps
T628 /workspace/coverage/cover_reg_top/19.hmac_intr_test.4111166716 Feb 18 12:47:03 PM PST 24 Feb 18 12:47:06 PM PST 24 52816758 ps
T629 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3744691224 Feb 18 12:47:03 PM PST 24 Feb 18 12:47:06 PM PST 24 44574878 ps
T92 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2475262435 Feb 18 12:47:01 PM PST 24 Feb 18 12:47:04 PM PST 24 22985277 ps
T630 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3778632361 Feb 18 12:46:44 PM PST 24 Feb 18 12:46:53 PM PST 24 252418681 ps
T631 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2557423987 Feb 18 12:46:44 PM PST 24 Feb 18 12:46:52 PM PST 24 28083700 ps
T632 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1428879686 Feb 18 12:46:46 PM PST 24 Feb 18 12:46:53 PM PST 24 36790174 ps
T93 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3862807337 Feb 18 12:46:35 PM PST 24 Feb 18 12:46:46 PM PST 24 163125580 ps
T633 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.100532409 Feb 18 12:46:48 PM PST 24 Feb 18 12:46:56 PM PST 24 13740279 ps
T634 /workspace/coverage/cover_reg_top/35.hmac_intr_test.51227258 Feb 18 12:47:05 PM PST 24 Feb 18 12:47:10 PM PST 24 13199517 ps
T635 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.4247928763 Feb 18 12:46:47 PM PST 24 Feb 18 12:46:55 PM PST 24 55891076 ps
T636 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1810695551 Feb 18 12:46:46 PM PST 24 Feb 18 12:46:59 PM PST 24 186112546 ps
T637 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1146680772 Feb 18 12:47:03 PM PST 24 Feb 18 12:47:07 PM PST 24 82889433 ps
T638 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.235698261 Feb 18 12:46:52 PM PST 24 Feb 18 12:47:00 PM PST 24 306925702 ps
T639 /workspace/coverage/cover_reg_top/49.hmac_intr_test.541513884 Feb 18 12:47:05 PM PST 24 Feb 18 12:47:09 PM PST 24 30796859 ps
T640 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1880124580 Feb 18 12:47:04 PM PST 24 Feb 18 12:47:08 PM PST 24 15233300 ps
T133 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3228869392 Feb 18 12:46:28 PM PST 24 Feb 18 12:46:34 PM PST 24 77297838 ps
T641 /workspace/coverage/cover_reg_top/14.hmac_intr_test.4023685651 Feb 18 12:46:45 PM PST 24 Feb 18 12:46:52 PM PST 24 12056995 ps
T642 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1612358498 Feb 18 12:46:57 PM PST 24 Feb 18 12:47:01 PM PST 24 21696473 ps
T643 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2906584710 Feb 18 12:47:09 PM PST 24 Feb 18 12:47:13 PM PST 24 30821595 ps
T644 /workspace/coverage/cover_reg_top/46.hmac_intr_test.860027402 Feb 18 12:47:09 PM PST 24 Feb 18 12:47:13 PM PST 24 140816002 ps
T134 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3523211560 Feb 18 12:46:33 PM PST 24 Feb 18 12:46:44 PM PST 24 360145470 ps
T645 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3777945380 Feb 18 12:47:05 PM PST 24 Feb 18 12:47:10 PM PST 24 18956665 ps
T646 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.4166291671 Feb 18 12:46:42 PM PST 24 Feb 18 12:46:52 PM PST 24 75888582 ps
T647 /workspace/coverage/cover_reg_top/9.hmac_intr_test.756527461 Feb 18 12:46:38 PM PST 24 Feb 18 12:46:49 PM PST 24 24223397 ps
T648 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1410788233 Feb 18 12:47:07 PM PST 24 Feb 18 12:47:12 PM PST 24 28455900 ps
T649 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1349757362 Feb 18 12:46:30 PM PST 24 Feb 18 12:46:37 PM PST 24 21980934 ps
T650 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1708216790 Feb 18 12:46:30 PM PST 24 Feb 18 12:46:37 PM PST 24 32286675 ps
T651 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1586450357 Feb 18 12:46:37 PM PST 24 Feb 18 12:46:50 PM PST 24 138233302 ps
T652 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2443021777 Feb 18 12:47:05 PM PST 24 Feb 18 12:47:10 PM PST 24 61641169 ps
T653 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1257876426 Feb 18 12:46:49 PM PST 24 Feb 18 12:46:57 PM PST 24 17977503 ps
T654 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2372758232 Feb 18 12:46:38 PM PST 24 Feb 18 12:46:55 PM PST 24 102583624 ps
T655 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.336184126 Feb 18 12:46:30 PM PST 24 Feb 18 12:46:37 PM PST 24 67579113 ps
T656 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.420786576 Feb 18 12:46:34 PM PST 24 Feb 18 12:46:45 PM PST 24 228150009 ps
T657 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1012235797 Feb 18 12:46:52 PM PST 24 Feb 18 12:46:58 PM PST 24 15542291 ps
T658 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3293582299 Feb 18 12:47:06 PM PST 24 Feb 18 12:47:11 PM PST 24 41609172 ps
T659 /workspace/coverage/cover_reg_top/1.hmac_intr_test.719591174 Feb 18 12:46:40 PM PST 24 Feb 18 12:46:50 PM PST 24 15556001 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.63320078 Feb 18 12:46:35 PM PST 24 Feb 18 12:46:46 PM PST 24 19068809 ps
T660 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.954684258 Feb 18 12:46:37 PM PST 24 Feb 18 12:46:49 PM PST 24 275564458 ps
T661 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3511257402 Feb 18 12:46:39 PM PST 24 Feb 18 12:46:50 PM PST 24 30874593 ps
T132 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1297580984 Feb 18 12:46:48 PM PST 24 Feb 18 12:46:56 PM PST 24 56461486 ps
T662 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.548883658 Feb 18 12:46:57 PM PST 24 Feb 18 12:47:01 PM PST 24 89287211 ps
T663 /workspace/coverage/cover_reg_top/45.hmac_intr_test.87910120 Feb 18 12:47:05 PM PST 24 Feb 18 12:47:10 PM PST 24 13659945 ps
T664 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1316031931 Feb 18 12:46:44 PM PST 24 Feb 18 12:46:53 PM PST 24 77988778 ps
T665 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1885990054 Feb 18 12:46:37 PM PST 24 Feb 18 12:46:48 PM PST 24 11817026 ps
T666 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3539323893 Feb 18 12:46:39 PM PST 24 Feb 18 12:46:51 PM PST 24 512571116 ps
T667 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.745720943 Feb 18 12:46:49 PM PST 24 Feb 18 12:46:57 PM PST 24 22846338 ps
T668 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1850615153 Feb 18 12:46:43 PM PST 24 Feb 18 12:46:53 PM PST 24 29766242 ps
T669 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1761146923 Feb 18 12:46:45 PM PST 24 Feb 18 12:46:53 PM PST 24 48375306 ps
T670 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4189426783 Feb 18 12:46:31 PM PST 24 Feb 18 12:46:39 PM PST 24 68346006 ps
T96 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1862549407 Feb 18 12:46:38 PM PST 24 Feb 18 12:46:49 PM PST 24 15791625 ps
T671 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3978211202 Feb 18 12:47:00 PM PST 24 Feb 18 12:47:03 PM PST 24 16394747 ps
T672 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2030441117 Feb 18 12:47:00 PM PST 24 Feb 18 12:47:03 PM PST 24 1043815179 ps
T673 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2526653791 Feb 18 12:47:01 PM PST 24 Feb 18 12:47:03 PM PST 24 49443095 ps
T674 /workspace/coverage/cover_reg_top/17.hmac_intr_test.4025297835 Feb 18 12:46:46 PM PST 24 Feb 18 12:46:53 PM PST 24 27717004 ps
T675 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.432709057 Feb 18 12:46:44 PM PST 24 Feb 18 12:46:52 PM PST 24 18543925 ps
T97 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.16060060 Feb 18 12:46:35 PM PST 24 Feb 18 12:46:48 PM PST 24 871269045 ps
T98 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1002533108 Feb 18 12:46:53 PM PST 24 Feb 18 12:46:58 PM PST 24 15198364 ps
T676 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1551993872 Feb 18 12:46:29 PM PST 24 Feb 18 12:46:36 PM PST 24 353925132 ps
T677 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1313272922 Feb 18 12:47:03 PM PST 24 Feb 18 12:47:06 PM PST 24 13194180 ps
T678 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1655016397 Feb 18 12:47:04 PM PST 24 Feb 18 12:47:08 PM PST 24 53053093 ps
T679 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2364674146 Feb 18 12:46:28 PM PST 24 Feb 18 12:46:33 PM PST 24 58207554 ps
T680 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2871885120 Feb 18 12:46:59 PM PST 24 Feb 18 12:47:02 PM PST 24 35265750 ps
T681 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1595376426 Feb 18 12:46:54 PM PST 24 Feb 18 12:46:59 PM PST 24 15412069 ps
T682 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3081614993 Feb 18 12:46:42 PM PST 24 Feb 18 12:46:52 PM PST 24 95951978 ps
T683 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1226679223 Feb 18 12:46:43 PM PST 24 Feb 18 12:46:53 PM PST 24 199336767 ps
T684 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1483833575 Feb 18 12:46:46 PM PST 24 Feb 18 12:46:53 PM PST 24 75636010 ps
T685 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1629422588 Feb 18 12:46:59 PM PST 24 Feb 18 12:47:02 PM PST 24 13692666 ps
T686 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.277989895 Feb 18 12:46:33 PM PST 24 Feb 18 12:46:46 PM PST 24 120551901 ps
T687 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3834667271 Feb 18 12:46:49 PM PST 24 Feb 18 12:47:00 PM PST 24 65456526 ps
T688 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3772365984 Feb 18 12:46:52 PM PST 24 Feb 18 12:46:59 PM PST 24 74758479 ps
T689 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4276232785 Feb 18 12:46:57 PM PST 24 Feb 18 12:47:01 PM PST 24 17511968 ps
T690 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1995197892 Feb 18 12:46:53 PM PST 24 Feb 18 12:46:59 PM PST 24 95414306 ps
T691 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2130294557 Feb 18 12:47:08 PM PST 24 Feb 18 12:47:13 PM PST 24 16120857 ps
T692 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2117837054 Feb 18 12:46:57 PM PST 24 Feb 18 12:47:01 PM PST 24 19788281 ps
T693 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.427326892 Feb 18 12:46:31 PM PST 24 Feb 18 12:46:39 PM PST 24 55055115 ps
T694 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.677041554 Feb 18 12:46:37 PM PST 24 Feb 18 12:46:50 PM PST 24 125600199 ps
T695 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3121037392 Feb 18 12:46:42 PM PST 24 Feb 18 12:46:51 PM PST 24 309398931 ps
T696 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3090135108 Feb 18 12:46:58 PM PST 24 Feb 18 12:47:03 PM PST 24 414684431 ps
T697 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1721103903 Feb 18 12:46:52 PM PST 24 Feb 18 12:46:58 PM PST 24 45824186 ps
T698 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2377700321 Feb 18 12:46:36 PM PST 24 Feb 18 12:46:49 PM PST 24 154081203 ps
T699 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3588644762 Feb 18 12:46:48 PM PST 24 Feb 18 12:46:57 PM PST 24 1303214714 ps
T700 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3269127638 Feb 18 12:46:40 PM PST 24 Feb 18 12:54:51 PM PST 24 36127738463 ps
T701 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.438221144 Feb 18 12:46:36 PM PST 24 Feb 18 12:46:49 PM PST 24 143349351 ps
T702 /workspace/coverage/cover_reg_top/26.hmac_intr_test.4203201237 Feb 18 12:46:56 PM PST 24 Feb 18 12:46:59 PM PST 24 85794792 ps
T703 /workspace/coverage/cover_reg_top/39.hmac_intr_test.445518087 Feb 18 12:47:04 PM PST 24 Feb 18 12:47:08 PM PST 24 45435041 ps
T704 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3296917026 Feb 18 12:46:44 PM PST 24 Feb 18 12:46:52 PM PST 24 86292393 ps
T705 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3510519842 Feb 18 12:46:42 PM PST 24 Feb 18 12:46:51 PM PST 24 52073309 ps
T706 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2899496790 Feb 18 12:46:41 PM PST 24 Feb 18 12:46:52 PM PST 24 343147902 ps
T136 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1034000951 Feb 18 12:46:53 PM PST 24 Feb 18 12:47:00 PM PST 24 342792085 ps
T707 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3893198530 Feb 18 12:46:45 PM PST 24 Feb 18 12:46:52 PM PST 24 25719444 ps
T99 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.99981644 Feb 18 12:46:34 PM PST 24 Feb 18 12:46:54 PM PST 24 975407948 ps
T708 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3998569370 Feb 18 12:46:38 PM PST 24 Feb 18 12:46:51 PM PST 24 104028855 ps
T709 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2183639356 Feb 18 12:46:54 PM PST 24 Feb 18 12:46:59 PM PST 24 21184742 ps
T100 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1136090585 Feb 18 12:46:47 PM PST 24 Feb 18 12:46:55 PM PST 24 13228145 ps
T710 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1459282468 Feb 18 12:47:04 PM PST 24 Feb 18 12:47:08 PM PST 24 17468791 ps
T711 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3341136137 Feb 18 12:46:37 PM PST 24 Feb 18 12:46:49 PM PST 24 24805211 ps
T712 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1719251420 Feb 18 12:46:46 PM PST 24 Feb 18 12:46:54 PM PST 24 72648290 ps
T713 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1540750019 Feb 18 12:46:46 PM PST 24 Feb 18 12:46:53 PM PST 24 26754239 ps
T714 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1293689875 Feb 18 12:46:46 PM PST 24 Feb 18 12:46:53 PM PST 24 26772797 ps
T715 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3279762897 Feb 18 12:47:05 PM PST 24 Feb 18 12:47:10 PM PST 24 33519769 ps
T716 /workspace/coverage/cover_reg_top/18.hmac_intr_test.972314353 Feb 18 12:46:54 PM PST 24 Feb 18 12:46:59 PM PST 24 21388346 ps
T130 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1063953108 Feb 18 12:46:39 PM PST 24 Feb 18 12:46:51 PM PST 24 108422772 ps
T717 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2696566934 Feb 18 12:46:42 PM PST 24 Feb 18 12:46:52 PM PST 24 195554339 ps
T718 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2906685332 Feb 18 12:46:39 PM PST 24 Feb 18 12:46:49 PM PST 24 50955191 ps
T719 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1325968700 Feb 18 12:46:49 PM PST 24 Feb 18 12:46:57 PM PST 24 65655025 ps
T720 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.8479466 Feb 18 12:46:56 PM PST 24 Feb 18 12:47:00 PM PST 24 54121423 ps

Test location /workspace/coverage/default/46.hmac_long_msg.3321765151
Short name T8
Test name
Test status
Simulation time 3606347634 ps
CPU time 89.18 seconds
Started Feb 18 01:48:03 PM PST 24
Finished Feb 18 01:49:39 PM PST 24
Peak memory 199596 kb
Host smart-f6f9c37e-be88-45b6-9a75-ae2cdb288ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321765151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3321765151
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.2543072614
Short name T5
Test name
Test status
Simulation time 58236225975 ps
CPU time 2237.36 seconds
Started Feb 18 01:48:33 PM PST 24
Finished Feb 18 02:25:54 PM PST 24
Peak memory 227940 kb
Host smart-580f46d7-44d3-4298-8925-b87eb289d844
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2543072614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.2543072614
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3077915593
Short name T56
Test name
Test status
Simulation time 120087361 ps
CPU time 2.3 seconds
Started Feb 18 12:46:37 PM PST 24
Finished Feb 18 12:46:50 PM PST 24
Peak memory 198664 kb
Host smart-64e2fcd4-abab-423f-acf1-355f2607bf35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077915593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3077915593
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2040855160
Short name T2
Test name
Test status
Simulation time 75038383 ps
CPU time 0.6 seconds
Started Feb 18 01:46:34 PM PST 24
Finished Feb 18 01:46:36 PM PST 24
Peak memory 194972 kb
Host smart-0bd56e84-c3c4-4aa7-b666-4b25aeae3be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040855160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2040855160
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2475262435
Short name T92
Test name
Test status
Simulation time 22985277 ps
CPU time 0.77 seconds
Started Feb 18 12:47:01 PM PST 24
Finished Feb 18 12:47:04 PM PST 24
Peak memory 194904 kb
Host smart-c5f1989c-f7ab-45b5-ab7f-9444bb39d1eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475262435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2475262435
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.4203189800
Short name T59
Test name
Test status
Simulation time 68421884090 ps
CPU time 766.04 seconds
Started Feb 18 01:48:55 PM PST 24
Finished Feb 18 02:01:43 PM PST 24
Peak memory 231900 kb
Host smart-30a695ed-7d3b-444d-a5dd-0662057be9b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203189800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.4203189800
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2749888678
Short name T42
Test name
Test status
Simulation time 191225062 ps
CPU time 0.9 seconds
Started Feb 18 01:45:23 PM PST 24
Finished Feb 18 01:45:32 PM PST 24
Peak memory 216600 kb
Host smart-efa41e34-989e-45ea-9459-b8fd62123d83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749888678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2749888678
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3342285185
Short name T65
Test name
Test status
Simulation time 398306009021 ps
CPU time 1534.19 seconds
Started Feb 18 01:45:24 PM PST 24
Finished Feb 18 02:11:05 PM PST 24
Peak memory 215976 kb
Host smart-30f70ac6-f9bc-4ce4-a5c5-684f6bedc932
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342285185 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3342285185
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.3286879990
Short name T16
Test name
Test status
Simulation time 459110681685 ps
CPU time 2124.49 seconds
Started Feb 18 01:48:28 PM PST 24
Finished Feb 18 02:23:54 PM PST 24
Peak memory 263888 kb
Host smart-87457145-33b8-4858-9a94-ae6ac98c6579
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286879990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.3286879990
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1868394887
Short name T129
Test name
Test status
Simulation time 265395754 ps
CPU time 1.83 seconds
Started Feb 18 12:46:53 PM PST 24
Finished Feb 18 12:47:00 PM PST 24
Peak memory 198188 kb
Host smart-22fb41f0-8e77-418d-b3b2-0d798d27694a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868394887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1868394887
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2837354165
Short name T110
Test name
Test status
Simulation time 3271821351 ps
CPU time 35.47 seconds
Started Feb 18 01:45:44 PM PST 24
Finished Feb 18 01:46:24 PM PST 24
Peak memory 199588 kb
Host smart-e6cda4dc-a42d-4e98-bac0-6c589a5c58ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837354165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2837354165
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.2969667804
Short name T60
Test name
Test status
Simulation time 280157730316 ps
CPU time 2697.24 seconds
Started Feb 18 01:49:00 PM PST 24
Finished Feb 18 02:33:59 PM PST 24
Peak memory 250928 kb
Host smart-518b1e1d-fa38-4e85-8082-0ee7ffad6dcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969667804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.2969667804
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.963360880
Short name T113
Test name
Test status
Simulation time 1308813157 ps
CPU time 78.1 seconds
Started Feb 18 01:46:29 PM PST 24
Finished Feb 18 01:47:50 PM PST 24
Peak memory 199552 kb
Host smart-2f861d06-8a74-405d-8ccf-dd550336eb85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963360880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.963360880
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_stress_all.186946557
Short name T70
Test name
Test status
Simulation time 113577229211 ps
CPU time 800.44 seconds
Started Feb 18 01:47:03 PM PST 24
Finished Feb 18 02:00:25 PM PST 24
Peak memory 231060 kb
Host smart-2f546581-b917-48d6-969a-e77409a95bca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186946557 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.186946557
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_error.2302845641
Short name T26
Test name
Test status
Simulation time 14701331552 ps
CPU time 228.38 seconds
Started Feb 18 01:45:09 PM PST 24
Finished Feb 18 01:49:02 PM PST 24
Peak memory 199616 kb
Host smart-77a25192-ff15-44b3-b3b3-a508944b9b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302845641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2302845641
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1063953108
Short name T130
Test name
Test status
Simulation time 108422772 ps
CPU time 2.26 seconds
Started Feb 18 12:46:39 PM PST 24
Finished Feb 18 12:46:51 PM PST 24
Peak memory 198636 kb
Host smart-1034faf1-1d88-4dcd-ac44-71fb7eed98c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063953108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1063953108
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1681139814
Short name T122
Test name
Test status
Simulation time 85296747020 ps
CPU time 1108.33 seconds
Started Feb 18 01:45:48 PM PST 24
Finished Feb 18 02:04:19 PM PST 24
Peak memory 199616 kb
Host smart-e75bdcb7-1d48-49c8-b591-306ced4d5001
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681139814 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1681139814
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3087184278
Short name T123
Test name
Test status
Simulation time 8365719384 ps
CPU time 34.85 seconds
Started Feb 18 01:46:29 PM PST 24
Finished Feb 18 01:47:07 PM PST 24
Peak memory 199612 kb
Host smart-456bd89d-d0fb-4823-9f81-6dde4f2ffd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087184278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3087184278
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.87346684
Short name T106
Test name
Test status
Simulation time 1203549233 ps
CPU time 53.06 seconds
Started Feb 18 01:47:15 PM PST 24
Finished Feb 18 01:48:13 PM PST 24
Peak memory 199604 kb
Host smart-91e74bb0-05df-4402-b8ef-e370b4849d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87346684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.87346684
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2499075084
Short name T32
Test name
Test status
Simulation time 1140455616 ps
CPU time 48.13 seconds
Started Feb 18 01:47:44 PM PST 24
Finished Feb 18 01:48:35 PM PST 24
Peak memory 199516 kb
Host smart-c6fe8639-856f-41f3-b6f0-99e1407e3c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499075084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2499075084
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.3938079557
Short name T63
Test name
Test status
Simulation time 331023475065 ps
CPU time 3099.55 seconds
Started Feb 18 01:48:05 PM PST 24
Finished Feb 18 02:39:51 PM PST 24
Peak memory 232480 kb
Host smart-3eb5ca60-a53e-4c4f-b396-70457b11125c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938079557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.3938079557
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1586450357
Short name T651
Test name
Test status
Simulation time 138233302 ps
CPU time 2.6 seconds
Started Feb 18 12:46:37 PM PST 24
Finished Feb 18 12:46:50 PM PST 24
Peak memory 192192 kb
Host smart-e25598ff-dc31-48ad-b4c0-14a250d10725
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586450357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1586450357
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.16060060
Short name T97
Test name
Test status
Simulation time 871269045 ps
CPU time 3.47 seconds
Started Feb 18 12:46:35 PM PST 24
Finished Feb 18 12:46:48 PM PST 24
Peak memory 192384 kb
Host smart-29294db3-1591-4665-854f-f3793137c5cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16060060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.16060060
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1349757362
Short name T649
Test name
Test status
Simulation time 21980934 ps
CPU time 0.65 seconds
Started Feb 18 12:46:30 PM PST 24
Finished Feb 18 12:46:37 PM PST 24
Peak memory 193972 kb
Host smart-8580fba6-fec4-4fde-9924-1e3a5807f62d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349757362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1349757362
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1708216790
Short name T650
Test name
Test status
Simulation time 32286675 ps
CPU time 1.9 seconds
Started Feb 18 12:46:30 PM PST 24
Finished Feb 18 12:46:37 PM PST 24
Peak memory 198932 kb
Host smart-1d636df3-b071-42b5-9a52-85ec86628ae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708216790 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1708216790
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.63320078
Short name T95
Test name
Test status
Simulation time 19068809 ps
CPU time 0.67 seconds
Started Feb 18 12:46:35 PM PST 24
Finished Feb 18 12:46:46 PM PST 24
Peak memory 194576 kb
Host smart-86990191-de25-4dad-85ca-6e404e4e5e78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63320078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.63320078
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3673959821
Short name T592
Test name
Test status
Simulation time 12761227 ps
CPU time 0.56 seconds
Started Feb 18 12:46:35 PM PST 24
Finished Feb 18 12:46:45 PM PST 24
Peak memory 183944 kb
Host smart-cbf6a698-0c6d-4a49-a201-f075350d7e7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673959821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3673959821
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.954684258
Short name T660
Test name
Test status
Simulation time 275564458 ps
CPU time 1.4 seconds
Started Feb 18 12:46:37 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 192544 kb
Host smart-7f5bda13-4ad5-41a1-882c-bfd5713b0f71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954684258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.954684258
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.336184126
Short name T655
Test name
Test status
Simulation time 67579113 ps
CPU time 1.69 seconds
Started Feb 18 12:46:30 PM PST 24
Finished Feb 18 12:46:37 PM PST 24
Peak memory 198808 kb
Host smart-0c164bf5-658a-4478-863f-e95b46811e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336184126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.336184126
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3228869392
Short name T133
Test name
Test status
Simulation time 77297838 ps
CPU time 1.71 seconds
Started Feb 18 12:46:28 PM PST 24
Finished Feb 18 12:46:34 PM PST 24
Peak memory 198416 kb
Host smart-7438b481-4cbe-4a49-9e67-35c61a8e89b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228869392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3228869392
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3539323893
Short name T666
Test name
Test status
Simulation time 512571116 ps
CPU time 2.66 seconds
Started Feb 18 12:46:39 PM PST 24
Finished Feb 18 12:46:51 PM PST 24
Peak memory 192396 kb
Host smart-26c8f97f-bfd1-4524-acea-08bfd324edba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539323893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3539323893
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3435442068
Short name T90
Test name
Test status
Simulation time 361293454 ps
CPU time 3.52 seconds
Started Feb 18 12:46:36 PM PST 24
Finished Feb 18 12:46:51 PM PST 24
Peak memory 191972 kb
Host smart-46957601-f0d8-4805-b996-f3b8370396e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435442068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3435442068
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3671667122
Short name T84
Test name
Test status
Simulation time 35800805 ps
CPU time 0.69 seconds
Started Feb 18 12:46:35 PM PST 24
Finished Feb 18 12:46:46 PM PST 24
Peak memory 194236 kb
Host smart-d391c38f-b429-435e-9ba5-07aeb73aba4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671667122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3671667122
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2377700321
Short name T698
Test name
Test status
Simulation time 154081203 ps
CPU time 2.16 seconds
Started Feb 18 12:46:36 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 198872 kb
Host smart-b0d3d914-4262-43b4-a41a-f46752427b0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377700321 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2377700321
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2644587189
Short name T600
Test name
Test status
Simulation time 17437326 ps
CPU time 0.62 seconds
Started Feb 18 12:46:33 PM PST 24
Finished Feb 18 12:46:43 PM PST 24
Peak memory 194008 kb
Host smart-d84f3b56-250a-420b-a466-970e5c4fee29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644587189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2644587189
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.719591174
Short name T659
Test name
Test status
Simulation time 15556001 ps
CPU time 0.6 seconds
Started Feb 18 12:46:40 PM PST 24
Finished Feb 18 12:46:50 PM PST 24
Peak memory 183908 kb
Host smart-8cacb19f-b677-42fa-b00e-34772e686ed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719591174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.719591174
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2364674146
Short name T679
Test name
Test status
Simulation time 58207554 ps
CPU time 1.1 seconds
Started Feb 18 12:46:28 PM PST 24
Finished Feb 18 12:46:33 PM PST 24
Peak memory 192568 kb
Host smart-c964ef61-6454-4553-8b0d-45fd3a0c282d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364674146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2364674146
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3998569370
Short name T708
Test name
Test status
Simulation time 104028855 ps
CPU time 2.42 seconds
Started Feb 18 12:46:38 PM PST 24
Finished Feb 18 12:46:51 PM PST 24
Peak memory 198776 kb
Host smart-dc9e3e91-59db-4d85-b0b8-c17af9f0574e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998569370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3998569370
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4189426783
Short name T670
Test name
Test status
Simulation time 68346006 ps
CPU time 1.33 seconds
Started Feb 18 12:46:31 PM PST 24
Finished Feb 18 12:46:39 PM PST 24
Peak memory 198180 kb
Host smart-33bdd38c-0607-423a-b867-027330e7f00d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189426783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.4189426783
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2696566934
Short name T717
Test name
Test status
Simulation time 195554339 ps
CPU time 2.32 seconds
Started Feb 18 12:46:42 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 198936 kb
Host smart-035b01c0-b071-4d3d-b7a7-0a573572d27b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696566934 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2696566934
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3565154506
Short name T91
Test name
Test status
Simulation time 45596319 ps
CPU time 0.72 seconds
Started Feb 18 12:46:43 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 194552 kb
Host smart-55366cf0-6769-4034-9d11-fb938f250879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565154506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3565154506
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1509520062
Short name T607
Test name
Test status
Simulation time 20052023 ps
CPU time 0.55 seconds
Started Feb 18 12:46:36 PM PST 24
Finished Feb 18 12:46:47 PM PST 24
Peak memory 183984 kb
Host smart-24fe2a52-8a3e-45e9-9b82-b3da1aa407fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509520062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1509520062
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2906685332
Short name T718
Test name
Test status
Simulation time 50955191 ps
CPU time 0.82 seconds
Started Feb 18 12:46:39 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 192336 kb
Host smart-7809d49f-002d-4fb5-b652-432edfa40045
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906685332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2906685332
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1850615153
Short name T668
Test name
Test status
Simulation time 29766242 ps
CPU time 1.77 seconds
Started Feb 18 12:46:43 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 198948 kb
Host smart-b60f7d6e-acbc-4030-8423-de8c461169d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850615153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1850615153
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.774549568
Short name T57
Test name
Test status
Simulation time 157123562 ps
CPU time 1.66 seconds
Started Feb 18 12:46:40 PM PST 24
Finished Feb 18 12:46:51 PM PST 24
Peak memory 198484 kb
Host smart-886ecfe4-f299-4b8a-883d-51f1e2f5f437
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774549568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.774549568
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1965480190
Short name T597
Test name
Test status
Simulation time 41700334 ps
CPU time 2.43 seconds
Started Feb 18 12:46:44 PM PST 24
Finished Feb 18 12:46:54 PM PST 24
Peak memory 198960 kb
Host smart-b50a770f-8673-41d2-815e-969b9cd103ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965480190 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1965480190
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1136090585
Short name T100
Test name
Test status
Simulation time 13228145 ps
CPU time 0.69 seconds
Started Feb 18 12:46:47 PM PST 24
Finished Feb 18 12:46:55 PM PST 24
Peak memory 194760 kb
Host smart-214b9ef7-9f0f-4c6c-9eef-a0a445c1ea33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136090585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1136090585
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1626260023
Short name T599
Test name
Test status
Simulation time 42581819 ps
CPU time 0.6 seconds
Started Feb 18 12:46:45 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 183904 kb
Host smart-b9a3e29b-554c-4621-99ed-3369f0652674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626260023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1626260023
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1012235797
Short name T657
Test name
Test status
Simulation time 15542291 ps
CPU time 0.8 seconds
Started Feb 18 12:46:52 PM PST 24
Finished Feb 18 12:46:58 PM PST 24
Peak memory 192316 kb
Host smart-2c34a690-413c-4e23-b534-cce2a7173316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012235797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1012235797
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3884650183
Short name T596
Test name
Test status
Simulation time 312339115 ps
CPU time 2.28 seconds
Started Feb 18 12:46:47 PM PST 24
Finished Feb 18 12:46:56 PM PST 24
Peak memory 198888 kb
Host smart-c54699ee-02c3-442a-8b1c-3375be9daedb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884650183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3884650183
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1297580984
Short name T132
Test name
Test status
Simulation time 56461486 ps
CPU time 1.21 seconds
Started Feb 18 12:46:48 PM PST 24
Finished Feb 18 12:46:56 PM PST 24
Peak memory 198068 kb
Host smart-5e8df12e-57b9-46b6-8e84-05d1e5d52707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297580984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1297580984
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3834667271
Short name T687
Test name
Test status
Simulation time 65456526 ps
CPU time 3.96 seconds
Started Feb 18 12:46:49 PM PST 24
Finished Feb 18 12:47:00 PM PST 24
Peak memory 198848 kb
Host smart-0775133f-773d-40c7-882a-6e10a123a82f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834667271 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3834667271
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1002533108
Short name T98
Test name
Test status
Simulation time 15198364 ps
CPU time 0.7 seconds
Started Feb 18 12:46:53 PM PST 24
Finished Feb 18 12:46:58 PM PST 24
Peak memory 195080 kb
Host smart-7acef7dd-c11e-4b3e-8d48-d4e94a4625fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002533108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1002533108
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1761146923
Short name T669
Test name
Test status
Simulation time 48375306 ps
CPU time 0.6 seconds
Started Feb 18 12:46:45 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 183984 kb
Host smart-0b074d5d-677b-486d-b935-1baf66a9bad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761146923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1761146923
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.448022736
Short name T627
Test name
Test status
Simulation time 91199780 ps
CPU time 1.06 seconds
Started Feb 18 12:46:52 PM PST 24
Finished Feb 18 12:46:58 PM PST 24
Peak memory 192684 kb
Host smart-dc11fb11-fadf-4c64-aaa6-60993fb8634b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448022736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.448022736
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2282846734
Short name T612
Test name
Test status
Simulation time 62203829 ps
CPU time 3.19 seconds
Started Feb 18 12:46:49 PM PST 24
Finished Feb 18 12:47:00 PM PST 24
Peak memory 198856 kb
Host smart-b416068c-5d70-4f7e-8cce-4705d2359a31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282846734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2282846734
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1483833575
Short name T684
Test name
Test status
Simulation time 75636010 ps
CPU time 1.12 seconds
Started Feb 18 12:46:46 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 197904 kb
Host smart-c98e7338-7c20-48ce-be71-d4b63da3ef19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483833575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1483833575
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.745720943
Short name T667
Test name
Test status
Simulation time 22846338 ps
CPU time 0.67 seconds
Started Feb 18 12:46:49 PM PST 24
Finished Feb 18 12:46:57 PM PST 24
Peak memory 194120 kb
Host smart-17a0d166-eea9-4f37-849d-63541b626905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745720943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.745720943
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1595376426
Short name T681
Test name
Test status
Simulation time 15412069 ps
CPU time 0.65 seconds
Started Feb 18 12:46:54 PM PST 24
Finished Feb 18 12:46:59 PM PST 24
Peak memory 184100 kb
Host smart-f2dd54a4-278c-4670-831f-c26103bcd596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595376426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1595376426
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2458950942
Short name T601
Test name
Test status
Simulation time 101486112 ps
CPU time 0.8 seconds
Started Feb 18 12:46:53 PM PST 24
Finished Feb 18 12:46:58 PM PST 24
Peak memory 192252 kb
Host smart-d92635c6-0113-46bf-b213-fff1c3b869d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458950942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2458950942
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1540750019
Short name T713
Test name
Test status
Simulation time 26754239 ps
CPU time 1.37 seconds
Started Feb 18 12:46:46 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 198700 kb
Host smart-899c3a33-6b8a-4503-b7a4-74bc66f921a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540750019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1540750019
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1316031931
Short name T664
Test name
Test status
Simulation time 77988778 ps
CPU time 1.25 seconds
Started Feb 18 12:46:44 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 198228 kb
Host smart-8abffc76-93a5-4c84-9238-85abb7412279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316031931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1316031931
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1257876426
Short name T653
Test name
Test status
Simulation time 17977503 ps
CPU time 0.64 seconds
Started Feb 18 12:46:49 PM PST 24
Finished Feb 18 12:46:57 PM PST 24
Peak memory 194248 kb
Host smart-840aaa50-3190-484d-98ab-99a9a8b98662
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257876426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1257876426
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.4023685651
Short name T641
Test name
Test status
Simulation time 12056995 ps
CPU time 0.63 seconds
Started Feb 18 12:46:45 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 183944 kb
Host smart-1d9a1698-6904-47e7-97a5-8a65c43a93bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023685651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.4023685651
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1293689875
Short name T714
Test name
Test status
Simulation time 26772797 ps
CPU time 0.85 seconds
Started Feb 18 12:46:46 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 195988 kb
Host smart-b5a624bf-963f-4e62-974a-591ec3b47887
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293689875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1293689875
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.235698261
Short name T638
Test name
Test status
Simulation time 306925702 ps
CPU time 2.69 seconds
Started Feb 18 12:46:52 PM PST 24
Finished Feb 18 12:47:00 PM PST 24
Peak memory 198840 kb
Host smart-f942f5ee-bc39-4f6a-9a13-b9cc47c44e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235698261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.235698261
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1034000951
Short name T136
Test name
Test status
Simulation time 342792085 ps
CPU time 2.46 seconds
Started Feb 18 12:46:53 PM PST 24
Finished Feb 18 12:47:00 PM PST 24
Peak memory 198144 kb
Host smart-0ffb4f60-b29d-4fd9-986b-21c95a978244
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034000951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1034000951
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1810695551
Short name T636
Test name
Test status
Simulation time 186112546 ps
CPU time 5.81 seconds
Started Feb 18 12:46:46 PM PST 24
Finished Feb 18 12:46:59 PM PST 24
Peak memory 198968 kb
Host smart-b8dacfa5-1a16-4b97-ac6d-81c9c053a1d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810695551 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1810695551
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.100532409
Short name T633
Test name
Test status
Simulation time 13740279 ps
CPU time 0.62 seconds
Started Feb 18 12:46:48 PM PST 24
Finished Feb 18 12:46:56 PM PST 24
Peak memory 194224 kb
Host smart-345882ec-0235-4360-8b4d-f58f997c77ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100532409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.100532409
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3893198530
Short name T707
Test name
Test status
Simulation time 25719444 ps
CPU time 0.57 seconds
Started Feb 18 12:46:45 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 184036 kb
Host smart-d474f8ba-cb85-4c5c-b591-0638760a1010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893198530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3893198530
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3588644762
Short name T699
Test name
Test status
Simulation time 1303214714 ps
CPU time 1.4 seconds
Started Feb 18 12:46:48 PM PST 24
Finished Feb 18 12:46:57 PM PST 24
Peak memory 192540 kb
Host smart-b35abe19-e637-40ac-aa15-f4d8bc42f708
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588644762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3588644762
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3772365984
Short name T688
Test name
Test status
Simulation time 74758479 ps
CPU time 1.69 seconds
Started Feb 18 12:46:52 PM PST 24
Finished Feb 18 12:46:59 PM PST 24
Peak memory 198916 kb
Host smart-c951cfa9-5878-477e-820f-13e03b524d99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772365984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3772365984
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2680987877
Short name T131
Test name
Test status
Simulation time 110640437 ps
CPU time 2.25 seconds
Started Feb 18 12:46:49 PM PST 24
Finished Feb 18 12:46:58 PM PST 24
Peak memory 198560 kb
Host smart-e39946f8-7a58-4b33-9884-c50c58c43575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680987877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2680987877
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.591617489
Short name T618
Test name
Test status
Simulation time 155588885341 ps
CPU time 469.38 seconds
Started Feb 18 12:46:49 PM PST 24
Finished Feb 18 12:54:45 PM PST 24
Peak memory 204200 kb
Host smart-2d4d1253-65d9-4ded-9fdd-84ef01df5480
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591617489 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.591617489
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.4247928763
Short name T635
Test name
Test status
Simulation time 55891076 ps
CPU time 0.7 seconds
Started Feb 18 12:46:47 PM PST 24
Finished Feb 18 12:46:55 PM PST 24
Peak memory 194616 kb
Host smart-ed2cab48-a674-4684-a204-48a062a1ec67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247928763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.4247928763
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1428879686
Short name T632
Test name
Test status
Simulation time 36790174 ps
CPU time 0.57 seconds
Started Feb 18 12:46:46 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 184096 kb
Host smart-fde5f1af-6305-4e8a-9e99-28dc0507c1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428879686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1428879686
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1325968700
Short name T719
Test name
Test status
Simulation time 65655025 ps
CPU time 1.08 seconds
Started Feb 18 12:46:49 PM PST 24
Finished Feb 18 12:46:57 PM PST 24
Peak memory 192420 kb
Host smart-1cef7823-6a92-42d0-8e55-22102a53284c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325968700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1325968700
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1719251420
Short name T712
Test name
Test status
Simulation time 72648290 ps
CPU time 1.77 seconds
Started Feb 18 12:46:46 PM PST 24
Finished Feb 18 12:46:54 PM PST 24
Peak memory 198632 kb
Host smart-c27529e4-9731-41c4-8a52-00d5866828af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719251420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1719251420
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.621950898
Short name T58
Test name
Test status
Simulation time 156505946 ps
CPU time 2.36 seconds
Started Feb 18 12:46:53 PM PST 24
Finished Feb 18 12:47:00 PM PST 24
Peak memory 198568 kb
Host smart-a7fbd065-5527-4914-8bb7-71d918e6f077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621950898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.621950898
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2870876316
Short name T623
Test name
Test status
Simulation time 318538100 ps
CPU time 5.41 seconds
Started Feb 18 12:46:58 PM PST 24
Finished Feb 18 12:47:06 PM PST 24
Peak memory 198956 kb
Host smart-f0010a0a-941f-42f4-83dd-f28807e49b5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870876316 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2870876316
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1721103903
Short name T697
Test name
Test status
Simulation time 45824186 ps
CPU time 0.61 seconds
Started Feb 18 12:46:52 PM PST 24
Finished Feb 18 12:46:58 PM PST 24
Peak memory 194236 kb
Host smart-a3b8569b-a02b-4e19-b3a4-15dc7409240a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721103903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1721103903
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.4025297835
Short name T674
Test name
Test status
Simulation time 27717004 ps
CPU time 0.58 seconds
Started Feb 18 12:46:46 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 184100 kb
Host smart-9d2b7bde-0b4a-453f-8509-8e0e6b11a607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025297835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.4025297835
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4276232785
Short name T689
Test name
Test status
Simulation time 17511968 ps
CPU time 0.86 seconds
Started Feb 18 12:46:57 PM PST 24
Finished Feb 18 12:47:01 PM PST 24
Peak memory 192324 kb
Host smart-21f5e966-0bc3-4fba-b36c-f66b160cbc5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276232785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4276232785
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1995197892
Short name T690
Test name
Test status
Simulation time 95414306 ps
CPU time 1.3 seconds
Started Feb 18 12:46:53 PM PST 24
Finished Feb 18 12:46:59 PM PST 24
Peak memory 198840 kb
Host smart-5c2f3778-aec8-49fc-9e70-dae1a84bcb2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995197892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1995197892
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.972314353
Short name T716
Test name
Test status
Simulation time 21388346 ps
CPU time 0.6 seconds
Started Feb 18 12:46:54 PM PST 24
Finished Feb 18 12:46:59 PM PST 24
Peak memory 184036 kb
Host smart-789e0886-da20-4b41-8709-d2b30a220db9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972314353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.972314353
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1146680772
Short name T637
Test name
Test status
Simulation time 82889433 ps
CPU time 1.09 seconds
Started Feb 18 12:47:03 PM PST 24
Finished Feb 18 12:47:07 PM PST 24
Peak memory 192460 kb
Host smart-2a0c0444-9e6f-4329-b0e3-15a60fcebb92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146680772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1146680772
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3090135108
Short name T696
Test name
Test status
Simulation time 414684431 ps
CPU time 2.54 seconds
Started Feb 18 12:46:58 PM PST 24
Finished Feb 18 12:47:03 PM PST 24
Peak memory 198924 kb
Host smart-132f1449-bd5e-4f71-9f0c-86f1cf32181a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090135108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3090135108
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.548883658
Short name T662
Test name
Test status
Simulation time 89287211 ps
CPU time 1.3 seconds
Started Feb 18 12:46:57 PM PST 24
Finished Feb 18 12:47:01 PM PST 24
Peak memory 198928 kb
Host smart-7ee6f0bb-bc20-4132-ad48-a2fb9cc20eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548883658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.548883658
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.8479466
Short name T720
Test name
Test status
Simulation time 54121423 ps
CPU time 0.74 seconds
Started Feb 18 12:46:56 PM PST 24
Finished Feb 18 12:47:00 PM PST 24
Peak memory 194416 kb
Host smart-bd5e1e31-3837-4564-842a-b9e9e0e925ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8479466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.8479466
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.4111166716
Short name T628
Test name
Test status
Simulation time 52816758 ps
CPU time 0.58 seconds
Started Feb 18 12:47:03 PM PST 24
Finished Feb 18 12:47:06 PM PST 24
Peak memory 184044 kb
Host smart-c811f3b3-e8aa-4a59-a7f6-31b7a77516ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111166716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.4111166716
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.445688170
Short name T620
Test name
Test status
Simulation time 92499131 ps
CPU time 1.55 seconds
Started Feb 18 12:46:56 PM PST 24
Finished Feb 18 12:47:00 PM PST 24
Peak memory 192524 kb
Host smart-1dd4ed37-895a-4958-84ce-87a1b684190d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445688170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.445688170
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.717391537
Short name T605
Test name
Test status
Simulation time 401300491 ps
CPU time 3.78 seconds
Started Feb 18 12:47:00 PM PST 24
Finished Feb 18 12:47:06 PM PST 24
Peak memory 198692 kb
Host smart-1f9db7f0-1a7f-48fb-83c7-19685b7f80f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717391537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.717391537
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2030441117
Short name T672
Test name
Test status
Simulation time 1043815179 ps
CPU time 1.26 seconds
Started Feb 18 12:47:00 PM PST 24
Finished Feb 18 12:47:03 PM PST 24
Peak memory 198460 kb
Host smart-125a1059-47d5-451d-aada-19fd9be05dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030441117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2030441117
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1849913802
Short name T609
Test name
Test status
Simulation time 210720327 ps
CPU time 1.29 seconds
Started Feb 18 12:46:33 PM PST 24
Finished Feb 18 12:46:44 PM PST 24
Peak memory 184308 kb
Host smart-2a1c024e-daff-4a58-ba72-7fa07e5d51ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849913802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1849913802
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2640246177
Short name T610
Test name
Test status
Simulation time 273036570 ps
CPU time 5.74 seconds
Started Feb 18 12:46:37 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 192208 kb
Host smart-552c31ac-d39d-4908-9244-326e04fe3d2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640246177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2640246177
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1190879687
Short name T85
Test name
Test status
Simulation time 14484725 ps
CPU time 0.59 seconds
Started Feb 18 12:46:35 PM PST 24
Finished Feb 18 12:46:46 PM PST 24
Peak memory 193624 kb
Host smart-5e58cbb4-584c-4e77-859e-b9a7c7b4c136
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190879687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1190879687
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1551993872
Short name T676
Test name
Test status
Simulation time 353925132 ps
CPU time 2.3 seconds
Started Feb 18 12:46:29 PM PST 24
Finished Feb 18 12:46:36 PM PST 24
Peak memory 198964 kb
Host smart-fcaf04bd-b85b-41b1-b078-d6af032aada0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551993872 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1551993872
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2380111704
Short name T88
Test name
Test status
Simulation time 35348677 ps
CPU time 0.74 seconds
Started Feb 18 12:46:42 PM PST 24
Finished Feb 18 12:46:51 PM PST 24
Peak memory 194604 kb
Host smart-69574056-51f2-4244-8ed9-6ccf48ae2ab1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380111704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2380111704
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1885990054
Short name T665
Test name
Test status
Simulation time 11817026 ps
CPU time 0.61 seconds
Started Feb 18 12:46:37 PM PST 24
Finished Feb 18 12:46:48 PM PST 24
Peak memory 183740 kb
Host smart-e7a5fb13-5815-4019-ad39-626346fe2d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885990054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1885990054
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.4166291671
Short name T646
Test name
Test status
Simulation time 75888582 ps
CPU time 1.39 seconds
Started Feb 18 12:46:42 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 192448 kb
Host smart-f213454d-a108-4196-8f62-e5215f11f923
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166291671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.4166291671
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.438221144
Short name T701
Test name
Test status
Simulation time 143349351 ps
CPU time 2.13 seconds
Started Feb 18 12:46:36 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 198440 kb
Host smart-ad569ca4-485b-4c26-b156-faa68a87b3c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438221144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.438221144
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3510519842
Short name T705
Test name
Test status
Simulation time 52073309 ps
CPU time 1.19 seconds
Started Feb 18 12:46:42 PM PST 24
Finished Feb 18 12:46:51 PM PST 24
Peak memory 198200 kb
Host smart-2738a81d-d131-42c2-8a68-ec52b49df2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510519842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3510519842
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1612358498
Short name T642
Test name
Test status
Simulation time 21696473 ps
CPU time 0.58 seconds
Started Feb 18 12:46:57 PM PST 24
Finished Feb 18 12:47:01 PM PST 24
Peak memory 184020 kb
Host smart-e58eb780-afb4-4eeb-8f84-2f944c1c0284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612358498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1612358498
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2871885120
Short name T680
Test name
Test status
Simulation time 35265750 ps
CPU time 0.61 seconds
Started Feb 18 12:46:59 PM PST 24
Finished Feb 18 12:47:02 PM PST 24
Peak memory 184048 kb
Host smart-dd68d149-b582-430e-a2ce-5d72ed1618d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871885120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2871885120
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.870290175
Short name T606
Test name
Test status
Simulation time 12079303 ps
CPU time 0.66 seconds
Started Feb 18 12:46:58 PM PST 24
Finished Feb 18 12:47:02 PM PST 24
Peak memory 184040 kb
Host smart-a96c3ec8-d765-4687-a015-1b0556f40ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870290175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.870290175
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1598021502
Short name T624
Test name
Test status
Simulation time 12276292 ps
CPU time 0.6 seconds
Started Feb 18 12:47:04 PM PST 24
Finished Feb 18 12:47:08 PM PST 24
Peak memory 184048 kb
Host smart-01470185-74e5-4f3b-bb50-03e94fcccfdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598021502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1598021502
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2526653791
Short name T673
Test name
Test status
Simulation time 49443095 ps
CPU time 0.62 seconds
Started Feb 18 12:47:01 PM PST 24
Finished Feb 18 12:47:03 PM PST 24
Peak memory 183924 kb
Host smart-45d8ac64-85ca-4161-a0b7-aa175d799fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526653791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2526653791
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1629422588
Short name T685
Test name
Test status
Simulation time 13692666 ps
CPU time 0.66 seconds
Started Feb 18 12:46:59 PM PST 24
Finished Feb 18 12:47:02 PM PST 24
Peak memory 183980 kb
Host smart-e73a5877-10c2-43ff-be1d-75183d8dfcae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629422588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1629422588
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.4203201237
Short name T702
Test name
Test status
Simulation time 85794792 ps
CPU time 0.6 seconds
Started Feb 18 12:46:56 PM PST 24
Finished Feb 18 12:46:59 PM PST 24
Peak memory 184028 kb
Host smart-d533ce46-5c7c-43bf-bf3b-3dc5a5101338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203201237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.4203201237
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2117837054
Short name T692
Test name
Test status
Simulation time 19788281 ps
CPU time 0.58 seconds
Started Feb 18 12:46:57 PM PST 24
Finished Feb 18 12:47:01 PM PST 24
Peak memory 183928 kb
Host smart-feb33ab3-b82e-41ca-8296-9f3f2b61a417
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117837054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2117837054
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2183639356
Short name T709
Test name
Test status
Simulation time 21184742 ps
CPU time 0.6 seconds
Started Feb 18 12:46:54 PM PST 24
Finished Feb 18 12:46:59 PM PST 24
Peak memory 183928 kb
Host smart-c0b1350a-3e6f-4895-9e4c-ad9ad633078a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183639356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2183639356
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3978211202
Short name T671
Test name
Test status
Simulation time 16394747 ps
CPU time 0.62 seconds
Started Feb 18 12:47:00 PM PST 24
Finished Feb 18 12:47:03 PM PST 24
Peak memory 184100 kb
Host smart-64b94b8d-1bc3-40ea-b19d-3c036ceed94e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978211202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3978211202
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.69625467
Short name T87
Test name
Test status
Simulation time 247064356 ps
CPU time 1.92 seconds
Started Feb 18 12:46:42 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 192440 kb
Host smart-858526e0-bf7f-4423-9bde-9bf8e6b7fc55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69625467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.69625467
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.99981644
Short name T99
Test name
Test status
Simulation time 975407948 ps
CPU time 10.09 seconds
Started Feb 18 12:46:34 PM PST 24
Finished Feb 18 12:46:54 PM PST 24
Peak memory 192456 kb
Host smart-8ae8cbbd-af28-4c22-85d9-5b9064608f37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99981644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.99981644
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3862807337
Short name T93
Test name
Test status
Simulation time 163125580 ps
CPU time 0.66 seconds
Started Feb 18 12:46:35 PM PST 24
Finished Feb 18 12:46:46 PM PST 24
Peak memory 194344 kb
Host smart-825b7847-c948-428f-9beb-84e737472150
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862807337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3862807337
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.277989895
Short name T686
Test name
Test status
Simulation time 120551901 ps
CPU time 3.21 seconds
Started Feb 18 12:46:33 PM PST 24
Finished Feb 18 12:46:46 PM PST 24
Peak memory 198956 kb
Host smart-51246b8d-51c2-4925-a80f-353870c540ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277989895 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.277989895
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2038278917
Short name T604
Test name
Test status
Simulation time 49926390 ps
CPU time 0.58 seconds
Started Feb 18 12:46:35 PM PST 24
Finished Feb 18 12:46:46 PM PST 24
Peak memory 193740 kb
Host smart-b87a651d-64f6-42db-b37d-3c8ea18634e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038278917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2038278917
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1005069484
Short name T622
Test name
Test status
Simulation time 44745393 ps
CPU time 0.55 seconds
Started Feb 18 12:46:38 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 183932 kb
Host smart-7eeaa179-0f5c-4e94-b13e-df097fa7782d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005069484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1005069484
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3121037392
Short name T695
Test name
Test status
Simulation time 309398931 ps
CPU time 1.33 seconds
Started Feb 18 12:46:42 PM PST 24
Finished Feb 18 12:46:51 PM PST 24
Peak memory 192392 kb
Host smart-fcc252a0-dc21-489c-a88b-31b9538679b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121037392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3121037392
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2750634112
Short name T593
Test name
Test status
Simulation time 55146108 ps
CPU time 1.61 seconds
Started Feb 18 12:46:34 PM PST 24
Finished Feb 18 12:46:46 PM PST 24
Peak memory 198908 kb
Host smart-b922b87c-0553-44ca-add3-a0dba28805f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750634112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2750634112
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3523211560
Short name T134
Test name
Test status
Simulation time 360145470 ps
CPU time 1.23 seconds
Started Feb 18 12:46:33 PM PST 24
Finished Feb 18 12:46:44 PM PST 24
Peak memory 198304 kb
Host smart-84d5265d-84f8-4b32-ad05-48b10de34cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523211560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3523211560
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2036000526
Short name T603
Test name
Test status
Simulation time 81031905 ps
CPU time 0.6 seconds
Started Feb 18 12:46:56 PM PST 24
Finished Feb 18 12:47:00 PM PST 24
Peak memory 184028 kb
Host smart-152927bf-8627-4521-a011-9b67c2955470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036000526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2036000526
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3279762897
Short name T715
Test name
Test status
Simulation time 33519769 ps
CPU time 0.61 seconds
Started Feb 18 12:47:05 PM PST 24
Finished Feb 18 12:47:10 PM PST 24
Peak memory 183916 kb
Host smart-c871ba55-b065-4cf4-a9a7-c2f159bf54fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279762897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3279762897
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1655016397
Short name T678
Test name
Test status
Simulation time 53053093 ps
CPU time 0.56 seconds
Started Feb 18 12:47:04 PM PST 24
Finished Feb 18 12:47:08 PM PST 24
Peak memory 184008 kb
Host smart-68e14897-308a-48e9-972b-7e42262df7bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655016397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1655016397
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.861047305
Short name T594
Test name
Test status
Simulation time 20948638 ps
CPU time 0.65 seconds
Started Feb 18 12:47:04 PM PST 24
Finished Feb 18 12:47:08 PM PST 24
Peak memory 183972 kb
Host smart-3d6ae41f-46ba-41c4-af50-80b7aab2df78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861047305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.861047305
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3744691224
Short name T629
Test name
Test status
Simulation time 44574878 ps
CPU time 0.59 seconds
Started Feb 18 12:47:03 PM PST 24
Finished Feb 18 12:47:06 PM PST 24
Peak memory 184004 kb
Host smart-c052666d-5c7a-4ab9-a910-48d22dd52649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744691224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3744691224
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.51227258
Short name T634
Test name
Test status
Simulation time 13199517 ps
CPU time 0.59 seconds
Started Feb 18 12:47:05 PM PST 24
Finished Feb 18 12:47:10 PM PST 24
Peak memory 183928 kb
Host smart-e76e7618-fceb-4ef7-8d61-c25ef27d6355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51227258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.51227258
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1410788233
Short name T648
Test name
Test status
Simulation time 28455900 ps
CPU time 0.6 seconds
Started Feb 18 12:47:07 PM PST 24
Finished Feb 18 12:47:12 PM PST 24
Peak memory 184028 kb
Host smart-1a1205e9-a1d7-40d7-b288-0227e9f48094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410788233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1410788233
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2443021777
Short name T652
Test name
Test status
Simulation time 61641169 ps
CPU time 0.61 seconds
Started Feb 18 12:47:05 PM PST 24
Finished Feb 18 12:47:10 PM PST 24
Peak memory 184040 kb
Host smart-d90ec50b-517d-4a15-84e1-946a5a4a62fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443021777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2443021777
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1459282468
Short name T710
Test name
Test status
Simulation time 17468791 ps
CPU time 0.66 seconds
Started Feb 18 12:47:04 PM PST 24
Finished Feb 18 12:47:08 PM PST 24
Peak memory 184044 kb
Host smart-5b58600d-fb75-48af-ad0a-cee76cfb4b4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459282468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1459282468
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.445518087
Short name T703
Test name
Test status
Simulation time 45435041 ps
CPU time 0.56 seconds
Started Feb 18 12:47:04 PM PST 24
Finished Feb 18 12:47:08 PM PST 24
Peak memory 184016 kb
Host smart-f9f1958a-0010-46b9-88af-63b301fe03b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445518087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.445518087
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2176053465
Short name T89
Test name
Test status
Simulation time 231927589 ps
CPU time 1.17 seconds
Started Feb 18 12:46:33 PM PST 24
Finished Feb 18 12:46:44 PM PST 24
Peak memory 184292 kb
Host smart-c940937d-7c7e-4e78-85d8-a393ac254304
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176053465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2176053465
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3279231269
Short name T94
Test name
Test status
Simulation time 3333880216 ps
CPU time 9.47 seconds
Started Feb 18 12:46:34 PM PST 24
Finished Feb 18 12:46:54 PM PST 24
Peak memory 192388 kb
Host smart-02c3bf03-8d9c-4a00-910f-ce8886d9bf1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279231269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3279231269
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2105918472
Short name T625
Test name
Test status
Simulation time 38209461 ps
CPU time 0.61 seconds
Started Feb 18 12:46:39 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 194148 kb
Host smart-1b85c994-926a-42e5-80c8-432ee5fbc968
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105918472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2105918472
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.988410467
Short name T64
Test name
Test status
Simulation time 84534919 ps
CPU time 2.22 seconds
Started Feb 18 12:46:42 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 198972 kb
Host smart-258ea92f-fbcb-464e-b1b1-99d2c4896446
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988410467 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.988410467
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1427697988
Short name T86
Test name
Test status
Simulation time 89409253 ps
CPU time 0.71 seconds
Started Feb 18 12:46:34 PM PST 24
Finished Feb 18 12:46:45 PM PST 24
Peak memory 194900 kb
Host smart-6cdf079c-7929-4e6f-bc9f-fe3fcd973878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427697988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1427697988
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1969380750
Short name T602
Test name
Test status
Simulation time 13015766 ps
CPU time 0.54 seconds
Started Feb 18 12:46:34 PM PST 24
Finished Feb 18 12:46:43 PM PST 24
Peak memory 184040 kb
Host smart-4f728e59-38dc-43c8-b133-c8a7176c6c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969380750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1969380750
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.427326892
Short name T693
Test name
Test status
Simulation time 55055115 ps
CPU time 1.28 seconds
Started Feb 18 12:46:31 PM PST 24
Finished Feb 18 12:46:39 PM PST 24
Peak memory 192536 kb
Host smart-d7dda7ad-bc5c-46b1-a3a4-b9c0c768ce4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427326892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.427326892
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1824713521
Short name T616
Test name
Test status
Simulation time 26428054 ps
CPU time 1.21 seconds
Started Feb 18 12:46:36 PM PST 24
Finished Feb 18 12:46:48 PM PST 24
Peak memory 198832 kb
Host smart-34d4b807-fc42-4ad6-9641-d935b0539d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824713521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1824713521
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3293582299
Short name T658
Test name
Test status
Simulation time 41609172 ps
CPU time 0.56 seconds
Started Feb 18 12:47:06 PM PST 24
Finished Feb 18 12:47:11 PM PST 24
Peak memory 184040 kb
Host smart-742c0770-a965-4503-ba8c-2ceec5b6673b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293582299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3293582299
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3854282053
Short name T621
Test name
Test status
Simulation time 11680522 ps
CPU time 0.59 seconds
Started Feb 18 12:47:05 PM PST 24
Finished Feb 18 12:47:10 PM PST 24
Peak memory 184036 kb
Host smart-4bfd0f18-c486-49ac-a040-4d8302139198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854282053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3854282053
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2130294557
Short name T691
Test name
Test status
Simulation time 16120857 ps
CPU time 0.62 seconds
Started Feb 18 12:47:08 PM PST 24
Finished Feb 18 12:47:13 PM PST 24
Peak memory 183980 kb
Host smart-6b1b3517-97f5-4af0-a30f-55e3116ac272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130294557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2130294557
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1313272922
Short name T677
Test name
Test status
Simulation time 13194180 ps
CPU time 0.56 seconds
Started Feb 18 12:47:03 PM PST 24
Finished Feb 18 12:47:06 PM PST 24
Peak memory 183980 kb
Host smart-f0743815-f92a-48e1-a620-c51cfe260280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313272922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1313272922
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3777945380
Short name T645
Test name
Test status
Simulation time 18956665 ps
CPU time 0.62 seconds
Started Feb 18 12:47:05 PM PST 24
Finished Feb 18 12:47:10 PM PST 24
Peak memory 184036 kb
Host smart-e22c717b-c9d1-4c6f-b75f-24ea2879ece1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777945380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3777945380
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.87910120
Short name T663
Test name
Test status
Simulation time 13659945 ps
CPU time 0.6 seconds
Started Feb 18 12:47:05 PM PST 24
Finished Feb 18 12:47:10 PM PST 24
Peak memory 184056 kb
Host smart-9aa85101-d941-4796-91eb-a992e8470d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87910120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.87910120
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.860027402
Short name T644
Test name
Test status
Simulation time 140816002 ps
CPU time 0.58 seconds
Started Feb 18 12:47:09 PM PST 24
Finished Feb 18 12:47:13 PM PST 24
Peak memory 183964 kb
Host smart-d8b2bfa7-b7f9-4828-9f53-9c715ab22ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860027402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.860027402
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2906584710
Short name T643
Test name
Test status
Simulation time 30821595 ps
CPU time 0.61 seconds
Started Feb 18 12:47:09 PM PST 24
Finished Feb 18 12:47:13 PM PST 24
Peak memory 183964 kb
Host smart-c2da7a82-7506-48b4-8a60-32950164c8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906584710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2906584710
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1880124580
Short name T640
Test name
Test status
Simulation time 15233300 ps
CPU time 0.61 seconds
Started Feb 18 12:47:04 PM PST 24
Finished Feb 18 12:47:08 PM PST 24
Peak memory 184032 kb
Host smart-cdfa8b1f-9978-48c5-9119-b3354bd5dee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880124580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1880124580
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.541513884
Short name T639
Test name
Test status
Simulation time 30796859 ps
CPU time 0.61 seconds
Started Feb 18 12:47:05 PM PST 24
Finished Feb 18 12:47:09 PM PST 24
Peak memory 184044 kb
Host smart-deeb24b1-048b-426f-8676-0aaad946e829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541513884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.541513884
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3269127638
Short name T700
Test name
Test status
Simulation time 36127738463 ps
CPU time 482.38 seconds
Started Feb 18 12:46:40 PM PST 24
Finished Feb 18 12:54:51 PM PST 24
Peak memory 209956 kb
Host smart-26709a16-6083-4ded-9a49-fd39a7aeabe4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269127638 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3269127638
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3727153356
Short name T611
Test name
Test status
Simulation time 72816049 ps
CPU time 0.7 seconds
Started Feb 18 12:46:34 PM PST 24
Finished Feb 18 12:46:44 PM PST 24
Peak memory 195124 kb
Host smart-2c1f1e8b-7bf2-4981-ae24-31c559a93a7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727153356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3727153356
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3376797496
Short name T591
Test name
Test status
Simulation time 73743012 ps
CPU time 0.56 seconds
Started Feb 18 12:46:39 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 183932 kb
Host smart-b67a6d93-f6cf-431f-949f-8cf912411660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376797496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3376797496
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.450418183
Short name T608
Test name
Test status
Simulation time 227677924 ps
CPU time 1.06 seconds
Started Feb 18 12:46:34 PM PST 24
Finished Feb 18 12:46:45 PM PST 24
Peak memory 192436 kb
Host smart-f2ade400-32cf-4431-88a0-60b580004c24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450418183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.450418183
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1384483765
Short name T613
Test name
Test status
Simulation time 210123327 ps
CPU time 1.76 seconds
Started Feb 18 12:46:35 PM PST 24
Finished Feb 18 12:46:47 PM PST 24
Peak memory 198784 kb
Host smart-956d11a0-6dff-488c-8298-45569ff44914
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384483765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1384483765
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2899496790
Short name T706
Test name
Test status
Simulation time 343147902 ps
CPU time 2.63 seconds
Started Feb 18 12:46:41 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 198980 kb
Host smart-f89f86bb-057d-4681-80ac-090caa9fb6b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899496790 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2899496790
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2546313375
Short name T615
Test name
Test status
Simulation time 13458056 ps
CPU time 0.67 seconds
Started Feb 18 12:46:39 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 194460 kb
Host smart-f4e611bf-a3b0-4f8e-8790-8b13589a0323
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546313375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2546313375
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.123861941
Short name T626
Test name
Test status
Simulation time 48797867 ps
CPU time 0.56 seconds
Started Feb 18 12:46:48 PM PST 24
Finished Feb 18 12:46:56 PM PST 24
Peak memory 183948 kb
Host smart-c0baf5a5-9227-423d-acc8-34cbc92bfa0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123861941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.123861941
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3778632361
Short name T630
Test name
Test status
Simulation time 252418681 ps
CPU time 1.43 seconds
Started Feb 18 12:46:44 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 192528 kb
Host smart-fa6239ff-11b1-48fb-ad14-5c931331ef14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778632361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3778632361
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.420786576
Short name T656
Test name
Test status
Simulation time 228150009 ps
CPU time 1.42 seconds
Started Feb 18 12:46:34 PM PST 24
Finished Feb 18 12:46:45 PM PST 24
Peak memory 198860 kb
Host smart-a77dde96-d547-4fac-9ab5-79b9ccf56a00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420786576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.420786576
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3081614993
Short name T682
Test name
Test status
Simulation time 95951978 ps
CPU time 1.68 seconds
Started Feb 18 12:46:42 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 198404 kb
Host smart-c9d5b121-92f3-4ae5-a39a-387fb423d220
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081614993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3081614993
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1862549407
Short name T96
Test name
Test status
Simulation time 15791625 ps
CPU time 0.68 seconds
Started Feb 18 12:46:38 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 194624 kb
Host smart-d80e50fb-ba8d-4c72-a7ea-2948e5641f72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862549407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1862549407
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.66322300
Short name T617
Test name
Test status
Simulation time 39250438 ps
CPU time 0.58 seconds
Started Feb 18 12:46:41 PM PST 24
Finished Feb 18 12:46:50 PM PST 24
Peak memory 183920 kb
Host smart-cd8478a9-e85a-450e-8d2b-daaec70fc5ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66322300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.66322300
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2557423987
Short name T631
Test name
Test status
Simulation time 28083700 ps
CPU time 0.8 seconds
Started Feb 18 12:46:44 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 195968 kb
Host smart-339287fb-120b-4465-8cc2-b524c15215b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557423987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2557423987
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1858911264
Short name T598
Test name
Test status
Simulation time 81420457 ps
CPU time 2.17 seconds
Started Feb 18 12:46:43 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 198888 kb
Host smart-047229d5-5374-4f35-a448-f848cc103ace
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858911264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1858911264
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1226679223
Short name T683
Test name
Test status
Simulation time 199336767 ps
CPU time 2.12 seconds
Started Feb 18 12:46:43 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 198708 kb
Host smart-dacd81bf-74ad-4b8c-9726-e9e5673fe7f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226679223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1226679223
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2372758232
Short name T654
Test name
Test status
Simulation time 102583624 ps
CPU time 6.33 seconds
Started Feb 18 12:46:38 PM PST 24
Finished Feb 18 12:46:55 PM PST 24
Peak memory 198984 kb
Host smart-b5596a0a-ac8e-4bcd-a6b3-c5257fbf9f99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372758232 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2372758232
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3296917026
Short name T704
Test name
Test status
Simulation time 86292393 ps
CPU time 0.73 seconds
Started Feb 18 12:46:44 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 194976 kb
Host smart-8f79b09d-75e8-473f-93d9-758b89f85838
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296917026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3296917026
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2619743062
Short name T595
Test name
Test status
Simulation time 12140886 ps
CPU time 0.57 seconds
Started Feb 18 12:46:43 PM PST 24
Finished Feb 18 12:46:51 PM PST 24
Peak memory 184024 kb
Host smart-da76a14a-815d-4357-ad92-68e5f341ea4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619743062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2619743062
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.432709057
Short name T675
Test name
Test status
Simulation time 18543925 ps
CPU time 0.79 seconds
Started Feb 18 12:46:44 PM PST 24
Finished Feb 18 12:46:52 PM PST 24
Peak memory 192236 kb
Host smart-72eaa5dd-dc7a-4ecd-9f2c-ae69764d9342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432709057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.432709057
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3912742167
Short name T614
Test name
Test status
Simulation time 329645461 ps
CPU time 1.86 seconds
Started Feb 18 12:46:36 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 198908 kb
Host smart-482c5372-cff1-4bdf-a955-fac980633f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912742167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3912742167
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3303879807
Short name T135
Test name
Test status
Simulation time 110900042 ps
CPU time 1.84 seconds
Started Feb 18 12:46:43 PM PST 24
Finished Feb 18 12:46:53 PM PST 24
Peak memory 198472 kb
Host smart-7950b694-d89b-4579-9f6e-58d729fe7656
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303879807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3303879807
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3341136137
Short name T711
Test name
Test status
Simulation time 24805211 ps
CPU time 0.67 seconds
Started Feb 18 12:46:37 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 194420 kb
Host smart-68ab897d-cb93-4bd5-8cdd-acc2c0e57265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341136137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3341136137
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.756527461
Short name T647
Test name
Test status
Simulation time 24223397 ps
CPU time 0.61 seconds
Started Feb 18 12:46:38 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 184020 kb
Host smart-deaaa9fb-f329-4bb4-8607-709c3d6d75ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756527461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.756527461
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3511257402
Short name T661
Test name
Test status
Simulation time 30874593 ps
CPU time 1.3 seconds
Started Feb 18 12:46:39 PM PST 24
Finished Feb 18 12:46:50 PM PST 24
Peak memory 196940 kb
Host smart-9b8497e9-fd88-41a2-8cc4-7e795c3961d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511257402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3511257402
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.677041554
Short name T694
Test name
Test status
Simulation time 125600199 ps
CPU time 2.79 seconds
Started Feb 18 12:46:37 PM PST 24
Finished Feb 18 12:46:50 PM PST 24
Peak memory 198876 kb
Host smart-7cf1dade-b66f-4e00-a790-c9eb6d7edba0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677041554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.677041554
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1060275738
Short name T619
Test name
Test status
Simulation time 106573296 ps
CPU time 1.23 seconds
Started Feb 18 12:46:36 PM PST 24
Finished Feb 18 12:46:49 PM PST 24
Peak memory 198100 kb
Host smart-c547d5d1-9084-4045-a9e8-556471322446
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060275738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1060275738
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1981434445
Short name T201
Test name
Test status
Simulation time 12201734 ps
CPU time 0.59 seconds
Started Feb 18 01:45:16 PM PST 24
Finished Feb 18 01:45:19 PM PST 24
Peak memory 193952 kb
Host smart-3e3748b1-c885-437d-ac06-9654bef89327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981434445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1981434445
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3484964141
Short name T50
Test name
Test status
Simulation time 629615554 ps
CPU time 16.48 seconds
Started Feb 18 01:45:10 PM PST 24
Finished Feb 18 01:45:31 PM PST 24
Peak memory 207700 kb
Host smart-b9af446e-a564-4dda-86ab-ae045b9b3182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3484964141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3484964141
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2158019503
Short name T385
Test name
Test status
Simulation time 801724835 ps
CPU time 8.82 seconds
Started Feb 18 01:45:19 PM PST 24
Finished Feb 18 01:45:38 PM PST 24
Peak memory 199284 kb
Host smart-a129c05f-d598-4ce1-8b9a-19909e4fa74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158019503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2158019503
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.414974679
Short name T549
Test name
Test status
Simulation time 5209948446 ps
CPU time 128.62 seconds
Started Feb 18 01:45:19 PM PST 24
Finished Feb 18 01:47:37 PM PST 24
Peak memory 199584 kb
Host smart-14b43544-fa12-4105-af9a-68fec1c6e8b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414974679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.414974679
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.4096265889
Short name T406
Test name
Test status
Simulation time 41615529428 ps
CPU time 57.92 seconds
Started Feb 18 01:45:26 PM PST 24
Finished Feb 18 01:46:30 PM PST 24
Peak memory 199352 kb
Host smart-ae0e5f1f-19dc-4699-b42b-57ec4ed25160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096265889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.4096265889
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2431731062
Short name T31
Test name
Test status
Simulation time 2635468226 ps
CPU time 71.23 seconds
Started Feb 18 01:45:13 PM PST 24
Finished Feb 18 01:46:27 PM PST 24
Peak memory 199584 kb
Host smart-f3fb30e3-b289-4341-9b5c-3caf3252a924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431731062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2431731062
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1664839172
Short name T392
Test name
Test status
Simulation time 225902105 ps
CPU time 2.99 seconds
Started Feb 18 01:45:10 PM PST 24
Finished Feb 18 01:45:17 PM PST 24
Peak memory 199524 kb
Host smart-ea6426e7-5375-49a3-886e-06dbe27b6d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664839172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1664839172
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.4008386043
Short name T470
Test name
Test status
Simulation time 163109000820 ps
CPU time 617.13 seconds
Started Feb 18 01:45:09 PM PST 24
Finished Feb 18 01:55:31 PM PST 24
Peak memory 240480 kb
Host smart-141c84aa-6821-4f7c-abc7-e3ad336e1b55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008386043 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.4008386043
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.676541212
Short name T350
Test name
Test status
Simulation time 95752252 ps
CPU time 0.91 seconds
Started Feb 18 01:45:11 PM PST 24
Finished Feb 18 01:45:16 PM PST 24
Peak memory 196636 kb
Host smart-00f924db-e6ba-4870-ae97-042f18e4d788
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676541212 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.676541212
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1741997851
Short name T508
Test name
Test status
Simulation time 8316995885 ps
CPU time 402.41 seconds
Started Feb 18 01:45:26 PM PST 24
Finished Feb 18 01:52:14 PM PST 24
Peak memory 199304 kb
Host smart-6c23c9d2-d8d5-4f05-8a3b-d908b2bbe589
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741997851 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.1741997851
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3817807531
Short name T17
Test name
Test status
Simulation time 8100625901 ps
CPU time 72.05 seconds
Started Feb 18 01:45:16 PM PST 24
Finished Feb 18 01:46:30 PM PST 24
Peak memory 199608 kb
Host smart-d3dd6da7-ea1f-48f9-82db-f405082bded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817807531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3817807531
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1796666595
Short name T176
Test name
Test status
Simulation time 14136409 ps
CPU time 0.65 seconds
Started Feb 18 01:45:26 PM PST 24
Finished Feb 18 01:45:33 PM PST 24
Peak memory 193688 kb
Host smart-1bf8da00-0b9b-4a4c-ae74-7fb2ccdb00f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796666595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1796666595
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.943397809
Short name T445
Test name
Test status
Simulation time 3003687668 ps
CPU time 22.02 seconds
Started Feb 18 01:45:11 PM PST 24
Finished Feb 18 01:45:37 PM PST 24
Peak memory 207792 kb
Host smart-72aed8fe-6fbe-4e83-ac70-c3eee8968ce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943397809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.943397809
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2291438721
Short name T393
Test name
Test status
Simulation time 1244879569 ps
CPU time 24.2 seconds
Started Feb 18 01:45:10 PM PST 24
Finished Feb 18 01:45:38 PM PST 24
Peak memory 199576 kb
Host smart-cb5cafc6-86e3-4799-9b5f-01efb32b15c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291438721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2291438721
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3471951855
Short name T332
Test name
Test status
Simulation time 944517145 ps
CPU time 49.41 seconds
Started Feb 18 01:45:20 PM PST 24
Finished Feb 18 01:46:18 PM PST 24
Peak memory 199520 kb
Host smart-51cc73a0-09e9-4c90-bb67-637d5efd6970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471951855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3471951855
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_long_msg.455525688
Short name T329
Test name
Test status
Simulation time 38775169925 ps
CPU time 78.38 seconds
Started Feb 18 01:45:09 PM PST 24
Finished Feb 18 01:46:32 PM PST 24
Peak memory 199584 kb
Host smart-7cdae18f-4a1b-4a0c-8903-124d817cb547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455525688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.455525688
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3339301077
Short name T44
Test name
Test status
Simulation time 167252491 ps
CPU time 0.91 seconds
Started Feb 18 01:45:26 PM PST 24
Finished Feb 18 01:45:33 PM PST 24
Peak memory 217720 kb
Host smart-c6ba4b6d-edf1-4ca7-b8a7-46e8e926a8ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339301077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3339301077
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.4084081907
Short name T401
Test name
Test status
Simulation time 44619028 ps
CPU time 0.84 seconds
Started Feb 18 01:45:11 PM PST 24
Finished Feb 18 01:45:16 PM PST 24
Peak memory 196812 kb
Host smart-76a77d1d-dc19-4265-b45b-72aff6ae985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084081907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4084081907
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.4245744721
Short name T547
Test name
Test status
Simulation time 105148020 ps
CPU time 0.92 seconds
Started Feb 18 01:45:23 PM PST 24
Finished Feb 18 01:45:32 PM PST 24
Peak memory 198080 kb
Host smart-54aa5eaa-2842-4cd5-9c27-f42813227028
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245744721 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.4245744721
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3701818714
Short name T53
Test name
Test status
Simulation time 82359129685 ps
CPU time 479.22 seconds
Started Feb 18 01:45:09 PM PST 24
Finished Feb 18 01:53:13 PM PST 24
Peak memory 199540 kb
Host smart-4b44688a-2729-40f9-a32a-cd5f66d61ea8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701818714 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.3701818714
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2904394813
Short name T208
Test name
Test status
Simulation time 2247256476 ps
CPU time 16.55 seconds
Started Feb 18 01:45:26 PM PST 24
Finished Feb 18 01:45:48 PM PST 24
Peak memory 199504 kb
Host smart-8ac84258-5727-4390-b397-bfb32103c203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904394813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2904394813
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1737945645
Short name T437
Test name
Test status
Simulation time 11273257 ps
CPU time 0.56 seconds
Started Feb 18 01:45:43 PM PST 24
Finished Feb 18 01:45:49 PM PST 24
Peak memory 193792 kb
Host smart-85dce530-8ec2-4941-bea1-d70a971fd50b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737945645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1737945645
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1450678538
Short name T307
Test name
Test status
Simulation time 704734001 ps
CPU time 22.81 seconds
Started Feb 18 01:45:44 PM PST 24
Finished Feb 18 01:46:12 PM PST 24
Peak memory 215848 kb
Host smart-e1798dea-20c8-4340-92b1-40c724e014c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450678538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1450678538
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1795587548
Short name T254
Test name
Test status
Simulation time 5582531256 ps
CPU time 5.52 seconds
Started Feb 18 01:45:45 PM PST 24
Finished Feb 18 01:45:55 PM PST 24
Peak memory 199492 kb
Host smart-d1d832a2-486e-4238-b3f5-6e14a9328573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795587548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1795587548
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1521475802
Short name T381
Test name
Test status
Simulation time 1833352307 ps
CPU time 101.36 seconds
Started Feb 18 01:45:42 PM PST 24
Finished Feb 18 01:47:29 PM PST 24
Peak memory 199532 kb
Host smart-c4392e93-cbd5-4533-bd3c-744e4846b911
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521475802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1521475802
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1706637257
Short name T424
Test name
Test status
Simulation time 2750575669 ps
CPU time 141.06 seconds
Started Feb 18 01:45:38 PM PST 24
Finished Feb 18 01:48:06 PM PST 24
Peak memory 199588 kb
Host smart-b88448e1-4bf9-4883-8426-f106f1e01c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706637257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1706637257
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3209164242
Short name T55
Test name
Test status
Simulation time 1854047473 ps
CPU time 25.65 seconds
Started Feb 18 01:45:42 PM PST 24
Finished Feb 18 01:46:13 PM PST 24
Peak memory 199536 kb
Host smart-7b0258cf-4368-416c-a02a-ae74a23dd5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209164242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3209164242
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.27689770
Short name T12
Test name
Test status
Simulation time 57727218 ps
CPU time 1.02 seconds
Started Feb 18 01:45:44 PM PST 24
Finished Feb 18 01:45:50 PM PST 24
Peak memory 198476 kb
Host smart-3d693757-2e6d-4a3b-81e8-9ae0b4be7748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27689770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.27689770
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3972351446
Short name T118
Test name
Test status
Simulation time 99117492442 ps
CPU time 1176.13 seconds
Started Feb 18 01:45:41 PM PST 24
Finished Feb 18 02:05:23 PM PST 24
Peak memory 224200 kb
Host smart-31b43d67-b31e-4924-b838-d4457edc9208
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972351446 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3972351446
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3059794926
Short name T77
Test name
Test status
Simulation time 184953557 ps
CPU time 1.11 seconds
Started Feb 18 01:45:41 PM PST 24
Finished Feb 18 01:45:48 PM PST 24
Peak memory 198304 kb
Host smart-ebaadbc0-0e97-4d1b-9938-956e6edf99e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059794926 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3059794926
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1963155432
Short name T489
Test name
Test status
Simulation time 27138755802 ps
CPU time 426.27 seconds
Started Feb 18 01:45:42 PM PST 24
Finished Feb 18 01:52:54 PM PST 24
Peak memory 199540 kb
Host smart-22c3153a-ee3d-475c-8aa2-501ae848f930
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963155432 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.1963155432
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1577098482
Short name T246
Test name
Test status
Simulation time 1512160251 ps
CPU time 49.51 seconds
Started Feb 18 01:45:42 PM PST 24
Finished Feb 18 01:46:37 PM PST 24
Peak memory 199560 kb
Host smart-7a687f10-a237-418e-a9d7-11459d4107c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577098482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1577098482
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2804738052
Short name T290
Test name
Test status
Simulation time 49144122 ps
CPU time 0.57 seconds
Started Feb 18 01:45:51 PM PST 24
Finished Feb 18 01:45:53 PM PST 24
Peak memory 193932 kb
Host smart-8d73a633-f508-45c8-bd9e-d3c2ac84370c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804738052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2804738052
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4186397692
Short name T417
Test name
Test status
Simulation time 753288330 ps
CPU time 34.39 seconds
Started Feb 18 01:45:40 PM PST 24
Finished Feb 18 01:46:21 PM PST 24
Peak memory 199508 kb
Host smart-43849365-9bf0-468d-bde4-3a61df094052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186397692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4186397692
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1812158344
Short name T269
Test name
Test status
Simulation time 4159282426 ps
CPU time 53.83 seconds
Started Feb 18 01:45:43 PM PST 24
Finished Feb 18 01:46:42 PM PST 24
Peak memory 199488 kb
Host smart-cb914eb2-94b0-4d61-b733-d25986a38b87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812158344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1812158344
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3478976647
Short name T552
Test name
Test status
Simulation time 1382375774 ps
CPU time 22.4 seconds
Started Feb 18 01:45:38 PM PST 24
Finished Feb 18 01:46:08 PM PST 24
Peak memory 199432 kb
Host smart-42fdb68a-dee3-455b-ac8d-fcfa8ca6da50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478976647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3478976647
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.630058607
Short name T412
Test name
Test status
Simulation time 1327379881 ps
CPU time 24.42 seconds
Started Feb 18 01:45:40 PM PST 24
Finished Feb 18 01:46:11 PM PST 24
Peak memory 199548 kb
Host smart-555ca1fb-828b-4fbe-b3da-46652439bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630058607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.630058607
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2301108249
Short name T491
Test name
Test status
Simulation time 104958927 ps
CPU time 1.55 seconds
Started Feb 18 01:45:43 PM PST 24
Finished Feb 18 01:45:49 PM PST 24
Peak memory 199516 kb
Host smart-5f0c545b-3ee6-40cf-a160-d329f5e325ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301108249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2301108249
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1392295513
Short name T10
Test name
Test status
Simulation time 475813783361 ps
CPU time 1568.72 seconds
Started Feb 18 01:45:47 PM PST 24
Finished Feb 18 02:11:59 PM PST 24
Peak memory 234636 kb
Host smart-a00dbaea-253b-47a1-b893-9cc401a968b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392295513 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1392295513
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1641189486
Short name T182
Test name
Test status
Simulation time 77357558 ps
CPU time 0.92 seconds
Started Feb 18 01:45:48 PM PST 24
Finished Feb 18 01:45:52 PM PST 24
Peak memory 197412 kb
Host smart-2b58cd14-316a-4b19-9a6a-45b01de9138d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641189486 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1641189486
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2001005590
Short name T582
Test name
Test status
Simulation time 30863258961 ps
CPU time 370.11 seconds
Started Feb 18 01:45:47 PM PST 24
Finished Feb 18 01:52:01 PM PST 24
Peak memory 199504 kb
Host smart-6297d53d-ab15-4506-bc02-bf4af443ef4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001005590 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.2001005590
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.605562731
Short name T304
Test name
Test status
Simulation time 1592099449 ps
CPU time 60.47 seconds
Started Feb 18 01:45:41 PM PST 24
Finished Feb 18 01:46:47 PM PST 24
Peak memory 199412 kb
Host smart-012d16d3-d6e4-48a5-9785-4421b582d0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605562731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.605562731
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1771276407
Short name T372
Test name
Test status
Simulation time 58618643 ps
CPU time 0.56 seconds
Started Feb 18 01:45:48 PM PST 24
Finished Feb 18 01:45:52 PM PST 24
Peak memory 193708 kb
Host smart-568d2028-fd75-40f3-bf92-4f3ab8cd2514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771276407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1771276407
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1443496544
Short name T459
Test name
Test status
Simulation time 2863020715 ps
CPU time 42.48 seconds
Started Feb 18 01:45:51 PM PST 24
Finished Feb 18 01:46:35 PM PST 24
Peak memory 207688 kb
Host smart-51054de2-bc24-43fb-a356-e8323b7d6051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443496544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1443496544
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.416627819
Short name T556
Test name
Test status
Simulation time 34875264169 ps
CPU time 43.81 seconds
Started Feb 18 01:45:52 PM PST 24
Finished Feb 18 01:46:37 PM PST 24
Peak memory 199488 kb
Host smart-af21cf60-17d1-47c5-bef8-83a0c9f4b0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416627819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.416627819
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3591607851
Short name T442
Test name
Test status
Simulation time 1335262276 ps
CPU time 69.08 seconds
Started Feb 18 01:45:47 PM PST 24
Finished Feb 18 01:47:00 PM PST 24
Peak memory 199516 kb
Host smart-25b38a80-82f4-430c-accb-ef14b4e4d395
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591607851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3591607851
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.699792829
Short name T451
Test name
Test status
Simulation time 7968662245 ps
CPU time 105.7 seconds
Started Feb 18 01:45:48 PM PST 24
Finished Feb 18 01:47:37 PM PST 24
Peak memory 199620 kb
Host smart-42600dc5-5dd6-4e95-8880-5885fe6a42f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699792829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.699792829
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.221531527
Short name T236
Test name
Test status
Simulation time 5740727668 ps
CPU time 26.04 seconds
Started Feb 18 01:45:50 PM PST 24
Finished Feb 18 01:46:18 PM PST 24
Peak memory 199608 kb
Host smart-7a2e3a43-9ae1-428b-97d9-f3d84ec40196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221531527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.221531527
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3768212455
Short name T527
Test name
Test status
Simulation time 60507017 ps
CPU time 1.64 seconds
Started Feb 18 01:45:48 PM PST 24
Finished Feb 18 01:45:53 PM PST 24
Peak memory 199468 kb
Host smart-cc47418f-6d7e-4d78-9faa-982232336e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768212455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3768212455
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.964826385
Short name T578
Test name
Test status
Simulation time 62942323 ps
CPU time 1.19 seconds
Started Feb 18 01:45:50 PM PST 24
Finished Feb 18 01:45:53 PM PST 24
Peak memory 197500 kb
Host smart-47dba5c8-0f39-4edf-8fc7-61bfbff3e6b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964826385 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.964826385
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1333342076
Short name T348
Test name
Test status
Simulation time 183128404126 ps
CPU time 504.42 seconds
Started Feb 18 01:45:48 PM PST 24
Finished Feb 18 01:54:16 PM PST 24
Peak memory 199584 kb
Host smart-d49e4543-163b-4f50-8f9e-8e762d89fd28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333342076 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.1333342076
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1698171872
Short name T28
Test name
Test status
Simulation time 956833678 ps
CPU time 49.12 seconds
Started Feb 18 01:45:47 PM PST 24
Finished Feb 18 01:46:40 PM PST 24
Peak memory 199504 kb
Host smart-6aa844d0-0694-4208-a5f4-095bafd5a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698171872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1698171872
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.3421313014
Short name T61
Test name
Test status
Simulation time 39475879712 ps
CPU time 341.33 seconds
Started Feb 18 01:48:47 PM PST 24
Finished Feb 18 01:54:30 PM PST 24
Peak memory 215816 kb
Host smart-62c78d68-8691-4ab2-b61d-02a95344361c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421313014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.3421313014
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2343013380
Short name T180
Test name
Test status
Simulation time 27090111 ps
CPU time 0.6 seconds
Started Feb 18 01:45:57 PM PST 24
Finished Feb 18 01:46:00 PM PST 24
Peak memory 193616 kb
Host smart-8f80d453-eefb-4635-a9e2-4c78c295dd80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343013380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2343013380
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3708426714
Short name T447
Test name
Test status
Simulation time 1179007893 ps
CPU time 11.21 seconds
Started Feb 18 01:45:52 PM PST 24
Finished Feb 18 01:46:04 PM PST 24
Peak memory 213888 kb
Host smart-41cd8964-b77f-4897-8dd5-4fa70f6a0c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708426714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3708426714
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.751318502
Short name T514
Test name
Test status
Simulation time 18480759741 ps
CPU time 38.28 seconds
Started Feb 18 01:45:53 PM PST 24
Finished Feb 18 01:46:34 PM PST 24
Peak memory 199564 kb
Host smart-dba9bcdd-e80f-4568-842b-a3770bf059fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751318502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.751318502
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.4014622086
Short name T587
Test name
Test status
Simulation time 11338100516 ps
CPU time 148.37 seconds
Started Feb 18 01:45:51 PM PST 24
Finished Feb 18 01:48:21 PM PST 24
Peak memory 199556 kb
Host smart-0efb3fd8-f1a3-4bf4-b3e7-62e8a46c0958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4014622086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4014622086
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.4253506417
Short name T49
Test name
Test status
Simulation time 11615690 ps
CPU time 0.58 seconds
Started Feb 18 01:45:52 PM PST 24
Finished Feb 18 01:45:55 PM PST 24
Peak memory 193740 kb
Host smart-ee57fd92-69da-4f20-a9c1-9de9e49d4c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253506417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.4253506417
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3683058839
Short name T154
Test name
Test status
Simulation time 873619684 ps
CPU time 45.58 seconds
Started Feb 18 01:45:48 PM PST 24
Finished Feb 18 01:46:37 PM PST 24
Peak memory 199496 kb
Host smart-5518ffa1-9c86-4a88-a5fd-e851c9e0a07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683058839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3683058839
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2007803729
Short name T191
Test name
Test status
Simulation time 195582623 ps
CPU time 2.7 seconds
Started Feb 18 01:45:48 PM PST 24
Finished Feb 18 01:45:54 PM PST 24
Peak memory 198776 kb
Host smart-61d70d5d-6040-4f97-b557-e6d5344fd561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007803729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2007803729
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.430851709
Short name T438
Test name
Test status
Simulation time 18430411751 ps
CPU time 888.49 seconds
Started Feb 18 01:45:52 PM PST 24
Finished Feb 18 02:00:43 PM PST 24
Peak memory 232424 kb
Host smart-e538ab35-d9e4-4033-9d03-332438eb92d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430851709 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.430851709
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.992729550
Short name T262
Test name
Test status
Simulation time 42352151 ps
CPU time 0.88 seconds
Started Feb 18 01:45:52 PM PST 24
Finished Feb 18 01:45:55 PM PST 24
Peak memory 196640 kb
Host smart-57dc97e4-14c6-432f-8b06-a369bc82bec1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992729550 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.992729550
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.4038209598
Short name T441
Test name
Test status
Simulation time 150946789152 ps
CPU time 462.99 seconds
Started Feb 18 01:45:52 PM PST 24
Finished Feb 18 01:53:37 PM PST 24
Peak memory 199548 kb
Host smart-6aabbe1c-dff7-42c7-99bc-64e9b18bf57a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038209598 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.4038209598
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2946984207
Short name T305
Test name
Test status
Simulation time 1968111099 ps
CPU time 78.05 seconds
Started Feb 18 01:45:57 PM PST 24
Finished Feb 18 01:47:18 PM PST 24
Peak memory 199360 kb
Host smart-bb080f42-67d8-4722-8296-4f5520238f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946984207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2946984207
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3474090302
Short name T256
Test name
Test status
Simulation time 12355147 ps
CPU time 0.55 seconds
Started Feb 18 01:46:00 PM PST 24
Finished Feb 18 01:46:04 PM PST 24
Peak memory 193920 kb
Host smart-914c63ba-07c2-4da6-9b86-332b157722f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474090302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3474090302
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2796013194
Short name T19
Test name
Test status
Simulation time 2269078619 ps
CPU time 16.08 seconds
Started Feb 18 01:46:00 PM PST 24
Finished Feb 18 01:46:20 PM PST 24
Peak memory 207736 kb
Host smart-130fc077-1648-4e59-9cc0-c13800c0542c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796013194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2796013194
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1796800963
Short name T126
Test name
Test status
Simulation time 1093984775 ps
CPU time 19.35 seconds
Started Feb 18 01:45:52 PM PST 24
Finished Feb 18 01:46:14 PM PST 24
Peak memory 199448 kb
Host smart-6860c031-178f-4971-8c3d-f518135f804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796800963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1796800963
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3058373961
Short name T558
Test name
Test status
Simulation time 6735074167 ps
CPU time 57.93 seconds
Started Feb 18 01:45:53 PM PST 24
Finished Feb 18 01:46:54 PM PST 24
Peak memory 199576 kb
Host smart-0de19c19-8a01-4cde-8055-64e3acdbfaa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058373961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3058373961
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3916300629
Short name T35
Test name
Test status
Simulation time 57735544607 ps
CPU time 106.66 seconds
Started Feb 18 01:46:00 PM PST 24
Finished Feb 18 01:47:50 PM PST 24
Peak memory 199584 kb
Host smart-807e0d94-8fe3-4ca7-a984-37c834fe59cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916300629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3916300629
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3982865479
Short name T377
Test name
Test status
Simulation time 9746224925 ps
CPU time 60.8 seconds
Started Feb 18 01:45:52 PM PST 24
Finished Feb 18 01:46:55 PM PST 24
Peak memory 199572 kb
Host smart-7530c644-2506-44fa-a760-5652f656354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982865479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3982865479
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2032672812
Short name T484
Test name
Test status
Simulation time 315845698 ps
CPU time 4.32 seconds
Started Feb 18 01:45:52 PM PST 24
Finished Feb 18 01:45:59 PM PST 24
Peak memory 199504 kb
Host smart-02fe27b6-a2d8-46b6-82ef-331d9c4f8e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032672812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2032672812
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2372566911
Short name T291
Test name
Test status
Simulation time 2244624526 ps
CPU time 93.48 seconds
Started Feb 18 01:45:58 PM PST 24
Finished Feb 18 01:47:35 PM PST 24
Peak memory 240436 kb
Host smart-79d8a7a5-e9a0-41fa-930b-587dfa9376e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372566911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2372566911
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1383739430
Short name T75
Test name
Test status
Simulation time 27278519 ps
CPU time 0.98 seconds
Started Feb 18 01:45:59 PM PST 24
Finished Feb 18 01:46:04 PM PST 24
Peak memory 196824 kb
Host smart-1d3892fe-e441-40f6-ae89-deddb397dabc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383739430 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1383739430
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3845800731
Short name T586
Test name
Test status
Simulation time 104818057181 ps
CPU time 437.44 seconds
Started Feb 18 01:46:01 PM PST 24
Finished Feb 18 01:53:21 PM PST 24
Peak memory 199496 kb
Host smart-562342b8-17fc-468b-86ce-d06109036fb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845800731 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.3845800731
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1126534412
Short name T184
Test name
Test status
Simulation time 6334260047 ps
CPU time 22.62 seconds
Started Feb 18 01:46:02 PM PST 24
Finished Feb 18 01:46:27 PM PST 24
Peak memory 199556 kb
Host smart-f1b1b94f-d51f-4240-8e67-006e8c78272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126534412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1126534412
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2521246696
Short name T158
Test name
Test status
Simulation time 13556035 ps
CPU time 0.59 seconds
Started Feb 18 01:46:08 PM PST 24
Finished Feb 18 01:46:12 PM PST 24
Peak memory 194924 kb
Host smart-4183a91c-d817-4b89-8c80-008f431c6ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521246696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2521246696
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1387255083
Short name T260
Test name
Test status
Simulation time 618854759 ps
CPU time 11.13 seconds
Started Feb 18 01:46:07 PM PST 24
Finished Feb 18 01:46:22 PM PST 24
Peak memory 207696 kb
Host smart-b9a8ace5-f441-459c-952f-ca90915c013e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1387255083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1387255083
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.760221669
Short name T152
Test name
Test status
Simulation time 4086343452 ps
CPU time 8.83 seconds
Started Feb 18 01:46:08 PM PST 24
Finished Feb 18 01:46:21 PM PST 24
Peak memory 199520 kb
Host smart-e8162396-2486-4ec6-992d-1bd4d2306c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760221669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.760221669
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3888748470
Short name T481
Test name
Test status
Simulation time 5812299906 ps
CPU time 73.63 seconds
Started Feb 18 01:46:08 PM PST 24
Finished Feb 18 01:47:26 PM PST 24
Peak memory 199548 kb
Host smart-a12f773d-dede-421d-a318-156e4191ec35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888748470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3888748470
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1983664409
Short name T164
Test name
Test status
Simulation time 1260959161 ps
CPU time 61.83 seconds
Started Feb 18 01:46:07 PM PST 24
Finished Feb 18 01:47:12 PM PST 24
Peak memory 199556 kb
Host smart-accf9981-d9bd-4ec3-adb6-3554346ab044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983664409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1983664409
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3771397332
Short name T362
Test name
Test status
Simulation time 23067869932 ps
CPU time 104.4 seconds
Started Feb 18 01:46:00 PM PST 24
Finished Feb 18 01:47:48 PM PST 24
Peak memory 199592 kb
Host smart-e93d762e-8641-48b5-a645-56fd12bf5392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771397332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3771397332
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2218711528
Short name T81
Test name
Test status
Simulation time 62558871 ps
CPU time 1.01 seconds
Started Feb 18 01:46:01 PM PST 24
Finished Feb 18 01:46:05 PM PST 24
Peak memory 198332 kb
Host smart-87c4c538-25ad-49e8-82ca-0e94af1c434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218711528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2218711528
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.664868527
Short name T538
Test name
Test status
Simulation time 20479201636 ps
CPU time 971.32 seconds
Started Feb 18 01:46:07 PM PST 24
Finished Feb 18 02:02:22 PM PST 24
Peak memory 232416 kb
Host smart-79fae8aa-c721-4e7d-82b8-9648cfda7d18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664868527 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.664868527
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.775180532
Short name T502
Test name
Test status
Simulation time 31675675 ps
CPU time 1.11 seconds
Started Feb 18 01:46:10 PM PST 24
Finished Feb 18 01:46:14 PM PST 24
Peak memory 197784 kb
Host smart-72eb5449-1269-49d0-9715-97e39457f7a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775180532 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.775180532
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.283807962
Short name T380
Test name
Test status
Simulation time 161767788853 ps
CPU time 431.98 seconds
Started Feb 18 01:46:06 PM PST 24
Finished Feb 18 01:53:22 PM PST 24
Peak memory 199476 kb
Host smart-074e84bb-ed11-4f83-85cd-fbb438dfd578
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283807962 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.hmac_test_sha_vectors.283807962
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1632782344
Short name T177
Test name
Test status
Simulation time 1310483720 ps
CPU time 4.34 seconds
Started Feb 18 01:46:12 PM PST 24
Finished Feb 18 01:46:18 PM PST 24
Peak memory 199432 kb
Host smart-dbbb1839-21ab-4864-b8c3-a8d26e4d66dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632782344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1632782344
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.4151715757
Short name T435
Test name
Test status
Simulation time 104694137 ps
CPU time 0.56 seconds
Started Feb 18 01:46:19 PM PST 24
Finished Feb 18 01:46:21 PM PST 24
Peak memory 193964 kb
Host smart-def29554-ddc6-4cd6-8d61-f9bb5005f380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151715757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4151715757
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1287724391
Short name T220
Test name
Test status
Simulation time 2648338195 ps
CPU time 44.98 seconds
Started Feb 18 01:46:12 PM PST 24
Finished Feb 18 01:46:59 PM PST 24
Peak memory 218988 kb
Host smart-e9846396-49ea-46c6-9e42-989c3cec696d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287724391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1287724391
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2647819646
Short name T117
Test name
Test status
Simulation time 2069622359 ps
CPU time 19.77 seconds
Started Feb 18 01:46:20 PM PST 24
Finished Feb 18 01:46:45 PM PST 24
Peak memory 199472 kb
Host smart-d2724eaf-29cc-457c-b37c-bced09037f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647819646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2647819646
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.46102363
Short name T515
Test name
Test status
Simulation time 1031874047 ps
CPU time 27.03 seconds
Started Feb 18 01:46:08 PM PST 24
Finished Feb 18 01:46:38 PM PST 24
Peak memory 199512 kb
Host smart-cba65f35-cab5-4010-b31a-e8ff58860653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46102363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.46102363
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1775718753
Short name T369
Test name
Test status
Simulation time 31451139998 ps
CPU time 129.57 seconds
Started Feb 18 01:46:20 PM PST 24
Finished Feb 18 01:48:32 PM PST 24
Peak memory 199552 kb
Host smart-0dcdb46d-2ab1-4ca4-bcfe-d368978e607c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775718753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1775718753
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1309528259
Short name T9
Test name
Test status
Simulation time 4761251211 ps
CPU time 59.75 seconds
Started Feb 18 01:46:08 PM PST 24
Finished Feb 18 01:47:12 PM PST 24
Peak memory 199560 kb
Host smart-14a596cf-8d5f-4a3a-ba15-cf5471c7fdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309528259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1309528259
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2085887613
Short name T37
Test name
Test status
Simulation time 566968478 ps
CPU time 3.13 seconds
Started Feb 18 01:46:06 PM PST 24
Finished Feb 18 01:46:13 PM PST 24
Peak memory 199484 kb
Host smart-18a1523e-fd46-4604-b026-ef668f1a4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085887613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2085887613
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1389697489
Short name T313
Test name
Test status
Simulation time 39517477391 ps
CPU time 426.64 seconds
Started Feb 18 01:46:19 PM PST 24
Finished Feb 18 01:53:28 PM PST 24
Peak memory 227932 kb
Host smart-4acc6dcf-a715-4953-977a-3615c3958ab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389697489 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1389697489
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3632516671
Short name T217
Test name
Test status
Simulation time 37698298 ps
CPU time 0.92 seconds
Started Feb 18 01:46:20 PM PST 24
Finished Feb 18 01:46:26 PM PST 24
Peak memory 196956 kb
Host smart-483fd1fa-017c-4d98-ba11-712073935adc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632516671 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3632516671
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1182474144
Short name T144
Test name
Test status
Simulation time 54385231043 ps
CPU time 420.71 seconds
Started Feb 18 01:46:19 PM PST 24
Finished Feb 18 01:53:21 PM PST 24
Peak memory 199512 kb
Host smart-e8d98638-6444-4d48-9946-1743b856a146
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182474144 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.1182474144
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2260583197
Short name T252
Test name
Test status
Simulation time 825794879 ps
CPU time 10.61 seconds
Started Feb 18 01:46:19 PM PST 24
Finished Feb 18 01:46:32 PM PST 24
Peak memory 199516 kb
Host smart-269e2556-36c7-4c04-b0fa-0166cdc4eea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260583197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2260583197
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.89157591
Short name T309
Test name
Test status
Simulation time 37492360 ps
CPU time 0.55 seconds
Started Feb 18 01:46:19 PM PST 24
Finished Feb 18 01:46:22 PM PST 24
Peak memory 193736 kb
Host smart-5b613f86-793f-497b-85dc-28185e5b946a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89157591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.89157591
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2918275262
Short name T352
Test name
Test status
Simulation time 1419635458 ps
CPU time 2.37 seconds
Started Feb 18 01:46:20 PM PST 24
Finished Feb 18 01:46:27 PM PST 24
Peak memory 199544 kb
Host smart-5847b2d7-eb7d-48b5-b056-22f90868f3bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2918275262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2918275262
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3445997996
Short name T382
Test name
Test status
Simulation time 878315983 ps
CPU time 7.79 seconds
Started Feb 18 01:46:22 PM PST 24
Finished Feb 18 01:46:33 PM PST 24
Peak memory 199532 kb
Host smart-d775801f-cf01-4a21-a7c5-cdbeb47ac283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445997996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3445997996
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3772056476
Short name T103
Test name
Test status
Simulation time 10370411095 ps
CPU time 143.04 seconds
Started Feb 18 01:46:20 PM PST 24
Finished Feb 18 01:48:48 PM PST 24
Peak memory 199660 kb
Host smart-492312e7-0cbb-4b27-9eb3-fe9b1241c9fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772056476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3772056476
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3728408624
Short name T255
Test name
Test status
Simulation time 8438227743 ps
CPU time 112.59 seconds
Started Feb 18 01:46:17 PM PST 24
Finished Feb 18 01:48:11 PM PST 24
Peak memory 199596 kb
Host smart-13dbc542-d6e7-4906-8eb2-05d4f1159dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728408624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3728408624
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3187791560
Short name T188
Test name
Test status
Simulation time 4794769401 ps
CPU time 68.24 seconds
Started Feb 18 01:46:19 PM PST 24
Finished Feb 18 01:47:29 PM PST 24
Peak memory 199500 kb
Host smart-24003785-42b2-45f9-ba8f-06b9d3e1e996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187791560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3187791560
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3580070302
Short name T204
Test name
Test status
Simulation time 76274841 ps
CPU time 1.09 seconds
Started Feb 18 01:46:19 PM PST 24
Finished Feb 18 01:46:22 PM PST 24
Peak memory 198196 kb
Host smart-40c76a75-16e9-4992-a8f5-9261700a2c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580070302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3580070302
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2543305752
Short name T428
Test name
Test status
Simulation time 27009098223 ps
CPU time 361.97 seconds
Started Feb 18 01:46:20 PM PST 24
Finished Feb 18 01:52:25 PM PST 24
Peak memory 207816 kb
Host smart-1c7a4856-9765-4b6e-82bb-4df4a71f1670
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543305752 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2543305752
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1159401659
Short name T143
Test name
Test status
Simulation time 610482774 ps
CPU time 1.22 seconds
Started Feb 18 01:46:21 PM PST 24
Finished Feb 18 01:46:26 PM PST 24
Peak memory 198284 kb
Host smart-748b4b7d-eb3c-485a-a469-af8193404ada
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159401659 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1159401659
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.106524986
Short name T171
Test name
Test status
Simulation time 6907873335 ps
CPU time 354.6 seconds
Started Feb 18 01:46:20 PM PST 24
Finished Feb 18 01:52:17 PM PST 24
Peak memory 199492 kb
Host smart-c9a9659c-293b-40e5-82b2-26d6b908d7ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106524986 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.hmac_test_sha_vectors.106524986
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2484116634
Short name T439
Test name
Test status
Simulation time 884036647 ps
CPU time 14.18 seconds
Started Feb 18 01:46:20 PM PST 24
Finished Feb 18 01:46:38 PM PST 24
Peak memory 199524 kb
Host smart-32042c7d-4822-4512-a992-66e5b945bb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484116634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2484116634
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1414039038
Short name T533
Test name
Test status
Simulation time 12665616 ps
CPU time 0.66 seconds
Started Feb 18 01:46:26 PM PST 24
Finished Feb 18 01:46:29 PM PST 24
Peak memory 193760 kb
Host smart-567666e1-69d7-4b07-b40d-de0032d476bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414039038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1414039038
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1627913593
Short name T125
Test name
Test status
Simulation time 6752948426 ps
CPU time 61.2 seconds
Started Feb 18 01:46:26 PM PST 24
Finished Feb 18 01:47:29 PM PST 24
Peak memory 232224 kb
Host smart-bd7b2556-1512-476c-8bd5-bc825fc8959e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627913593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1627913593
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2273410781
Short name T450
Test name
Test status
Simulation time 1020723931 ps
CPU time 13.29 seconds
Started Feb 18 01:46:27 PM PST 24
Finished Feb 18 01:46:42 PM PST 24
Peak memory 199536 kb
Host smart-4926f1c7-8b24-44e2-b885-579addce5c74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2273410781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2273410781
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3208397040
Short name T371
Test name
Test status
Simulation time 11739416264 ps
CPU time 154.74 seconds
Started Feb 18 01:46:23 PM PST 24
Finished Feb 18 01:49:01 PM PST 24
Peak memory 199472 kb
Host smart-baf74f3b-9b60-4fab-a058-52b2f0cca697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208397040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3208397040
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.664470720
Short name T181
Test name
Test status
Simulation time 9317397578 ps
CPU time 61.15 seconds
Started Feb 18 01:46:23 PM PST 24
Finished Feb 18 01:47:27 PM PST 24
Peak memory 199620 kb
Host smart-b7a09917-475a-4974-8a1c-a4e1d979b098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664470720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.664470720
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.402685738
Short name T455
Test name
Test status
Simulation time 1267241202 ps
CPU time 3.62 seconds
Started Feb 18 01:46:20 PM PST 24
Finished Feb 18 01:46:26 PM PST 24
Peak memory 199548 kb
Host smart-e17b3d70-278c-4643-b2c2-de2570641c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402685738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.402685738
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.638991565
Short name T490
Test name
Test status
Simulation time 42043388065 ps
CPU time 135.73 seconds
Started Feb 18 01:46:23 PM PST 24
Finished Feb 18 01:48:42 PM PST 24
Peak memory 215972 kb
Host smart-af35d275-3ff4-44e9-b626-1dc311230e86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638991565 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.638991565
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.1909923309
Short name T328
Test name
Test status
Simulation time 39120078 ps
CPU time 0.94 seconds
Started Feb 18 01:46:23 PM PST 24
Finished Feb 18 01:46:27 PM PST 24
Peak memory 196892 kb
Host smart-72a669d8-c6f4-4b10-b646-8dec3c8f910c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909923309 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.1909923309
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2972736164
Short name T568
Test name
Test status
Simulation time 46863883278 ps
CPU time 326.65 seconds
Started Feb 18 01:46:22 PM PST 24
Finished Feb 18 01:51:52 PM PST 24
Peak memory 199520 kb
Host smart-b3fff128-46bb-4bc5-9d94-7d9b4c25ce44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972736164 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.2972736164
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.747002286
Short name T557
Test name
Test status
Simulation time 1948182501 ps
CPU time 23.54 seconds
Started Feb 18 01:46:23 PM PST 24
Finished Feb 18 01:46:50 PM PST 24
Peak memory 199464 kb
Host smart-fc2ef91b-c666-450c-a2a9-8e69cd68f867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747002286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.747002286
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1421602248
Short name T579
Test name
Test status
Simulation time 24457239 ps
CPU time 0.57 seconds
Started Feb 18 01:46:27 PM PST 24
Finished Feb 18 01:46:30 PM PST 24
Peak memory 193952 kb
Host smart-8ab9d3ad-4cbc-47be-a4f5-dbacd89d789c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421602248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1421602248
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3737824424
Short name T570
Test name
Test status
Simulation time 1561601190 ps
CPU time 19.12 seconds
Started Feb 18 01:46:29 PM PST 24
Finished Feb 18 01:46:51 PM PST 24
Peak memory 207736 kb
Host smart-121c031e-5891-4f84-8b74-6a1d5f8b7a0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737824424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3737824424
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.501252179
Short name T247
Test name
Test status
Simulation time 826222744 ps
CPU time 24.62 seconds
Started Feb 18 01:46:28 PM PST 24
Finished Feb 18 01:46:55 PM PST 24
Peak memory 199408 kb
Host smart-21f79ff8-0050-4039-aa42-ddbdb5a9f278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501252179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.501252179
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_error.2176533722
Short name T169
Test name
Test status
Simulation time 338142712 ps
CPU time 15.8 seconds
Started Feb 18 01:46:23 PM PST 24
Finished Feb 18 01:46:42 PM PST 24
Peak memory 199412 kb
Host smart-d69f6c96-7f10-46a8-8452-12c3830b1a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176533722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2176533722
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1145872249
Short name T387
Test name
Test status
Simulation time 986608321 ps
CPU time 18.19 seconds
Started Feb 18 01:46:23 PM PST 24
Finished Feb 18 01:46:44 PM PST 24
Peak memory 199564 kb
Host smart-e82f96b5-58d6-4b8d-bc22-4152447d344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145872249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1145872249
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1156170751
Short name T265
Test name
Test status
Simulation time 70479765 ps
CPU time 0.97 seconds
Started Feb 18 01:46:21 PM PST 24
Finished Feb 18 01:46:26 PM PST 24
Peak memory 198392 kb
Host smart-69c265da-1885-4324-8218-df6770fe8370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156170751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1156170751
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.881372671
Short name T251
Test name
Test status
Simulation time 141460586550 ps
CPU time 507.15 seconds
Started Feb 18 01:46:23 PM PST 24
Finished Feb 18 01:54:53 PM PST 24
Peak memory 217040 kb
Host smart-5a6bf5bc-967c-45fe-b9b7-c9f45ce7a3d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881372671 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.881372671
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2042924200
Short name T458
Test name
Test status
Simulation time 33287546 ps
CPU time 0.9 seconds
Started Feb 18 01:46:28 PM PST 24
Finished Feb 18 01:46:30 PM PST 24
Peak memory 196672 kb
Host smart-2101f17b-9d51-448c-b573-6d59d79e2df7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042924200 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2042924200
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3878614397
Short name T157
Test name
Test status
Simulation time 17451167626 ps
CPU time 418.48 seconds
Started Feb 18 01:46:28 PM PST 24
Finished Feb 18 01:53:29 PM PST 24
Peak memory 199544 kb
Host smart-45eed6b8-3f68-4839-a03d-04e0acc0e80a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878614397 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.3878614397
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.132177920
Short name T277
Test name
Test status
Simulation time 6320236042 ps
CPU time 75.96 seconds
Started Feb 18 01:46:27 PM PST 24
Finished Feb 18 01:47:45 PM PST 24
Peak memory 199616 kb
Host smart-0ed6b896-3918-48b0-b291-eda4fa3b7266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132177920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.132177920
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1166208787
Short name T138
Test name
Test status
Simulation time 13836911 ps
CPU time 0.59 seconds
Started Feb 18 01:45:33 PM PST 24
Finished Feb 18 01:45:37 PM PST 24
Peak memory 194724 kb
Host smart-113baf0a-6703-4c35-832a-64626a77e11d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166208787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1166208787
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2057837798
Short name T496
Test name
Test status
Simulation time 6836370784 ps
CPU time 30.57 seconds
Started Feb 18 01:45:32 PM PST 24
Finished Feb 18 01:46:07 PM PST 24
Peak memory 215144 kb
Host smart-df764c0d-dbc4-4cba-977b-5022290ca43f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057837798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2057837798
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2849235728
Short name T315
Test name
Test status
Simulation time 2367958743 ps
CPU time 43.91 seconds
Started Feb 18 01:45:30 PM PST 24
Finished Feb 18 01:46:18 PM PST 24
Peak memory 199536 kb
Host smart-7435ffc6-9eb9-4d2d-aec6-5b98865f068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849235728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2849235728
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2961110964
Short name T292
Test name
Test status
Simulation time 1708263997 ps
CPU time 26.22 seconds
Started Feb 18 01:45:32 PM PST 24
Finished Feb 18 01:46:02 PM PST 24
Peak memory 199512 kb
Host smart-1635cf8b-5c5a-419f-b04a-a4adbf3b998e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961110964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2961110964
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2432890350
Short name T27
Test name
Test status
Simulation time 20439995428 ps
CPU time 92.34 seconds
Started Feb 18 01:45:25 PM PST 24
Finished Feb 18 01:47:04 PM PST 24
Peak memory 199620 kb
Host smart-dad7a810-f132-4568-9ac7-b04a38a14940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432890350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2432890350
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3989130076
Short name T444
Test name
Test status
Simulation time 1738788086 ps
CPU time 29.93 seconds
Started Feb 18 01:45:24 PM PST 24
Finished Feb 18 01:46:01 PM PST 24
Peak memory 199572 kb
Host smart-7e07d8b0-b5e7-4105-997b-8a8ef28ff5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989130076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3989130076
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3254900961
Short name T43
Test name
Test status
Simulation time 58949274 ps
CPU time 0.89 seconds
Started Feb 18 01:45:26 PM PST 24
Finished Feb 18 01:45:33 PM PST 24
Peak memory 216812 kb
Host smart-b4c4a9f1-0d17-4166-8167-a707296021ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254900961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3254900961
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.870535162
Short name T400
Test name
Test status
Simulation time 152197495 ps
CPU time 2.03 seconds
Started Feb 18 01:45:18 PM PST 24
Finished Feb 18 01:45:30 PM PST 24
Peak memory 199488 kb
Host smart-26434153-aec2-466e-bdd9-99ce93b78fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870535162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.870535162
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1015905208
Short name T374
Test name
Test status
Simulation time 76572754974 ps
CPU time 613.37 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:55:53 PM PST 24
Peak memory 199616 kb
Host smart-67a2d8dc-1dd9-43e1-8c10-290288701603
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015905208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1015905208
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.141317284
Short name T3
Test name
Test status
Simulation time 782003311 ps
CPU time 0.91 seconds
Started Feb 18 01:45:25 PM PST 24
Finished Feb 18 01:45:33 PM PST 24
Peak memory 196792 kb
Host smart-ac33d659-55e2-4acb-9c89-81714947bc4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141317284 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.141317284
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.624719873
Short name T460
Test name
Test status
Simulation time 8682164760 ps
CPU time 419.18 seconds
Started Feb 18 01:45:33 PM PST 24
Finished Feb 18 01:52:35 PM PST 24
Peak memory 199460 kb
Host smart-46e17e67-3f7a-4fe3-ba23-a96d5109de50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624719873 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.hmac_test_sha_vectors.624719873
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1190847773
Short name T548
Test name
Test status
Simulation time 263941223 ps
CPU time 1.99 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:45:42 PM PST 24
Peak memory 199416 kb
Host smart-7189c3f5-49df-496d-b940-0fb87c811932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190847773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1190847773
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.4170272886
Short name T145
Test name
Test status
Simulation time 40411218 ps
CPU time 0.61 seconds
Started Feb 18 01:46:34 PM PST 24
Finished Feb 18 01:46:36 PM PST 24
Peak memory 193748 kb
Host smart-1fa33d48-c071-471a-af21-f1bf0817f0a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170272886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.4170272886
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3716418746
Short name T288
Test name
Test status
Simulation time 6378666799 ps
CPU time 12.87 seconds
Started Feb 18 01:46:29 PM PST 24
Finished Feb 18 01:46:45 PM PST 24
Peak memory 207832 kb
Host smart-25f9467c-5811-4a2c-8049-b20c32016a0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716418746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3716418746
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1195804211
Short name T294
Test name
Test status
Simulation time 2448350853 ps
CPU time 21.28 seconds
Started Feb 18 01:46:29 PM PST 24
Finished Feb 18 01:46:53 PM PST 24
Peak memory 199572 kb
Host smart-8fee1ba4-3f79-4e65-9445-b21e0a60ca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195804211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1195804211
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3222877941
Short name T235
Test name
Test status
Simulation time 4451248743 ps
CPU time 114.75 seconds
Started Feb 18 01:46:29 PM PST 24
Finished Feb 18 01:48:26 PM PST 24
Peak memory 199512 kb
Host smart-6a33ebd3-9448-4972-8a4e-590c062aa042
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222877941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3222877941
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3651543595
Short name T142
Test name
Test status
Simulation time 2441798473 ps
CPU time 31.18 seconds
Started Feb 18 01:46:21 PM PST 24
Finished Feb 18 01:46:56 PM PST 24
Peak memory 199596 kb
Host smart-f7335bb8-7fb9-4627-906b-764d0e504306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651543595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3651543595
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.757220443
Short name T499
Test name
Test status
Simulation time 8163721223 ps
CPU time 58.95 seconds
Started Feb 18 01:46:28 PM PST 24
Finished Feb 18 01:47:28 PM PST 24
Peak memory 199568 kb
Host smart-a995a251-1dd4-432f-ae38-aa2fce945d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757220443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.757220443
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.927001282
Short name T482
Test name
Test status
Simulation time 105449327 ps
CPU time 1.49 seconds
Started Feb 18 01:46:28 PM PST 24
Finished Feb 18 01:46:32 PM PST 24
Peak memory 199220 kb
Host smart-e6ec381d-244a-4417-9d36-4eab4482bfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927001282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.927001282
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2229513395
Short name T120
Test name
Test status
Simulation time 39291791592 ps
CPU time 650.5 seconds
Started Feb 18 01:46:30 PM PST 24
Finished Feb 18 01:57:23 PM PST 24
Peak memory 199652 kb
Host smart-44d86cdd-f1b4-4041-a6c6-57131f6e2c8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229513395 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2229513395
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.2172071165
Short name T173
Test name
Test status
Simulation time 456047456 ps
CPU time 1 seconds
Started Feb 18 01:46:33 PM PST 24
Finished Feb 18 01:46:36 PM PST 24
Peak memory 196740 kb
Host smart-277a0cb2-3781-4c1a-ad5a-1d10c5023ad6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172071165 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.2172071165
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.10330718
Short name T379
Test name
Test status
Simulation time 7233498259 ps
CPU time 345.71 seconds
Started Feb 18 01:46:32 PM PST 24
Finished Feb 18 01:52:20 PM PST 24
Peak memory 199532 kb
Host smart-f977e4c4-e297-46b1-9600-a48fd7e64aca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10330718 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.hmac_test_sha_vectors.10330718
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2356148264
Short name T420
Test name
Test status
Simulation time 2383992803 ps
CPU time 30.32 seconds
Started Feb 18 01:46:38 PM PST 24
Finished Feb 18 01:47:10 PM PST 24
Peak memory 199548 kb
Host smart-6983eb44-2f46-4288-b1d6-df56ba469c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356148264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2356148264
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2686367531
Short name T21
Test name
Test status
Simulation time 151562705 ps
CPU time 2.69 seconds
Started Feb 18 01:46:33 PM PST 24
Finished Feb 18 01:46:38 PM PST 24
Peak memory 199576 kb
Host smart-18b81a73-bc52-4d5e-9073-d8cd64c50e48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2686367531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2686367531
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3162067543
Short name T334
Test name
Test status
Simulation time 563478012 ps
CPU time 24.4 seconds
Started Feb 18 01:46:35 PM PST 24
Finished Feb 18 01:47:01 PM PST 24
Peak memory 199392 kb
Host smart-6f91cbf7-7e4f-4a28-88b8-d0742c240805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162067543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3162067543
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3187215102
Short name T398
Test name
Test status
Simulation time 1982906300 ps
CPU time 37.15 seconds
Started Feb 18 01:46:32 PM PST 24
Finished Feb 18 01:47:12 PM PST 24
Peak memory 199524 kb
Host smart-f7fca730-e77e-470d-9228-44f1a72057cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3187215102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3187215102
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2446849926
Short name T475
Test name
Test status
Simulation time 4799514934 ps
CPU time 67.65 seconds
Started Feb 18 01:46:31 PM PST 24
Finished Feb 18 01:47:41 PM PST 24
Peak memory 199552 kb
Host smart-a8587e2a-9849-4cf5-8fa9-e476844a00ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446849926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2446849926
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.4061720136
Short name T172
Test name
Test status
Simulation time 8330088606 ps
CPU time 74.3 seconds
Started Feb 18 01:46:36 PM PST 24
Finished Feb 18 01:47:53 PM PST 24
Peak memory 199592 kb
Host smart-030978eb-f6c7-4fc9-b527-fcc8e0595dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061720136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4061720136
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3168618256
Short name T167
Test name
Test status
Simulation time 764507193 ps
CPU time 3.37 seconds
Started Feb 18 01:46:33 PM PST 24
Finished Feb 18 01:46:39 PM PST 24
Peak memory 199488 kb
Host smart-e2dad04f-e9fa-45b5-a230-86ca733ebc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168618256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3168618256
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1500389062
Short name T281
Test name
Test status
Simulation time 4602041533 ps
CPU time 226.59 seconds
Started Feb 18 01:46:33 PM PST 24
Finished Feb 18 01:50:22 PM PST 24
Peak memory 199632 kb
Host smart-78000bcb-431a-4d05-b38c-6dfd228e6126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500389062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1500389062
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3244068454
Short name T370
Test name
Test status
Simulation time 258639994 ps
CPU time 1.24 seconds
Started Feb 18 01:46:33 PM PST 24
Finished Feb 18 01:46:36 PM PST 24
Peak memory 198740 kb
Host smart-578e76cd-dad9-4d74-b561-5f1524591e31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244068454 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3244068454
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1906099532
Short name T149
Test name
Test status
Simulation time 33126884109 ps
CPU time 411.95 seconds
Started Feb 18 01:46:33 PM PST 24
Finished Feb 18 01:53:27 PM PST 24
Peak memory 199492 kb
Host smart-59f76b3b-892b-45ff-866b-18198dbcecb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906099532 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.1906099532
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2537832573
Short name T153
Test name
Test status
Simulation time 11137053325 ps
CPU time 48.18 seconds
Started Feb 18 01:46:36 PM PST 24
Finished Feb 18 01:47:27 PM PST 24
Peak memory 199604 kb
Host smart-a4907e4f-ded2-4d2d-92d3-0299579de2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537832573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2537832573
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2974005083
Short name T465
Test name
Test status
Simulation time 13486371 ps
CPU time 0.58 seconds
Started Feb 18 01:46:39 PM PST 24
Finished Feb 18 01:46:41 PM PST 24
Peak memory 193696 kb
Host smart-1fa3dbe1-16f9-4516-9cab-acdd175d08b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974005083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2974005083
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3858102645
Short name T456
Test name
Test status
Simulation time 21885367737 ps
CPU time 42.46 seconds
Started Feb 18 01:46:32 PM PST 24
Finished Feb 18 01:47:17 PM PST 24
Peak memory 224180 kb
Host smart-3836de48-5971-433f-9bf3-8e0f2b0b49ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3858102645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3858102645
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.618722473
Short name T186
Test name
Test status
Simulation time 3621798422 ps
CPU time 21.98 seconds
Started Feb 18 01:46:33 PM PST 24
Finished Feb 18 01:46:57 PM PST 24
Peak memory 199636 kb
Host smart-28fbd498-ed3d-4e2a-8d35-5d5175126d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618722473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.618722473
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3331554906
Short name T20
Test name
Test status
Simulation time 2833491268 ps
CPU time 150.35 seconds
Started Feb 18 01:46:36 PM PST 24
Finished Feb 18 01:49:08 PM PST 24
Peak memory 199544 kb
Host smart-e695d5fe-2c3f-4a94-b95b-83582d8c948b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331554906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3331554906
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.6821819
Short name T140
Test name
Test status
Simulation time 59719270 ps
CPU time 1.53 seconds
Started Feb 18 01:46:33 PM PST 24
Finished Feb 18 01:46:36 PM PST 24
Peak memory 199340 kb
Host smart-8384b3f2-6afc-4246-9dce-9a027fe00d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6821819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.6821819
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3011920415
Short name T212
Test name
Test status
Simulation time 6585278839 ps
CPU time 76.1 seconds
Started Feb 18 01:46:31 PM PST 24
Finished Feb 18 01:47:50 PM PST 24
Peak memory 199596 kb
Host smart-e6e8e215-7d18-4b66-a0cf-59bcf936fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011920415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3011920415
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1502614631
Short name T359
Test name
Test status
Simulation time 207155615 ps
CPU time 3.26 seconds
Started Feb 18 01:46:34 PM PST 24
Finished Feb 18 01:46:39 PM PST 24
Peak memory 199508 kb
Host smart-8592f270-cf99-4253-b51f-e0db0d169ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502614631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1502614631
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2934029957
Short name T259
Test name
Test status
Simulation time 15551944512 ps
CPU time 64.99 seconds
Started Feb 18 01:46:33 PM PST 24
Finished Feb 18 01:47:40 PM PST 24
Peak memory 232300 kb
Host smart-b79eb0f6-36c4-43b3-bb06-307a91b65fe9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934029957 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2934029957
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2243936282
Short name T244
Test name
Test status
Simulation time 30859657 ps
CPU time 1.13 seconds
Started Feb 18 01:46:36 PM PST 24
Finished Feb 18 01:46:39 PM PST 24
Peak memory 197456 kb
Host smart-3e72990d-f676-4d87-8d15-2b9a4318b4d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243936282 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2243936282
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2259332756
Short name T560
Test name
Test status
Simulation time 14615855188 ps
CPU time 358.72 seconds
Started Feb 18 01:46:34 PM PST 24
Finished Feb 18 01:52:34 PM PST 24
Peak memory 199472 kb
Host smart-7422a30b-a787-44a1-a3bd-e3035d86197a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259332756 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.2259332756
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.710849148
Short name T314
Test name
Test status
Simulation time 8123300434 ps
CPU time 11.44 seconds
Started Feb 18 01:46:30 PM PST 24
Finished Feb 18 01:46:44 PM PST 24
Peak memory 199608 kb
Host smart-8a006d30-4500-4e7d-a018-cbb119c5758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710849148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.710849148
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1075615858
Short name T318
Test name
Test status
Simulation time 49648827 ps
CPU time 0.59 seconds
Started Feb 18 01:46:43 PM PST 24
Finished Feb 18 01:46:46 PM PST 24
Peak memory 193756 kb
Host smart-5fc61fd2-eecc-49d7-83d0-32b689be2028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075615858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1075615858
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.740559348
Short name T156
Test name
Test status
Simulation time 332527876 ps
CPU time 2.59 seconds
Started Feb 18 01:46:44 PM PST 24
Finished Feb 18 01:46:48 PM PST 24
Peak memory 199528 kb
Host smart-92929694-5aef-4ad0-aa4f-f1908fef03ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740559348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.740559348
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1972002569
Short name T78
Test name
Test status
Simulation time 8923361660 ps
CPU time 37.38 seconds
Started Feb 18 01:46:38 PM PST 24
Finished Feb 18 01:47:18 PM PST 24
Peak memory 199556 kb
Host smart-06446f1d-3e04-4faa-8649-1bacd8d0aac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972002569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1972002569
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1310943812
Short name T285
Test name
Test status
Simulation time 599458049 ps
CPU time 30.83 seconds
Started Feb 18 01:46:38 PM PST 24
Finished Feb 18 01:47:11 PM PST 24
Peak memory 199512 kb
Host smart-e1766d40-7ca0-4606-8a0b-c7a7247478ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310943812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1310943812
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2473484128
Short name T569
Test name
Test status
Simulation time 11740408501 ps
CPU time 43.51 seconds
Started Feb 18 01:46:38 PM PST 24
Finished Feb 18 01:47:24 PM PST 24
Peak memory 199584 kb
Host smart-b2e84a85-9470-4d71-823e-d0f0f0de04cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473484128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2473484128
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.162484760
Short name T202
Test name
Test status
Simulation time 727441797 ps
CPU time 4 seconds
Started Feb 18 01:46:38 PM PST 24
Finished Feb 18 01:46:44 PM PST 24
Peak memory 199488 kb
Host smart-bd0054cd-d70e-4cef-a9a3-5a3b708c34a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162484760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.162484760
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2491825084
Short name T273
Test name
Test status
Simulation time 185285129 ps
CPU time 2.28 seconds
Started Feb 18 01:46:42 PM PST 24
Finished Feb 18 01:46:47 PM PST 24
Peak memory 199400 kb
Host smart-49b0a039-b6b2-4282-8383-117769b44e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491825084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2491825084
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3211268571
Short name T67
Test name
Test status
Simulation time 31356435358 ps
CPU time 446.87 seconds
Started Feb 18 01:46:38 PM PST 24
Finished Feb 18 01:54:07 PM PST 24
Peak memory 216020 kb
Host smart-e29f2a63-57ce-47c9-8e9e-2f675d8c5a7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211268571 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3211268571
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1574917130
Short name T139
Test name
Test status
Simulation time 29123991 ps
CPU time 0.89 seconds
Started Feb 18 01:46:42 PM PST 24
Finished Feb 18 01:46:45 PM PST 24
Peak memory 196800 kb
Host smart-ac38cc7c-c3a4-4469-8cb5-c5da2484ed5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574917130 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1574917130
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3800593909
Short name T390
Test name
Test status
Simulation time 45648102801 ps
CPU time 441.57 seconds
Started Feb 18 01:46:39 PM PST 24
Finished Feb 18 01:54:02 PM PST 24
Peak memory 199524 kb
Host smart-f2ede568-ba0f-41d3-866b-f97d51059939
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800593909 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.3800593909
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2582727622
Short name T319
Test name
Test status
Simulation time 2648806235 ps
CPU time 48.95 seconds
Started Feb 18 01:46:41 PM PST 24
Finished Feb 18 01:47:33 PM PST 24
Peak memory 199520 kb
Host smart-5a4029b2-7d63-47cf-82fe-35bf57408aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582727622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2582727622
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3392421132
Short name T539
Test name
Test status
Simulation time 16504559 ps
CPU time 0.55 seconds
Started Feb 18 01:46:40 PM PST 24
Finished Feb 18 01:46:43 PM PST 24
Peak memory 193784 kb
Host smart-4db6f414-4e37-4167-b215-3dc52181d91b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392421132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3392421132
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2005256916
Short name T360
Test name
Test status
Simulation time 2541683604 ps
CPU time 36.89 seconds
Started Feb 18 01:46:41 PM PST 24
Finished Feb 18 01:47:20 PM PST 24
Peak memory 215824 kb
Host smart-2d4b57e0-6580-46e0-82f4-dfe17429d948
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005256916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2005256916
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1010936001
Short name T446
Test name
Test status
Simulation time 4007530228 ps
CPU time 12.16 seconds
Started Feb 18 01:46:40 PM PST 24
Finished Feb 18 01:46:55 PM PST 24
Peak memory 199480 kb
Host smart-3d3f376b-8400-4311-9bd0-ee9d2d40a290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010936001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1010936001
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1685252692
Short name T419
Test name
Test status
Simulation time 1955958685 ps
CPU time 104.36 seconds
Started Feb 18 01:46:42 PM PST 24
Finished Feb 18 01:48:29 PM PST 24
Peak memory 199520 kb
Host smart-6877889f-0839-4a8e-9c82-9a1d57328a48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685252692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1685252692
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.363578174
Short name T512
Test name
Test status
Simulation time 52564355 ps
CPU time 0.62 seconds
Started Feb 18 01:46:40 PM PST 24
Finished Feb 18 01:46:44 PM PST 24
Peak memory 194628 kb
Host smart-e8d05d66-2d43-4cd1-9741-d9f4c1318a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363578174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.363578174
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2754569191
Short name T383
Test name
Test status
Simulation time 10257015930 ps
CPU time 70.06 seconds
Started Feb 18 01:46:41 PM PST 24
Finished Feb 18 01:47:54 PM PST 24
Peak memory 199488 kb
Host smart-80289b30-c570-4116-9124-f334f595b207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754569191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2754569191
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.146822355
Short name T11
Test name
Test status
Simulation time 51690560 ps
CPU time 1.36 seconds
Started Feb 18 01:46:42 PM PST 24
Finished Feb 18 01:46:46 PM PST 24
Peak memory 199148 kb
Host smart-09555ddd-3a94-4887-b008-d47732c08bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146822355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.146822355
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3788076204
Short name T71
Test name
Test status
Simulation time 48234436251 ps
CPU time 99.42 seconds
Started Feb 18 01:46:42 PM PST 24
Finished Feb 18 01:48:24 PM PST 24
Peak memory 199592 kb
Host smart-9eaf0452-ec17-45ca-8cff-cde5669b5f8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788076204 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3788076204
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1949422987
Short name T190
Test name
Test status
Simulation time 108231052 ps
CPU time 1.14 seconds
Started Feb 18 01:46:38 PM PST 24
Finished Feb 18 01:46:41 PM PST 24
Peak memory 198488 kb
Host smart-c1916b27-cea5-4ac0-a2ce-f1e0e1c1cb4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949422987 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1949422987
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3702092353
Short name T200
Test name
Test status
Simulation time 50950435271 ps
CPU time 438.32 seconds
Started Feb 18 01:46:38 PM PST 24
Finished Feb 18 01:53:58 PM PST 24
Peak memory 199560 kb
Host smart-ab085764-2745-47fe-b523-dbafbf119d4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702092353 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.3702092353
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.645566900
Short name T160
Test name
Test status
Simulation time 3249737704 ps
CPU time 23.32 seconds
Started Feb 18 01:46:38 PM PST 24
Finished Feb 18 01:47:04 PM PST 24
Peak memory 199584 kb
Host smart-624c072e-c9b2-4ba1-b2c9-b99b1c04e36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645566900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.645566900
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3942741130
Short name T339
Test name
Test status
Simulation time 14479861 ps
CPU time 0.58 seconds
Started Feb 18 01:46:49 PM PST 24
Finished Feb 18 01:46:51 PM PST 24
Peak memory 193740 kb
Host smart-2505b7cb-2a4a-4024-964c-254565a6db1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942741130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3942741130
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3557806831
Short name T302
Test name
Test status
Simulation time 4951616316 ps
CPU time 29.86 seconds
Started Feb 18 01:46:50 PM PST 24
Finished Feb 18 01:47:22 PM PST 24
Peak memory 219100 kb
Host smart-3e401f06-ed84-44ae-a4a7-09b6c62b58c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557806831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3557806831
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.898352022
Short name T194
Test name
Test status
Simulation time 802920753 ps
CPU time 33.28 seconds
Started Feb 18 01:46:49 PM PST 24
Finished Feb 18 01:47:24 PM PST 24
Peak memory 199548 kb
Host smart-0893a9af-5184-4485-a665-5e8e76691041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898352022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.898352022
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1740433664
Short name T405
Test name
Test status
Simulation time 2156082605 ps
CPU time 57 seconds
Started Feb 18 01:46:50 PM PST 24
Finished Feb 18 01:47:49 PM PST 24
Peak memory 199600 kb
Host smart-ccf9fa44-8156-4838-a04a-6de1948f73d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740433664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1740433664
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.4217354197
Short name T239
Test name
Test status
Simulation time 6147964221 ps
CPU time 26.57 seconds
Started Feb 18 01:46:52 PM PST 24
Finished Feb 18 01:47:20 PM PST 24
Peak memory 199504 kb
Host smart-101c1c5b-51b4-4ccc-a532-14ce6d89cdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217354197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4217354197
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2486296295
Short name T364
Test name
Test status
Simulation time 16813781379 ps
CPU time 75.19 seconds
Started Feb 18 01:46:48 PM PST 24
Finished Feb 18 01:48:06 PM PST 24
Peak memory 199576 kb
Host smart-85b492cd-427b-427d-879d-b5bb8dc10aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486296295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2486296295
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.4254638341
Short name T52
Test name
Test status
Simulation time 5066383528 ps
CPU time 3.4 seconds
Started Feb 18 01:46:39 PM PST 24
Finished Feb 18 01:46:44 PM PST 24
Peak memory 199532 kb
Host smart-936fa5cf-9452-4827-9af7-b5957659be60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254638341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.4254638341
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3931824382
Short name T104
Test name
Test status
Simulation time 315212370786 ps
CPU time 886.84 seconds
Started Feb 18 01:46:51 PM PST 24
Finished Feb 18 02:01:40 PM PST 24
Peak memory 229756 kb
Host smart-36c78d71-5d5f-44e4-be47-ca4da2c4f5ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931824382 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3931824382
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.2824122694
Short name T349
Test name
Test status
Simulation time 76612410 ps
CPU time 0.97 seconds
Started Feb 18 01:46:50 PM PST 24
Finished Feb 18 01:46:53 PM PST 24
Peak memory 196728 kb
Host smart-b9621ee8-5328-428f-a86d-11bbc519b1bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824122694 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.2824122694
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3729674560
Short name T509
Test name
Test status
Simulation time 8837059278 ps
CPU time 403.73 seconds
Started Feb 18 01:46:48 PM PST 24
Finished Feb 18 01:53:34 PM PST 24
Peak memory 199452 kb
Host smart-0608f9ca-a5b3-416b-9132-a9964670038a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729674560 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.3729674560
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.678834044
Short name T537
Test name
Test status
Simulation time 37766340441 ps
CPU time 76.9 seconds
Started Feb 18 01:46:48 PM PST 24
Finished Feb 18 01:48:07 PM PST 24
Peak memory 199644 kb
Host smart-cb772202-4295-4dcc-bfca-7bb9fca5434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678834044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.678834044
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.830496807
Short name T361
Test name
Test status
Simulation time 21046844 ps
CPU time 0.6 seconds
Started Feb 18 01:46:57 PM PST 24
Finished Feb 18 01:46:59 PM PST 24
Peak memory 193740 kb
Host smart-442e6bd6-fee7-4f52-99ae-d5073760518e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830496807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.830496807
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3110876596
Short name T580
Test name
Test status
Simulation time 972492834 ps
CPU time 32.62 seconds
Started Feb 18 01:46:49 PM PST 24
Finished Feb 18 01:47:23 PM PST 24
Peak memory 217948 kb
Host smart-0e4c86df-2b9b-488b-ad50-dd9fbdd349ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110876596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3110876596
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1613104115
Short name T203
Test name
Test status
Simulation time 1666481248 ps
CPU time 18.51 seconds
Started Feb 18 01:46:50 PM PST 24
Finished Feb 18 01:47:11 PM PST 24
Peak memory 199520 kb
Host smart-0e7bb212-d485-40d9-8dab-c125c4ff5cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613104115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1613104115
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1004657753
Short name T376
Test name
Test status
Simulation time 561011619 ps
CPU time 29.54 seconds
Started Feb 18 01:46:53 PM PST 24
Finished Feb 18 01:47:25 PM PST 24
Peak memory 199484 kb
Host smart-2f32793d-21d3-43c7-9c0b-efb7d886590c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004657753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1004657753
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2908638397
Short name T353
Test name
Test status
Simulation time 10862958258 ps
CPU time 137.84 seconds
Started Feb 18 01:46:48 PM PST 24
Finished Feb 18 01:49:07 PM PST 24
Peak memory 199540 kb
Host smart-d8185bed-ad5e-4d6a-97ee-9caca129758a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908638397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2908638397
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1091253230
Short name T82
Test name
Test status
Simulation time 9885715311 ps
CPU time 61.37 seconds
Started Feb 18 01:46:50 PM PST 24
Finished Feb 18 01:47:53 PM PST 24
Peak memory 199564 kb
Host smart-f9000fc7-0ea1-4319-a436-55d4f8c71bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091253230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1091253230
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3997817240
Short name T261
Test name
Test status
Simulation time 95465608 ps
CPU time 1.57 seconds
Started Feb 18 01:46:51 PM PST 24
Finished Feb 18 01:46:54 PM PST 24
Peak memory 199096 kb
Host smart-db6bfcce-fdd9-4365-9930-675e2e449968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997817240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3997817240
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3936718871
Short name T452
Test name
Test status
Simulation time 10390226212 ps
CPU time 529.5 seconds
Started Feb 18 01:46:50 PM PST 24
Finished Feb 18 01:55:41 PM PST 24
Peak memory 199596 kb
Host smart-659de4a3-bff9-49f3-8261-80f0a977410d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936718871 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3936718871
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1524456729
Short name T219
Test name
Test status
Simulation time 41573814 ps
CPU time 0.95 seconds
Started Feb 18 01:46:51 PM PST 24
Finished Feb 18 01:46:54 PM PST 24
Peak memory 197424 kb
Host smart-c0655a81-2c47-41d5-a232-28a8b334068e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524456729 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1524456729
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3852883264
Short name T457
Test name
Test status
Simulation time 102965295191 ps
CPU time 438.01 seconds
Started Feb 18 01:46:50 PM PST 24
Finished Feb 18 01:54:10 PM PST 24
Peak memory 199524 kb
Host smart-ad41d77f-d2b1-4b0e-92ee-97570902e30e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852883264 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.3852883264
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.4208075065
Short name T178
Test name
Test status
Simulation time 3150868815 ps
CPU time 19.85 seconds
Started Feb 18 01:46:48 PM PST 24
Finished Feb 18 01:47:09 PM PST 24
Peak memory 199576 kb
Host smart-9fb582c9-8ed9-4822-9e0d-3f157d979159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208075065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4208075065
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1074014871
Short name T335
Test name
Test status
Simulation time 26864541 ps
CPU time 0.59 seconds
Started Feb 18 01:46:59 PM PST 24
Finished Feb 18 01:47:01 PM PST 24
Peak memory 193880 kb
Host smart-af2e0e86-b637-4fa5-8856-cfed929ce64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074014871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1074014871
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2899322530
Short name T366
Test name
Test status
Simulation time 150316302 ps
CPU time 5.35 seconds
Started Feb 18 01:46:54 PM PST 24
Finished Feb 18 01:47:01 PM PST 24
Peak memory 215436 kb
Host smart-df6116c9-6615-4d8d-b6e8-40617a98ce25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899322530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2899322530
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3352039243
Short name T503
Test name
Test status
Simulation time 17655481595 ps
CPU time 74.44 seconds
Started Feb 18 01:46:52 PM PST 24
Finished Feb 18 01:48:09 PM PST 24
Peak memory 199552 kb
Host smart-14a75529-e6b1-4c46-b619-8b294bb3a562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352039243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3352039243
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3519687361
Short name T469
Test name
Test status
Simulation time 482507608 ps
CPU time 24.56 seconds
Started Feb 18 01:46:57 PM PST 24
Finished Feb 18 01:47:23 PM PST 24
Peak memory 199456 kb
Host smart-26ddc1f3-2900-4c56-9312-27111a1824b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519687361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3519687361
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.705887646
Short name T389
Test name
Test status
Simulation time 4183328060 ps
CPU time 51.13 seconds
Started Feb 18 01:47:00 PM PST 24
Finished Feb 18 01:47:53 PM PST 24
Peak memory 199564 kb
Host smart-003c6f57-24c1-4e51-9ee4-2651c8369646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705887646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.705887646
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1898470701
Short name T410
Test name
Test status
Simulation time 17194184287 ps
CPU time 74.46 seconds
Started Feb 18 01:46:59 PM PST 24
Finished Feb 18 01:48:14 PM PST 24
Peak memory 199596 kb
Host smart-0036bb3e-8fac-4acd-8d70-5c3faf2ac633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898470701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1898470701
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1057495153
Short name T159
Test name
Test status
Simulation time 156733236 ps
CPU time 1.32 seconds
Started Feb 18 01:46:57 PM PST 24
Finished Feb 18 01:47:00 PM PST 24
Peak memory 199460 kb
Host smart-f02660a5-832a-4e41-8348-e9a84a8aadc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057495153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1057495153
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3126363262
Short name T72
Test name
Test status
Simulation time 136296573553 ps
CPU time 1626.96 seconds
Started Feb 18 01:46:58 PM PST 24
Finished Feb 18 02:14:06 PM PST 24
Peak memory 215340 kb
Host smart-1e1012d2-d3e6-4580-a35d-6ef8c570fe92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126363262 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3126363262
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1252875542
Short name T325
Test name
Test status
Simulation time 94418332 ps
CPU time 0.91 seconds
Started Feb 18 01:47:03 PM PST 24
Finished Feb 18 01:47:06 PM PST 24
Peak memory 197492 kb
Host smart-0574509a-2be8-4596-808a-e9b57268a40e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252875542 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1252875542
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.4189078005
Short name T517
Test name
Test status
Simulation time 3861002548 ps
CPU time 70.19 seconds
Started Feb 18 01:46:54 PM PST 24
Finished Feb 18 01:48:06 PM PST 24
Peak memory 199596 kb
Host smart-e056d88d-7281-4ce9-8650-acd4db0d9c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189078005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.4189078005
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2612889642
Short name T525
Test name
Test status
Simulation time 16275963 ps
CPU time 0.62 seconds
Started Feb 18 01:47:00 PM PST 24
Finished Feb 18 01:47:03 PM PST 24
Peak memory 194728 kb
Host smart-ed6d2e2c-568b-4f12-9ca5-3dbe06b80a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612889642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2612889642
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3483197063
Short name T340
Test name
Test status
Simulation time 1060600853 ps
CPU time 13.59 seconds
Started Feb 18 01:46:52 PM PST 24
Finished Feb 18 01:47:07 PM PST 24
Peak memory 199436 kb
Host smart-324e7952-595f-40a5-b5e4-0787988a430a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483197063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3483197063
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.496864135
Short name T14
Test name
Test status
Simulation time 8564422000 ps
CPU time 11.76 seconds
Started Feb 18 01:46:53 PM PST 24
Finished Feb 18 01:47:07 PM PST 24
Peak memory 199532 kb
Host smart-a535da6d-577a-4123-a7b3-4ccbd0b88c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496864135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.496864135
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3638923815
Short name T378
Test name
Test status
Simulation time 1818799576 ps
CPU time 99.63 seconds
Started Feb 18 01:46:53 PM PST 24
Finished Feb 18 01:48:35 PM PST 24
Peak memory 199536 kb
Host smart-b6c659f0-19fc-4556-a7ff-795bbca13110
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638923815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3638923815
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2218405259
Short name T275
Test name
Test status
Simulation time 6731722786 ps
CPU time 162.82 seconds
Started Feb 18 01:47:03 PM PST 24
Finished Feb 18 01:49:48 PM PST 24
Peak memory 199544 kb
Host smart-e5a40ff3-24e9-46e6-8bd8-d64036420003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218405259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2218405259
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2680087243
Short name T213
Test name
Test status
Simulation time 15958515392 ps
CPU time 99.9 seconds
Started Feb 18 01:46:57 PM PST 24
Finished Feb 18 01:48:38 PM PST 24
Peak memory 199604 kb
Host smart-eeae840f-23bf-40ff-b75a-a50f1198e248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680087243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2680087243
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3091273680
Short name T189
Test name
Test status
Simulation time 493693958 ps
CPU time 2.11 seconds
Started Feb 18 01:46:58 PM PST 24
Finished Feb 18 01:47:01 PM PST 24
Peak memory 199516 kb
Host smart-8ad3da4c-6404-4938-a55d-b0d6c4b5a413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091273680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3091273680
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3648204305
Short name T234
Test name
Test status
Simulation time 35113036810 ps
CPU time 729.07 seconds
Started Feb 18 01:47:02 PM PST 24
Finished Feb 18 01:59:13 PM PST 24
Peak memory 199596 kb
Host smart-13940033-a64f-445c-996a-4694df3a89e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648204305 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3648204305
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.315069741
Short name T467
Test name
Test status
Simulation time 32553496 ps
CPU time 1.12 seconds
Started Feb 18 01:47:03 PM PST 24
Finished Feb 18 01:47:07 PM PST 24
Peak memory 198536 kb
Host smart-bbbbd7fd-f498-45c4-8494-93baa1c2f2c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315069741 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.315069741
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.521760358
Short name T231
Test name
Test status
Simulation time 38597921729 ps
CPU time 434.36 seconds
Started Feb 18 01:47:01 PM PST 24
Finished Feb 18 01:54:17 PM PST 24
Peak memory 199520 kb
Host smart-69b5b86a-9c76-4812-b768-75de47f0a64f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521760358 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.hmac_test_sha_vectors.521760358
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3023394082
Short name T79
Test name
Test status
Simulation time 347599445 ps
CPU time 9.22 seconds
Started Feb 18 01:46:52 PM PST 24
Finished Feb 18 01:47:04 PM PST 24
Peak memory 199528 kb
Host smart-74a20101-ede8-4282-b8c5-13a11e5b06c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023394082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3023394082
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4156593874
Short name T264
Test name
Test status
Simulation time 43794941 ps
CPU time 0.59 seconds
Started Feb 18 01:47:02 PM PST 24
Finished Feb 18 01:47:05 PM PST 24
Peak memory 193764 kb
Host smart-797558ef-2206-42bc-b42d-0f4e9f526e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156593874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4156593874
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.171663752
Short name T240
Test name
Test status
Simulation time 188943784 ps
CPU time 6.45 seconds
Started Feb 18 01:47:01 PM PST 24
Finished Feb 18 01:47:10 PM PST 24
Peak memory 215880 kb
Host smart-7bc03c5e-d06f-4d89-a4b2-8389e0a475df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171663752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.171663752
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2887272948
Short name T440
Test name
Test status
Simulation time 872525679 ps
CPU time 40.14 seconds
Started Feb 18 01:47:03 PM PST 24
Finished Feb 18 01:47:45 PM PST 24
Peak memory 199476 kb
Host smart-f534e369-e03c-47bc-9384-47f960d956cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887272948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2887272948
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4260621241
Short name T572
Test name
Test status
Simulation time 770219139 ps
CPU time 21.64 seconds
Started Feb 18 01:47:04 PM PST 24
Finished Feb 18 01:47:28 PM PST 24
Peak memory 199028 kb
Host smart-24d49303-6988-4476-ace4-c284645dbbe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260621241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4260621241
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.433011537
Short name T553
Test name
Test status
Simulation time 2946746498 ps
CPU time 33.94 seconds
Started Feb 18 01:47:01 PM PST 24
Finished Feb 18 01:47:38 PM PST 24
Peak memory 199612 kb
Host smart-9e0294d9-2f40-4c21-983a-0f3c4450cc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433011537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.433011537
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4290529806
Short name T338
Test name
Test status
Simulation time 1162963530 ps
CPU time 14.49 seconds
Started Feb 18 01:47:04 PM PST 24
Finished Feb 18 01:47:21 PM PST 24
Peak memory 198968 kb
Host smart-2c9ad184-3574-4f03-8d18-f07ddc81b963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290529806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4290529806
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.262167115
Short name T409
Test name
Test status
Simulation time 643031155 ps
CPU time 4.17 seconds
Started Feb 18 01:47:03 PM PST 24
Finished Feb 18 01:47:09 PM PST 24
Peak memory 199504 kb
Host smart-c2c21f56-77eb-4959-8875-5a9a257c64b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262167115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.262167115
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3488747751
Short name T274
Test name
Test status
Simulation time 50686595 ps
CPU time 0.98 seconds
Started Feb 18 01:47:04 PM PST 24
Finished Feb 18 01:47:07 PM PST 24
Peak memory 197448 kb
Host smart-43c64e62-8b6a-49e5-be32-c71b9711effb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488747751 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3488747751
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2830542153
Short name T504
Test name
Test status
Simulation time 15951709821 ps
CPU time 399.67 seconds
Started Feb 18 01:47:01 PM PST 24
Finished Feb 18 01:53:43 PM PST 24
Peak memory 199552 kb
Host smart-7a3c0e8d-fe92-4bec-9ffe-2cb455914b99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830542153 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.2830542153
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.338215547
Short name T554
Test name
Test status
Simulation time 4996498018 ps
CPU time 64.1 seconds
Started Feb 18 01:47:04 PM PST 24
Finished Feb 18 01:48:11 PM PST 24
Peak memory 199556 kb
Host smart-b5bed34c-de6f-4888-87f8-bf7d29ba9aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338215547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.338215547
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.4183756547
Short name T543
Test name
Test status
Simulation time 17752842 ps
CPU time 0.57 seconds
Started Feb 18 01:45:31 PM PST 24
Finished Feb 18 01:45:35 PM PST 24
Peak memory 193668 kb
Host smart-2b38e5ae-5fc8-4a77-a59d-373f59331404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183756547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.4183756547
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.520888378
Short name T279
Test name
Test status
Simulation time 437950176 ps
CPU time 5.43 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:45:45 PM PST 24
Peak memory 224092 kb
Host smart-21242f00-0864-42bd-b72f-a8c7d40e34de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520888378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.520888378
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1592364666
Short name T411
Test name
Test status
Simulation time 3353264052 ps
CPU time 44.68 seconds
Started Feb 18 01:45:29 PM PST 24
Finished Feb 18 01:46:18 PM PST 24
Peak memory 199488 kb
Host smart-a7be9568-3962-4f77-b2c9-bae777afd981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592364666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1592364666
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1613817487
Short name T529
Test name
Test status
Simulation time 3946684438 ps
CPU time 53.91 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:46:35 PM PST 24
Peak memory 199516 kb
Host smart-b96cef6c-96ea-407c-b611-8a07390cc121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613817487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1613817487
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.692369217
Short name T343
Test name
Test status
Simulation time 5753498569 ps
CPU time 134.17 seconds
Started Feb 18 01:45:31 PM PST 24
Finished Feb 18 01:47:49 PM PST 24
Peak memory 199644 kb
Host smart-e767a0f7-dd6d-4fa4-952d-113069fe9043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692369217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.692369217
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3946736495
Short name T336
Test name
Test status
Simulation time 1808315017 ps
CPU time 49.76 seconds
Started Feb 18 01:45:25 PM PST 24
Finished Feb 18 01:46:21 PM PST 24
Peak memory 199492 kb
Host smart-eadd79e6-5254-4c80-9585-26d7dbc7f510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946736495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3946736495
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1922044931
Short name T46
Test name
Test status
Simulation time 87317226 ps
CPU time 0.81 seconds
Started Feb 18 01:45:34 PM PST 24
Finished Feb 18 01:45:38 PM PST 24
Peak memory 216496 kb
Host smart-a0e8881a-289b-48e4-92bc-702ea16f780e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922044931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1922044931
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1147321386
Short name T205
Test name
Test status
Simulation time 1237252954 ps
CPU time 3.5 seconds
Started Feb 18 01:45:24 PM PST 24
Finished Feb 18 01:45:35 PM PST 24
Peak memory 199532 kb
Host smart-f6fa5318-5870-4f79-bfa0-7c362397eaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147321386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1147321386
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2816710304
Short name T513
Test name
Test status
Simulation time 141345929469 ps
CPU time 801.48 seconds
Started Feb 18 01:45:26 PM PST 24
Finished Feb 18 01:58:53 PM PST 24
Peak memory 199660 kb
Host smart-4ba2e111-47d5-484f-8e61-b50fad609737
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816710304 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2816710304
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1228134342
Short name T462
Test name
Test status
Simulation time 48039515 ps
CPU time 1.02 seconds
Started Feb 18 01:45:24 PM PST 24
Finished Feb 18 01:45:32 PM PST 24
Peak memory 197492 kb
Host smart-8ac663e1-628d-4f76-b9ed-a7c314961c04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228134342 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1228134342
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.4155639362
Short name T407
Test name
Test status
Simulation time 40080373131 ps
CPU time 409.76 seconds
Started Feb 18 01:45:25 PM PST 24
Finished Feb 18 01:52:21 PM PST 24
Peak memory 199404 kb
Host smart-699c5b7c-083d-4cf0-b400-f1c6c84a4bee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155639362 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.4155639362
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2131896168
Short name T155
Test name
Test status
Simulation time 368765237 ps
CPU time 5.89 seconds
Started Feb 18 01:45:31 PM PST 24
Finished Feb 18 01:45:40 PM PST 24
Peak memory 199564 kb
Host smart-afb80ec8-b824-4070-94ff-0b9dae2e07ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131896168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2131896168
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1691367028
Short name T526
Test name
Test status
Simulation time 14813470 ps
CPU time 0.57 seconds
Started Feb 18 01:47:00 PM PST 24
Finished Feb 18 01:47:02 PM PST 24
Peak memory 194696 kb
Host smart-acfec6d5-a95e-453d-bdb6-b3af27f1f282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691367028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1691367028
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.831407049
Short name T565
Test name
Test status
Simulation time 146691617 ps
CPU time 5.11 seconds
Started Feb 18 01:47:03 PM PST 24
Finished Feb 18 01:47:11 PM PST 24
Peak memory 199488 kb
Host smart-3c6f8c23-7580-49cc-9955-ccd9686ffc8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831407049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.831407049
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.473588821
Short name T323
Test name
Test status
Simulation time 1159809343 ps
CPU time 25.01 seconds
Started Feb 18 01:46:59 PM PST 24
Finished Feb 18 01:47:26 PM PST 24
Peak memory 199492 kb
Host smart-9366d1ea-d1f4-422b-851b-8d4bca7ba029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473588821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.473588821
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1621945382
Short name T590
Test name
Test status
Simulation time 20355827053 ps
CPU time 55.23 seconds
Started Feb 18 01:47:00 PM PST 24
Finished Feb 18 01:47:57 PM PST 24
Peak memory 199560 kb
Host smart-f19af4e4-2291-417e-9831-62a5523cdabb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621945382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1621945382
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3047901863
Short name T471
Test name
Test status
Simulation time 19682410296 ps
CPU time 76.38 seconds
Started Feb 18 01:47:06 PM PST 24
Finished Feb 18 01:48:26 PM PST 24
Peak memory 199508 kb
Host smart-65a31030-ddbd-407d-96fb-42384f624d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047901863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3047901863
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3998826222
Short name T342
Test name
Test status
Simulation time 24312551283 ps
CPU time 68.92 seconds
Started Feb 18 01:47:04 PM PST 24
Finished Feb 18 01:48:16 PM PST 24
Peak memory 199536 kb
Host smart-07fd9e9f-f2f8-4284-81f7-f49ada83a995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998826222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3998826222
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3188471870
Short name T355
Test name
Test status
Simulation time 395533340 ps
CPU time 2.89 seconds
Started Feb 18 01:47:07 PM PST 24
Finished Feb 18 01:47:13 PM PST 24
Peak memory 199228 kb
Host smart-babb3ace-7690-4338-88c8-849a41aacd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188471870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3188471870
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3013264427
Short name T119
Test name
Test status
Simulation time 158233856007 ps
CPU time 2091.83 seconds
Started Feb 18 01:47:01 PM PST 24
Finished Feb 18 02:21:55 PM PST 24
Peak memory 199600 kb
Host smart-49026b21-5712-4f29-bff1-44e5913b38f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013264427 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3013264427
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3546099574
Short name T165
Test name
Test status
Simulation time 132505500 ps
CPU time 1.14 seconds
Started Feb 18 01:47:02 PM PST 24
Finished Feb 18 01:47:05 PM PST 24
Peak memory 198124 kb
Host smart-87d984c4-93c5-4aa2-b4f4-ec5e6903881a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546099574 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3546099574
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3627699457
Short name T433
Test name
Test status
Simulation time 7075647774 ps
CPU time 355.25 seconds
Started Feb 18 01:47:03 PM PST 24
Finished Feb 18 01:53:00 PM PST 24
Peak memory 199572 kb
Host smart-5ec96c68-6878-4cf6-9d91-ea178eeb0ccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627699457 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.3627699457
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3932554962
Short name T388
Test name
Test status
Simulation time 9814808315 ps
CPU time 55.77 seconds
Started Feb 18 01:47:07 PM PST 24
Finished Feb 18 01:48:06 PM PST 24
Peak memory 199496 kb
Host smart-beb60327-87b3-48e4-a944-27346c5959cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932554962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3932554962
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.4262684884
Short name T272
Test name
Test status
Simulation time 15713981 ps
CPU time 0.58 seconds
Started Feb 18 01:47:19 PM PST 24
Finished Feb 18 01:47:23 PM PST 24
Peak memory 193768 kb
Host smart-b622d5e2-77de-42fd-9d0f-b5642b65cd26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262684884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4262684884
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2999994435
Short name T477
Test name
Test status
Simulation time 991156620 ps
CPU time 29.6 seconds
Started Feb 18 01:47:12 PM PST 24
Finished Feb 18 01:47:45 PM PST 24
Peak memory 199520 kb
Host smart-cbeb853d-3377-4c6d-a362-8c6a00244123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999994435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2999994435
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.4165170278
Short name T218
Test name
Test status
Simulation time 2217341399 ps
CPU time 49.04 seconds
Started Feb 18 01:47:12 PM PST 24
Finished Feb 18 01:48:05 PM PST 24
Peak memory 199448 kb
Host smart-2f38d052-fb4a-427a-bb18-b9e2404863e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165170278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4165170278
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.4161465718
Short name T486
Test name
Test status
Simulation time 6249133403 ps
CPU time 81.73 seconds
Started Feb 18 01:47:13 PM PST 24
Finished Feb 18 01:48:38 PM PST 24
Peak memory 199600 kb
Host smart-4d53d179-29b2-408a-b7a6-bc0dc586b5b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4161465718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.4161465718
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1547215589
Short name T39
Test name
Test status
Simulation time 2511671112 ps
CPU time 31.25 seconds
Started Feb 18 01:47:11 PM PST 24
Finished Feb 18 01:47:46 PM PST 24
Peak memory 199536 kb
Host smart-1b72aef4-d528-416d-b204-2fea297fb9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547215589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1547215589
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2526863775
Short name T221
Test name
Test status
Simulation time 1275375062 ps
CPU time 63.75 seconds
Started Feb 18 01:47:00 PM PST 24
Finished Feb 18 01:48:04 PM PST 24
Peak memory 199480 kb
Host smart-cd37cedb-5e8c-41d1-8304-f461db6e0025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526863775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2526863775
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3133425354
Short name T228
Test name
Test status
Simulation time 2273677957 ps
CPU time 2.68 seconds
Started Feb 18 01:47:03 PM PST 24
Finished Feb 18 01:47:08 PM PST 24
Peak memory 199376 kb
Host smart-cf839ef9-48c8-4006-9933-54168d53ddb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133425354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3133425354
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1665299503
Short name T311
Test name
Test status
Simulation time 42521434054 ps
CPU time 1020.39 seconds
Started Feb 18 01:47:13 PM PST 24
Finished Feb 18 02:04:17 PM PST 24
Peak memory 215216 kb
Host smart-98cd8b23-6ebf-4cff-a82f-76745b50f7ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665299503 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1665299503
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1446487933
Short name T341
Test name
Test status
Simulation time 27726124 ps
CPU time 0.88 seconds
Started Feb 18 01:47:22 PM PST 24
Finished Feb 18 01:47:27 PM PST 24
Peak memory 196744 kb
Host smart-cf46f897-2418-400c-a420-21fbf23ef1df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446487933 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1446487933
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2805849336
Short name T80
Test name
Test status
Simulation time 82294096097 ps
CPU time 478.03 seconds
Started Feb 18 01:47:13 PM PST 24
Finished Feb 18 01:55:15 PM PST 24
Peak memory 199544 kb
Host smart-256d3d9c-168e-4cef-9447-d01db98b07e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805849336 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.2805849336
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2615011767
Short name T427
Test name
Test status
Simulation time 178209655 ps
CPU time 0.57 seconds
Started Feb 18 01:47:13 PM PST 24
Finished Feb 18 01:47:17 PM PST 24
Peak memory 193768 kb
Host smart-0f44c656-fe14-4ec8-9c2a-4d043c4e9b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615011767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2615011767
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1531360990
Short name T500
Test name
Test status
Simulation time 1617989734 ps
CPU time 56.31 seconds
Started Feb 18 01:47:12 PM PST 24
Finished Feb 18 01:48:12 PM PST 24
Peak memory 230324 kb
Host smart-567fba06-7c3e-4732-bbca-a2a1b5faa554
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531360990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1531360990
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2174935513
Short name T229
Test name
Test status
Simulation time 109258604 ps
CPU time 2.73 seconds
Started Feb 18 01:47:12 PM PST 24
Finished Feb 18 01:47:18 PM PST 24
Peak memory 199600 kb
Host smart-d1c687fa-5790-4361-ae70-ac7b8c8b7308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174935513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2174935513
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2798427501
Short name T577
Test name
Test status
Simulation time 1090055002 ps
CPU time 32.26 seconds
Started Feb 18 01:47:18 PM PST 24
Finished Feb 18 01:47:55 PM PST 24
Peak memory 199512 kb
Host smart-ba6a2968-58e6-4656-9856-191c7b1abc43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798427501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2798427501
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.4152151385
Short name T263
Test name
Test status
Simulation time 11499608310 ps
CPU time 195.62 seconds
Started Feb 18 01:47:18 PM PST 24
Finished Feb 18 01:50:37 PM PST 24
Peak memory 199520 kb
Host smart-4dc3c612-8adf-419f-ac40-e9729234b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152151385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.4152151385
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.657179909
Short name T414
Test name
Test status
Simulation time 3848907765 ps
CPU time 52.56 seconds
Started Feb 18 01:47:13 PM PST 24
Finished Feb 18 01:48:09 PM PST 24
Peak memory 199592 kb
Host smart-bf7f7a3d-3db5-4f01-a688-0d15fa77dd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657179909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.657179909
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.247057491
Short name T522
Test name
Test status
Simulation time 78585187 ps
CPU time 1.37 seconds
Started Feb 18 01:47:12 PM PST 24
Finished Feb 18 01:47:17 PM PST 24
Peak memory 199384 kb
Host smart-c2686ef0-c30f-41e7-8a87-472249c4327e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247057491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.247057491
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3368480455
Short name T68
Test name
Test status
Simulation time 112039940652 ps
CPU time 1446.62 seconds
Started Feb 18 01:47:20 PM PST 24
Finished Feb 18 02:11:32 PM PST 24
Peak memory 240532 kb
Host smart-3b528bb9-c0f2-41b0-8f49-212e552beb25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368480455 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3368480455
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3898484049
Short name T161
Test name
Test status
Simulation time 263928460 ps
CPU time 1.15 seconds
Started Feb 18 01:47:14 PM PST 24
Finished Feb 18 01:47:19 PM PST 24
Peak memory 198540 kb
Host smart-e79c7980-3b7c-4c33-8eaa-34c26261afdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898484049 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3898484049
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.4269223719
Short name T531
Test name
Test status
Simulation time 51840309103 ps
CPU time 431.95 seconds
Started Feb 18 01:47:13 PM PST 24
Finished Feb 18 01:54:28 PM PST 24
Peak memory 199556 kb
Host smart-7a26aff8-2b0c-404d-b86e-3d0a1e2d1eba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269223719 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.4269223719
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1069026031
Short name T330
Test name
Test status
Simulation time 3715546055 ps
CPU time 11.89 seconds
Started Feb 18 01:47:14 PM PST 24
Finished Feb 18 01:47:30 PM PST 24
Peak memory 199584 kb
Host smart-b569655b-dbce-4e2e-aee7-66ad125bdde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069026031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1069026031
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1649358905
Short name T345
Test name
Test status
Simulation time 28348979 ps
CPU time 0.63 seconds
Started Feb 18 01:47:20 PM PST 24
Finished Feb 18 01:47:25 PM PST 24
Peak memory 193940 kb
Host smart-83345d7d-593d-42fb-b287-c1ccc93f6d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649358905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1649358905
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2599373665
Short name T18
Test name
Test status
Simulation time 1090737908 ps
CPU time 33.59 seconds
Started Feb 18 01:47:19 PM PST 24
Finished Feb 18 01:47:57 PM PST 24
Peak memory 207712 kb
Host smart-8646d988-2917-4dd7-a2db-2535980e01fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599373665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2599373665
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2154766391
Short name T480
Test name
Test status
Simulation time 1020050182 ps
CPU time 16.42 seconds
Started Feb 18 01:47:15 PM PST 24
Finished Feb 18 01:47:36 PM PST 24
Peak memory 199480 kb
Host smart-1c481914-9266-452c-9a19-97517fb3827d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154766391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2154766391
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1538492712
Short name T128
Test name
Test status
Simulation time 1824293083 ps
CPU time 97.19 seconds
Started Feb 18 01:47:21 PM PST 24
Finished Feb 18 01:49:03 PM PST 24
Peak memory 199536 kb
Host smart-4522b363-d20d-4cd7-8a45-15f680fe3519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538492712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1538492712
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.574542856
Short name T187
Test name
Test status
Simulation time 2281053179 ps
CPU time 108.64 seconds
Started Feb 18 01:47:23 PM PST 24
Finished Feb 18 01:49:16 PM PST 24
Peak memory 199652 kb
Host smart-30935a08-5b8d-4979-aecf-96f8ef5333cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574542856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.574542856
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.4135518985
Short name T468
Test name
Test status
Simulation time 4278640254 ps
CPU time 78.3 seconds
Started Feb 18 01:47:21 PM PST 24
Finished Feb 18 01:48:44 PM PST 24
Peak memory 199560 kb
Host smart-a4cc2f76-8cb9-4dc5-9600-741b949767b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135518985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.4135518985
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1410689223
Short name T575
Test name
Test status
Simulation time 346753590 ps
CPU time 4.53 seconds
Started Feb 18 01:47:15 PM PST 24
Finished Feb 18 01:47:24 PM PST 24
Peak memory 199496 kb
Host smart-2fa57528-45bd-42ed-a08b-87766f41c8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410689223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1410689223
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.184048551
Short name T108
Test name
Test status
Simulation time 39844697218 ps
CPU time 705.16 seconds
Started Feb 18 01:47:21 PM PST 24
Finished Feb 18 01:59:11 PM PST 24
Peak memory 234940 kb
Host smart-3803f598-6325-4310-9d78-f957a76372ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184048551 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.184048551
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.4247222355
Short name T62
Test name
Test status
Simulation time 5615376398 ps
CPU time 264.3 seconds
Started Feb 18 01:47:18 PM PST 24
Finished Feb 18 01:51:46 PM PST 24
Peak memory 237352 kb
Host smart-0aef9e4e-0c76-41ff-9f2c-4781b33fa19e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247222355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.4247222355
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2326980347
Short name T404
Test name
Test status
Simulation time 58744314 ps
CPU time 1.23 seconds
Started Feb 18 01:47:17 PM PST 24
Finished Feb 18 01:47:22 PM PST 24
Peak memory 197676 kb
Host smart-67b97952-57cb-49d1-8084-c15f68677bff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326980347 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2326980347
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3772712757
Short name T571
Test name
Test status
Simulation time 15980478979 ps
CPU time 405.68 seconds
Started Feb 18 01:47:19 PM PST 24
Finished Feb 18 01:54:09 PM PST 24
Peak memory 199536 kb
Host smart-0fb56d8a-707c-4039-8f6a-59c972ec64b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772712757 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.3772712757
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3659446313
Short name T15
Test name
Test status
Simulation time 747971962 ps
CPU time 13.41 seconds
Started Feb 18 01:47:18 PM PST 24
Finished Feb 18 01:47:35 PM PST 24
Peak memory 199496 kb
Host smart-0beefd76-9fca-4c88-a44e-20e594ed4578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659446313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3659446313
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.277816917
Short name T403
Test name
Test status
Simulation time 45474733 ps
CPU time 0.58 seconds
Started Feb 18 01:47:23 PM PST 24
Finished Feb 18 01:47:28 PM PST 24
Peak memory 193756 kb
Host smart-92ce9af2-4288-4ac3-a13a-220095ab9e06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277816917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.277816917
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.906996626
Short name T422
Test name
Test status
Simulation time 1129263870 ps
CPU time 37.86 seconds
Started Feb 18 01:47:18 PM PST 24
Finished Feb 18 01:48:00 PM PST 24
Peak memory 231452 kb
Host smart-b318b1dc-62ed-4f08-81e7-d5aef0cdb35e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906996626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.906996626
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1007655966
Short name T222
Test name
Test status
Simulation time 1986302053 ps
CPU time 36.67 seconds
Started Feb 18 01:47:17 PM PST 24
Finished Feb 18 01:47:58 PM PST 24
Peak memory 199516 kb
Host smart-662a51f4-ca1b-4067-9061-72e0492dee91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007655966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1007655966
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1568180836
Short name T396
Test name
Test status
Simulation time 205315954 ps
CPU time 10.98 seconds
Started Feb 18 01:47:18 PM PST 24
Finished Feb 18 01:47:33 PM PST 24
Peak memory 199508 kb
Host smart-17fcd6fa-76ea-4228-917e-c6bb0a3ddd77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568180836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1568180836
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.751375442
Short name T214
Test name
Test status
Simulation time 37598240889 ps
CPU time 164.4 seconds
Started Feb 18 01:47:21 PM PST 24
Finished Feb 18 01:50:11 PM PST 24
Peak memory 199672 kb
Host smart-ba57965c-531b-4d96-a78c-d858bd0699e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751375442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.751375442
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1223239243
Short name T474
Test name
Test status
Simulation time 2696354205 ps
CPU time 29.97 seconds
Started Feb 18 01:47:15 PM PST 24
Finished Feb 18 01:47:49 PM PST 24
Peak memory 199564 kb
Host smart-2fa2adff-547a-431b-bde3-84ea2d21652e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223239243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1223239243
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3029624134
Short name T584
Test name
Test status
Simulation time 74135824 ps
CPU time 2.18 seconds
Started Feb 18 01:47:18 PM PST 24
Finished Feb 18 01:47:24 PM PST 24
Peak memory 199408 kb
Host smart-17beb178-b57f-4bf8-9879-9c072f6b5379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029624134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3029624134
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1847588678
Short name T324
Test name
Test status
Simulation time 485391798934 ps
CPU time 1411.62 seconds
Started Feb 18 01:47:17 PM PST 24
Finished Feb 18 02:10:53 PM PST 24
Peak memory 199624 kb
Host smart-fe6ab48a-b4fa-49e0-b74f-6e90408f1147
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847588678 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1847588678
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2385088861
Short name T207
Test name
Test status
Simulation time 83026398 ps
CPU time 1.15 seconds
Started Feb 18 01:47:21 PM PST 24
Finished Feb 18 01:47:27 PM PST 24
Peak memory 198052 kb
Host smart-6bd3009b-abf3-41c2-9323-3d98434cd5c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385088861 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2385088861
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1953219516
Short name T299
Test name
Test status
Simulation time 152083295599 ps
CPU time 458.14 seconds
Started Feb 18 01:47:19 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 199520 kb
Host smart-988e0e39-f56c-4e26-9f71-cb8eefa10eee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953219516 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_sha_vectors.1953219516
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1842040299
Short name T463
Test name
Test status
Simulation time 3908974393 ps
CPU time 47.25 seconds
Started Feb 18 01:47:18 PM PST 24
Finished Feb 18 01:48:10 PM PST 24
Peak memory 199632 kb
Host smart-10475e78-835c-46fc-aa9a-84678a1aff72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842040299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1842040299
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2235893293
Short name T284
Test name
Test status
Simulation time 11047963 ps
CPU time 0.58 seconds
Started Feb 18 01:47:27 PM PST 24
Finished Feb 18 01:47:31 PM PST 24
Peak memory 193768 kb
Host smart-a4333f4f-8a96-4e14-bb1a-14806e12bbc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235893293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2235893293
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3167865335
Short name T493
Test name
Test status
Simulation time 656962913 ps
CPU time 24.65 seconds
Started Feb 18 01:47:20 PM PST 24
Finished Feb 18 01:47:50 PM PST 24
Peak memory 224056 kb
Host smart-f4dbc6c3-bc99-4430-b4ca-744ff278ddf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167865335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3167865335
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3945024871
Short name T121
Test name
Test status
Simulation time 7368207027 ps
CPU time 34.81 seconds
Started Feb 18 01:47:28 PM PST 24
Finished Feb 18 01:48:06 PM PST 24
Peak memory 199360 kb
Host smart-33ba794b-7a29-4669-a36b-f3905c669d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945024871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3945024871
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2313734145
Short name T22
Test name
Test status
Simulation time 1433265883 ps
CPU time 40.39 seconds
Started Feb 18 01:47:28 PM PST 24
Finished Feb 18 01:48:11 PM PST 24
Peak memory 199352 kb
Host smart-002ee8a8-b8ee-430f-b8b3-5acf3d1b757e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313734145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2313734145
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.643805304
Short name T146
Test name
Test status
Simulation time 2170327644 ps
CPU time 97.7 seconds
Started Feb 18 01:47:23 PM PST 24
Finished Feb 18 01:49:05 PM PST 24
Peak memory 199668 kb
Host smart-e00744d8-ca06-407a-8c6a-e1eea1645e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643805304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.643805304
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1562488670
Short name T225
Test name
Test status
Simulation time 23381334350 ps
CPU time 102 seconds
Started Feb 18 01:47:22 PM PST 24
Finished Feb 18 01:49:09 PM PST 24
Peak memory 199532 kb
Host smart-f5f171b6-be6b-4bd8-a691-35bde118da97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562488670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1562488670
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.407914489
Short name T199
Test name
Test status
Simulation time 100369257 ps
CPU time 2.45 seconds
Started Feb 18 01:47:19 PM PST 24
Finished Feb 18 01:47:26 PM PST 24
Peak memory 199528 kb
Host smart-b46f5fe8-db0e-46ab-9bec-c598eb47bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407914489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.407914489
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.108444800
Short name T453
Test name
Test status
Simulation time 1426361594 ps
CPU time 22.32 seconds
Started Feb 18 01:47:23 PM PST 24
Finished Feb 18 01:47:49 PM PST 24
Peak memory 199504 kb
Host smart-5e541c4b-eeee-47af-85f9-ea4de357709d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108444800 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.108444800
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3529362751
Short name T516
Test name
Test status
Simulation time 246930421 ps
CPU time 1.19 seconds
Started Feb 18 01:47:24 PM PST 24
Finished Feb 18 01:47:29 PM PST 24
Peak memory 198484 kb
Host smart-d48a9bb5-133b-408a-9c70-4dddac231643
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529362751 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.3529362751
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.4237312993
Short name T216
Test name
Test status
Simulation time 140833701868 ps
CPU time 383.62 seconds
Started Feb 18 01:47:28 PM PST 24
Finished Feb 18 01:53:55 PM PST 24
Peak memory 199480 kb
Host smart-33de0f14-353a-46de-8e41-208a35ac0166
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237312993 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_sha_vectors.4237312993
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3713219290
Short name T233
Test name
Test status
Simulation time 2505841494 ps
CPU time 14.51 seconds
Started Feb 18 01:47:23 PM PST 24
Finished Feb 18 01:47:42 PM PST 24
Peak memory 199492 kb
Host smart-c0ba9a0a-a230-4091-8636-d009126ab128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713219290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3713219290
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.123824340
Short name T354
Test name
Test status
Simulation time 11573804 ps
CPU time 0.57 seconds
Started Feb 18 01:47:25 PM PST 24
Finished Feb 18 01:47:30 PM PST 24
Peak memory 193736 kb
Host smart-fdfefab4-c34f-44d3-85a4-7e2fc216be00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123824340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.123824340
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.4291081219
Short name T245
Test name
Test status
Simulation time 2398909763 ps
CPU time 39.37 seconds
Started Feb 18 01:47:25 PM PST 24
Finished Feb 18 01:48:08 PM PST 24
Peak memory 215920 kb
Host smart-157cb471-86e9-4dd7-82e2-d13f0f6fd04c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291081219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4291081219
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.76234979
Short name T497
Test name
Test status
Simulation time 1337684385 ps
CPU time 24.81 seconds
Started Feb 18 01:47:24 PM PST 24
Finished Feb 18 01:47:53 PM PST 24
Peak memory 199512 kb
Host smart-fbe7eaa6-22fe-461b-b644-9a7def315694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76234979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.76234979
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1162342486
Short name T436
Test name
Test status
Simulation time 2466165444 ps
CPU time 63.99 seconds
Started Feb 18 01:47:28 PM PST 24
Finished Feb 18 01:48:35 PM PST 24
Peak memory 199636 kb
Host smart-ce98bb82-5f88-4a44-9e3f-11038bed390a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162342486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1162342486
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3247627414
Short name T83
Test name
Test status
Simulation time 44328024657 ps
CPU time 136.83 seconds
Started Feb 18 01:47:28 PM PST 24
Finished Feb 18 01:49:48 PM PST 24
Peak memory 199544 kb
Host smart-d6e2db2c-828a-461b-99a7-eb6f1804d807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247627414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3247627414
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1038930077
Short name T391
Test name
Test status
Simulation time 5261304455 ps
CPU time 46.31 seconds
Started Feb 18 01:47:27 PM PST 24
Finished Feb 18 01:48:16 PM PST 24
Peak memory 199576 kb
Host smart-57dfda99-24b6-4943-bd51-a0f5207d6c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038930077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1038930077
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2916090884
Short name T563
Test name
Test status
Simulation time 1506600617 ps
CPU time 3.17 seconds
Started Feb 18 01:47:28 PM PST 24
Finished Feb 18 01:47:34 PM PST 24
Peak memory 199508 kb
Host smart-7e325c33-3e25-460b-8adf-79e9a6974437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916090884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2916090884
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.690106916
Short name T283
Test name
Test status
Simulation time 16172419960 ps
CPU time 98.37 seconds
Started Feb 18 01:47:29 PM PST 24
Finished Feb 18 01:49:10 PM PST 24
Peak memory 199572 kb
Host smart-b7de0d4e-c7e6-4a7b-a6fc-fb445d150a83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690106916 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.690106916
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.3863501648
Short name T7
Test name
Test status
Simulation time 19962006314 ps
CPU time 630.07 seconds
Started Feb 18 01:47:27 PM PST 24
Finished Feb 18 01:58:00 PM PST 24
Peak memory 228428 kb
Host smart-04667f9d-1c91-46e3-a041-df0a7fe48b6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3863501648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.3863501648
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3618482328
Short name T34
Test name
Test status
Simulation time 107054905 ps
CPU time 1.16 seconds
Started Feb 18 01:47:29 PM PST 24
Finished Feb 18 01:47:33 PM PST 24
Peak memory 198356 kb
Host smart-dfed4757-ab38-4c79-93a6-909b22239ae8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618482328 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3618482328
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1559462617
Short name T408
Test name
Test status
Simulation time 40231754074 ps
CPU time 458.01 seconds
Started Feb 18 01:47:29 PM PST 24
Finished Feb 18 01:55:09 PM PST 24
Peak memory 199504 kb
Host smart-37bf5aa0-d6b2-4299-a019-b082929850fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559462617 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_sha_vectors.1559462617
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2553560029
Short name T573
Test name
Test status
Simulation time 563676522 ps
CPU time 5.18 seconds
Started Feb 18 01:47:29 PM PST 24
Finished Feb 18 01:47:37 PM PST 24
Peak memory 199488 kb
Host smart-608d3af2-d007-4e35-a1cd-652995ffbccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553560029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2553560029
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.466668640
Short name T175
Test name
Test status
Simulation time 17747317 ps
CPU time 0.59 seconds
Started Feb 18 01:47:36 PM PST 24
Finished Feb 18 01:47:38 PM PST 24
Peak memory 193928 kb
Host smart-6eb9f783-47e1-40dd-9feb-f1f993824dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466668640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.466668640
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.4045728115
Short name T238
Test name
Test status
Simulation time 2682204156 ps
CPU time 47.71 seconds
Started Feb 18 01:47:23 PM PST 24
Finished Feb 18 01:48:15 PM PST 24
Peak memory 231340 kb
Host smart-1687768c-c9e2-43db-9e5c-5586b46e4614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045728115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4045728115
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3870377133
Short name T310
Test name
Test status
Simulation time 5765912466 ps
CPU time 67.42 seconds
Started Feb 18 01:47:28 PM PST 24
Finished Feb 18 01:48:38 PM PST 24
Peak memory 199548 kb
Host smart-d9d7afff-ff9c-4800-957f-92bb9a65d8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870377133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3870377133
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2540858383
Short name T300
Test name
Test status
Simulation time 19215504230 ps
CPU time 122.27 seconds
Started Feb 18 01:47:26 PM PST 24
Finished Feb 18 01:49:32 PM PST 24
Peak memory 199596 kb
Host smart-c8ce8f8a-5840-4a64-91bd-ad30d6bd9564
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540858383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2540858383
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4286307539
Short name T373
Test name
Test status
Simulation time 3297961282 ps
CPU time 40.43 seconds
Started Feb 18 01:47:24 PM PST 24
Finished Feb 18 01:48:08 PM PST 24
Peak memory 199576 kb
Host smart-cd1f9695-09f3-43a4-a683-77935206703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286307539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4286307539
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1463570694
Short name T368
Test name
Test status
Simulation time 7729941399 ps
CPU time 48.01 seconds
Started Feb 18 01:47:29 PM PST 24
Finished Feb 18 01:48:20 PM PST 24
Peak memory 199556 kb
Host smart-afa48484-6a9d-440e-9a66-559bbf4beef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463570694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1463570694
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3321770916
Short name T197
Test name
Test status
Simulation time 65166015 ps
CPU time 1.69 seconds
Started Feb 18 01:47:29 PM PST 24
Finished Feb 18 01:47:34 PM PST 24
Peak memory 199544 kb
Host smart-8db8e38f-7ec4-447d-9659-a1a7a69087d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321770916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3321770916
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.976535475
Short name T546
Test name
Test status
Simulation time 6356623536 ps
CPU time 14.25 seconds
Started Feb 18 01:47:32 PM PST 24
Finished Feb 18 01:47:48 PM PST 24
Peak memory 199536 kb
Host smart-78466d0a-484b-4a60-b520-f9d04294c5ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976535475 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.976535475
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1963447156
Short name T588
Test name
Test status
Simulation time 31340324 ps
CPU time 1.16 seconds
Started Feb 18 01:47:35 PM PST 24
Finished Feb 18 01:47:38 PM PST 24
Peak memory 199432 kb
Host smart-7fcb42c3-5d1b-42b9-80ce-24ad970617f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963447156 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1963447156
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3102963736
Short name T562
Test name
Test status
Simulation time 114148058531 ps
CPU time 479.45 seconds
Started Feb 18 01:47:32 PM PST 24
Finished Feb 18 01:55:34 PM PST 24
Peak memory 199580 kb
Host smart-d3458255-eb28-4735-b993-3bee7dc35fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102963736 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.3102963736
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3768666604
Short name T147
Test name
Test status
Simulation time 3988289469 ps
CPU time 74.06 seconds
Started Feb 18 01:47:25 PM PST 24
Finished Feb 18 01:48:43 PM PST 24
Peak memory 199620 kb
Host smart-f333efc8-1f74-4401-a0a5-abeb83d1d384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768666604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3768666604
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.38557228
Short name T466
Test name
Test status
Simulation time 26560009 ps
CPU time 0.6 seconds
Started Feb 18 01:47:31 PM PST 24
Finished Feb 18 01:47:34 PM PST 24
Peak memory 193732 kb
Host smart-7be6099b-e86f-45c9-ac7a-521180546d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38557228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.38557228
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3864041477
Short name T111
Test name
Test status
Simulation time 1896157917 ps
CPU time 35.37 seconds
Started Feb 18 01:47:30 PM PST 24
Finished Feb 18 01:48:08 PM PST 24
Peak memory 215844 kb
Host smart-37dc40d1-9e5c-4783-896a-94e9855021db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864041477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3864041477
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2169730967
Short name T227
Test name
Test status
Simulation time 7526712277 ps
CPU time 36.89 seconds
Started Feb 18 01:47:32 PM PST 24
Finished Feb 18 01:48:11 PM PST 24
Peak memory 199536 kb
Host smart-d7accd64-6660-49a4-9b7e-c71058a7d46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169730967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2169730967
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3752815213
Short name T519
Test name
Test status
Simulation time 6505732935 ps
CPU time 85.51 seconds
Started Feb 18 01:47:33 PM PST 24
Finished Feb 18 01:49:01 PM PST 24
Peak memory 199576 kb
Host smart-4370d09f-2349-446f-9aa7-03c7b24fd1c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752815213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3752815213
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1043762978
Short name T195
Test name
Test status
Simulation time 1363506172 ps
CPU time 8.04 seconds
Started Feb 18 01:47:30 PM PST 24
Finished Feb 18 01:47:40 PM PST 24
Peak memory 199476 kb
Host smart-bcbbc9c0-72a8-4dde-b59b-3e2744c76eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043762978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1043762978
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.85288693
Short name T278
Test name
Test status
Simulation time 1070714910 ps
CPU time 57.68 seconds
Started Feb 18 01:47:32 PM PST 24
Finished Feb 18 01:48:33 PM PST 24
Peak memory 199540 kb
Host smart-01e3ac2a-b3d8-4eaa-9764-e4294661e824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85288693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.85288693
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1445067411
Short name T282
Test name
Test status
Simulation time 391453233 ps
CPU time 4.51 seconds
Started Feb 18 01:47:34 PM PST 24
Finished Feb 18 01:47:41 PM PST 24
Peak memory 199560 kb
Host smart-80a94b53-97ef-4ec8-9ea3-f0d3a05a67a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445067411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1445067411
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3045577724
Short name T248
Test name
Test status
Simulation time 95610562898 ps
CPU time 1130.74 seconds
Started Feb 18 01:47:34 PM PST 24
Finished Feb 18 02:06:27 PM PST 24
Peak memory 229388 kb
Host smart-8a036f70-37bc-4817-941b-73985070c108
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045577724 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3045577724
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2324982638
Short name T485
Test name
Test status
Simulation time 123220707 ps
CPU time 1.16 seconds
Started Feb 18 01:47:36 PM PST 24
Finished Feb 18 01:47:39 PM PST 24
Peak memory 198284 kb
Host smart-d2e79343-f2fc-412d-b81c-332747ceaeff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324982638 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2324982638
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3191847663
Short name T476
Test name
Test status
Simulation time 34593760839 ps
CPU time 394.85 seconds
Started Feb 18 01:47:32 PM PST 24
Finished Feb 18 01:54:09 PM PST 24
Peak memory 199524 kb
Host smart-d818bcf2-d90d-4a4c-bd00-5796510c7034
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191847663 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.3191847663
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.485509072
Short name T33
Test name
Test status
Simulation time 11612983094 ps
CPU time 71.81 seconds
Started Feb 18 01:47:35 PM PST 24
Finished Feb 18 01:48:49 PM PST 24
Peak memory 199520 kb
Host smart-8d8f200a-f4ff-42a7-ae9d-fffe8a96ec6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485509072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.485509072
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1423828127
Short name T230
Test name
Test status
Simulation time 34942983 ps
CPU time 0.52 seconds
Started Feb 18 01:47:44 PM PST 24
Finished Feb 18 01:47:47 PM PST 24
Peak memory 193780 kb
Host smart-15aa53b9-c133-4a8d-902a-ef6bfd1adb39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423828127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1423828127
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3098464095
Short name T333
Test name
Test status
Simulation time 12567189711 ps
CPU time 52.02 seconds
Started Feb 18 01:47:39 PM PST 24
Finished Feb 18 01:48:32 PM PST 24
Peak memory 215456 kb
Host smart-98e23f26-52fc-458b-aed8-004faae0ebab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098464095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3098464095
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.948362311
Short name T464
Test name
Test status
Simulation time 277100341 ps
CPU time 5.84 seconds
Started Feb 18 01:47:30 PM PST 24
Finished Feb 18 01:47:39 PM PST 24
Peak memory 199488 kb
Host smart-86be84d8-344a-4d73-a4e9-55f9664b36db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948362311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.948362311
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3648390276
Short name T105
Test name
Test status
Simulation time 2387313212 ps
CPU time 59.96 seconds
Started Feb 18 01:47:33 PM PST 24
Finished Feb 18 01:48:36 PM PST 24
Peak memory 199604 kb
Host smart-fdedc37e-89e4-43fa-af45-93acd34cfd50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648390276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3648390276
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3301526759
Short name T174
Test name
Test status
Simulation time 2411216839 ps
CPU time 28.61 seconds
Started Feb 18 01:47:47 PM PST 24
Finished Feb 18 01:48:21 PM PST 24
Peak memory 199508 kb
Host smart-03d46735-f963-443b-a69d-09c09a344510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301526759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3301526759
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3418183768
Short name T250
Test name
Test status
Simulation time 2019833105 ps
CPU time 108.16 seconds
Started Feb 18 01:47:38 PM PST 24
Finished Feb 18 01:49:28 PM PST 24
Peak memory 199536 kb
Host smart-c4e37a58-e82b-4aa5-a3d0-613b8608d06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418183768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3418183768
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3919435902
Short name T211
Test name
Test status
Simulation time 126207571 ps
CPU time 0.7 seconds
Started Feb 18 01:47:34 PM PST 24
Finished Feb 18 01:47:37 PM PST 24
Peak memory 196268 kb
Host smart-0b6b9756-1c6d-4448-b345-e9dbc04eda0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919435902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3919435902
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2382349958
Short name T506
Test name
Test status
Simulation time 21334150370 ps
CPU time 336.47 seconds
Started Feb 18 01:47:47 PM PST 24
Finished Feb 18 01:53:28 PM PST 24
Peak memory 199628 kb
Host smart-24350684-fe19-4d14-ac74-6f3857896e2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382349958 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2382349958
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2376974550
Short name T448
Test name
Test status
Simulation time 39347659 ps
CPU time 0.99 seconds
Started Feb 18 01:47:45 PM PST 24
Finished Feb 18 01:47:49 PM PST 24
Peak memory 197516 kb
Host smart-b5fa8ba7-b25a-4bce-826a-6bb137b13639
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376974550 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2376974550
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.520924406
Short name T276
Test name
Test status
Simulation time 32710809910 ps
CPU time 438.52 seconds
Started Feb 18 01:47:47 PM PST 24
Finished Feb 18 01:55:09 PM PST 24
Peak memory 199520 kb
Host smart-c831c761-7e57-4fb1-8ea5-03dfb5ad1715
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520924406 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.hmac_test_sha_vectors.520924406
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4132187106
Short name T170
Test name
Test status
Simulation time 158547301 ps
CPU time 8.25 seconds
Started Feb 18 01:47:43 PM PST 24
Finished Feb 18 01:47:53 PM PST 24
Peak memory 199580 kb
Host smart-3389ca67-5d39-404f-8a0d-dcd357ab69a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132187106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4132187106
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3937717115
Short name T286
Test name
Test status
Simulation time 35651369 ps
CPU time 0.57 seconds
Started Feb 18 01:45:34 PM PST 24
Finished Feb 18 01:45:39 PM PST 24
Peak memory 193744 kb
Host smart-a3115c78-e9e3-418e-8d5c-10e2ee652c15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937717115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3937717115
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1839512773
Short name T196
Test name
Test status
Simulation time 823641660 ps
CPU time 15.26 seconds
Started Feb 18 01:45:32 PM PST 24
Finished Feb 18 01:45:51 PM PST 24
Peak memory 207664 kb
Host smart-681fc010-6336-4156-98be-6463b3bae9e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839512773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1839512773
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3600060331
Short name T423
Test name
Test status
Simulation time 1009317916 ps
CPU time 48.03 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:46:30 PM PST 24
Peak memory 199428 kb
Host smart-2822e728-f303-4e99-b167-f43470494a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600060331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3600060331
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.570579895
Short name T109
Test name
Test status
Simulation time 40849217534 ps
CPU time 152.57 seconds
Started Feb 18 01:45:33 PM PST 24
Finished Feb 18 01:48:09 PM PST 24
Peak memory 199612 kb
Host smart-2570e1dd-6f90-4686-b889-7011c62a552f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570579895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.570579895
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2382211402
Short name T524
Test name
Test status
Simulation time 1547012317 ps
CPU time 24.23 seconds
Started Feb 18 01:45:34 PM PST 24
Finished Feb 18 01:46:03 PM PST 24
Peak memory 199580 kb
Host smart-a487b3e4-d0f7-452c-a276-93deb3ddf663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382211402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2382211402
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1978163102
Short name T532
Test name
Test status
Simulation time 8850094010 ps
CPU time 30.06 seconds
Started Feb 18 01:45:41 PM PST 24
Finished Feb 18 01:46:17 PM PST 24
Peak memory 199576 kb
Host smart-ab0972ec-adad-480a-8960-ab8368d17b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978163102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1978163102
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3972306571
Short name T45
Test name
Test status
Simulation time 339703514 ps
CPU time 0.95 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:45:42 PM PST 24
Peak memory 217724 kb
Host smart-d2b1d686-61f0-4a18-88bd-b9182bbab1e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972306571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3972306571
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3066200199
Short name T384
Test name
Test status
Simulation time 124740156 ps
CPU time 3.32 seconds
Started Feb 18 01:45:33 PM PST 24
Finished Feb 18 01:45:40 PM PST 24
Peak memory 199520 kb
Host smart-42f08832-b215-4031-b3d2-acd51384c418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066200199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3066200199
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2071503567
Short name T41
Test name
Test status
Simulation time 305585505627 ps
CPU time 969.19 seconds
Started Feb 18 01:45:32 PM PST 24
Finished Feb 18 02:01:44 PM PST 24
Peak memory 234404 kb
Host smart-42888757-8498-470d-a369-31fc38359cb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071503567 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2071503567
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3240655878
Short name T478
Test name
Test status
Simulation time 104337869 ps
CPU time 1.17 seconds
Started Feb 18 01:45:37 PM PST 24
Finished Feb 18 01:45:45 PM PST 24
Peak memory 198600 kb
Host smart-df11ba6b-b689-4a5b-8594-4a0ccabc64e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240655878 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3240655878
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1426931681
Short name T116
Test name
Test status
Simulation time 170132469868 ps
CPU time 463.85 seconds
Started Feb 18 01:45:31 PM PST 24
Finished Feb 18 01:53:19 PM PST 24
Peak memory 199388 kb
Host smart-6cf00d75-db72-4fe2-b279-50d64578ba68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426931681 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.1426931681
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3639827400
Short name T494
Test name
Test status
Simulation time 3002792169 ps
CPU time 44.95 seconds
Started Feb 18 01:45:34 PM PST 24
Finished Feb 18 01:46:24 PM PST 24
Peak memory 199628 kb
Host smart-847b8fb2-85c8-42bc-8b5f-6f4151611b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639827400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3639827400
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1697658490
Short name T13
Test name
Test status
Simulation time 15101104 ps
CPU time 0.64 seconds
Started Feb 18 01:47:56 PM PST 24
Finished Feb 18 01:48:03 PM PST 24
Peak memory 193896 kb
Host smart-6c5be7a8-0926-40f5-8249-a762e0eb3df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697658490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1697658490
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1359380167
Short name T24
Test name
Test status
Simulation time 1529897233 ps
CPU time 26.96 seconds
Started Feb 18 01:47:41 PM PST 24
Finished Feb 18 01:48:09 PM PST 24
Peak memory 232276 kb
Host smart-609ce470-0d52-4684-97ff-ab608b5ae138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359380167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1359380167
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3939051838
Short name T367
Test name
Test status
Simulation time 35629702 ps
CPU time 0.99 seconds
Started Feb 18 01:47:47 PM PST 24
Finished Feb 18 01:47:52 PM PST 24
Peak memory 199172 kb
Host smart-08333d8d-99e5-4394-a041-0e5b7df035b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939051838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3939051838
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3797606480
Short name T224
Test name
Test status
Simulation time 772400933 ps
CPU time 40.51 seconds
Started Feb 18 01:47:43 PM PST 24
Finished Feb 18 01:48:26 PM PST 24
Peak memory 199456 kb
Host smart-aa1029b7-c55e-4f1b-bdc0-653e82ff5222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797606480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3797606480
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2375893478
Short name T232
Test name
Test status
Simulation time 7429385402 ps
CPU time 61.68 seconds
Started Feb 18 01:47:46 PM PST 24
Finished Feb 18 01:48:51 PM PST 24
Peak memory 199556 kb
Host smart-c1f8a995-aac2-40f6-b205-10470be86069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375893478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2375893478
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.118407810
Short name T270
Test name
Test status
Simulation time 6951847382 ps
CPU time 87.61 seconds
Started Feb 18 01:47:45 PM PST 24
Finished Feb 18 01:49:15 PM PST 24
Peak memory 199600 kb
Host smart-bf4132a8-d286-43b2-a61e-5f7570f7546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118407810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.118407810
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1443885303
Short name T495
Test name
Test status
Simulation time 235913835 ps
CPU time 3.28 seconds
Started Feb 18 01:47:40 PM PST 24
Finished Feb 18 01:47:45 PM PST 24
Peak memory 199460 kb
Host smart-769b3c80-3e1d-4087-b4d6-71db8adf5e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443885303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1443885303
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2703203965
Short name T249
Test name
Test status
Simulation time 36322113094 ps
CPU time 873.53 seconds
Started Feb 18 01:47:53 PM PST 24
Finished Feb 18 02:02:33 PM PST 24
Peak memory 199656 kb
Host smart-eeafd15f-5249-497e-9ebb-9bd8d4c2ac8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703203965 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2703203965
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.1610353371
Short name T4
Test name
Test status
Simulation time 49566197 ps
CPU time 1.01 seconds
Started Feb 18 01:47:41 PM PST 24
Finished Feb 18 01:47:43 PM PST 24
Peak memory 197136 kb
Host smart-070614df-15be-4409-99fd-544929b3e792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610353371 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.1610353371
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2004554921
Short name T541
Test name
Test status
Simulation time 17453869494 ps
CPU time 455.79 seconds
Started Feb 18 01:47:40 PM PST 24
Finished Feb 18 01:55:18 PM PST 24
Peak memory 199564 kb
Host smart-bde41b3c-1a93-4488-8d31-45d2c166e6d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004554921 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.2004554921
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2091857211
Short name T432
Test name
Test status
Simulation time 41017620 ps
CPU time 0.56 seconds
Started Feb 18 01:47:52 PM PST 24
Finished Feb 18 01:47:59 PM PST 24
Peak memory 193744 kb
Host smart-1eff72f4-8833-4440-bcb1-e716414b8df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091857211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2091857211
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3591245852
Short name T561
Test name
Test status
Simulation time 330588288 ps
CPU time 13.24 seconds
Started Feb 18 01:47:51 PM PST 24
Finished Feb 18 01:48:11 PM PST 24
Peak memory 221092 kb
Host smart-a2c4af83-69b3-4b97-bea9-be8ac995f1c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591245852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3591245852
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1955832100
Short name T510
Test name
Test status
Simulation time 1189243228 ps
CPU time 40.95 seconds
Started Feb 18 01:47:55 PM PST 24
Finished Feb 18 01:48:41 PM PST 24
Peak memory 199488 kb
Host smart-f80c8b18-666f-4e2d-8e6e-053f8a4e7d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955832100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1955832100
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1955715422
Short name T253
Test name
Test status
Simulation time 4786070210 ps
CPU time 62.78 seconds
Started Feb 18 01:47:52 PM PST 24
Finished Feb 18 01:49:02 PM PST 24
Peak memory 199560 kb
Host smart-53dece83-63cf-44a7-8a79-386a9bc76276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955715422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1955715422
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1007568085
Short name T215
Test name
Test status
Simulation time 12442413647 ps
CPU time 118.69 seconds
Started Feb 18 01:47:52 PM PST 24
Finished Feb 18 01:49:58 PM PST 24
Peak memory 199520 kb
Host smart-8001fda0-43ab-4061-ae2d-d7dd9ac34be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007568085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1007568085
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3611543296
Short name T421
Test name
Test status
Simulation time 6837354019 ps
CPU time 71.83 seconds
Started Feb 18 01:47:57 PM PST 24
Finished Feb 18 01:49:15 PM PST 24
Peak memory 199536 kb
Host smart-c66054c8-dcc1-4dfd-8c6a-845b51e8e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611543296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3611543296
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.230014037
Short name T166
Test name
Test status
Simulation time 188144472 ps
CPU time 4.52 seconds
Started Feb 18 01:47:51 PM PST 24
Finished Feb 18 01:48:02 PM PST 24
Peak memory 199488 kb
Host smart-93125365-9edd-486b-8f7c-3248ec73ec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230014037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.230014037
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.821338051
Short name T107
Test name
Test status
Simulation time 53166064087 ps
CPU time 943.04 seconds
Started Feb 18 01:47:52 PM PST 24
Finished Feb 18 02:03:42 PM PST 24
Peak memory 229316 kb
Host smart-3db883bb-0d38-4ebd-bec0-4a94cd203e5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821338051 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.821338051
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.694115303
Short name T431
Test name
Test status
Simulation time 105406753 ps
CPU time 0.9 seconds
Started Feb 18 01:47:57 PM PST 24
Finished Feb 18 01:48:04 PM PST 24
Peak memory 196656 kb
Host smart-deb70877-70b3-477d-a3c3-f96099a230ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694115303 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.694115303
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.198465484
Short name T540
Test name
Test status
Simulation time 124146461072 ps
CPU time 417.61 seconds
Started Feb 18 01:47:51 PM PST 24
Finished Feb 18 01:54:55 PM PST 24
Peak memory 199568 kb
Host smart-542f1283-1f6c-4e34-9ab1-ab852f409bc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198465484 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.hmac_test_sha_vectors.198465484
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3355223833
Short name T296
Test name
Test status
Simulation time 154729865 ps
CPU time 1.87 seconds
Started Feb 18 01:47:50 PM PST 24
Finished Feb 18 01:47:58 PM PST 24
Peak memory 199548 kb
Host smart-c2515fbb-2d81-4266-adda-139223bad872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355223833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3355223833
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2310503760
Short name T567
Test name
Test status
Simulation time 73772424 ps
CPU time 0.55 seconds
Started Feb 18 01:47:58 PM PST 24
Finished Feb 18 01:48:05 PM PST 24
Peak memory 193768 kb
Host smart-866a713c-7610-4eff-a8f2-c86d0edb6236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310503760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2310503760
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1000799204
Short name T237
Test name
Test status
Simulation time 1069255209 ps
CPU time 34.3 seconds
Started Feb 18 01:47:53 PM PST 24
Finished Feb 18 01:48:34 PM PST 24
Peak memory 214956 kb
Host smart-5c3ff85a-6b69-470c-b191-7456587e6022
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000799204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1000799204
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2011356453
Short name T483
Test name
Test status
Simulation time 287812183 ps
CPU time 3.61 seconds
Started Feb 18 01:47:58 PM PST 24
Finished Feb 18 01:48:08 PM PST 24
Peak memory 199452 kb
Host smart-8b72f912-e2e2-4061-8690-03efefb6462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011356453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2011356453
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.573333488
Short name T112
Test name
Test status
Simulation time 3163425959 ps
CPU time 82.87 seconds
Started Feb 18 01:47:50 PM PST 24
Finished Feb 18 01:49:20 PM PST 24
Peak memory 199520 kb
Host smart-3df7a08f-9e25-4e45-9d07-93e56fa25c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573333488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.573333488
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2918128288
Short name T124
Test name
Test status
Simulation time 840723305 ps
CPU time 41.05 seconds
Started Feb 18 01:47:52 PM PST 24
Finished Feb 18 01:48:40 PM PST 24
Peak memory 199500 kb
Host smart-a55e425b-60a4-4b0b-afbf-868d27a09007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918128288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2918128288
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2282034006
Short name T268
Test name
Test status
Simulation time 2782976515 ps
CPU time 34.93 seconds
Started Feb 18 01:47:59 PM PST 24
Finished Feb 18 01:48:40 PM PST 24
Peak memory 199572 kb
Host smart-35f4aeaa-6252-46e9-8bee-5c7a5d69ef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282034006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2282034006
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1491519460
Short name T536
Test name
Test status
Simulation time 355499346 ps
CPU time 2.5 seconds
Started Feb 18 01:47:57 PM PST 24
Finished Feb 18 01:48:06 PM PST 24
Peak memory 199452 kb
Host smart-a0e810bd-4bbf-449f-9748-323253caf264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491519460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1491519460
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1197981097
Short name T69
Test name
Test status
Simulation time 60131264601 ps
CPU time 240.58 seconds
Started Feb 18 01:47:58 PM PST 24
Finished Feb 18 01:52:05 PM PST 24
Peak memory 226324 kb
Host smart-f8ac7103-b1c4-48ea-8584-d866ba37c565
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197981097 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1197981097
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1153510008
Short name T413
Test name
Test status
Simulation time 106679078 ps
CPU time 1.15 seconds
Started Feb 18 01:47:53 PM PST 24
Finished Feb 18 01:48:01 PM PST 24
Peak memory 198032 kb
Host smart-e753fc89-f35c-492b-8420-fdc60a220212
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153510008 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1153510008
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2340504452
Short name T267
Test name
Test status
Simulation time 28755283416 ps
CPU time 447.62 seconds
Started Feb 18 01:47:51 PM PST 24
Finished Feb 18 01:55:26 PM PST 24
Peak memory 199328 kb
Host smart-8732e90c-06f6-4acf-815e-9e5a6f8750b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340504452 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.2340504452
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2566123861
Short name T137
Test name
Test status
Simulation time 2196377151 ps
CPU time 54.62 seconds
Started Feb 18 01:47:53 PM PST 24
Finished Feb 18 01:48:54 PM PST 24
Peak memory 199584 kb
Host smart-f261fc9d-26bb-4771-8b11-5f2f1520a7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566123861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2566123861
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.371081607
Short name T223
Test name
Test status
Simulation time 14028898 ps
CPU time 0.57 seconds
Started Feb 18 01:48:05 PM PST 24
Finished Feb 18 01:48:12 PM PST 24
Peak memory 193928 kb
Host smart-e66ab419-4249-4a14-b4ab-25c396b03e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371081607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.371081607
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.4290067741
Short name T23
Test name
Test status
Simulation time 697804983 ps
CPU time 24.32 seconds
Started Feb 18 01:47:59 PM PST 24
Finished Feb 18 01:48:29 PM PST 24
Peak memory 215840 kb
Host smart-1dd13729-70a6-47c5-9dde-a4ed6a625380
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290067741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.4290067741
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2486067981
Short name T559
Test name
Test status
Simulation time 1200136819 ps
CPU time 57.58 seconds
Started Feb 18 01:47:59 PM PST 24
Finished Feb 18 01:49:03 PM PST 24
Peak memory 199528 kb
Host smart-59dea2cf-4f60-4f3e-baed-1420dcef954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486067981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2486067981
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1585903934
Short name T386
Test name
Test status
Simulation time 932507290 ps
CPU time 24.05 seconds
Started Feb 18 01:47:59 PM PST 24
Finished Feb 18 01:48:29 PM PST 24
Peak memory 199472 kb
Host smart-7c2763ed-2161-4d85-9834-80b6218a363f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585903934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1585903934
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.71679710
Short name T271
Test name
Test status
Simulation time 73694519843 ps
CPU time 66.54 seconds
Started Feb 18 01:48:07 PM PST 24
Finished Feb 18 01:49:19 PM PST 24
Peak memory 199672 kb
Host smart-f6607d98-6f6f-40a3-9843-36e05366cc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71679710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.71679710
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1933665583
Short name T521
Test name
Test status
Simulation time 185573637 ps
CPU time 2.78 seconds
Started Feb 18 01:48:00 PM PST 24
Finished Feb 18 01:48:10 PM PST 24
Peak memory 199472 kb
Host smart-361abc5f-b424-4b12-930c-2695be4ac918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933665583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1933665583
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3847625351
Short name T258
Test name
Test status
Simulation time 314080247 ps
CPU time 4.47 seconds
Started Feb 18 01:47:57 PM PST 24
Finished Feb 18 01:48:08 PM PST 24
Peak memory 199432 kb
Host smart-d7e90363-2c00-4627-98a6-c7e8c7ab5a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847625351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3847625351
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2425687314
Short name T534
Test name
Test status
Simulation time 14444806595 ps
CPU time 371.3 seconds
Started Feb 18 01:47:59 PM PST 24
Finished Feb 18 01:54:17 PM PST 24
Peak memory 215928 kb
Host smart-a2757dfb-a026-44cc-8ff0-bd9b1d303af7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425687314 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2425687314
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1376045661
Short name T179
Test name
Test status
Simulation time 247316967 ps
CPU time 0.88 seconds
Started Feb 18 01:47:54 PM PST 24
Finished Feb 18 01:48:01 PM PST 24
Peak memory 196520 kb
Host smart-0173b81d-9552-4aa1-a0ec-36318caf0d32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376045661 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1376045661
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2209382082
Short name T544
Test name
Test status
Simulation time 104768122546 ps
CPU time 411.16 seconds
Started Feb 18 01:48:05 PM PST 24
Finished Feb 18 01:55:03 PM PST 24
Peak memory 199520 kb
Host smart-da18c63d-810c-45d4-80dc-c9eb276381da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209382082 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.2209382082
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.11462246
Short name T301
Test name
Test status
Simulation time 31276486687 ps
CPU time 40.63 seconds
Started Feb 18 01:48:00 PM PST 24
Finished Feb 18 01:48:48 PM PST 24
Peak memory 199560 kb
Host smart-b4497f63-3bb3-4d86-9be0-c5c623eaf0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11462246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.11462246
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3048209610
Short name T487
Test name
Test status
Simulation time 14642695 ps
CPU time 0.61 seconds
Started Feb 18 01:48:04 PM PST 24
Finished Feb 18 01:48:12 PM PST 24
Peak memory 193688 kb
Host smart-f923b6e5-76d1-46b3-aa67-e6cc77ed3c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048209610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3048209610
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3919436473
Short name T576
Test name
Test status
Simulation time 2470924635 ps
CPU time 21.48 seconds
Started Feb 18 01:48:02 PM PST 24
Finished Feb 18 01:48:30 PM PST 24
Peak memory 220084 kb
Host smart-3e2e3400-9ab4-46f2-8550-c9d932a8dae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919436473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3919436473
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2490742289
Short name T241
Test name
Test status
Simulation time 179180261 ps
CPU time 3.75 seconds
Started Feb 18 01:48:04 PM PST 24
Finished Feb 18 01:48:14 PM PST 24
Peak memory 199400 kb
Host smart-0c69e6f2-fb21-486c-96e9-f2c7f5f2cfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490742289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2490742289
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2252792957
Short name T449
Test name
Test status
Simulation time 617099604 ps
CPU time 9.61 seconds
Started Feb 18 01:48:00 PM PST 24
Finished Feb 18 01:48:16 PM PST 24
Peak memory 199552 kb
Host smart-f747ce0e-dffc-406e-bd02-c9ee46267efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252792957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2252792957
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1832905109
Short name T347
Test name
Test status
Simulation time 57727128 ps
CPU time 0.81 seconds
Started Feb 18 01:48:02 PM PST 24
Finished Feb 18 01:48:09 PM PST 24
Peak memory 196500 kb
Host smart-21eb8077-15ed-45a7-b049-2769a16bdc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832905109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1832905109
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4077190305
Short name T76
Test name
Test status
Simulation time 18894233461 ps
CPU time 63.78 seconds
Started Feb 18 01:48:01 PM PST 24
Finished Feb 18 01:49:12 PM PST 24
Peak memory 199608 kb
Host smart-ea3d190c-dcb1-41b5-b60c-c089fd9d94e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077190305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4077190305
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3096174206
Short name T321
Test name
Test status
Simulation time 3406771782 ps
CPU time 3.68 seconds
Started Feb 18 01:48:03 PM PST 24
Finished Feb 18 01:48:13 PM PST 24
Peak memory 199520 kb
Host smart-e8cbd414-c29b-459a-92ae-b9e439cf4053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096174206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3096174206
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2580163862
Short name T73
Test name
Test status
Simulation time 157004539839 ps
CPU time 913.2 seconds
Started Feb 18 01:48:11 PM PST 24
Finished Feb 18 02:03:28 PM PST 24
Peak memory 199592 kb
Host smart-5cb4d06e-c60f-42c3-8ae7-31c308421185
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580163862 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2580163862
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2796856221
Short name T331
Test name
Test status
Simulation time 98403569 ps
CPU time 0.89 seconds
Started Feb 18 01:48:03 PM PST 24
Finished Feb 18 01:48:10 PM PST 24
Peak memory 196628 kb
Host smart-e49e5f61-c704-4876-ad2a-49bf6da3f819
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796856221 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2796856221
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3476406435
Short name T163
Test name
Test status
Simulation time 70063929377 ps
CPU time 378.97 seconds
Started Feb 18 01:48:09 PM PST 24
Finished Feb 18 01:54:32 PM PST 24
Peak memory 199556 kb
Host smart-81987309-3774-4a5a-b226-6584a2d48b2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476406435 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.3476406435
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2920678447
Short name T127
Test name
Test status
Simulation time 7485881372 ps
CPU time 45.37 seconds
Started Feb 18 01:48:09 PM PST 24
Finished Feb 18 01:48:59 PM PST 24
Peak memory 199644 kb
Host smart-35381199-6d19-4f62-a8ab-1336fd8f6309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920678447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2920678447
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3339256281
Short name T297
Test name
Test status
Simulation time 20944466 ps
CPU time 0.62 seconds
Started Feb 18 01:48:02 PM PST 24
Finished Feb 18 01:48:09 PM PST 24
Peak memory 193728 kb
Host smart-d4064910-c927-4202-9985-09f47ef9f2c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339256281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3339256281
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.441540613
Short name T498
Test name
Test status
Simulation time 1353799746 ps
CPU time 22.27 seconds
Started Feb 18 01:48:10 PM PST 24
Finished Feb 18 01:48:36 PM PST 24
Peak memory 207688 kb
Host smart-efefc569-4d9a-4529-9086-0019b39cebec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441540613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.441540613
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.472718632
Short name T399
Test name
Test status
Simulation time 7336780165 ps
CPU time 55.42 seconds
Started Feb 18 01:48:11 PM PST 24
Finished Feb 18 01:49:10 PM PST 24
Peak memory 199540 kb
Host smart-e13083e7-187c-4d36-8558-999e906a90b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472718632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.472718632
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2876535939
Short name T280
Test name
Test status
Simulation time 2512111142 ps
CPU time 65.26 seconds
Started Feb 18 01:48:03 PM PST 24
Finished Feb 18 01:49:15 PM PST 24
Peak memory 199544 kb
Host smart-885955fa-2716-4fa9-a4f8-5ac1a4c6946d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876535939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2876535939
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.894540149
Short name T550
Test name
Test status
Simulation time 4540086379 ps
CPU time 59.63 seconds
Started Feb 18 01:48:03 PM PST 24
Finished Feb 18 01:49:09 PM PST 24
Peak memory 199544 kb
Host smart-67cb9d52-982d-4a18-9c30-c1f9c4fa565f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894540149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.894540149
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3136553259
Short name T1
Test name
Test status
Simulation time 38227506751 ps
CPU time 82.58 seconds
Started Feb 18 01:48:10 PM PST 24
Finished Feb 18 01:49:37 PM PST 24
Peak memory 199544 kb
Host smart-cb6cc328-a730-47ad-8207-2ea26a85c953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136553259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3136553259
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3289123509
Short name T327
Test name
Test status
Simulation time 411784104 ps
CPU time 4.57 seconds
Started Feb 18 01:48:02 PM PST 24
Finished Feb 18 01:48:13 PM PST 24
Peak memory 199476 kb
Host smart-cb4b6d0c-7021-4a3e-b3cf-f7c676e0114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289123509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3289123509
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2486956189
Short name T351
Test name
Test status
Simulation time 44361264395 ps
CPU time 1042.69 seconds
Started Feb 18 01:48:03 PM PST 24
Finished Feb 18 02:05:32 PM PST 24
Peak memory 215668 kb
Host smart-7a848a21-f32a-499c-92a2-268fe1c8440e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486956189 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2486956189
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2038848396
Short name T295
Test name
Test status
Simulation time 27537816 ps
CPU time 0.97 seconds
Started Feb 18 01:48:04 PM PST 24
Finished Feb 18 01:48:12 PM PST 24
Peak memory 197384 kb
Host smart-f59d2985-0fee-4aaa-bfd8-c2ddea130d41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038848396 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2038848396
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4073875206
Short name T418
Test name
Test status
Simulation time 10539058508 ps
CPU time 84.28 seconds
Started Feb 18 01:48:10 PM PST 24
Finished Feb 18 01:49:39 PM PST 24
Peak memory 199536 kb
Host smart-d02715e5-449f-458c-9dd5-9404e950e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073875206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4073875206
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3358834275
Short name T312
Test name
Test status
Simulation time 11464083 ps
CPU time 0.57 seconds
Started Feb 18 01:48:09 PM PST 24
Finished Feb 18 01:48:14 PM PST 24
Peak memory 193952 kb
Host smart-f7cd83ce-53fd-4adc-8935-d378262186f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358834275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3358834275
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3442184023
Short name T198
Test name
Test status
Simulation time 626768527 ps
CPU time 21.53 seconds
Started Feb 18 01:48:09 PM PST 24
Finished Feb 18 01:48:35 PM PST 24
Peak memory 221024 kb
Host smart-866df6ea-730e-47a5-afcb-eb439b90d3da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3442184023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3442184023
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1049087955
Short name T293
Test name
Test status
Simulation time 7075891052 ps
CPU time 34.57 seconds
Started Feb 18 01:48:09 PM PST 24
Finished Feb 18 01:48:47 PM PST 24
Peak memory 199616 kb
Host smart-1359cb09-3f9b-457a-ae25-a1661d70e97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049087955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1049087955
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1743235757
Short name T51
Test name
Test status
Simulation time 464924107 ps
CPU time 5.89 seconds
Started Feb 18 01:48:09 PM PST 24
Finished Feb 18 01:48:19 PM PST 24
Peak memory 199088 kb
Host smart-f900f1cc-0af2-4a89-bc16-5ad6b4bbb6d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743235757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1743235757
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.4130575844
Short name T454
Test name
Test status
Simulation time 16074657830 ps
CPU time 45.31 seconds
Started Feb 18 01:48:04 PM PST 24
Finished Feb 18 01:48:56 PM PST 24
Peak memory 199500 kb
Host smart-63824463-b396-4bd5-ad37-868a54c3892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130575844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.4130575844
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_smoke.1450923230
Short name T193
Test name
Test status
Simulation time 103221569 ps
CPU time 1.54 seconds
Started Feb 18 01:48:03 PM PST 24
Finished Feb 18 01:48:11 PM PST 24
Peak memory 198116 kb
Host smart-59c6f884-1aa2-4eab-82c7-89bd78267ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450923230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1450923230
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.90344354
Short name T426
Test name
Test status
Simulation time 174404653438 ps
CPU time 552.4 seconds
Started Feb 18 01:48:01 PM PST 24
Finished Feb 18 01:57:20 PM PST 24
Peak memory 234236 kb
Host smart-36fc8c47-84e3-4abb-a5e1-f48aec74f19a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90344354 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.90344354
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3411438453
Short name T185
Test name
Test status
Simulation time 216663663 ps
CPU time 1.22 seconds
Started Feb 18 01:48:03 PM PST 24
Finished Feb 18 01:48:11 PM PST 24
Peak memory 197980 kb
Host smart-82a870d5-39e3-4bf6-9bc9-d8ba9dba0553
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411438453 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3411438453
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1754539043
Short name T316
Test name
Test status
Simulation time 110072674753 ps
CPU time 472.99 seconds
Started Feb 18 01:48:04 PM PST 24
Finished Feb 18 01:56:04 PM PST 24
Peak memory 199524 kb
Host smart-1163aa28-98ff-44c6-8f9b-c166da5ab1b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754539043 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.1754539043
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3059187606
Short name T322
Test name
Test status
Simulation time 697871076 ps
CPU time 5.84 seconds
Started Feb 18 01:48:09 PM PST 24
Finished Feb 18 01:48:19 PM PST 24
Peak memory 199564 kb
Host smart-240f644b-ff1b-4459-ad11-9ab0725a3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059187606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3059187606
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3248934744
Short name T535
Test name
Test status
Simulation time 38503361 ps
CPU time 0.55 seconds
Started Feb 18 01:48:10 PM PST 24
Finished Feb 18 01:48:14 PM PST 24
Peak memory 193780 kb
Host smart-29a64a2f-32ec-4a8e-aaf1-0e995606d666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248934744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3248934744
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.626455295
Short name T357
Test name
Test status
Simulation time 814962967 ps
CPU time 16.07 seconds
Started Feb 18 01:48:10 PM PST 24
Finished Feb 18 01:48:30 PM PST 24
Peak memory 233980 kb
Host smart-ba9efc34-8ac0-4222-a8fe-c1fe07878e76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626455295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.626455295
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.4237411299
Short name T473
Test name
Test status
Simulation time 1050137319 ps
CPU time 14.21 seconds
Started Feb 18 01:48:13 PM PST 24
Finished Feb 18 01:48:31 PM PST 24
Peak memory 199428 kb
Host smart-d4c64611-5ee6-40b0-8f06-9732f99503e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237411299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4237411299
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3358739774
Short name T38
Test name
Test status
Simulation time 2411683267 ps
CPU time 19.01 seconds
Started Feb 18 01:48:09 PM PST 24
Finished Feb 18 01:48:32 PM PST 24
Peak memory 199560 kb
Host smart-9bf1344b-c667-40b3-aa8d-153cb624d887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358739774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3358739774
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1611284379
Short name T585
Test name
Test status
Simulation time 65644653404 ps
CPU time 217.64 seconds
Started Feb 18 01:48:12 PM PST 24
Finished Feb 18 01:51:53 PM PST 24
Peak memory 199568 kb
Host smart-ec1fa392-31da-4077-80a7-b8beb8edafe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611284379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1611284379
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4132305498
Short name T507
Test name
Test status
Simulation time 753008798 ps
CPU time 38.99 seconds
Started Feb 18 01:48:08 PM PST 24
Finished Feb 18 01:48:51 PM PST 24
Peak memory 199536 kb
Host smart-76e5c081-693a-427f-af41-3039043dcc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132305498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4132305498
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3311123050
Short name T148
Test name
Test status
Simulation time 535992034 ps
CPU time 3.05 seconds
Started Feb 18 01:48:10 PM PST 24
Finished Feb 18 01:48:18 PM PST 24
Peak memory 199396 kb
Host smart-53e4f86d-fc17-42f4-9a03-f7e82f06ec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311123050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3311123050
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.680939683
Short name T48
Test name
Test status
Simulation time 10257041359 ps
CPU time 488.99 seconds
Started Feb 18 01:48:18 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 228692 kb
Host smart-c2174fb8-0a1b-49cb-86e1-f1cddb34623c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680939683 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.680939683
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3064527490
Short name T551
Test name
Test status
Simulation time 109580568 ps
CPU time 1.22 seconds
Started Feb 18 01:48:10 PM PST 24
Finished Feb 18 01:48:16 PM PST 24
Peak memory 198348 kb
Host smart-6530ba85-a96f-4b1b-ad9f-8436a7cc2241
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064527490 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3064527490
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2118322061
Short name T566
Test name
Test status
Simulation time 14840597360 ps
CPU time 351.12 seconds
Started Feb 18 01:48:09 PM PST 24
Finished Feb 18 01:54:04 PM PST 24
Peak memory 199532 kb
Host smart-22328d58-fdf6-4cdd-b41a-e92fd1fe5748
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118322061 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.2118322061
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.4191102878
Short name T530
Test name
Test status
Simulation time 15105966782 ps
CPU time 63 seconds
Started Feb 18 01:48:10 PM PST 24
Finished Feb 18 01:49:17 PM PST 24
Peak memory 199612 kb
Host smart-e6389b4d-7d1f-46f7-9353-5e861c073b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191102878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.4191102878
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.4065883903
Short name T303
Test name
Test status
Simulation time 39436001 ps
CPU time 0.57 seconds
Started Feb 18 01:48:17 PM PST 24
Finished Feb 18 01:48:19 PM PST 24
Peak memory 193940 kb
Host smart-ded007d9-85ca-40fa-963e-b1691c90a487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065883903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4065883903
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2501161927
Short name T501
Test name
Test status
Simulation time 7617432541 ps
CPU time 26.93 seconds
Started Feb 18 01:48:10 PM PST 24
Finished Feb 18 01:48:41 PM PST 24
Peak memory 215912 kb
Host smart-c2c998f4-9e0d-4fa1-b138-2c2fbc442378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2501161927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2501161927
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3144480974
Short name T461
Test name
Test status
Simulation time 2497190728 ps
CPU time 46.64 seconds
Started Feb 18 01:48:15 PM PST 24
Finished Feb 18 01:49:04 PM PST 24
Peak memory 199556 kb
Host smart-3ddf351d-614e-4c46-9e55-2184814303e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144480974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3144480974
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3682097894
Short name T375
Test name
Test status
Simulation time 1080351636 ps
CPU time 53.99 seconds
Started Feb 18 01:48:17 PM PST 24
Finished Feb 18 01:49:13 PM PST 24
Peak memory 199472 kb
Host smart-e1fbdbc7-ac74-4d84-b719-c99f201033c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682097894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3682097894
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.665205522
Short name T266
Test name
Test status
Simulation time 1721897559 ps
CPU time 40.57 seconds
Started Feb 18 01:48:17 PM PST 24
Finished Feb 18 01:48:59 PM PST 24
Peak memory 199340 kb
Host smart-b299cf63-a7d2-4a9a-8bb9-a514d9570ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665205522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.665205522
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3767227273
Short name T298
Test name
Test status
Simulation time 11759277286 ps
CPU time 55.01 seconds
Started Feb 18 01:48:08 PM PST 24
Finished Feb 18 01:49:08 PM PST 24
Peak memory 199552 kb
Host smart-848acdce-7373-4c55-b95d-33f301ced26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767227273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3767227273
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2423520407
Short name T394
Test name
Test status
Simulation time 185854720 ps
CPU time 2.31 seconds
Started Feb 18 01:48:09 PM PST 24
Finished Feb 18 01:48:16 PM PST 24
Peak memory 199252 kb
Host smart-dc1adaed-fcdf-4518-b278-52971d4ee5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423520407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2423520407
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3567190241
Short name T66
Test name
Test status
Simulation time 27935803589 ps
CPU time 394.89 seconds
Started Feb 18 01:48:15 PM PST 24
Finished Feb 18 01:54:52 PM PST 24
Peak memory 199652 kb
Host smart-21c051e0-cc51-47ea-939f-0ef4e9526bca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567190241 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3567190241
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1365356126
Short name T74
Test name
Test status
Simulation time 41553020 ps
CPU time 1.02 seconds
Started Feb 18 01:48:18 PM PST 24
Finished Feb 18 01:48:21 PM PST 24
Peak memory 197176 kb
Host smart-4fd26032-9218-43b2-acd4-779ed175ce85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365356126 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1365356126
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.516445210
Short name T162
Test name
Test status
Simulation time 98351071509 ps
CPU time 484.51 seconds
Started Feb 18 01:48:17 PM PST 24
Finished Feb 18 01:56:24 PM PST 24
Peak memory 199552 kb
Host smart-b0d945e5-5ff2-4882-89e1-5bacd9e1f345
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516445210 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.hmac_test_sha_vectors.516445210
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1163021844
Short name T306
Test name
Test status
Simulation time 532569161 ps
CPU time 6.86 seconds
Started Feb 18 01:48:14 PM PST 24
Finished Feb 18 01:48:24 PM PST 24
Peak memory 199568 kb
Host smart-4f76147c-10ff-49cc-8b93-14431971b416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163021844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1163021844
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3139190588
Short name T358
Test name
Test status
Simulation time 13631722 ps
CPU time 0.59 seconds
Started Feb 18 01:48:25 PM PST 24
Finished Feb 18 01:48:26 PM PST 24
Peak memory 193672 kb
Host smart-5818685c-4239-49bc-939c-35a566609cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139190588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3139190588
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2296278969
Short name T397
Test name
Test status
Simulation time 1377805485 ps
CPU time 10.13 seconds
Started Feb 18 01:48:17 PM PST 24
Finished Feb 18 01:48:29 PM PST 24
Peak memory 207744 kb
Host smart-7bbe2eaf-9aac-478f-a145-ad9cb2d0e260
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296278969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2296278969
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2987253213
Short name T320
Test name
Test status
Simulation time 3854762931 ps
CPU time 44.82 seconds
Started Feb 18 01:48:19 PM PST 24
Finished Feb 18 01:49:05 PM PST 24
Peak memory 199500 kb
Host smart-9bfeaed7-58cd-4be8-a08e-85d19fb92769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987253213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2987253213
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2220945082
Short name T542
Test name
Test status
Simulation time 9601368969 ps
CPU time 116.16 seconds
Started Feb 18 01:48:25 PM PST 24
Finished Feb 18 01:50:23 PM PST 24
Peak memory 199556 kb
Host smart-28a34718-bddf-4843-baab-17b2eefe08cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220945082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2220945082
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1371649570
Short name T168
Test name
Test status
Simulation time 16408975138 ps
CPU time 120.29 seconds
Started Feb 18 01:48:24 PM PST 24
Finished Feb 18 01:50:25 PM PST 24
Peak memory 199584 kb
Host smart-90d6d2e3-bec9-4ba7-b7e5-e931979fe448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371649570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1371649570
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3566085740
Short name T36
Test name
Test status
Simulation time 10179751523 ps
CPU time 39.08 seconds
Started Feb 18 01:48:16 PM PST 24
Finished Feb 18 01:48:57 PM PST 24
Peak memory 199620 kb
Host smart-3a1c3316-0b4f-4df2-9885-76c5ec849ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566085740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3566085740
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3813386763
Short name T150
Test name
Test status
Simulation time 389218935 ps
CPU time 3.81 seconds
Started Feb 18 01:48:19 PM PST 24
Finished Feb 18 01:48:24 PM PST 24
Peak memory 199460 kb
Host smart-5770fe12-002d-45ba-b571-5d5bca47bae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813386763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3813386763
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1906641631
Short name T488
Test name
Test status
Simulation time 252546860801 ps
CPU time 1389.53 seconds
Started Feb 18 01:48:15 PM PST 24
Finished Feb 18 02:11:27 PM PST 24
Peak memory 240540 kb
Host smart-663ad0b5-be71-4ce0-9dff-2a0dc50bab4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906641631 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1906641631
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2730663527
Short name T317
Test name
Test status
Simulation time 83416285 ps
CPU time 0.94 seconds
Started Feb 18 01:48:16 PM PST 24
Finished Feb 18 01:48:19 PM PST 24
Peak memory 196720 kb
Host smart-4be7aab3-be16-44ec-8afa-d9e2d0aa75e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730663527 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2730663527
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.662782962
Short name T337
Test name
Test status
Simulation time 5834379366 ps
CPU time 54.69 seconds
Started Feb 18 01:48:16 PM PST 24
Finished Feb 18 01:49:13 PM PST 24
Peak memory 199572 kb
Host smart-9679e807-0fe6-498a-94b0-a60fb475c1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662782962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.662782962
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1937299653
Short name T25
Test name
Test status
Simulation time 33895533 ps
CPU time 0.55 seconds
Started Feb 18 01:45:33 PM PST 24
Finished Feb 18 01:45:37 PM PST 24
Peak memory 193760 kb
Host smart-dbdc12b2-9c46-4015-a20f-6a47e3541784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937299653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1937299653
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2038297735
Short name T443
Test name
Test status
Simulation time 2208551708 ps
CPU time 36.96 seconds
Started Feb 18 01:45:37 PM PST 24
Finished Feb 18 01:46:21 PM PST 24
Peak memory 223940 kb
Host smart-8d9aca57-0d1a-4da7-9430-108b22b2128d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038297735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2038297735
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1586271316
Short name T47
Test name
Test status
Simulation time 1574059690 ps
CPU time 71.59 seconds
Started Feb 18 01:45:32 PM PST 24
Finished Feb 18 01:46:47 PM PST 24
Peak memory 199524 kb
Host smart-e60212aa-f8d6-4c21-8f18-b01215ab89e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586271316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1586271316
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.4111800790
Short name T520
Test name
Test status
Simulation time 2423296500 ps
CPU time 34.59 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:46:17 PM PST 24
Peak memory 199552 kb
Host smart-22707b58-bd25-4d40-9536-23ba919f6ad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4111800790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.4111800790
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1939500372
Short name T363
Test name
Test status
Simulation time 30673773958 ps
CPU time 133.26 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:47:53 PM PST 24
Peak memory 199652 kb
Host smart-bd997cdd-3d53-4797-9198-5f1a987dcf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939500372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1939500372
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2015909730
Short name T505
Test name
Test status
Simulation time 2231301287 ps
CPU time 59.84 seconds
Started Feb 18 01:45:38 PM PST 24
Finished Feb 18 01:46:45 PM PST 24
Peak memory 199636 kb
Host smart-bd67fc3a-d6e4-4d59-98f6-1d63a6f8bd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015909730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2015909730
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2359959435
Short name T308
Test name
Test status
Simulation time 744112828 ps
CPU time 2.46 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:45:45 PM PST 24
Peak memory 199452 kb
Host smart-c94b1f7a-1013-419e-8f3c-ca07ed89fe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359959435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2359959435
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1301997288
Short name T346
Test name
Test status
Simulation time 10962574607 ps
CPU time 535.44 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:54:37 PM PST 24
Peak memory 199548 kb
Host smart-5902119c-b92b-4524-8919-3fbbd6ff5403
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301997288 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1301997288
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3916606661
Short name T151
Test name
Test status
Simulation time 631110958 ps
CPU time 1.1 seconds
Started Feb 18 01:45:34 PM PST 24
Finished Feb 18 01:45:40 PM PST 24
Peak memory 197948 kb
Host smart-b077b457-a3ae-4b21-b801-060fa4693f27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916606661 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3916606661
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1538137594
Short name T289
Test name
Test status
Simulation time 19146862420 ps
CPU time 388.47 seconds
Started Feb 18 01:45:31 PM PST 24
Finished Feb 18 01:52:03 PM PST 24
Peak memory 199560 kb
Host smart-f8843bad-b306-4d54-8bd5-c3fd6630a285
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538137594 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.1538137594
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.901816211
Short name T192
Test name
Test status
Simulation time 4011936874 ps
CPU time 17.83 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:45:59 PM PST 24
Peak memory 199560 kb
Host smart-8b5a0614-fdad-46ea-8199-7ffe89b7b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901816211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.901816211
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.31814431
Short name T6
Test name
Test status
Simulation time 688003305474 ps
CPU time 3164.14 seconds
Started Feb 18 01:48:26 PM PST 24
Finished Feb 18 02:41:12 PM PST 24
Peak memory 265276 kb
Host smart-fbe33394-4842-4982-a80f-4c515ef63f29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31814431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.31814431
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2276620438
Short name T430
Test name
Test status
Simulation time 24036783 ps
CPU time 0.56 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:45:43 PM PST 24
Peak memory 193900 kb
Host smart-c416a499-2c02-4eed-820a-7b1407926546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276620438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2276620438
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4266166724
Short name T344
Test name
Test status
Simulation time 1804132823 ps
CPU time 64.47 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:46:46 PM PST 24
Peak memory 232300 kb
Host smart-edf65524-6624-43da-8f30-b90211aca73c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266166724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4266166724
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.4114875315
Short name T365
Test name
Test status
Simulation time 629755255 ps
CPU time 28.08 seconds
Started Feb 18 01:45:42 PM PST 24
Finished Feb 18 01:46:15 PM PST 24
Peak memory 199556 kb
Host smart-e06d54c2-9e0e-4ff2-9fc8-bab5d2b6ca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114875315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4114875315
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3855680441
Short name T29
Test name
Test status
Simulation time 9350065861 ps
CPU time 130.34 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:47:52 PM PST 24
Peak memory 199584 kb
Host smart-96230649-fdec-4e39-a863-5df597d36005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3855680441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3855680441
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3926486626
Short name T54
Test name
Test status
Simulation time 813439434 ps
CPU time 39.93 seconds
Started Feb 18 01:45:33 PM PST 24
Finished Feb 18 01:46:16 PM PST 24
Peak memory 199536 kb
Host smart-cdcfc5e8-e2c8-4fca-b5a3-7f93bf5c5f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926486626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3926486626
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3981465934
Short name T242
Test name
Test status
Simulation time 21790169039 ps
CPU time 72.86 seconds
Started Feb 18 01:45:37 PM PST 24
Finished Feb 18 01:46:57 PM PST 24
Peak memory 199556 kb
Host smart-5a5f4528-410d-4d01-97b4-f96de8dfd700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981465934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3981465934
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3509334455
Short name T206
Test name
Test status
Simulation time 159793419 ps
CPU time 3.83 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:45:45 PM PST 24
Peak memory 199560 kb
Host smart-d68fec73-560c-46f2-a4b7-a9942379054c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509334455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3509334455
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.710185895
Short name T528
Test name
Test status
Simulation time 2821540481 ps
CPU time 139.29 seconds
Started Feb 18 01:45:33 PM PST 24
Finished Feb 18 01:47:56 PM PST 24
Peak memory 199620 kb
Host smart-7b5fe6f0-3fa9-4d97-bab3-655009ae1213
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710185895 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.710185895
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.263381721
Short name T564
Test name
Test status
Simulation time 48421792 ps
CPU time 0.95 seconds
Started Feb 18 01:45:42 PM PST 24
Finished Feb 18 01:45:48 PM PST 24
Peak memory 196996 kb
Host smart-c5cf1975-4fe0-4bee-b17f-7893e13bd986
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263381721 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.263381721
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3039685370
Short name T102
Test name
Test status
Simulation time 22240565213 ps
CPU time 360.3 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:51:40 PM PST 24
Peak memory 199600 kb
Host smart-1c9ea2f6-71c5-4d96-85fb-baee8b22f31b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039685370 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.3039685370
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1119467699
Short name T545
Test name
Test status
Simulation time 119353431 ps
CPU time 6.39 seconds
Started Feb 18 01:45:33 PM PST 24
Finished Feb 18 01:45:44 PM PST 24
Peak memory 199544 kb
Host smart-8c1254ce-d960-4e33-928f-b2ed60f86178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119467699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1119467699
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2211202228
Short name T183
Test name
Test status
Simulation time 12184994 ps
CPU time 0.59 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:45:41 PM PST 24
Peak memory 193744 kb
Host smart-d6e57ceb-d01b-4bd8-9523-d3a16c39b6fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211202228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2211202228
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3417389389
Short name T30
Test name
Test status
Simulation time 720288783 ps
CPU time 26.16 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:46:06 PM PST 24
Peak memory 224168 kb
Host smart-c782a613-49b5-43e2-8bfa-4c434aeb4331
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417389389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3417389389
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1931990842
Short name T257
Test name
Test status
Simulation time 811949591 ps
CPU time 15.01 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:45:56 PM PST 24
Peak memory 199628 kb
Host smart-4de4012e-e04b-43cf-bbf1-526834ae2224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931990842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1931990842
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1014465764
Short name T326
Test name
Test status
Simulation time 1833066311 ps
CPU time 25.68 seconds
Started Feb 18 01:45:37 PM PST 24
Finished Feb 18 01:46:09 PM PST 24
Peak memory 199532 kb
Host smart-8562f847-6018-4849-a55f-56eab83a9351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014465764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1014465764
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2944705856
Short name T101
Test name
Test status
Simulation time 16429190375 ps
CPU time 141 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:48:02 PM PST 24
Peak memory 199652 kb
Host smart-b8be59cd-f188-4a7a-a8c5-0bc30781ed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944705856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2944705856
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.711766629
Short name T472
Test name
Test status
Simulation time 50902383 ps
CPU time 2.45 seconds
Started Feb 18 01:45:34 PM PST 24
Finished Feb 18 01:45:41 PM PST 24
Peak memory 199524 kb
Host smart-94f7e373-f047-4d4d-a7f1-1eacf80aff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711766629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.711766629
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2358735882
Short name T395
Test name
Test status
Simulation time 27123960 ps
CPU time 0.92 seconds
Started Feb 18 01:45:37 PM PST 24
Finished Feb 18 01:45:45 PM PST 24
Peak memory 197336 kb
Host smart-0d37f4d5-9ad1-455c-9f8f-c72537a95fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358735882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2358735882
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.280370305
Short name T574
Test name
Test status
Simulation time 234928266604 ps
CPU time 796.86 seconds
Started Feb 18 01:45:44 PM PST 24
Finished Feb 18 01:59:05 PM PST 24
Peak memory 215952 kb
Host smart-0a6720da-39cf-4b95-a746-8c1bd50e8858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280370305 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.280370305
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.4195237086
Short name T511
Test name
Test status
Simulation time 205982898 ps
CPU time 0.99 seconds
Started Feb 18 01:45:37 PM PST 24
Finished Feb 18 01:45:45 PM PST 24
Peak memory 198144 kb
Host smart-cf7eeb6e-ab73-4112-aaf1-179c4bc30046
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195237086 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.4195237086
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3904312974
Short name T479
Test name
Test status
Simulation time 31540861258 ps
CPU time 379.08 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:52:01 PM PST 24
Peak memory 199516 kb
Host smart-e6d20d5f-b026-4d83-a82b-0464d834ee31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904312974 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.3904312974
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2048505495
Short name T226
Test name
Test status
Simulation time 2410573215 ps
CPU time 85.01 seconds
Started Feb 18 01:45:39 PM PST 24
Finished Feb 18 01:47:11 PM PST 24
Peak memory 199612 kb
Host smart-33c07498-3e01-4bc2-b668-10bfb867257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048505495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2048505495
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.587134856
Short name T243
Test name
Test status
Simulation time 11137464 ps
CPU time 0.57 seconds
Started Feb 18 01:45:38 PM PST 24
Finished Feb 18 01:45:46 PM PST 24
Peak memory 193944 kb
Host smart-113fdfc3-5ea0-4f19-b798-23da8cdc613a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587134856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.587134856
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.614848097
Short name T523
Test name
Test status
Simulation time 511882859 ps
CPU time 13.59 seconds
Started Feb 18 01:45:41 PM PST 24
Finished Feb 18 01:46:01 PM PST 24
Peak memory 199480 kb
Host smart-7def913d-2b65-4a12-978e-bab996b95f92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614848097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.614848097
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2118505659
Short name T356
Test name
Test status
Simulation time 484441821 ps
CPU time 21.98 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:46:01 PM PST 24
Peak memory 199476 kb
Host smart-c415fe0a-157b-45c9-89bc-7734425b6170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118505659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2118505659
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2828550357
Short name T210
Test name
Test status
Simulation time 985823623 ps
CPU time 48.55 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:46:31 PM PST 24
Peak memory 199472 kb
Host smart-209e30d3-4ba8-43e8-96e6-8f5b8c448b21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828550357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2828550357
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1570592695
Short name T518
Test name
Test status
Simulation time 14591833720 ps
CPU time 69.18 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:46:50 PM PST 24
Peak memory 199552 kb
Host smart-7e1847ea-f955-4dea-88fc-aaa3812745dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570592695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1570592695
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.223830267
Short name T416
Test name
Test status
Simulation time 6853333259 ps
CPU time 60.47 seconds
Started Feb 18 01:45:37 PM PST 24
Finished Feb 18 01:46:44 PM PST 24
Peak memory 199564 kb
Host smart-e328e7ae-d3b2-4a65-a929-1291ba9737c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223830267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.223830267
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3931968408
Short name T141
Test name
Test status
Simulation time 707078934 ps
CPU time 3.76 seconds
Started Feb 18 01:45:44 PM PST 24
Finished Feb 18 01:45:52 PM PST 24
Peak memory 199112 kb
Host smart-7ac03b3d-3edc-44da-af09-fe1fb36e7e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931968408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3931968408
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.307134712
Short name T115
Test name
Test status
Simulation time 53675205321 ps
CPU time 663.15 seconds
Started Feb 18 01:45:41 PM PST 24
Finished Feb 18 01:56:50 PM PST 24
Peak memory 227628 kb
Host smart-53645804-c281-4e4d-9988-7a2d04024f55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307134712 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.307134712
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1123807298
Short name T402
Test name
Test status
Simulation time 110346037 ps
CPU time 1.04 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:45:43 PM PST 24
Peak memory 199140 kb
Host smart-ec21a602-dfb8-43a2-b83b-4220499ba448
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123807298 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1123807298
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.555373656
Short name T287
Test name
Test status
Simulation time 132919287251 ps
CPU time 508.1 seconds
Started Feb 18 01:45:39 PM PST 24
Finished Feb 18 01:54:14 PM PST 24
Peak memory 199492 kb
Host smart-331621cc-ba70-4c45-87cc-ec1224a3c7c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555373656 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.hmac_test_sha_vectors.555373656
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2057328257
Short name T589
Test name
Test status
Simulation time 2584338019 ps
CPU time 49.4 seconds
Started Feb 18 01:45:41 PM PST 24
Finished Feb 18 01:46:36 PM PST 24
Peak memory 199520 kb
Host smart-b984ff99-c36c-487c-bd06-976c02f47e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057328257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2057328257
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.63804374
Short name T415
Test name
Test status
Simulation time 48207121 ps
CPU time 0.59 seconds
Started Feb 18 01:45:34 PM PST 24
Finished Feb 18 01:45:39 PM PST 24
Peak memory 193956 kb
Host smart-01d5d693-d06e-4980-8a5a-849b93846584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63804374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.63804374
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1224741126
Short name T425
Test name
Test status
Simulation time 1136111673 ps
CPU time 5.87 seconds
Started Feb 18 01:45:44 PM PST 24
Finished Feb 18 01:45:54 PM PST 24
Peak memory 207668 kb
Host smart-0473b59c-0b52-47d8-803b-2875a62370b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1224741126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1224741126
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1964595468
Short name T429
Test name
Test status
Simulation time 166648822 ps
CPU time 7.29 seconds
Started Feb 18 01:45:38 PM PST 24
Finished Feb 18 01:45:52 PM PST 24
Peak memory 199428 kb
Host smart-f0282a20-f462-4090-a84a-c54ea5c854be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964595468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1964595468
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.980900288
Short name T434
Test name
Test status
Simulation time 390205744 ps
CPU time 9.19 seconds
Started Feb 18 01:45:41 PM PST 24
Finished Feb 18 01:45:57 PM PST 24
Peak memory 199436 kb
Host smart-30c6e91b-8b66-4a29-a573-20b537e6dfa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980900288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.980900288
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1779592505
Short name T555
Test name
Test status
Simulation time 15889886541 ps
CPU time 37.67 seconds
Started Feb 18 01:45:41 PM PST 24
Finished Feb 18 01:46:25 PM PST 24
Peak memory 199564 kb
Host smart-21d2194e-47db-440f-b81d-452fa1b47b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779592505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1779592505
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1162216103
Short name T209
Test name
Test status
Simulation time 4372329024 ps
CPU time 59.69 seconds
Started Feb 18 01:45:35 PM PST 24
Finished Feb 18 01:46:40 PM PST 24
Peak memory 199664 kb
Host smart-88103ce9-c591-4a2a-96be-dc0388e30c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162216103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1162216103
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2632284559
Short name T581
Test name
Test status
Simulation time 65399277 ps
CPU time 0.71 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:45:43 PM PST 24
Peak memory 195676 kb
Host smart-7f7e9163-25c9-44b4-b0f9-723fd892a92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632284559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2632284559
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.532793702
Short name T114
Test name
Test status
Simulation time 48935698732 ps
CPU time 830.52 seconds
Started Feb 18 01:45:33 PM PST 24
Finished Feb 18 01:59:27 PM PST 24
Peak memory 207768 kb
Host smart-550c9a37-4b48-4de4-a802-64bf4f6670c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532793702 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.532793702
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.81508750
Short name T492
Test name
Test status
Simulation time 81761229 ps
CPU time 0.95 seconds
Started Feb 18 01:45:37 PM PST 24
Finished Feb 18 01:45:44 PM PST 24
Peak memory 197240 kb
Host smart-8f81ee86-9606-4556-bdd5-0190d3b9b6f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81508750 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.hmac_test_hmac_vectors.81508750
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.1912419332
Short name T583
Test name
Test status
Simulation time 120028630747 ps
CPU time 480.4 seconds
Started Feb 18 01:45:37 PM PST 24
Finished Feb 18 01:53:45 PM PST 24
Peak memory 199444 kb
Host smart-d761614c-91fb-4a02-a25b-0601a8237920
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912419332 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_sha_vectors.1912419332
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1758560899
Short name T40
Test name
Test status
Simulation time 1700603726 ps
CPU time 30.95 seconds
Started Feb 18 01:45:36 PM PST 24
Finished Feb 18 01:46:13 PM PST 24
Peak memory 199568 kb
Host smart-b6a6903a-0dde-423e-8469-1f2fc270b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758560899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1758560899
Directory /workspace/9.hmac_wipe_secret/latest
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