Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13484479	1			T1	552		T2	246		T3	184
all_values[1]	13484479	1			T1	552		T2	246		T3	184
all_values[2]	13484479	1			T1	552		T2	246		T3	184

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103492

1

T3

3

T7

229

T10

4

auto[1]

40349945

1

T1

1656

T2

738

T3

549

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28710300

1

T1

1310

T2

503

T3

354

auto[1]

11743137

1

T1

346

T2

235

T3

198

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	39401	1			T3	1		T13	5		T141	3
all_values[0]	auto[0]	auto[1]	494	1			T3	2		T13	2		T21	2
all_values[0]	auto[1]	auto[0]	13399119	1			T1	494		T2	198		T3	163
all_values[0]	auto[1]	auto[1]	45465	1			T1	58		T2	48		T3	18
all_values[1]	auto[0]	auto[0]	19691	1			T7	40		T10	2		T9	1014
all_values[1]	auto[0]	auto[1]	16263	1			T7	189		T10	2		T9	490
all_values[1]	auto[1]	auto[0]	7284742	1			T1	264		T2	59		T3	6
all_values[1]	auto[1]	auto[1]	6163783	1			T1	288		T2	187		T3	178
all_values[2]	auto[0]	auto[0]	21389	1			T21	6		T22	690		T29	82
all_values[2]	auto[0]	auto[1]	6254	1			T20	5		T56	872		T104	101
all_values[2]	auto[1]	auto[0]	7945958	1			T1	552		T2	246		T3	184
all_values[2]	auto[1]	auto[1]	5510878	1			T21	113013		T38	51		T32	29301