Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6567765

1

T1

139

T2

2026

T3

7

auto[1]

2566797

1

T1

194

T2

2053

T3

9

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2556489

1

T1

195

T2

1897

T3

7

auto[1]

6578073

1

T1

138

T2

2182

T3

9

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5788569

1

T1

153

T2

2377

T3

12

auto[1]

3345993

1

T1

180

T2

1702

T3

4

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5688428	1			T1	289		T2	3192		T7	12339
fifo_depth[1]	448564	1			T1	12		T2	185		T7	653
fifo_depth[2]	383285	1			T1	18		T2	278		T7	247
fifo_depth[3]	318470	1			T1	7		T2	136		T7	62
fifo_depth[4]	300954	1			T1	6		T2	197		T7	22
fifo_depth[5]	255787	1			T2	53		T3	1		T7	10
fifo_depth[6]	262041	1			T1	1		T2	33		T7	1
fifo_depth[7]	224070	1			T2	5		T3	2		T10	1236
fifo_depth[8]	259675	1			T3	5		T10	2482		T9	721
fifo_depth[9]	150864	1			T10	1044		T9	554		T8	9
fifo_depth[10]	150332	1			T3	3		T10	1389		T9	371
fifo_depth[11]	91738	1			T10	1244		T9	199		T8	2
fifo_depth[12]	145612	1			T3	2		T10	2471		T9	92
fifo_depth[13]	66178	1			T10	1154		T9	53		T8	3
fifo_depth[14]	99402	1			T3	1		T10	1955		T9	11
fifo_depth[15]	58622	1			T10	1609		T9	5		T8	1
fifo_depth[16]	230540	1			T3	2		T10	3397		T9	3

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3446134

1

T1

44

T2

887

T3

16

auto[1]

5688428

1

T1

289

T2

3192

T7

12339

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8904022

1

T1

333

T2

4079

T3

14

auto[1]

230540

1

T3

2

T10

3397

T9

3

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

219719

1

T2

44

T3

2

T7

50

auto[0]

auto[0]

auto[0]

auto[1]

235697

1

T2

111

T3

3

T7

90

auto[0]

auto[0]

auto[1]

auto[0]

1001619

1

T2

169

T3

4

T7

172

auto[0]

auto[0]

auto[1]

auto[1]

218094

1

T2

146

T3

3

T7

32

auto[0]

auto[1]

auto[0]

auto[0]

459948

1

T1

17

T2

149

T3

1

auto[0]

auto[1]

auto[0]

auto[1]

421746

1

T1

11

T2

117

T3

1

auto[0]

auto[1]

auto[1]

auto[0]

451879

1

T1

4

T2

71

T7

207

auto[0]

auto[1]

auto[1]

auto[1]

437432

1

T1

12

T2

80

T3

2

auto[1]

auto[0]

auto[0]

auto[0]

230138

1

T1

33

T2

111

T7

625

auto[1]

auto[0]

auto[0]

auto[1]

234208

1

T1

45

T2

468

T7

1146

auto[1]

auto[0]

auto[1]

auto[0]

3421174

1

T1

17

T2

929

T7

2112

auto[1]

auto[0]

auto[1]

auto[1]

227920

1

T1

58

T2

399

T7

400

auto[1]

auto[1]

auto[0]

auto[0]

373765

1

T1

56

T2

392

T7

1737

auto[1]

auto[1]

auto[0]

auto[1]

381268

1

T1

33

T2

505

T7

1744

auto[1]

auto[1]

auto[1]

auto[0]

409523

1

T1

12

T2

161

T7

2494

auto[1]

auto[1]

auto[1]

auto[1]

410432

1

T1

35

T2

227

T7

2081

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

425350

1

T1

33

T2

155

T3

2

auto[0]

auto[0]

auto[0]

auto[1]

441125

1

T1

45

T2

579

T3

3

auto[0]

auto[0]

auto[1]

auto[0]

4392897

1

T1

17

T2

1098

T3

3

auto[0]

auto[0]

auto[1]

auto[1]

420964

1

T1

58

T2

545

T3

3

auto[0]

auto[1]

auto[0]

auto[0]

798711

1

T1

73

T2

541

T3

1

auto[0]

auto[1]

auto[0]

auto[1]

780725

1

T1

44

T2

622

T3

1

auto[0]

auto[1]

auto[1]

auto[0]

826562

1

T1

16

T2

232

T7

2701

auto[0]

auto[1]

auto[1]

auto[1]

817688

1

T1

47

T2

307

T3

1

auto[1]

auto[0]

auto[0]

auto[0]

24507

1

T10

495

T8

1

T21

114

auto[1]

auto[0]

auto[0]

auto[1]

28780

1

T10

436

T21

169

T40

1265

auto[1]

auto[0]

auto[1]

auto[0]

29896

1

T3

1

T10

162

T21

1005

auto[1]

auto[0]

auto[1]

auto[1]

25050

1

T10

471

T8

1

T21

112

auto[1]

auto[1]

auto[0]

auto[0]

35002

1

T10

221

T9

1

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

22289

1

T10

12

T28

1

T21

462

auto[1]

auto[1]

auto[1]

auto[0]

34840

1

T10

1159

T9

1

T28

1

auto[1]

auto[1]

auto[1]

auto[1]

30176

1

T3

1

T10

441

T9

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	230138	1			T1	33		T2	111		T7	625
fifo_depth[0]	auto[0]	auto[0]	auto[1]	234208	1			T1	45		T2	468		T7	1146
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3421174	1			T1	17		T2	929		T7	2112
fifo_depth[0]	auto[0]	auto[1]	auto[1]	227920	1			T1	58		T2	399		T7	400
fifo_depth[0]	auto[1]	auto[0]	auto[0]	373765	1			T1	56		T2	392		T7	1737
fifo_depth[0]	auto[1]	auto[0]	auto[1]	381268	1			T1	33		T2	505		T7	1744
fifo_depth[0]	auto[1]	auto[1]	auto[0]	409523	1			T1	12		T2	161		T7	2494
fifo_depth[0]	auto[1]	auto[1]	auto[1]	410432	1			T1	35		T2	227		T7	2081
fifo_depth[1]	auto[0]	auto[0]	auto[0]	19525	1			T2	13		T7	36		T10	30
fifo_depth[1]	auto[0]	auto[0]	auto[1]	19642	1			T2	8		T7	55		T10	1
fifo_depth[1]	auto[0]	auto[1]	auto[0]	211242	1			T2	57		T7	122		T10	101
fifo_depth[1]	auto[0]	auto[1]	auto[1]	18942	1			T2	27		T7	19		T10	141
fifo_depth[1]	auto[1]	auto[0]	auto[0]	43426	1			T1	6		T2	27		T7	85
fifo_depth[1]	auto[1]	auto[0]	auto[1]	44256	1			T1	3		T2	32		T7	85
fifo_depth[1]	auto[1]	auto[1]	auto[0]	45970	1			T1	1		T2	9		T7	141
fifo_depth[1]	auto[1]	auto[1]	auto[1]	45561	1			T1	2		T2	12		T7	110
fifo_depth[2]	auto[0]	auto[0]	auto[0]	17653	1			T2	9		T7	10		T10	53
fifo_depth[2]	auto[0]	auto[0]	auto[1]	18591	1			T2	55		T7	29		T10	4
fifo_depth[2]	auto[0]	auto[1]	auto[0]	164914	1			T2	45		T7	30		T10	340
fifo_depth[2]	auto[0]	auto[1]	auto[1]	16872	1			T2	47		T7	9		T10	134
fifo_depth[2]	auto[1]	auto[0]	auto[0]	40421	1			T1	8		T2	44		T7	40
fifo_depth[2]	auto[1]	auto[0]	auto[1]	40188	1			T1	4		T2	30		T7	35
fifo_depth[2]	auto[1]	auto[1]	auto[0]	42785	1			T1	2		T2	22		T7	51
fifo_depth[2]	auto[1]	auto[1]	auto[1]	41861	1			T1	4		T2	26		T7	43
fifo_depth[3]	auto[0]	auto[0]	auto[0]	14763	1			T2	7		T7	2		T10	56
fifo_depth[3]	auto[0]	auto[0]	auto[1]	15445	1			T2	11		T7	5		T10	49
fifo_depth[3]	auto[0]	auto[1]	auto[0]	126030	1			T2	21		T7	13		T10	344
fifo_depth[3]	auto[0]	auto[1]	auto[1]	14006	1			T2	25		T7	2		T10	158
fifo_depth[3]	auto[1]	auto[0]	auto[0]	36463	1			T1	2		T2	28		T7	9
fifo_depth[3]	auto[1]	auto[0]	auto[1]	36177	1			T1	2		T2	21		T7	9
fifo_depth[3]	auto[1]	auto[1]	auto[0]	38247	1			T2	12		T7	9		T10	181
fifo_depth[3]	auto[1]	auto[1]	auto[1]	37339	1			T1	3		T2	11		T7	13
fifo_depth[4]	auto[0]	auto[0]	auto[0]	17551	1			T2	6		T7	2		T10	94
fifo_depth[4]	auto[0]	auto[0]	auto[1]	17023	1			T2	29		T7	1		T10	66
fifo_depth[4]	auto[0]	auto[1]	auto[0]	96005	1			T2	26		T7	5		T10	364
fifo_depth[4]	auto[0]	auto[1]	auto[1]	15966	1			T2	31		T7	1		T10	180
fifo_depth[4]	auto[1]	auto[0]	auto[0]	39522	1			T1	1		T2	39		T7	3
fifo_depth[4]	auto[1]	auto[0]	auto[1]	37723	1			T1	1		T2	29		T7	3
fifo_depth[4]	auto[1]	auto[1]	auto[0]	39344	1			T1	1		T2	17		T7	5
fifo_depth[4]	auto[1]	auto[1]	auto[1]	37820	1			T1	3		T2	20		T7	2
fifo_depth[5]	auto[0]	auto[0]	auto[0]	13271	1			T2	3		T10	85		T12	34
fifo_depth[5]	auto[0]	auto[0]	auto[1]	13993	1			T2	2		T3	1		T10	59
fifo_depth[5]	auto[0]	auto[1]	auto[0]	76997	1			T2	14		T7	2		T10	342
fifo_depth[5]	auto[0]	auto[1]	auto[1]	12990	1			T2	10		T7	1		T10	159
fifo_depth[5]	auto[1]	auto[0]	auto[0]	34666	1			T2	8		T7	2		T10	100
fifo_depth[5]	auto[1]	auto[0]	auto[1]	33707	1			T2	4		T10	25		T9	123
fifo_depth[5]	auto[1]	auto[1]	auto[0]	35595	1			T2	5		T7	1		T10	253
fifo_depth[5]	auto[1]	auto[1]	auto[1]	34568	1			T2	7		T7	4		T10	137
fifo_depth[6]	auto[0]	auto[0]	auto[0]	15498	1			T2	6		T10	103		T8	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	14641	1			T2	4		T10	43		T12	29
fifo_depth[6]	auto[0]	auto[1]	auto[0]	69594	1			T2	6		T10	308		T12	10
fifo_depth[6]	auto[0]	auto[1]	auto[1]	14704	1			T2	5		T10	158		T12	15
fifo_depth[6]	auto[1]	auto[0]	auto[0]	38626	1			T2	2		T10	102		T9	167
fifo_depth[6]	auto[1]	auto[0]	auto[1]	36100	1			T1	1		T10	71		T9	112
fifo_depth[6]	auto[1]	auto[1]	auto[0]	37241	1			T2	6		T10	219		T9	307
fifo_depth[6]	auto[1]	auto[1]	auto[1]	35637	1			T2	4		T7	1		T10	97
fifo_depth[7]	auto[0]	auto[0]	auto[0]	12369	1			T3	1		T10	73		T8	2
fifo_depth[7]	auto[0]	auto[0]	auto[1]	12611	1			T2	2		T10	69		T12	21
fifo_depth[7]	auto[0]	auto[1]	auto[0]	55851	1			T10	333		T21	1670		T40	148
fifo_depth[7]	auto[0]	auto[1]	auto[1]	12524	1			T2	1		T10	163		T12	6
fifo_depth[7]	auto[1]	auto[0]	auto[0]	32669	1			T2	1		T10	111		T9	149
fifo_depth[7]	auto[1]	auto[0]	auto[1]	31585	1			T2	1		T3	1		T10	73
fifo_depth[7]	auto[1]	auto[1]	auto[0]	33649	1			T10	276		T9	296		T8	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	32812	1			T10	138		T9	365		T8	1
fifo_depth[8]	auto[0]	auto[0]	auto[0]	18035	1			T10	100		T12	28		T21	377
fifo_depth[8]	auto[0]	auto[0]	auto[1]	21048	1			T10	560		T12	10		T21	154
fifo_depth[8]	auto[0]	auto[1]	auto[0]	49671	1			T3	2		T10	282		T8	1
fifo_depth[8]	auto[0]	auto[1]	auto[1]	20469	1			T3	2		T10	186		T12	42
fifo_depth[8]	auto[1]	auto[0]	auto[0]	39006	1			T10	116		T9	111		T8	2
fifo_depth[8]	auto[1]	auto[0]	auto[1]	36291	1			T10	38		T9	81		T12	5
fifo_depth[8]	auto[1]	auto[1]	auto[0]	37800	1			T10	816		T9	234		T12	46
fifo_depth[8]	auto[1]	auto[1]	auto[1]	37355	1			T3	1		T10	384		T9	295
fifo_depth[9]	auto[0]	auto[0]	auto[0]	9289	1			T10	81		T12	2		T21	82
fifo_depth[9]	auto[0]	auto[0]	auto[1]	9230	1			T10	41		T8	2		T12	3
fifo_depth[9]	auto[0]	auto[1]	auto[0]	30845	1			T10	286		T8	1		T21	853
fifo_depth[9]	auto[0]	auto[1]	auto[1]	9653	1			T10	143		T8	1		T12	1
fifo_depth[9]	auto[1]	auto[0]	auto[0]	23314	1			T10	106		T9	74		T13	4
fifo_depth[9]	auto[1]	auto[0]	auto[1]	21636	1			T10	45		T9	48		T8	1
fifo_depth[9]	auto[1]	auto[1]	auto[0]	23144	1			T10	210		T9	198		T8	1
fifo_depth[9]	auto[1]	auto[1]	auto[1]	23753	1			T10	132		T9	234		T8	3
fifo_depth[10]	auto[0]	auto[0]	auto[0]	12699	1			T10	162		T12	9		T21	285
fifo_depth[10]	auto[0]	auto[0]	auto[1]	11459	1			T3	1		T10	82		T12	4
fifo_depth[10]	auto[0]	auto[1]	auto[0]	25850	1			T10	305		T12	1		T21	754
fifo_depth[10]	auto[0]	auto[1]	auto[1]	12308	1			T3	1		T10	102		T8	1
fifo_depth[10]	auto[1]	auto[0]	auto[0]	25131	1			T3	1		T10	80		T9	52
fifo_depth[10]	auto[1]	auto[0]	auto[1]	20609	1			T10	32		T9	32		T8	1
fifo_depth[10]	auto[1]	auto[1]	auto[0]	20693	1			T10	222		T9	141		T12	10
fifo_depth[10]	auto[1]	auto[1]	auto[1]	21583	1			T10	404		T9	146		T13	1
fifo_depth[11]	auto[0]	auto[0]	auto[0]	7615	1			T10	129		T12	1		T21	52
fifo_depth[11]	auto[0]	auto[0]	auto[1]	7292	1			T10	42		T12	2		T21	29
fifo_depth[11]	auto[0]	auto[1]	auto[0]	15514	1			T10	313		T21	406		T40	49
fifo_depth[11]	auto[0]	auto[1]	auto[1]	6846	1			T10	71		T8	1		T21	254
fifo_depth[11]	auto[1]	auto[0]	auto[0]	14893	1			T10	52		T9	33		T28	14
fifo_depth[11]	auto[1]	auto[0]	auto[1]	12013	1			T10	63		T9	17		T12	1
fifo_depth[11]	auto[1]	auto[1]	auto[0]	13070	1			T10	227		T9	78		T27	1
fifo_depth[11]	auto[1]	auto[1]	auto[1]	14495	1			T10	347		T9	71		T8	1
fifo_depth[12]	auto[0]	auto[0]	auto[0]	13906	1			T3	1		T10	133		T21	205
fifo_depth[12]	auto[0]	auto[0]	auto[1]	18429	1			T3	1		T10	475		T21	106
fifo_depth[12]	auto[0]	auto[1]	auto[0]	19195	1			T10	249		T21	704		T40	19
fifo_depth[12]	auto[0]	auto[1]	auto[1]	14609	1			T10	81		T21	209		T40	39
fifo_depth[12]	auto[1]	auto[0]	auto[0]	23271	1			T10	210		T9	14		T28	10
fifo_depth[12]	auto[1]	auto[0]	auto[1]	19912	1			T10	39		T9	14		T28	10
fifo_depth[12]	auto[1]	auto[1]	auto[0]	18692	1			T10	735		T9	29		T28	16
fifo_depth[12]	auto[1]	auto[1]	auto[1]	17598	1			T10	549		T9	35		T8	1
fifo_depth[13]	auto[0]	auto[0]	auto[0]	6708	1			T10	126		T21	25		T40	2
fifo_depth[13]	auto[0]	auto[0]	auto[1]	7709	1			T10	60		T8	2		T21	35
fifo_depth[13]	auto[0]	auto[1]	auto[0]	9172	1			T10	279		T21	206		T40	2
fifo_depth[13]	auto[0]	auto[1]	auto[1]	6504	1			T10	46		T21	142		T40	15
fifo_depth[13]	auto[1]	auto[0]	auto[0]	9895	1			T10	41		T9	4		T28	4
fifo_depth[13]	auto[1]	auto[0]	auto[1]	8560	1			T10	19		T9	8		T8	1
fifo_depth[13]	auto[1]	auto[1]	auto[0]	8199	1			T10	246		T9	22		T28	3
fifo_depth[13]	auto[1]	auto[1]	auto[1]	9431	1			T10	337		T9	19		T28	1
fifo_depth[14]	auto[0]	auto[0]	auto[0]	10474	1			T10	120		T8	1		T21	150
fifo_depth[14]	auto[0]	auto[0]	auto[1]	12297	1			T10	295		T21	227		T40	148
fifo_depth[14]	auto[0]	auto[1]	auto[0]	13278	1			T3	1		T10	234		T8	2
fifo_depth[14]	auto[0]	auto[1]	auto[1]	10527	1			T10	231		T21	156		T40	13
fifo_depth[14]	auto[1]	auto[0]	auto[0]	15743	1			T10	306		T9	4		T28	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	13092	1			T10	15		T9	1		T8	1
fifo_depth[14]	auto[1]	auto[1]	auto[0]	13622	1			T10	446		T9	4		T28	4
fifo_depth[14]	auto[1]	auto[1]	auto[1]	10369	1			T10	308		T9	2		T28	1
fifo_depth[15]	auto[0]	auto[0]	auto[0]	5856	1			T10	80		T21	20		T23	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	7507	1			T10	231		T21	146		T40	47
fifo_depth[15]	auto[0]	auto[1]	auto[0]	7565	1			T10	189		T21	109		T23	1
fifo_depth[15]	auto[0]	auto[1]	auto[1]	6124	1			T10	201		T21	112		T40	12
fifo_depth[15]	auto[1]	auto[0]	auto[0]	7900	1			T10	215		T9	1		T28	2
fifo_depth[15]	auto[1]	auto[0]	auto[1]	7608	1			T10	16		T21	516		T40	33
fifo_depth[15]	auto[1]	auto[1]	auto[0]	8988	1			T10	450		T9	2		T8	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	7074	1			T10	227		T9	2		T21	97
fifo_depth[16]	auto[0]	auto[0]	auto[0]	24507	1			T10	495		T8	1		T21	114
fifo_depth[16]	auto[0]	auto[0]	auto[1]	28780	1			T10	436		T21	169		T40	1265
fifo_depth[16]	auto[0]	auto[1]	auto[0]	29896	1			T3	1		T10	162		T21	1005
fifo_depth[16]	auto[0]	auto[1]	auto[1]	25050	1			T10	471		T8	1		T21	112
fifo_depth[16]	auto[1]	auto[0]	auto[0]	35002	1			T10	221		T9	1		T8	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	22289	1			T10	12		T28	1		T21	462
fifo_depth[16]	auto[1]	auto[1]	auto[0]	34840	1			T10	1159		T9	1		T28	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	30176	1			T3	1		T10	441		T9	1