Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13484479	1			T1	552		T2	246		T3	184
all_pins[1]	13484479	1			T1	552		T2	246		T3	184
all_pins[2]	13484479	1			T1	552		T2	246		T3	184

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	28671046	1			T1	1308		T2	500		T3	353
values[0x1]	11782391	1			T1	348		T2	238		T3	199
transitions[0x0=>0x1]	10242031	1			T1	309		T2	198		T3	179
transitions[0x1=>0x0]	10242046	1			T1	309		T2	199		T3	179

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13437929	1			T1	492		T2	196		T3	164
all_pins[0]	values[0x1]	46550	1			T1	60		T2	50		T3	20
all_pins[0]	transitions[0x0=>0x1]	46491	1			T1	60		T2	49		T3	20
all_pins[0]	transitions[0x1=>0x0]	5510834	1			T21	113013		T38	51		T32	29301
all_pins[1]	values[0x0]	7259516	1			T1	264		T2	58		T3	5
all_pins[1]	values[0x1]	6224963	1			T1	288		T2	188		T3	179
all_pins[1]	transitions[0x0=>0x1]	6188521	1			T1	249		T2	149		T3	159
all_pins[1]	transitions[0x1=>0x0]	10108	1			T1	21		T2	11		T7	11
all_pins[2]	values[0x0]	7973601	1			T1	552		T2	246		T3	184
all_pins[2]	values[0x1]	5510878	1			T21	113013		T38	51		T32	29301
all_pins[2]	transitions[0x0=>0x1]	4007019	1			T21	82339		T38	42		T32	25775
all_pins[2]	transitions[0x1=>0x0]	4721104	1			T1	288		T2	188		T3	179