Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 924 1 T20 10 T56 20 T57 14
all_values[1] 924 1 T20 10 T56 20 T57 14
all_values[2] 924 1 T20 10 T56 20 T57 14


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1380 1 T20 19 T56 29 T57 20
auto[1] 1392 1 T20 11 T56 31 T57 22


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1031 1 T20 12 T56 17 T57 16
auto[1] 1741 1 T20 18 T56 43 T57 26


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1589 1 T20 21 T56 31 T57 24
auto[1] 1183 1 T20 9 T56 29 T57 18


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 192 1 T20 4 T56 7 T57 4
all_values[0] auto[0] auto[0] auto[1] 98 1 T20 1 T56 2 T57 1
all_values[0] auto[0] auto[1] auto[0] 179 1 T20 3 T56 1 T57 2
all_values[0] auto[0] auto[1] auto[1] 79 1 T56 2 T57 1 T5 3
all_values[0] auto[1] auto[0] auto[1] 208 1 T20 2 T56 6 T57 4
all_values[0] auto[1] auto[1] auto[1] 168 1 T56 2 T57 2 T5 7
all_values[1] auto[0] auto[0] auto[0] 167 1 T20 3 T56 3 T57 2
all_values[1] auto[0] auto[0] auto[1] 98 1 T20 3 T56 1 T5 4
all_values[1] auto[0] auto[1] auto[0] 165 1 T56 2 T57 3 T5 11
all_values[1] auto[0] auto[1] auto[1] 94 1 T20 2 T56 2 T57 3
all_values[1] auto[1] auto[0] auto[1] 197 1 T56 2 T57 2 T5 6
all_values[1] auto[1] auto[1] auto[1] 203 1 T20 2 T56 10 T57 4
all_values[2] auto[0] auto[0] auto[0] 157 1 T20 1 T56 1 T57 1
all_values[2] auto[0] auto[0] auto[1] 81 1 T20 3 T56 3 T57 1
all_values[2] auto[0] auto[1] auto[0] 171 1 T20 1 T56 3 T57 4
all_values[2] auto[0] auto[1] auto[1] 108 1 T56 4 T57 2 T5 4
all_values[2] auto[1] auto[0] auto[1] 182 1 T20 2 T56 4 T57 5
all_values[2] auto[1] auto[1] auto[1] 225 1 T20 3 T56 5 T57 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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