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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.81 99.55 98.55 100.00 96.30 98.47 99.49 99.31


Total test records in report: 727
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T534 /workspace/coverage/default/20.hmac_burst_wr.982377196 Feb 21 02:14:14 PM PST 24 Feb 21 02:15:02 PM PST 24 1012874294 ps
T535 /workspace/coverage/default/24.hmac_error.3432775312 Feb 21 02:14:50 PM PST 24 Feb 21 02:16:02 PM PST 24 5802649188 ps
T536 /workspace/coverage/default/1.hmac_long_msg.1469390413 Feb 21 02:12:25 PM PST 24 Feb 21 02:13:56 PM PST 24 12207362222 ps
T537 /workspace/coverage/default/34.hmac_test_hmac_vectors.602685058 Feb 21 02:16:24 PM PST 24 Feb 21 02:16:26 PM PST 24 199721717 ps
T538 /workspace/coverage/default/46.hmac_wipe_secret.743954026 Feb 21 02:17:53 PM PST 24 Feb 21 02:18:36 PM PST 24 4066384446 ps
T539 /workspace/coverage/default/30.hmac_test_hmac_vectors.2747767904 Feb 21 02:15:46 PM PST 24 Feb 21 02:15:48 PM PST 24 33448296 ps
T78 /workspace/coverage/default/23.hmac_stress_all.1575931367 Feb 21 02:14:43 PM PST 24 Feb 21 02:30:17 PM PST 24 439721231827 ps
T540 /workspace/coverage/default/31.hmac_error.4211656157 Feb 21 02:15:46 PM PST 24 Feb 21 02:16:19 PM PST 24 1737340540 ps
T541 /workspace/coverage/default/45.hmac_test_hmac_vectors.1990593774 Feb 21 02:17:54 PM PST 24 Feb 21 02:17:56 PM PST 24 112017325 ps
T542 /workspace/coverage/default/49.hmac_long_msg.737273772 Feb 21 02:18:21 PM PST 24 Feb 21 02:19:39 PM PST 24 5463905508 ps
T543 /workspace/coverage/default/43.hmac_smoke.1600964440 Feb 21 02:17:17 PM PST 24 Feb 21 02:17:19 PM PST 24 351528350 ps
T544 /workspace/coverage/default/46.hmac_back_pressure.3255272407 Feb 21 02:17:55 PM PST 24 Feb 21 02:18:55 PM PST 24 14406774715 ps
T545 /workspace/coverage/default/32.hmac_wipe_secret.3186951597 Feb 21 02:15:48 PM PST 24 Feb 21 02:16:07 PM PST 24 5329147207 ps
T546 /workspace/coverage/default/40.hmac_test_hmac_vectors.1025686385 Feb 21 02:17:08 PM PST 24 Feb 21 02:17:10 PM PST 24 112743576 ps
T547 /workspace/coverage/default/5.hmac_test_hmac_vectors.3776627682 Feb 21 02:13:00 PM PST 24 Feb 21 02:13:01 PM PST 24 74920661 ps
T548 /workspace/coverage/default/49.hmac_test_hmac_vectors.1661607051 Feb 21 02:18:31 PM PST 24 Feb 21 02:18:32 PM PST 24 108424451 ps
T549 /workspace/coverage/default/47.hmac_long_msg.255320087 Feb 21 02:17:57 PM PST 24 Feb 21 02:19:18 PM PST 24 52093127950 ps
T550 /workspace/coverage/default/15.hmac_smoke.3795524499 Feb 21 02:13:56 PM PST 24 Feb 21 02:13:58 PM PST 24 171043215 ps
T551 /workspace/coverage/default/27.hmac_back_pressure.2519635990 Feb 21 02:15:21 PM PST 24 Feb 21 02:15:47 PM PST 24 1323102118 ps
T552 /workspace/coverage/default/32.hmac_burst_wr.4266992872 Feb 21 02:15:56 PM PST 24 Feb 21 02:16:45 PM PST 24 6183565596 ps
T553 /workspace/coverage/default/37.hmac_datapath_stress.3046724678 Feb 21 02:16:34 PM PST 24 Feb 21 02:18:17 PM PST 24 1834045194 ps
T554 /workspace/coverage/default/22.hmac_stress_all.2650126930 Feb 21 02:14:42 PM PST 24 Feb 21 02:29:35 PM PST 24 111548334768 ps
T555 /workspace/coverage/default/49.hmac_error.3461014536 Feb 21 02:18:23 PM PST 24 Feb 21 02:19:08 PM PST 24 17364467673 ps
T556 /workspace/coverage/default/31.hmac_long_msg.1109701468 Feb 21 02:15:44 PM PST 24 Feb 21 02:16:22 PM PST 24 1988020001 ps
T557 /workspace/coverage/default/15.hmac_error.3800835149 Feb 21 02:13:55 PM PST 24 Feb 21 02:15:11 PM PST 24 12060082962 ps
T558 /workspace/coverage/default/30.hmac_stress_all.2154802365 Feb 21 02:15:45 PM PST 24 Feb 21 02:28:05 PM PST 24 42464170101 ps
T559 /workspace/coverage/default/8.hmac_datapath_stress.3716585239 Feb 21 02:13:11 PM PST 24 Feb 21 02:15:29 PM PST 24 24552404502 ps
T560 /workspace/coverage/default/24.hmac_test_hmac_vectors.1095434317 Feb 21 02:14:52 PM PST 24 Feb 21 02:14:53 PM PST 24 116082413 ps
T561 /workspace/coverage/default/47.hmac_burst_wr.2756669058 Feb 21 02:18:02 PM PST 24 Feb 21 02:18:13 PM PST 24 872528232 ps
T562 /workspace/coverage/default/14.hmac_wipe_secret.1222706958 Feb 21 02:13:36 PM PST 24 Feb 21 02:14:15 PM PST 24 3137155577 ps
T563 /workspace/coverage/default/0.hmac_error.3714295732 Feb 21 02:12:30 PM PST 24 Feb 21 02:14:35 PM PST 24 19703819654 ps
T564 /workspace/coverage/default/10.hmac_test_sha_vectors.394058320 Feb 21 02:13:12 PM PST 24 Feb 21 02:20:06 PM PST 24 33021572745 ps
T565 /workspace/coverage/default/39.hmac_burst_wr.1048833919 Feb 21 02:16:56 PM PST 24 Feb 21 02:17:14 PM PST 24 1215037686 ps
T566 /workspace/coverage/default/42.hmac_test_sha_vectors.3468792973 Feb 21 02:17:16 PM PST 24 Feb 21 02:24:11 PM PST 24 7911564207 ps
T567 /workspace/coverage/default/40.hmac_smoke.557452778 Feb 21 02:16:57 PM PST 24 Feb 21 02:16:59 PM PST 24 50532880 ps
T568 /workspace/coverage/default/44.hmac_alert_test.2949669780 Feb 21 02:17:42 PM PST 24 Feb 21 02:17:45 PM PST 24 55166656 ps
T569 /workspace/coverage/default/45.hmac_burst_wr.2948879199 Feb 21 02:17:48 PM PST 24 Feb 21 02:18:44 PM PST 24 2471112893 ps
T570 /workspace/coverage/default/28.hmac_back_pressure.3906023043 Feb 21 02:15:30 PM PST 24 Feb 21 02:15:56 PM PST 24 3082024400 ps
T571 /workspace/coverage/default/19.hmac_wipe_secret.1043480859 Feb 21 02:14:06 PM PST 24 Feb 21 02:14:20 PM PST 24 894586933 ps
T572 /workspace/coverage/default/5.hmac_alert_test.3779910407 Feb 21 02:12:59 PM PST 24 Feb 21 02:13:00 PM PST 24 28820682 ps
T573 /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.2890927771 Feb 21 02:16:31 PM PST 24 Feb 21 02:20:27 PM PST 24 63757494558 ps
T574 /workspace/coverage/default/15.hmac_back_pressure.441346267 Feb 21 02:13:45 PM PST 24 Feb 21 02:13:55 PM PST 24 397516405 ps
T575 /workspace/coverage/default/24.hmac_alert_test.109878047 Feb 21 02:15:05 PM PST 24 Feb 21 02:15:07 PM PST 24 81145703 ps
T576 /workspace/coverage/default/46.hmac_burst_wr.4186839972 Feb 21 02:17:55 PM PST 24 Feb 21 02:18:38 PM PST 24 8931664306 ps
T108 /workspace/coverage/default/29.hmac_datapath_stress.1763635998 Feb 21 02:15:38 PM PST 24 Feb 21 02:17:26 PM PST 24 4244754956 ps
T577 /workspace/coverage/default/18.hmac_wipe_secret.925245950 Feb 21 02:14:06 PM PST 24 Feb 21 02:15:07 PM PST 24 1513074804 ps
T578 /workspace/coverage/default/46.hmac_test_sha_vectors.1942803519 Feb 21 02:17:53 PM PST 24 Feb 21 02:25:06 PM PST 24 111106503088 ps
T579 /workspace/coverage/default/26.hmac_test_sha_vectors.4290109985 Feb 21 02:15:21 PM PST 24 Feb 21 02:22:50 PM PST 24 9042921896 ps
T580 /workspace/coverage/default/43.hmac_datapath_stress.2093749980 Feb 21 02:17:26 PM PST 24 Feb 21 02:18:41 PM PST 24 2878427196 ps
T581 /workspace/coverage/default/31.hmac_back_pressure.2223286198 Feb 21 02:15:43 PM PST 24 Feb 21 02:16:10 PM PST 24 673169566 ps
T582 /workspace/coverage/default/21.hmac_alert_test.2230321819 Feb 21 02:14:41 PM PST 24 Feb 21 02:14:42 PM PST 24 38420582 ps
T583 /workspace/coverage/default/38.hmac_test_hmac_vectors.2681677061 Feb 21 02:16:43 PM PST 24 Feb 21 02:16:45 PM PST 24 199071101 ps
T584 /workspace/coverage/default/9.hmac_error.694532685 Feb 21 02:13:23 PM PST 24 Feb 21 02:14:22 PM PST 24 16898889765 ps
T585 /workspace/coverage/default/42.hmac_wipe_secret.1733485251 Feb 21 02:17:28 PM PST 24 Feb 21 02:17:35 PM PST 24 1277687566 ps
T586 /workspace/coverage/default/38.hmac_wipe_secret.3831196189 Feb 21 02:16:45 PM PST 24 Feb 21 02:16:48 PM PST 24 190110913 ps
T587 /workspace/coverage/default/8.hmac_stress_all.1018198834 Feb 21 02:13:08 PM PST 24 Feb 21 02:35:33 PM PST 24 224446278270 ps
T588 /workspace/coverage/default/27.hmac_test_hmac_vectors.1017900128 Feb 21 02:15:28 PM PST 24 Feb 21 02:15:29 PM PST 24 63715334 ps
T589 /workspace/coverage/default/31.hmac_smoke.3207309974 Feb 21 02:15:44 PM PST 24 Feb 21 02:15:47 PM PST 24 146040013 ps
T590 /workspace/coverage/default/16.hmac_back_pressure.2454869643 Feb 21 02:13:54 PM PST 24 Feb 21 02:14:57 PM PST 24 1795255602 ps
T591 /workspace/coverage/default/42.hmac_long_msg.603446260 Feb 21 02:17:17 PM PST 24 Feb 21 02:17:53 PM PST 24 680861063 ps
T592 /workspace/coverage/default/19.hmac_smoke.3941331396 Feb 21 02:14:06 PM PST 24 Feb 21 02:14:10 PM PST 24 799269316 ps
T593 /workspace/coverage/default/47.hmac_smoke.2806073092 Feb 21 02:17:53 PM PST 24 Feb 21 02:17:57 PM PST 24 934392489 ps
T594 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3988755141 Feb 21 02:54:44 PM PST 24 Feb 21 02:54:48 PM PST 24 175738448 ps
T53 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2677466772 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:32 PM PST 24 191594439 ps
T595 /workspace/coverage/cover_reg_top/20.hmac_intr_test.97899686 Feb 21 02:55:04 PM PST 24 Feb 21 02:55:05 PM PST 24 15122410 ps
T596 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.328492702 Feb 21 02:54:41 PM PST 24 Feb 21 02:54:43 PM PST 24 30813484 ps
T597 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.536982220 Feb 21 02:54:34 PM PST 24 Feb 21 02:54:35 PM PST 24 87923560 ps
T598 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3511563919 Feb 21 02:54:38 PM PST 24 Feb 21 02:54:39 PM PST 24 28472026 ps
T599 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1989578988 Feb 21 02:54:52 PM PST 24 Feb 21 02:54:53 PM PST 24 31122136 ps
T54 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.444989371 Feb 21 02:54:39 PM PST 24 Feb 21 02:54:41 PM PST 24 218373827 ps
T600 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3456670734 Feb 21 02:54:26 PM PST 24 Feb 21 02:54:28 PM PST 24 76453461 ps
T601 /workspace/coverage/cover_reg_top/30.hmac_intr_test.287867323 Feb 21 02:55:06 PM PST 24 Feb 21 02:55:07 PM PST 24 136505437 ps
T602 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1750050872 Feb 21 02:54:35 PM PST 24 Feb 21 02:54:37 PM PST 24 51286976 ps
T88 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.709775707 Feb 21 02:54:36 PM PST 24 Feb 21 02:54:45 PM PST 24 762325810 ps
T603 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1377272402 Feb 21 02:55:09 PM PST 24 Feb 21 02:55:10 PM PST 24 14136331 ps
T604 /workspace/coverage/cover_reg_top/43.hmac_intr_test.177959620 Feb 21 02:55:08 PM PST 24 Feb 21 02:55:09 PM PST 24 41106347 ps
T605 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3357378970 Feb 21 02:55:14 PM PST 24 Feb 21 02:55:15 PM PST 24 20055419 ps
T55 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3501008708 Feb 21 02:54:35 PM PST 24 Feb 21 02:54:37 PM PST 24 1168426748 ps
T606 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3829316952 Feb 21 02:54:44 PM PST 24 Feb 21 02:54:46 PM PST 24 28550511 ps
T607 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2462066869 Feb 21 02:55:11 PM PST 24 Feb 21 02:55:12 PM PST 24 58958394 ps
T608 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2446259530 Feb 21 02:54:29 PM PST 24 Feb 21 02:54:33 PM PST 24 234535089 ps
T609 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2703733310 Feb 21 02:54:24 PM PST 24 Feb 21 02:54:27 PM PST 24 160711342 ps
T610 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.208721927 Feb 21 02:54:26 PM PST 24 Feb 21 02:54:29 PM PST 24 73809773 ps
T611 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2004272355 Feb 21 02:54:28 PM PST 24 Feb 21 02:54:29 PM PST 24 358064033 ps
T89 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3413330665 Feb 21 02:54:33 PM PST 24 Feb 21 02:54:34 PM PST 24 26819402 ps
T147 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2980289603 Feb 21 02:54:55 PM PST 24 Feb 21 02:54:56 PM PST 24 64364521 ps
T612 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2875323290 Feb 21 02:54:31 PM PST 24 Feb 21 02:54:32 PM PST 24 16062534 ps
T613 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1195383934 Feb 21 02:55:08 PM PST 24 Feb 21 02:55:09 PM PST 24 25760659 ps
T614 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2852970111 Feb 21 02:54:26 PM PST 24 Feb 21 02:54:28 PM PST 24 250605639 ps
T615 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1328876596 Feb 21 02:55:03 PM PST 24 Feb 21 02:55:04 PM PST 24 18380413 ps
T142 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1345365585 Feb 21 02:54:32 PM PST 24 Feb 21 02:54:34 PM PST 24 1079697208 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3431532380 Feb 21 02:54:25 PM PST 24 Feb 21 02:54:28 PM PST 24 159978484 ps
T616 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3069877112 Feb 21 02:54:38 PM PST 24 Feb 21 02:54:39 PM PST 24 11973966 ps
T617 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1730058906 Feb 21 02:54:38 PM PST 24 Feb 21 02:54:41 PM PST 24 208029298 ps
T143 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2199740402 Feb 21 02:54:39 PM PST 24 Feb 21 02:54:42 PM PST 24 2209360409 ps
T618 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1920297074 Feb 21 02:54:23 PM PST 24 Feb 21 02:54:34 PM PST 24 16047659731 ps
T144 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2664338779 Feb 21 02:54:38 PM PST 24 Feb 21 02:54:41 PM PST 24 313273329 ps
T619 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3454633125 Feb 21 02:54:35 PM PST 24 Feb 21 02:54:36 PM PST 24 14428598 ps
T620 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1728602610 Feb 21 02:55:08 PM PST 24 Feb 21 02:55:13 PM PST 24 66634360 ps
T621 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3115087705 Feb 21 02:55:04 PM PST 24 Feb 21 02:55:05 PM PST 24 12330418 ps
T622 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.97637414 Feb 21 02:54:26 PM PST 24 Feb 21 02:57:15 PM PST 24 25738416216 ps
T623 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1171294287 Feb 21 02:54:51 PM PST 24 Feb 21 02:54:52 PM PST 24 21785219 ps
T624 /workspace/coverage/cover_reg_top/2.hmac_intr_test.737065598 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:31 PM PST 24 19998125 ps
T625 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.731496005 Feb 21 02:54:47 PM PST 24 Feb 21 02:54:49 PM PST 24 38137902 ps
T626 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2121697383 Feb 21 02:55:04 PM PST 24 Feb 21 02:55:05 PM PST 24 58171066 ps
T627 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3859676976 Feb 21 02:54:34 PM PST 24 Feb 21 02:54:35 PM PST 24 56438717 ps
T628 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3246339847 Feb 21 02:54:35 PM PST 24 Feb 21 02:54:37 PM PST 24 64531128 ps
T148 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2937363498 Feb 21 02:54:32 PM PST 24 Feb 21 02:54:34 PM PST 24 74839480 ps
T629 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3546561305 Feb 21 02:54:32 PM PST 24 Feb 21 02:54:37 PM PST 24 908856775 ps
T630 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1316120726 Feb 21 02:55:02 PM PST 24 Feb 21 02:55:03 PM PST 24 72714096 ps
T631 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1950602042 Feb 21 02:54:23 PM PST 24 Feb 21 02:54:25 PM PST 24 33317657 ps
T632 /workspace/coverage/cover_reg_top/22.hmac_intr_test.276045337 Feb 21 02:54:59 PM PST 24 Feb 21 02:55:00 PM PST 24 19294363 ps
T633 /workspace/coverage/cover_reg_top/19.hmac_intr_test.286916444 Feb 21 02:55:01 PM PST 24 Feb 21 02:55:02 PM PST 24 111309676 ps
T634 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2722729512 Feb 21 02:54:32 PM PST 24 Feb 21 02:54:34 PM PST 24 120065230 ps
T635 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1155100030 Feb 21 02:55:04 PM PST 24 Feb 21 02:55:05 PM PST 24 156297554 ps
T150 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1881840543 Feb 21 02:54:54 PM PST 24 Feb 21 02:54:56 PM PST 24 194111123 ps
T636 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1324741891 Feb 21 02:54:32 PM PST 24 Feb 21 02:54:33 PM PST 24 44900024 ps
T153 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.701222327 Feb 21 02:54:52 PM PST 24 Feb 21 02:54:54 PM PST 24 145179539 ps
T637 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2551275966 Feb 21 02:55:08 PM PST 24 Feb 21 02:55:10 PM PST 24 13812358 ps
T638 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.684226595 Feb 21 02:54:48 PM PST 24 Feb 21 02:54:49 PM PST 24 35871588 ps
T639 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3473548542 Feb 21 02:55:06 PM PST 24 Feb 21 02:55:07 PM PST 24 20284208 ps
T640 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2751204663 Feb 21 02:54:38 PM PST 24 Feb 21 02:54:39 PM PST 24 95652079 ps
T641 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2603036713 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:31 PM PST 24 16864194 ps
T642 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1211312192 Feb 21 02:55:03 PM PST 24 Feb 21 02:55:04 PM PST 24 13909964 ps
T643 /workspace/coverage/cover_reg_top/28.hmac_intr_test.546681247 Feb 21 02:55:02 PM PST 24 Feb 21 02:55:03 PM PST 24 17992669 ps
T91 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1143957816 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:36 PM PST 24 137083819 ps
T644 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3740128259 Feb 21 02:54:53 PM PST 24 Feb 21 02:54:58 PM PST 24 860282711 ps
T645 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3060145607 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:31 PM PST 24 37119331 ps
T646 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2713139117 Feb 21 02:54:35 PM PST 24 Feb 21 02:54:40 PM PST 24 511972526 ps
T647 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1662098621 Feb 21 02:54:31 PM PST 24 Feb 21 02:54:34 PM PST 24 155586067 ps
T92 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2794507467 Feb 21 02:54:47 PM PST 24 Feb 21 02:54:48 PM PST 24 65415466 ps
T648 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3460021862 Feb 21 02:55:08 PM PST 24 Feb 21 02:55:10 PM PST 24 90683423 ps
T649 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2521898774 Feb 21 02:54:37 PM PST 24 Feb 21 02:54:38 PM PST 24 41027408 ps
T650 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4140744689 Feb 21 02:54:44 PM PST 24 Feb 21 03:01:37 PM PST 24 84128234104 ps
T651 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2656848023 Feb 21 02:54:38 PM PST 24 Feb 21 02:54:41 PM PST 24 984509630 ps
T652 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3280448128 Feb 21 02:54:47 PM PST 24 Feb 21 02:54:48 PM PST 24 20171326 ps
T653 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3445623503 Feb 21 02:55:09 PM PST 24 Feb 21 02:55:10 PM PST 24 44646361 ps
T654 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1749971796 Feb 21 02:54:29 PM PST 24 Feb 21 02:54:29 PM PST 24 12884629 ps
T93 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.77205897 Feb 21 02:55:04 PM PST 24 Feb 21 02:55:05 PM PST 24 70944576 ps
T655 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.159879962 Feb 21 02:54:32 PM PST 24 Feb 21 02:54:33 PM PST 24 16215796 ps
T656 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4228388606 Feb 21 02:54:57 PM PST 24 Feb 21 02:55:00 PM PST 24 293312450 ps
T657 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1967677111 Feb 21 02:54:55 PM PST 24 Feb 21 02:57:09 PM PST 24 43771989182 ps
T658 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1139566412 Feb 21 02:54:47 PM PST 24 Feb 21 02:54:48 PM PST 24 384576454 ps
T659 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2002695923 Feb 21 02:55:10 PM PST 24 Feb 21 02:55:11 PM PST 24 11027113 ps
T660 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3046725802 Feb 21 02:54:44 PM PST 24 Feb 21 02:54:45 PM PST 24 61311076 ps
T94 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2072104201 Feb 21 02:54:44 PM PST 24 Feb 21 02:54:45 PM PST 24 21296870 ps
T661 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3548389928 Feb 21 02:55:07 PM PST 24 Feb 21 02:55:08 PM PST 24 12390045 ps
T662 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3280641663 Feb 21 02:54:29 PM PST 24 Feb 21 02:54:30 PM PST 24 89812570 ps
T663 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2493151653 Feb 21 02:55:06 PM PST 24 Feb 21 02:55:09 PM PST 24 2198710649 ps
T664 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2257539999 Feb 21 02:54:45 PM PST 24 Feb 21 02:54:47 PM PST 24 65706471 ps
T665 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3719103518 Feb 21 02:54:45 PM PST 24 Feb 21 02:54:46 PM PST 24 36421965 ps
T666 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3884872384 Feb 21 02:55:02 PM PST 24 Feb 21 02:55:04 PM PST 24 195773685 ps
T145 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2641206504 Feb 21 02:54:52 PM PST 24 Feb 21 02:54:54 PM PST 24 119005561 ps
T667 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3244901319 Feb 21 02:55:01 PM PST 24 Feb 21 02:55:02 PM PST 24 273428913 ps
T668 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3514355681 Feb 21 02:54:28 PM PST 24 Feb 21 02:54:29 PM PST 24 19814533 ps
T669 /workspace/coverage/cover_reg_top/0.hmac_intr_test.996130067 Feb 21 02:54:25 PM PST 24 Feb 21 02:54:26 PM PST 24 11973229 ps
T670 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.559156906 Feb 21 02:54:49 PM PST 24 Feb 21 02:54:51 PM PST 24 66459083 ps
T671 /workspace/coverage/cover_reg_top/9.hmac_intr_test.4261566495 Feb 21 02:54:28 PM PST 24 Feb 21 02:54:29 PM PST 24 36598709 ps
T672 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2101500016 Feb 21 02:54:47 PM PST 24 Feb 21 02:54:50 PM PST 24 142414041 ps
T673 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3512901957 Feb 21 02:54:55 PM PST 24 Feb 21 02:54:55 PM PST 24 15036900 ps
T674 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1067402178 Feb 21 02:55:03 PM PST 24 Feb 21 02:55:04 PM PST 24 59109459 ps
T675 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2707846670 Feb 21 02:54:51 PM PST 24 Feb 21 02:54:54 PM PST 24 128896847 ps
T676 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1850701272 Feb 21 02:54:35 PM PST 24 Feb 21 02:54:38 PM PST 24 63864520 ps
T677 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1652067511 Feb 21 02:54:52 PM PST 24 Feb 21 02:54:56 PM PST 24 206980174 ps
T678 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1785751997 Feb 21 02:54:25 PM PST 24 Feb 21 02:54:35 PM PST 24 2707845893 ps
T679 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1822998843 Feb 21 02:54:31 PM PST 24 Feb 21 02:54:33 PM PST 24 61188422 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3152663892 Feb 21 02:54:34 PM PST 24 Feb 21 02:54:37 PM PST 24 113894502 ps
T680 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2252304685 Feb 21 02:54:51 PM PST 24 Feb 21 02:54:54 PM PST 24 281210074 ps
T681 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3977078409 Feb 21 02:54:54 PM PST 24 Feb 21 02:54:55 PM PST 24 38488834 ps
T682 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3269151501 Feb 21 02:54:47 PM PST 24 Feb 21 02:54:50 PM PST 24 147039514 ps
T683 /workspace/coverage/cover_reg_top/38.hmac_intr_test.730943709 Feb 21 02:55:08 PM PST 24 Feb 21 02:55:10 PM PST 24 14716019 ps
T684 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1004448880 Feb 21 02:54:36 PM PST 24 Feb 21 02:54:37 PM PST 24 46133618 ps
T685 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2734514427 Feb 21 02:55:08 PM PST 24 Feb 21 02:55:10 PM PST 24 44871756 ps
T686 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3986668883 Feb 21 02:55:06 PM PST 24 Feb 21 02:55:07 PM PST 24 24515978 ps
T96 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1012842212 Feb 21 02:54:32 PM PST 24 Feb 21 02:54:34 PM PST 24 46560709 ps
T151 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4140583092 Feb 21 02:55:12 PM PST 24 Feb 21 02:55:13 PM PST 24 102518801 ps
T687 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3923696644 Feb 21 02:55:08 PM PST 24 Feb 21 02:55:09 PM PST 24 15306520 ps
T688 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3412488447 Feb 21 02:54:44 PM PST 24 Feb 21 02:54:45 PM PST 24 16498994 ps
T689 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1232177911 Feb 21 02:55:01 PM PST 24 Feb 21 02:55:02 PM PST 24 35335686 ps
T690 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.987101520 Feb 21 02:54:29 PM PST 24 Feb 21 02:54:33 PM PST 24 65532738 ps
T97 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.521889865 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:31 PM PST 24 19715974 ps
T691 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3586682397 Feb 21 02:55:04 PM PST 24 Feb 21 02:55:05 PM PST 24 55620063 ps
T692 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2381410599 Feb 21 02:54:34 PM PST 24 Feb 21 02:54:36 PM PST 24 27752836 ps
T693 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3151632010 Feb 21 02:54:51 PM PST 24 Feb 21 02:54:53 PM PST 24 59605279 ps
T98 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4005130132 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:31 PM PST 24 50725198 ps
T694 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.381381046 Feb 21 02:54:24 PM PST 24 Feb 21 02:54:26 PM PST 24 178492811 ps
T695 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2231876430 Feb 21 02:54:33 PM PST 24 Feb 21 02:54:36 PM PST 24 709463885 ps
T696 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4068903294 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:31 PM PST 24 93207813 ps
T697 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2046663028 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:31 PM PST 24 16159849 ps
T698 /workspace/coverage/cover_reg_top/12.hmac_intr_test.787076260 Feb 21 02:54:47 PM PST 24 Feb 21 02:54:48 PM PST 24 50267141 ps
T699 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3184116505 Feb 21 02:54:27 PM PST 24 Feb 21 02:54:28 PM PST 24 284624261 ps
T700 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.463934424 Feb 21 02:54:23 PM PST 24 Feb 21 02:54:25 PM PST 24 494076389 ps
T146 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4042828405 Feb 21 02:54:29 PM PST 24 Feb 21 02:54:32 PM PST 24 1240076076 ps
T99 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.322242183 Feb 21 02:54:26 PM PST 24 Feb 21 02:54:27 PM PST 24 59811379 ps
T701 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2723804502 Feb 21 02:55:12 PM PST 24 Feb 21 02:55:13 PM PST 24 114146489 ps
T702 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2594290835 Feb 21 02:54:53 PM PST 24 Feb 21 02:54:55 PM PST 24 360089370 ps
T102 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3302006915 Feb 21 02:54:51 PM PST 24 Feb 21 02:54:51 PM PST 24 38411035 ps
T703 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3229035373 Feb 21 02:55:08 PM PST 24 Feb 21 02:55:09 PM PST 24 90304253 ps
T704 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1771585983 Feb 21 02:54:44 PM PST 24 Feb 21 02:55:33 PM PST 24 31050914827 ps
T705 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2956196522 Feb 21 02:55:00 PM PST 24 Feb 21 02:55:01 PM PST 24 56716252 ps
T706 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3725091813 Feb 21 02:54:59 PM PST 24 Feb 21 02:55:01 PM PST 24 138772742 ps
T707 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2610155922 Feb 21 02:55:17 PM PST 24 Feb 21 02:55:18 PM PST 24 14114710 ps
T708 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3757098637 Feb 21 02:54:50 PM PST 24 Feb 21 02:54:51 PM PST 24 85969326 ps
T709 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3246892572 Feb 21 02:54:35 PM PST 24 Feb 21 02:54:37 PM PST 24 80510947 ps
T710 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1459486514 Feb 21 02:54:35 PM PST 24 Feb 21 02:54:37 PM PST 24 56452213 ps
T711 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2048282844 Feb 21 02:55:07 PM PST 24 Feb 21 02:55:09 PM PST 24 23207850 ps
T712 /workspace/coverage/cover_reg_top/32.hmac_intr_test.596721392 Feb 21 02:55:06 PM PST 24 Feb 21 02:55:07 PM PST 24 17256781 ps
T713 /workspace/coverage/cover_reg_top/29.hmac_intr_test.556442107 Feb 21 02:55:07 PM PST 24 Feb 21 02:55:08 PM PST 24 179026285 ps
T714 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2844061390 Feb 21 02:54:54 PM PST 24 Feb 21 02:54:55 PM PST 24 239652979 ps
T715 /workspace/coverage/cover_reg_top/14.hmac_intr_test.705419634 Feb 21 02:54:54 PM PST 24 Feb 21 02:54:55 PM PST 24 11694415 ps
T152 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4289553687 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:32 PM PST 24 65515556 ps
T716 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2394182858 Feb 21 02:54:49 PM PST 24 Feb 21 02:54:51 PM PST 24 337457995 ps
T717 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3042005458 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:30 PM PST 24 13822443 ps
T718 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.579765989 Feb 21 02:54:47 PM PST 24 Feb 21 02:54:48 PM PST 24 214459026 ps
T719 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2409713878 Feb 21 02:54:38 PM PST 24 Feb 21 02:54:40 PM PST 24 22045802 ps
T720 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3558465751 Feb 21 02:54:30 PM PST 24 Feb 21 02:54:30 PM PST 24 16093552 ps
T721 /workspace/coverage/cover_reg_top/15.hmac_intr_test.614023813 Feb 21 02:54:53 PM PST 24 Feb 21 02:54:54 PM PST 24 11829179 ps
T100 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1185861103 Feb 21 02:54:27 PM PST 24 Feb 21 02:54:30 PM PST 24 868081585 ps
T722 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.668687661 Feb 21 02:54:55 PM PST 24 Feb 21 02:55:00 PM PST 24 160643053 ps
T149 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.892325753 Feb 21 02:54:29 PM PST 24 Feb 21 02:54:31 PM PST 24 554778650 ps
T101 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2450966736 Feb 21 02:54:46 PM PST 24 Feb 21 02:54:47 PM PST 24 125701428 ps
T723 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1523143892 Feb 21 02:54:42 PM PST 24 Feb 21 02:54:44 PM PST 24 324956827 ps
T724 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2105172123 Feb 21 02:55:04 PM PST 24 Feb 21 02:55:05 PM PST 24 19267470 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2802700945 Feb 21 02:54:29 PM PST 24 Feb 21 02:54:30 PM PST 24 22700407 ps
T725 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1360351400 Feb 21 02:55:08 PM PST 24 Feb 21 02:55:11 PM PST 24 149934685 ps
T726 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3028286899 Feb 21 02:54:38 PM PST 24 Feb 21 02:54:40 PM PST 24 150596237 ps
T727 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2751311304 Feb 21 02:54:29 PM PST 24 Feb 21 02:54:31 PM PST 24 77619096 ps

Test location /workspace/coverage/default/22.hmac_burst_wr.4173550250
Short name T12
Test name
Test status
Simulation time 32670635274 ps
CPU time 48.41 seconds
Started Feb 21 02:14:42 PM PST 24
Finished Feb 21 02:15:31 PM PST 24
Peak memory 199880 kb
Host smart-0c753b9b-729c-494c-b8bf-99710bda90b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173550250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4173550250
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2890197191
Short name T5
Test name
Test status
Simulation time 7359739567 ps
CPU time 340.41 seconds
Started Feb 21 02:13:10 PM PST 24
Finished Feb 21 02:18:51 PM PST 24
Peak memory 215512 kb
Host smart-24d11a50-ed46-4c15-884e-eda92fb0c493
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890197191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2890197191
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2889817879
Short name T21
Test name
Test status
Simulation time 23879332654 ps
CPU time 1142.15 seconds
Started Feb 21 02:17:08 PM PST 24
Finished Feb 21 02:36:10 PM PST 24
Peak memory 240244 kb
Host smart-78613e6d-1d59-4d55-914c-301315adfe50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889817879 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2889817879
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1236119005
Short name T41
Test name
Test status
Simulation time 58747035 ps
CPU time 0.88 seconds
Started Feb 21 02:12:29 PM PST 24
Finished Feb 21 02:12:30 PM PST 24
Peak memory 215680 kb
Host smart-743ad184-843d-4079-992f-3dee86a1723d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236119005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1236119005
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.681385085
Short name T14
Test name
Test status
Simulation time 66012885776 ps
CPU time 1372.55 seconds
Started Feb 21 02:13:57 PM PST 24
Finished Feb 21 02:36:50 PM PST 24
Peak memory 227284 kb
Host smart-baa9b05f-5688-4558-b3a2-8d92cd7b267b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=681385085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.681385085
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2664338779
Short name T144
Test name
Test status
Simulation time 313273329 ps
CPU time 2.58 seconds
Started Feb 21 02:54:38 PM PST 24
Finished Feb 21 02:54:41 PM PST 24
Peak memory 198808 kb
Host smart-777a009c-ac53-4ec3-a33e-07b4312afc40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664338779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2664338779
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/33.hmac_stress_all.558657946
Short name T57
Test name
Test status
Simulation time 161891947584 ps
CPU time 1051.92 seconds
Started Feb 21 02:16:03 PM PST 24
Finished Feb 21 02:33:36 PM PST 24
Peak memory 223260 kb
Host smart-c0d0b4a9-0fda-44eb-b61b-446b28904e62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558657946 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.558657946
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3431532380
Short name T90
Test name
Test status
Simulation time 159978484 ps
CPU time 2.67 seconds
Started Feb 21 02:54:25 PM PST 24
Finished Feb 21 02:54:28 PM PST 24
Peak memory 192916 kb
Host smart-919828a3-11bd-435d-a3ae-d9fe51968ce6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431532380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3431532380
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1076031199
Short name T117
Test name
Test status
Simulation time 4488552200 ps
CPU time 122.96 seconds
Started Feb 21 02:15:26 PM PST 24
Finished Feb 21 02:17:29 PM PST 24
Peak memory 199628 kb
Host smart-c68ea38e-f3ba-47a2-8030-83fd29e89679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1076031199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1076031199
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3600453297
Short name T35
Test name
Test status
Simulation time 14785993 ps
CPU time 0.57 seconds
Started Feb 21 02:12:25 PM PST 24
Finished Feb 21 02:12:26 PM PST 24
Peak memory 193760 kb
Host smart-ee811645-154c-40b1-9fed-3d56d95a0e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600453297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3600453297
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_stress_all.213840665
Short name T136
Test name
Test status
Simulation time 7888670742 ps
CPU time 367.25 seconds
Started Feb 21 02:13:58 PM PST 24
Finished Feb 21 02:20:06 PM PST 24
Peak memory 241636 kb
Host smart-01cd667e-ff9b-4e03-835e-bccfcdc138c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213840665 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.213840665
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1763635998
Short name T108
Test name
Test status
Simulation time 4244754956 ps
CPU time 107.58 seconds
Started Feb 21 02:15:38 PM PST 24
Finished Feb 21 02:17:26 PM PST 24
Peak memory 199624 kb
Host smart-c544e738-3169-46cf-8d24-70f552f0918c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763635998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1763635998
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.726223493
Short name T113
Test name
Test status
Simulation time 1695595910 ps
CPU time 43.1 seconds
Started Feb 21 02:16:03 PM PST 24
Finished Feb 21 02:16:47 PM PST 24
Peak memory 199440 kb
Host smart-0f242f8e-9ce9-4028-973e-3e416370111b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726223493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.726223493
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2677466772
Short name T53
Test name
Test status
Simulation time 191594439 ps
CPU time 1.84 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:32 PM PST 24
Peak memory 198752 kb
Host smart-efb91008-4cd3-4334-98ff-f17ae1eadb6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677466772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2677466772
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1881840543
Short name T150
Test name
Test status
Simulation time 194111123 ps
CPU time 1.96 seconds
Started Feb 21 02:54:54 PM PST 24
Finished Feb 21 02:54:56 PM PST 24
Peak memory 198692 kb
Host smart-73a17821-1fa3-4dc3-a78a-34e396f644b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881840543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1881840543
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_stress_all.759939578
Short name T56
Test name
Test status
Simulation time 20865102448 ps
CPU time 899.37 seconds
Started Feb 21 02:13:21 PM PST 24
Finished Feb 21 02:28:21 PM PST 24
Peak memory 232392 kb
Host smart-1ad6341d-8da4-41b1-9996-b71f50715910
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759939578 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.759939578
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1993373797
Short name T24
Test name
Test status
Simulation time 4669053027 ps
CPU time 104.85 seconds
Started Feb 21 02:14:06 PM PST 24
Finished Feb 21 02:15:51 PM PST 24
Peak memory 199584 kb
Host smart-f5e0cf0d-edc8-49e8-a22e-ae71548abe90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993373797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1993373797
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3218490027
Short name T140
Test name
Test status
Simulation time 25405842015 ps
CPU time 463.82 seconds
Started Feb 21 02:18:08 PM PST 24
Finished Feb 21 02:25:52 PM PST 24
Peak memory 199632 kb
Host smart-9fd04e45-389d-4d87-ab38-c548ce832564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218490027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3218490027
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4275115688
Short name T3
Test name
Test status
Simulation time 2073095090 ps
CPU time 18.08 seconds
Started Feb 21 02:17:06 PM PST 24
Finished Feb 21 02:17:25 PM PST 24
Peak memory 219044 kb
Host smart-828bde6d-589d-49e4-9c61-623ea5598720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4275115688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4275115688
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2937363498
Short name T148
Test name
Test status
Simulation time 74839480 ps
CPU time 1.71 seconds
Started Feb 21 02:54:32 PM PST 24
Finished Feb 21 02:54:34 PM PST 24
Peak memory 198748 kb
Host smart-24110e51-51b7-468c-bf79-2de1b502bd5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937363498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2937363498
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.982377196
Short name T534
Test name
Test status
Simulation time 1012874294 ps
CPU time 47.48 seconds
Started Feb 21 02:14:14 PM PST 24
Finished Feb 21 02:15:02 PM PST 24
Peak memory 199492 kb
Host smart-a00722ba-88b0-493c-aca5-af92dba865e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982377196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.982377196
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2310465879
Short name T138
Test name
Test status
Simulation time 3222415352 ps
CPU time 85.51 seconds
Started Feb 21 02:15:17 PM PST 24
Finished Feb 21 02:16:43 PM PST 24
Peak memory 199584 kb
Host smart-102e87b5-0715-4969-90ed-9d9f15b2756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310465879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2310465879
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2534271257
Short name T133
Test name
Test status
Simulation time 126644539865 ps
CPU time 764.81 seconds
Started Feb 21 02:16:56 PM PST 24
Finished Feb 21 02:29:41 PM PST 24
Peak memory 224276 kb
Host smart-62e00391-5187-4875-99ac-884b24fc0407
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534271257 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2534271257
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_long_msg.744743568
Short name T134
Test name
Test status
Simulation time 5969373970 ps
CPU time 87.41 seconds
Started Feb 21 02:18:02 PM PST 24
Finished Feb 21 02:19:30 PM PST 24
Peak memory 199620 kb
Host smart-0fb1c46c-e13c-43a6-9b5a-8ab7a72e82da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744743568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.744743568
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_stress_all.884595091
Short name T139
Test name
Test status
Simulation time 21862730807 ps
CPU time 265.13 seconds
Started Feb 21 02:12:58 PM PST 24
Finished Feb 21 02:17:24 PM PST 24
Peak memory 199692 kb
Host smart-6f7611b3-08e0-4d16-8cd5-122aeab350f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884595091 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.884595091
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1185861103
Short name T100
Test name
Test status
Simulation time 868081585 ps
CPU time 2.5 seconds
Started Feb 21 02:54:27 PM PST 24
Finished Feb 21 02:54:30 PM PST 24
Peak memory 196268 kb
Host smart-e681cdad-897d-40d4-bbeb-a84d5a84c740
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185861103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1185861103
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1920297074
Short name T618
Test name
Test status
Simulation time 16047659731 ps
CPU time 9.56 seconds
Started Feb 21 02:54:23 PM PST 24
Finished Feb 21 02:54:34 PM PST 24
Peak memory 192572 kb
Host smart-c28f4faa-63a2-4353-93a2-84b1822a12c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920297074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1920297074
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3859676976
Short name T627
Test name
Test status
Simulation time 56438717 ps
CPU time 0.62 seconds
Started Feb 21 02:54:34 PM PST 24
Finished Feb 21 02:54:35 PM PST 24
Peak memory 194328 kb
Host smart-8b5b2853-e7bf-4ef1-9776-8568d12e83bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859676976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3859676976
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3456670734
Short name T600
Test name
Test status
Simulation time 76453461 ps
CPU time 1.28 seconds
Started Feb 21 02:54:26 PM PST 24
Finished Feb 21 02:54:28 PM PST 24
Peak memory 199068 kb
Host smart-00976c99-44cd-4c52-b34b-bedd4859ffca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456670734 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3456670734
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.322242183
Short name T99
Test name
Test status
Simulation time 59811379 ps
CPU time 0.71 seconds
Started Feb 21 02:54:26 PM PST 24
Finished Feb 21 02:54:27 PM PST 24
Peak memory 195136 kb
Host smart-23d9da83-7aec-4d12-8940-c99324834779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322242183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.322242183
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.996130067
Short name T669
Test name
Test status
Simulation time 11973229 ps
CPU time 0.55 seconds
Started Feb 21 02:54:25 PM PST 24
Finished Feb 21 02:54:26 PM PST 24
Peak memory 184184 kb
Host smart-017e5148-9ce2-4a6e-bd4b-248f2de4ac63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996130067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.996130067
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.463934424
Short name T700
Test name
Test status
Simulation time 494076389 ps
CPU time 1.39 seconds
Started Feb 21 02:54:23 PM PST 24
Finished Feb 21 02:54:25 PM PST 24
Peak memory 192728 kb
Host smart-f557dd4f-bd36-4e4e-bd5c-f41cdc56b547
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463934424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.463934424
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1662098621
Short name T647
Test name
Test status
Simulation time 155586067 ps
CPU time 3.4 seconds
Started Feb 21 02:54:31 PM PST 24
Finished Feb 21 02:54:34 PM PST 24
Peak memory 199124 kb
Host smart-a068b61a-4b4a-4bac-94df-98fbd90403b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662098621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1662098621
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1785751997
Short name T678
Test name
Test status
Simulation time 2707845893 ps
CPU time 9.05 seconds
Started Feb 21 02:54:25 PM PST 24
Finished Feb 21 02:54:35 PM PST 24
Peak memory 192704 kb
Host smart-dc9555c4-61a8-4273-8515-af8cf26658a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785751997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1785751997
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3060145607
Short name T645
Test name
Test status
Simulation time 37119331 ps
CPU time 0.69 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:31 PM PST 24
Peak memory 194600 kb
Host smart-828a3585-a20c-45b8-a3f5-59a351d757e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060145607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3060145607
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.97637414
Short name T622
Test name
Test status
Simulation time 25738416216 ps
CPU time 168.4 seconds
Started Feb 21 02:54:26 PM PST 24
Finished Feb 21 02:57:15 PM PST 24
Peak memory 207588 kb
Host smart-01b07c04-73a1-4e7f-9fa1-46c388798c68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97637414 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.97637414
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3514355681
Short name T668
Test name
Test status
Simulation time 19814533 ps
CPU time 0.73 seconds
Started Feb 21 02:54:28 PM PST 24
Finished Feb 21 02:54:29 PM PST 24
Peak memory 194908 kb
Host smart-cf8c2c29-4b35-401c-9b43-ce0fbc223891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514355681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3514355681
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3558465751
Short name T720
Test name
Test status
Simulation time 16093552 ps
CPU time 0.58 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:30 PM PST 24
Peak memory 184152 kb
Host smart-2c1ca743-a119-40c3-9fa4-f4405b906602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558465751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3558465751
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2751311304
Short name T727
Test name
Test status
Simulation time 77619096 ps
CPU time 1.31 seconds
Started Feb 21 02:54:29 PM PST 24
Finished Feb 21 02:54:31 PM PST 24
Peak memory 192652 kb
Host smart-643f19d6-5e0a-4074-bf7b-546fb87e46bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751311304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2751311304
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2703733310
Short name T609
Test name
Test status
Simulation time 160711342 ps
CPU time 1.95 seconds
Started Feb 21 02:54:24 PM PST 24
Finished Feb 21 02:54:27 PM PST 24
Peak memory 199100 kb
Host smart-a9952d3a-8f98-4181-8d4e-851ce5c1918d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703733310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2703733310
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4042828405
Short name T146
Test name
Test status
Simulation time 1240076076 ps
CPU time 2.52 seconds
Started Feb 21 02:54:29 PM PST 24
Finished Feb 21 02:54:32 PM PST 24
Peak memory 199100 kb
Host smart-272292f1-3502-4754-8aa4-c3ebc4d9d3ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042828405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.4042828405
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2713139117
Short name T646
Test name
Test status
Simulation time 511972526 ps
CPU time 3.7 seconds
Started Feb 21 02:54:35 PM PST 24
Finished Feb 21 02:54:40 PM PST 24
Peak memory 199132 kb
Host smart-af4d7a9e-8d6e-4263-a71c-430da726a78d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713139117 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2713139117
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3046725802
Short name T660
Test name
Test status
Simulation time 61311076 ps
CPU time 0.73 seconds
Started Feb 21 02:54:44 PM PST 24
Finished Feb 21 02:54:45 PM PST 24
Peak memory 194804 kb
Host smart-15a76460-8bb8-4f62-ac1e-ba7060822a3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046725802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3046725802
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1749971796
Short name T654
Test name
Test status
Simulation time 12884629 ps
CPU time 0.56 seconds
Started Feb 21 02:54:29 PM PST 24
Finished Feb 21 02:54:29 PM PST 24
Peak memory 184212 kb
Host smart-0125bbab-4309-4ed6-918b-5d0fff9e611f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749971796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1749971796
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3246892572
Short name T709
Test name
Test status
Simulation time 80510947 ps
CPU time 1.5 seconds
Started Feb 21 02:54:35 PM PST 24
Finished Feb 21 02:54:37 PM PST 24
Peak memory 192700 kb
Host smart-ffd2ad3a-d506-4b23-baa0-4ecb401811bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246892572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3246892572
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1730058906
Short name T617
Test name
Test status
Simulation time 208029298 ps
CPU time 2.58 seconds
Started Feb 21 02:54:38 PM PST 24
Finished Feb 21 02:54:41 PM PST 24
Peak memory 199136 kb
Host smart-86cf66e8-e002-4992-9566-bc87ac6beb99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730058906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1730058906
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.444989371
Short name T54
Test name
Test status
Simulation time 218373827 ps
CPU time 1.22 seconds
Started Feb 21 02:54:39 PM PST 24
Finished Feb 21 02:54:41 PM PST 24
Peak memory 198276 kb
Host smart-6cdfe2f5-eb8b-4850-8cd8-6d80f13f879d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444989371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.444989371
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2656848023
Short name T651
Test name
Test status
Simulation time 984509630 ps
CPU time 2.38 seconds
Started Feb 21 02:54:38 PM PST 24
Finished Feb 21 02:54:41 PM PST 24
Peak memory 199116 kb
Host smart-75232746-07b0-4dea-840a-5b20ae2c18eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656848023 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2656848023
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3280448128
Short name T652
Test name
Test status
Simulation time 20171326 ps
CPU time 0.72 seconds
Started Feb 21 02:54:47 PM PST 24
Finished Feb 21 02:54:48 PM PST 24
Peak memory 195020 kb
Host smart-7d5a28df-da2c-4e87-a605-6ebcb372b470
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280448128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3280448128
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3246339847
Short name T628
Test name
Test status
Simulation time 64531128 ps
CPU time 0.61 seconds
Started Feb 21 02:54:35 PM PST 24
Finished Feb 21 02:54:37 PM PST 24
Peak memory 184184 kb
Host smart-4f05694b-307f-45b6-b3ef-f78aea0a1f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246339847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3246339847
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1750050872
Short name T602
Test name
Test status
Simulation time 51286976 ps
CPU time 0.81 seconds
Started Feb 21 02:54:35 PM PST 24
Finished Feb 21 02:54:37 PM PST 24
Peak memory 192504 kb
Host smart-b9f04464-8c82-4aa0-bc97-b86be7cd9822
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750050872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1750050872
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3988755141
Short name T594
Test name
Test status
Simulation time 175738448 ps
CPU time 3.18 seconds
Started Feb 21 02:54:44 PM PST 24
Finished Feb 21 02:54:48 PM PST 24
Peak memory 199140 kb
Host smart-c9d33f20-aa12-460d-a90f-de77e5dcd9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988755141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3988755141
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.684226595
Short name T638
Test name
Test status
Simulation time 35871588 ps
CPU time 1.32 seconds
Started Feb 21 02:54:48 PM PST 24
Finished Feb 21 02:54:49 PM PST 24
Peak memory 198788 kb
Host smart-01aee545-1328-4f6e-8de5-5536a6912749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684226595 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.684226595
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.77205897
Short name T93
Test name
Test status
Simulation time 70944576 ps
CPU time 0.74 seconds
Started Feb 21 02:55:04 PM PST 24
Finished Feb 21 02:55:05 PM PST 24
Peak memory 195360 kb
Host smart-9b38894c-3972-4c46-bbf0-0199910f44e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77205897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.77205897
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.787076260
Short name T698
Test name
Test status
Simulation time 50267141 ps
CPU time 0.63 seconds
Started Feb 21 02:54:47 PM PST 24
Finished Feb 21 02:54:48 PM PST 24
Peak memory 184172 kb
Host smart-2704d23d-2831-4c56-bdca-f4c461f6f078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787076260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.787076260
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3719103518
Short name T665
Test name
Test status
Simulation time 36421965 ps
CPU time 0.82 seconds
Started Feb 21 02:54:45 PM PST 24
Finished Feb 21 02:54:46 PM PST 24
Peak memory 192496 kb
Host smart-18d34a2c-8070-4ddd-8521-e19330e0250d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719103518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3719103518
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2707846670
Short name T675
Test name
Test status
Simulation time 128896847 ps
CPU time 2.92 seconds
Started Feb 21 02:54:51 PM PST 24
Finished Feb 21 02:54:54 PM PST 24
Peak memory 199128 kb
Host smart-03088710-0c61-4300-a0b9-bd02722f2395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707846670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2707846670
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3884872384
Short name T666
Test name
Test status
Simulation time 195773685 ps
CPU time 1.76 seconds
Started Feb 21 02:55:02 PM PST 24
Finished Feb 21 02:55:04 PM PST 24
Peak memory 198512 kb
Host smart-17d926e1-31c3-4bc3-918a-ea4f4e2ab8d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884872384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3884872384
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4140744689
Short name T650
Test name
Test status
Simulation time 84128234104 ps
CPU time 412.25 seconds
Started Feb 21 02:54:44 PM PST 24
Finished Feb 21 03:01:37 PM PST 24
Peak memory 203184 kb
Host smart-069fab8e-81fc-4de7-9ad4-31317ecb1d90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140744689 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.4140744689
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3977078409
Short name T681
Test name
Test status
Simulation time 38488834 ps
CPU time 0.68 seconds
Started Feb 21 02:54:54 PM PST 24
Finished Feb 21 02:54:55 PM PST 24
Peak memory 194668 kb
Host smart-8cd5ec11-f38d-490a-805d-5edbdf5c90fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977078409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3977078409
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3460021862
Short name T648
Test name
Test status
Simulation time 90683423 ps
CPU time 0.58 seconds
Started Feb 21 02:55:08 PM PST 24
Finished Feb 21 02:55:10 PM PST 24
Peak memory 184228 kb
Host smart-a0640ad6-b72a-400c-bbb2-2fe0f8260513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460021862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3460021862
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.559156906
Short name T670
Test name
Test status
Simulation time 66459083 ps
CPU time 1.23 seconds
Started Feb 21 02:54:49 PM PST 24
Finished Feb 21 02:54:51 PM PST 24
Peak memory 192700 kb
Host smart-6a1a3561-903b-459d-b620-372a63685b5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559156906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.559156906
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3151632010
Short name T693
Test name
Test status
Simulation time 59605279 ps
CPU time 1.61 seconds
Started Feb 21 02:54:51 PM PST 24
Finished Feb 21 02:54:53 PM PST 24
Peak memory 199092 kb
Host smart-de2d659c-8f0a-4e2e-bc47-2acb9594e977
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151632010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3151632010
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.4140583092
Short name T151
Test name
Test status
Simulation time 102518801 ps
CPU time 1.17 seconds
Started Feb 21 02:55:12 PM PST 24
Finished Feb 21 02:55:13 PM PST 24
Peak memory 198236 kb
Host smart-e54edc4e-5cd0-4305-a679-2ede0884d36a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140583092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.4140583092
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2394182858
Short name T716
Test name
Test status
Simulation time 337457995 ps
CPU time 1.3 seconds
Started Feb 21 02:54:49 PM PST 24
Finished Feb 21 02:54:51 PM PST 24
Peak memory 199004 kb
Host smart-5c23417d-03d0-4d80-8e59-e83c4a0add4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394182858 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2394182858
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2450966736
Short name T101
Test name
Test status
Simulation time 125701428 ps
CPU time 0.75 seconds
Started Feb 21 02:54:46 PM PST 24
Finished Feb 21 02:54:47 PM PST 24
Peak memory 195148 kb
Host smart-59bf21c3-85e1-4fa4-b7d5-36e8de6c0f33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450966736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2450966736
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.705419634
Short name T715
Test name
Test status
Simulation time 11694415 ps
CPU time 0.6 seconds
Started Feb 21 02:54:54 PM PST 24
Finished Feb 21 02:54:55 PM PST 24
Peak memory 184200 kb
Host smart-4227250c-9f58-4898-a672-5ab5f9924600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705419634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.705419634
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1171294287
Short name T623
Test name
Test status
Simulation time 21785219 ps
CPU time 0.81 seconds
Started Feb 21 02:54:51 PM PST 24
Finished Feb 21 02:54:52 PM PST 24
Peak memory 195768 kb
Host smart-61f94e44-50a3-4222-a3d5-cb0090dd5c4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171294287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1171294287
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2493151653
Short name T663
Test name
Test status
Simulation time 2198710649 ps
CPU time 2.62 seconds
Started Feb 21 02:55:06 PM PST 24
Finished Feb 21 02:55:09 PM PST 24
Peak memory 199204 kb
Host smart-3e3da4db-bce1-4654-986a-7f20fd92a9e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493151653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2493151653
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2252304685
Short name T680
Test name
Test status
Simulation time 281210074 ps
CPU time 2.22 seconds
Started Feb 21 02:54:51 PM PST 24
Finished Feb 21 02:54:54 PM PST 24
Peak memory 199120 kb
Host smart-c1ab4177-c746-4d7b-bf35-0f48971f0aa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252304685 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2252304685
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3586682397
Short name T691
Test name
Test status
Simulation time 55620063 ps
CPU time 0.66 seconds
Started Feb 21 02:55:04 PM PST 24
Finished Feb 21 02:55:05 PM PST 24
Peak memory 194836 kb
Host smart-a2d58fef-4b4d-4e38-a6b7-f7437a37a431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586682397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3586682397
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.614023813
Short name T721
Test name
Test status
Simulation time 11829179 ps
CPU time 0.58 seconds
Started Feb 21 02:54:53 PM PST 24
Finished Feb 21 02:54:54 PM PST 24
Peak memory 184164 kb
Host smart-c8f2cb0c-f9a8-414f-a80f-91339d6c7d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614023813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.614023813
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3757098637
Short name T708
Test name
Test status
Simulation time 85969326 ps
CPU time 1.05 seconds
Started Feb 21 02:54:50 PM PST 24
Finished Feb 21 02:54:51 PM PST 24
Peak memory 192700 kb
Host smart-22802f32-66f7-4c74-a48f-b75d68dd25bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757098637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3757098637
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.579765989
Short name T718
Test name
Test status
Simulation time 214459026 ps
CPU time 1.34 seconds
Started Feb 21 02:54:47 PM PST 24
Finished Feb 21 02:54:48 PM PST 24
Peak memory 198008 kb
Host smart-ea9dfa21-d054-4651-8336-c787b15a670a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579765989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.579765989
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2641206504
Short name T145
Test name
Test status
Simulation time 119005561 ps
CPU time 1.87 seconds
Started Feb 21 02:54:52 PM PST 24
Finished Feb 21 02:54:54 PM PST 24
Peak memory 198748 kb
Host smart-91e68c02-b795-49c0-80a5-6a03b24947ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641206504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2641206504
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1967677111
Short name T657
Test name
Test status
Simulation time 43771989182 ps
CPU time 133.98 seconds
Started Feb 21 02:54:55 PM PST 24
Finished Feb 21 02:57:09 PM PST 24
Peak memory 199184 kb
Host smart-64cbdf13-3b9a-4e02-814a-314c742e313f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967677111 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1967677111
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3473548542
Short name T639
Test name
Test status
Simulation time 20284208 ps
CPU time 0.75 seconds
Started Feb 21 02:55:06 PM PST 24
Finished Feb 21 02:55:07 PM PST 24
Peak memory 195044 kb
Host smart-32e846ab-8a20-4b00-b300-9171e8619c08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473548542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3473548542
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3923696644
Short name T687
Test name
Test status
Simulation time 15306520 ps
CPU time 0.65 seconds
Started Feb 21 02:55:08 PM PST 24
Finished Feb 21 02:55:09 PM PST 24
Peak memory 184196 kb
Host smart-1c1b13a6-8869-41af-9e0f-d2321f4dd20f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923696644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3923696644
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1989578988
Short name T599
Test name
Test status
Simulation time 31122136 ps
CPU time 0.82 seconds
Started Feb 21 02:54:52 PM PST 24
Finished Feb 21 02:54:53 PM PST 24
Peak memory 192484 kb
Host smart-5568245b-7fc5-4aa7-b4bb-96691bf7523f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989578988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1989578988
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2594290835
Short name T702
Test name
Test status
Simulation time 360089370 ps
CPU time 1.45 seconds
Started Feb 21 02:54:53 PM PST 24
Finished Feb 21 02:54:55 PM PST 24
Peak memory 198068 kb
Host smart-5903dfaf-1573-4c1f-9f73-b73055922113
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594290835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2594290835
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.701222327
Short name T153
Test name
Test status
Simulation time 145179539 ps
CPU time 1.74 seconds
Started Feb 21 02:54:52 PM PST 24
Finished Feb 21 02:54:54 PM PST 24
Peak memory 198636 kb
Host smart-e01397db-57ed-4401-8c90-5034d42367c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701222327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.701222327
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1652067511
Short name T677
Test name
Test status
Simulation time 206980174 ps
CPU time 3.85 seconds
Started Feb 21 02:54:52 PM PST 24
Finished Feb 21 02:54:56 PM PST 24
Peak memory 199112 kb
Host smart-7e9c3db3-19b5-4af1-8533-f4a98c4e32ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652067511 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1652067511
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1067402178
Short name T674
Test name
Test status
Simulation time 59109459 ps
CPU time 0.7 seconds
Started Feb 21 02:55:03 PM PST 24
Finished Feb 21 02:55:04 PM PST 24
Peak memory 194980 kb
Host smart-0b670197-38e9-4fea-99e0-513e3b267644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067402178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1067402178
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3412488447
Short name T688
Test name
Test status
Simulation time 16498994 ps
CPU time 0.61 seconds
Started Feb 21 02:54:44 PM PST 24
Finished Feb 21 02:54:45 PM PST 24
Peak memory 184208 kb
Host smart-4b7b3c79-9dd3-47b0-acd3-85aefb3492c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412488447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3412488447
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3725091813
Short name T706
Test name
Test status
Simulation time 138772742 ps
CPU time 1.17 seconds
Started Feb 21 02:54:59 PM PST 24
Finished Feb 21 02:55:01 PM PST 24
Peak memory 192696 kb
Host smart-5788f577-7e49-47fe-8336-47904b04b6e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725091813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3725091813
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.668687661
Short name T722
Test name
Test status
Simulation time 160643053 ps
CPU time 4.04 seconds
Started Feb 21 02:54:55 PM PST 24
Finished Feb 21 02:55:00 PM PST 24
Peak memory 199136 kb
Host smart-3c15ff11-73a6-4d8c-94f6-24f3c441833e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668687661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.668687661
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2980289603
Short name T147
Test name
Test status
Simulation time 64364521 ps
CPU time 1.23 seconds
Started Feb 21 02:54:55 PM PST 24
Finished Feb 21 02:54:56 PM PST 24
Peak memory 198400 kb
Host smart-c4883986-37c7-4bac-b078-2be546114dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980289603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2980289603
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1728602610
Short name T620
Test name
Test status
Simulation time 66634360 ps
CPU time 4.39 seconds
Started Feb 21 02:55:08 PM PST 24
Finished Feb 21 02:55:13 PM PST 24
Peak memory 199128 kb
Host smart-a2dfa762-4c1f-498e-9035-cb8f7cebc10c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728602610 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1728602610
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2072104201
Short name T94
Test name
Test status
Simulation time 21296870 ps
CPU time 0.73 seconds
Started Feb 21 02:54:44 PM PST 24
Finished Feb 21 02:54:45 PM PST 24
Peak memory 195160 kb
Host smart-9bfe5220-49cf-4ff5-a331-54c888e46f98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072104201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2072104201
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3986668883
Short name T686
Test name
Test status
Simulation time 24515978 ps
CPU time 0.61 seconds
Started Feb 21 02:55:06 PM PST 24
Finished Feb 21 02:55:07 PM PST 24
Peak memory 184192 kb
Host smart-b4e24043-b317-492e-a8e8-8c3e6aea721d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986668883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3986668883
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3244901319
Short name T667
Test name
Test status
Simulation time 273428913 ps
CPU time 1.33 seconds
Started Feb 21 02:55:01 PM PST 24
Finished Feb 21 02:55:02 PM PST 24
Peak memory 197044 kb
Host smart-61dbb07e-3c52-49df-9bec-3a1ed9aaf2ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244901319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3244901319
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3740128259
Short name T644
Test name
Test status
Simulation time 860282711 ps
CPU time 4.06 seconds
Started Feb 21 02:54:53 PM PST 24
Finished Feb 21 02:54:58 PM PST 24
Peak memory 199132 kb
Host smart-e9a41963-439f-4481-a576-80d96b3369e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740128259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3740128259
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2844061390
Short name T714
Test name
Test status
Simulation time 239652979 ps
CPU time 1.26 seconds
Started Feb 21 02:54:54 PM PST 24
Finished Feb 21 02:54:55 PM PST 24
Peak memory 198412 kb
Host smart-38d83683-db2b-43c6-900a-f3bdca40aa80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844061390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2844061390
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4228388606
Short name T656
Test name
Test status
Simulation time 293312450 ps
CPU time 2.49 seconds
Started Feb 21 02:54:57 PM PST 24
Finished Feb 21 02:55:00 PM PST 24
Peak memory 199120 kb
Host smart-7ef91a1b-a845-4023-a472-5844ad8e71ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228388606 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4228388606
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3302006915
Short name T102
Test name
Test status
Simulation time 38411035 ps
CPU time 0.65 seconds
Started Feb 21 02:54:51 PM PST 24
Finished Feb 21 02:54:51 PM PST 24
Peak memory 194240 kb
Host smart-05bf8bc7-1f6c-4c42-8ac1-939b43f6f9ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302006915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3302006915
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.286916444
Short name T633
Test name
Test status
Simulation time 111309676 ps
CPU time 0.58 seconds
Started Feb 21 02:55:01 PM PST 24
Finished Feb 21 02:55:02 PM PST 24
Peak memory 184132 kb
Host smart-524fe759-b5a0-4cc7-8793-759924bc7c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286916444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.286916444
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2956196522
Short name T705
Test name
Test status
Simulation time 56716252 ps
CPU time 1.32 seconds
Started Feb 21 02:55:00 PM PST 24
Finished Feb 21 02:55:01 PM PST 24
Peak memory 197268 kb
Host smart-085f7385-1b39-4bec-be9b-82ddf14e0bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956196522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2956196522
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1360351400
Short name T725
Test name
Test status
Simulation time 149934685 ps
CPU time 1.87 seconds
Started Feb 21 02:55:08 PM PST 24
Finished Feb 21 02:55:11 PM PST 24
Peak memory 199028 kb
Host smart-240b5d54-ca9e-415f-8ded-4c0ae819b2ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360351400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1360351400
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2257539999
Short name T664
Test name
Test status
Simulation time 65706471 ps
CPU time 1.24 seconds
Started Feb 21 02:54:45 PM PST 24
Finished Feb 21 02:54:47 PM PST 24
Peak memory 198552 kb
Host smart-cd0c1095-9286-4bbf-a689-89138d7c8b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257539999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2257539999
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3152663892
Short name T95
Test name
Test status
Simulation time 113894502 ps
CPU time 2 seconds
Started Feb 21 02:54:34 PM PST 24
Finished Feb 21 02:54:37 PM PST 24
Peak memory 192660 kb
Host smart-9100c2da-1612-474b-a8fc-946a9e2719d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152663892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3152663892
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1143957816
Short name T91
Test name
Test status
Simulation time 137083819 ps
CPU time 5.62 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:36 PM PST 24
Peak memory 192656 kb
Host smart-20816f61-beb2-4246-a6e6-82872a3ee7c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143957816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1143957816
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2046663028
Short name T697
Test name
Test status
Simulation time 16159849 ps
CPU time 0.62 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:31 PM PST 24
Peak memory 194352 kb
Host smart-c4b6c4e2-b176-4ab4-a112-dcc61d160f53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046663028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2046663028
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2852970111
Short name T614
Test name
Test status
Simulation time 250605639 ps
CPU time 1.36 seconds
Started Feb 21 02:54:26 PM PST 24
Finished Feb 21 02:54:28 PM PST 24
Peak memory 199124 kb
Host smart-c936fa05-d139-4202-81b7-55ef0b7f2b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852970111 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2852970111
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.536982220
Short name T597
Test name
Test status
Simulation time 87923560 ps
CPU time 0.61 seconds
Started Feb 21 02:54:34 PM PST 24
Finished Feb 21 02:54:35 PM PST 24
Peak memory 194244 kb
Host smart-2f3adbb3-c1c5-458a-8b4b-868dbe69e355
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536982220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.536982220
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.737065598
Short name T624
Test name
Test status
Simulation time 19998125 ps
CPU time 0.62 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:31 PM PST 24
Peak memory 184196 kb
Host smart-853e7611-b25d-4b79-b0d6-2594ba649338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737065598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.737065598
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2603036713
Short name T641
Test name
Test status
Simulation time 16864194 ps
CPU time 0.83 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:31 PM PST 24
Peak memory 195836 kb
Host smart-a34bf13e-3122-44f8-a1a6-4cae15301cb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603036713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2603036713
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.987101520
Short name T690
Test name
Test status
Simulation time 65532738 ps
CPU time 3.62 seconds
Started Feb 21 02:54:29 PM PST 24
Finished Feb 21 02:54:33 PM PST 24
Peak memory 199104 kb
Host smart-f844baa3-4ebc-4810-83a6-643f7efe10b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987101520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.987101520
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.892325753
Short name T149
Test name
Test status
Simulation time 554778650 ps
CPU time 2.34 seconds
Started Feb 21 02:54:29 PM PST 24
Finished Feb 21 02:54:31 PM PST 24
Peak memory 198672 kb
Host smart-0ad8df94-a9b1-4fd5-9044-09bb0ae9523a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892325753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.892325753
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.97899686
Short name T595
Test name
Test status
Simulation time 15122410 ps
CPU time 0.56 seconds
Started Feb 21 02:55:04 PM PST 24
Finished Feb 21 02:55:05 PM PST 24
Peak memory 184208 kb
Host smart-65fee0ae-089f-4961-affa-ee17f63e9297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97899686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.97899686
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3512901957
Short name T673
Test name
Test status
Simulation time 15036900 ps
CPU time 0.61 seconds
Started Feb 21 02:54:55 PM PST 24
Finished Feb 21 02:54:55 PM PST 24
Peak memory 184200 kb
Host smart-46868bb6-f58d-4e42-b990-02dbd7c58788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512901957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3512901957
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.276045337
Short name T632
Test name
Test status
Simulation time 19294363 ps
CPU time 0.58 seconds
Started Feb 21 02:54:59 PM PST 24
Finished Feb 21 02:55:00 PM PST 24
Peak memory 184168 kb
Host smart-d8e61858-2383-48e8-bec1-1580eede03b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276045337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.276045337
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2734514427
Short name T685
Test name
Test status
Simulation time 44871756 ps
CPU time 0.65 seconds
Started Feb 21 02:55:08 PM PST 24
Finished Feb 21 02:55:10 PM PST 24
Peak memory 184204 kb
Host smart-78a2f23d-cb38-4f23-9320-338f6d75894a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734514427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2734514427
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1328876596
Short name T615
Test name
Test status
Simulation time 18380413 ps
CPU time 0.61 seconds
Started Feb 21 02:55:03 PM PST 24
Finished Feb 21 02:55:04 PM PST 24
Peak memory 184172 kb
Host smart-62053138-cb8c-4e43-ab43-8371f8cdabb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328876596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1328876596
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3229035373
Short name T703
Test name
Test status
Simulation time 90304253 ps
CPU time 0.6 seconds
Started Feb 21 02:55:08 PM PST 24
Finished Feb 21 02:55:09 PM PST 24
Peak memory 184228 kb
Host smart-4f1c75b5-462e-4b7c-8e07-c99f153fba7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229035373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3229035373
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1211312192
Short name T642
Test name
Test status
Simulation time 13909964 ps
CPU time 0.59 seconds
Started Feb 21 02:55:03 PM PST 24
Finished Feb 21 02:55:04 PM PST 24
Peak memory 184180 kb
Host smart-2fdc2c3b-db40-4e03-bc3d-9857a7f4b6e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211312192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1211312192
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2723804502
Short name T701
Test name
Test status
Simulation time 114146489 ps
CPU time 0.59 seconds
Started Feb 21 02:55:12 PM PST 24
Finished Feb 21 02:55:13 PM PST 24
Peak memory 184188 kb
Host smart-dfc7daf5-e8dc-4b78-ad72-e6424e77d141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723804502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2723804502
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.546681247
Short name T643
Test name
Test status
Simulation time 17992669 ps
CPU time 0.64 seconds
Started Feb 21 02:55:02 PM PST 24
Finished Feb 21 02:55:03 PM PST 24
Peak memory 184204 kb
Host smart-e976ecba-2bad-4141-9ab2-7034508dc8c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546681247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.546681247
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.556442107
Short name T713
Test name
Test status
Simulation time 179026285 ps
CPU time 0.63 seconds
Started Feb 21 02:55:07 PM PST 24
Finished Feb 21 02:55:08 PM PST 24
Peak memory 184200 kb
Host smart-6cc444dd-9d7d-4810-90e2-7efa72bb3f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556442107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.556442107
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2004272355
Short name T611
Test name
Test status
Simulation time 358064033 ps
CPU time 1.18 seconds
Started Feb 21 02:54:28 PM PST 24
Finished Feb 21 02:54:29 PM PST 24
Peak memory 184548 kb
Host smart-be403bd8-7cf6-450f-9124-87afac4a5bcb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004272355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2004272355
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2446259530
Short name T608
Test name
Test status
Simulation time 234535089 ps
CPU time 3.55 seconds
Started Feb 21 02:54:29 PM PST 24
Finished Feb 21 02:54:33 PM PST 24
Peak memory 192648 kb
Host smart-e479301a-10e0-4ec1-b0dc-5c68e7bfba49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446259530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2446259530
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.521889865
Short name T97
Test name
Test status
Simulation time 19715974 ps
CPU time 0.72 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:31 PM PST 24
Peak memory 194768 kb
Host smart-fb3f581b-d137-4258-9456-340b3cc75329
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521889865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.521889865
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.208721927
Short name T610
Test name
Test status
Simulation time 73809773 ps
CPU time 2.3 seconds
Started Feb 21 02:54:26 PM PST 24
Finished Feb 21 02:54:29 PM PST 24
Peak memory 199076 kb
Host smart-c32fe087-73be-4bb1-888c-3e7e9a8000e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208721927 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.208721927
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3184116505
Short name T699
Test name
Test status
Simulation time 284624261 ps
CPU time 0.74 seconds
Started Feb 21 02:54:27 PM PST 24
Finished Feb 21 02:54:28 PM PST 24
Peak memory 195152 kb
Host smart-41ae95bc-003d-48c7-a949-73fc179ddf21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184116505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3184116505
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3042005458
Short name T717
Test name
Test status
Simulation time 13822443 ps
CPU time 0.55 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:30 PM PST 24
Peak memory 184164 kb
Host smart-6f2139d0-2334-4ad2-b45f-948f57603af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042005458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3042005458
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1950602042
Short name T631
Test name
Test status
Simulation time 33317657 ps
CPU time 1.31 seconds
Started Feb 21 02:54:23 PM PST 24
Finished Feb 21 02:54:25 PM PST 24
Peak memory 197008 kb
Host smart-090ea8f4-9c2c-4471-9ce6-940b0824a6ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950602042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1950602042
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3280641663
Short name T662
Test name
Test status
Simulation time 89812570 ps
CPU time 1.33 seconds
Started Feb 21 02:54:29 PM PST 24
Finished Feb 21 02:54:30 PM PST 24
Peak memory 199124 kb
Host smart-07deb8f9-8fe4-4997-afec-c30b2983352f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280641663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3280641663
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.381381046
Short name T694
Test name
Test status
Simulation time 178492811 ps
CPU time 1.76 seconds
Started Feb 21 02:54:24 PM PST 24
Finished Feb 21 02:54:26 PM PST 24
Peak memory 198728 kb
Host smart-2c650956-6e64-4d45-8631-0bb748b9e0d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381381046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.381381046
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.287867323
Short name T601
Test name
Test status
Simulation time 136505437 ps
CPU time 0.62 seconds
Started Feb 21 02:55:06 PM PST 24
Finished Feb 21 02:55:07 PM PST 24
Peak memory 184180 kb
Host smart-9a915022-9411-4a37-a6d2-ef4ed69e8cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287867323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.287867323
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2462066869
Short name T607
Test name
Test status
Simulation time 58958394 ps
CPU time 0.58 seconds
Started Feb 21 02:55:11 PM PST 24
Finished Feb 21 02:55:12 PM PST 24
Peak memory 184200 kb
Host smart-320d342f-09ef-4e9b-96a7-5b5fc0f712ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462066869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2462066869
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.596721392
Short name T712
Test name
Test status
Simulation time 17256781 ps
CPU time 0.59 seconds
Started Feb 21 02:55:06 PM PST 24
Finished Feb 21 02:55:07 PM PST 24
Peak memory 184200 kb
Host smart-b2a310ac-f436-467d-b6e9-0ba0ed2b66a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596721392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.596721392
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3357378970
Short name T605
Test name
Test status
Simulation time 20055419 ps
CPU time 0.58 seconds
Started Feb 21 02:55:14 PM PST 24
Finished Feb 21 02:55:15 PM PST 24
Peak memory 184180 kb
Host smart-4a499156-85b3-48cc-8075-17f5c473aadb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357378970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3357378970
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1232177911
Short name T689
Test name
Test status
Simulation time 35335686 ps
CPU time 0.61 seconds
Started Feb 21 02:55:01 PM PST 24
Finished Feb 21 02:55:02 PM PST 24
Peak memory 184192 kb
Host smart-071ff812-9930-477d-ad33-3efa11343329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232177911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1232177911
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3548389928
Short name T661
Test name
Test status
Simulation time 12390045 ps
CPU time 0.57 seconds
Started Feb 21 02:55:07 PM PST 24
Finished Feb 21 02:55:08 PM PST 24
Peak memory 184200 kb
Host smart-2b6e7e2a-c363-477a-b822-5c5f06864736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548389928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3548389928
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2105172123
Short name T724
Test name
Test status
Simulation time 19267470 ps
CPU time 0.6 seconds
Started Feb 21 02:55:04 PM PST 24
Finished Feb 21 02:55:05 PM PST 24
Peak memory 184188 kb
Host smart-edea9f11-df6f-4713-bfde-9f0c842cc4e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105172123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2105172123
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2048282844
Short name T711
Test name
Test status
Simulation time 23207850 ps
CPU time 0.59 seconds
Started Feb 21 02:55:07 PM PST 24
Finished Feb 21 02:55:09 PM PST 24
Peak memory 184184 kb
Host smart-ed6809e9-99d2-443d-9a24-ee2c54a4f058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048282844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2048282844
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.730943709
Short name T683
Test name
Test status
Simulation time 14716019 ps
CPU time 0.61 seconds
Started Feb 21 02:55:08 PM PST 24
Finished Feb 21 02:55:10 PM PST 24
Peak memory 184188 kb
Host smart-45a53d1d-3250-4f9c-9f52-b6ebade6e707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730943709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.730943709
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2551275966
Short name T637
Test name
Test status
Simulation time 13812358 ps
CPU time 0.61 seconds
Started Feb 21 02:55:08 PM PST 24
Finished Feb 21 02:55:10 PM PST 24
Peak memory 184156 kb
Host smart-033eb836-a579-497f-b173-140622282adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551275966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2551275966
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1012842212
Short name T96
Test name
Test status
Simulation time 46560709 ps
CPU time 1.22 seconds
Started Feb 21 02:54:32 PM PST 24
Finished Feb 21 02:54:34 PM PST 24
Peak memory 195144 kb
Host smart-6c0cdec5-babb-47f5-aff5-d0eea73dfaa7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012842212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1012842212
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.709775707
Short name T88
Test name
Test status
Simulation time 762325810 ps
CPU time 8.34 seconds
Started Feb 21 02:54:36 PM PST 24
Finished Feb 21 02:54:45 PM PST 24
Peak memory 192688 kb
Host smart-be3eca12-5c57-4807-9c16-7d8f4816e68e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709775707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.709775707
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3413330665
Short name T89
Test name
Test status
Simulation time 26819402 ps
CPU time 0.75 seconds
Started Feb 21 02:54:33 PM PST 24
Finished Feb 21 02:54:34 PM PST 24
Peak memory 194940 kb
Host smart-cd6e0bf1-7e8c-4ba1-ac62-4312be42a832
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413330665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3413330665
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1771585983
Short name T704
Test name
Test status
Simulation time 31050914827 ps
CPU time 48.98 seconds
Started Feb 21 02:54:44 PM PST 24
Finished Feb 21 02:55:33 PM PST 24
Peak memory 207012 kb
Host smart-9c0e40e2-ce55-430b-a7c7-3f9349c87b3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771585983 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1771585983
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2802700945
Short name T103
Test name
Test status
Simulation time 22700407 ps
CPU time 0.69 seconds
Started Feb 21 02:54:29 PM PST 24
Finished Feb 21 02:54:30 PM PST 24
Peak memory 195160 kb
Host smart-699d66bc-d97f-4344-8281-a75e1188d67d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802700945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2802700945
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2521898774
Short name T649
Test name
Test status
Simulation time 41027408 ps
CPU time 0.63 seconds
Started Feb 21 02:54:37 PM PST 24
Finished Feb 21 02:54:38 PM PST 24
Peak memory 184196 kb
Host smart-462e4413-6e4a-419b-b894-8d191a9636d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521898774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2521898774
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1139566412
Short name T658
Test name
Test status
Simulation time 384576454 ps
CPU time 1.17 seconds
Started Feb 21 02:54:47 PM PST 24
Finished Feb 21 02:54:48 PM PST 24
Peak memory 192532 kb
Host smart-e562f37b-30e6-4937-aceb-783b99f140b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139566412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1139566412
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2101500016
Short name T672
Test name
Test status
Simulation time 142414041 ps
CPU time 3.13 seconds
Started Feb 21 02:54:47 PM PST 24
Finished Feb 21 02:54:50 PM PST 24
Peak memory 198900 kb
Host smart-e446a3c0-da24-46c3-92b5-dc5170857a18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101500016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2101500016
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3115087705
Short name T621
Test name
Test status
Simulation time 12330418 ps
CPU time 0.58 seconds
Started Feb 21 02:55:04 PM PST 24
Finished Feb 21 02:55:05 PM PST 24
Peak memory 184196 kb
Host smart-ffc5c20a-7210-4ffd-ba67-f17e6da3585e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115087705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3115087705
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1316120726
Short name T630
Test name
Test status
Simulation time 72714096 ps
CPU time 0.64 seconds
Started Feb 21 02:55:02 PM PST 24
Finished Feb 21 02:55:03 PM PST 24
Peak memory 184440 kb
Host smart-ef3e182e-f766-42c5-b7d0-99947bd6bc6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316120726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1316120726
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1377272402
Short name T603
Test name
Test status
Simulation time 14136331 ps
CPU time 0.58 seconds
Started Feb 21 02:55:09 PM PST 24
Finished Feb 21 02:55:10 PM PST 24
Peak memory 184408 kb
Host smart-b85d27e4-2424-45a1-96aa-96627908b972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377272402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1377272402
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.177959620
Short name T604
Test name
Test status
Simulation time 41106347 ps
CPU time 0.57 seconds
Started Feb 21 02:55:08 PM PST 24
Finished Feb 21 02:55:09 PM PST 24
Peak memory 184140 kb
Host smart-76ba0935-7049-401e-bf88-b7325c0fde55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177959620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.177959620
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2610155922
Short name T707
Test name
Test status
Simulation time 14114710 ps
CPU time 0.6 seconds
Started Feb 21 02:55:17 PM PST 24
Finished Feb 21 02:55:18 PM PST 24
Peak memory 184264 kb
Host smart-7e95e7c2-3aaa-4607-b12d-8dfb93bf7bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610155922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2610155922
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1195383934
Short name T613
Test name
Test status
Simulation time 25760659 ps
CPU time 0.56 seconds
Started Feb 21 02:55:08 PM PST 24
Finished Feb 21 02:55:09 PM PST 24
Peak memory 184184 kb
Host smart-a1971885-08dc-4505-a903-ef10c9baa7c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195383934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1195383934
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1155100030
Short name T635
Test name
Test status
Simulation time 156297554 ps
CPU time 0.59 seconds
Started Feb 21 02:55:04 PM PST 24
Finished Feb 21 02:55:05 PM PST 24
Peak memory 184200 kb
Host smart-19d9792d-40c1-4446-8fdf-e03202717fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155100030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1155100030
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2002695923
Short name T659
Test name
Test status
Simulation time 11027113 ps
CPU time 0.62 seconds
Started Feb 21 02:55:10 PM PST 24
Finished Feb 21 02:55:11 PM PST 24
Peak memory 184200 kb
Host smart-f1b8a67e-fd36-4a6f-b4b0-9f71bc4df73d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002695923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2002695923
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2121697383
Short name T626
Test name
Test status
Simulation time 58171066 ps
CPU time 0.59 seconds
Started Feb 21 02:55:04 PM PST 24
Finished Feb 21 02:55:05 PM PST 24
Peak memory 184188 kb
Host smart-cac44c08-bdf8-426a-817f-5cc99a265d66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121697383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2121697383
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3445623503
Short name T653
Test name
Test status
Simulation time 44646361 ps
CPU time 0.61 seconds
Started Feb 21 02:55:09 PM PST 24
Finished Feb 21 02:55:10 PM PST 24
Peak memory 184412 kb
Host smart-2d07bec6-4fbe-4f3a-84f1-c4cd51a4e6f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445623503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3445623503
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1822998843
Short name T679
Test name
Test status
Simulation time 61188422 ps
CPU time 1.27 seconds
Started Feb 21 02:54:31 PM PST 24
Finished Feb 21 02:54:33 PM PST 24
Peak memory 198892 kb
Host smart-7ff78ffa-824a-4de4-9b86-63b996ff8cc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822998843 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1822998843
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4005130132
Short name T98
Test name
Test status
Simulation time 50725198 ps
CPU time 0.63 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:31 PM PST 24
Peak memory 194976 kb
Host smart-954f706e-939e-4b11-b691-52a876e48624
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005130132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.4005130132
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3511563919
Short name T598
Test name
Test status
Simulation time 28472026 ps
CPU time 0.67 seconds
Started Feb 21 02:54:38 PM PST 24
Finished Feb 21 02:54:39 PM PST 24
Peak memory 184192 kb
Host smart-387fd52e-bbed-4090-9dd5-abf8ea1b366f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511563919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3511563919
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2751204663
Short name T640
Test name
Test status
Simulation time 95652079 ps
CPU time 1.33 seconds
Started Feb 21 02:54:38 PM PST 24
Finished Feb 21 02:54:39 PM PST 24
Peak memory 192816 kb
Host smart-8f621dc2-ff09-44e2-bf2a-2dd2c3cec2e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751204663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2751204663
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2231876430
Short name T695
Test name
Test status
Simulation time 709463885 ps
CPU time 3.5 seconds
Started Feb 21 02:54:33 PM PST 24
Finished Feb 21 02:54:36 PM PST 24
Peak memory 199164 kb
Host smart-bcd6491a-7465-4fcb-a1ac-73382b1b99c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231876430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2231876430
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4289553687
Short name T152
Test name
Test status
Simulation time 65515556 ps
CPU time 1.19 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:32 PM PST 24
Peak memory 198156 kb
Host smart-057e2fea-94f4-486b-9ea1-0b9cd35d5bfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289553687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.4289553687
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2409713878
Short name T719
Test name
Test status
Simulation time 22045802 ps
CPU time 1.32 seconds
Started Feb 21 02:54:38 PM PST 24
Finished Feb 21 02:54:40 PM PST 24
Peak memory 199144 kb
Host smart-5c2abb70-7534-47de-930d-b738315ece52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409713878 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2409713878
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1324741891
Short name T636
Test name
Test status
Simulation time 44900024 ps
CPU time 0.61 seconds
Started Feb 21 02:54:32 PM PST 24
Finished Feb 21 02:54:33 PM PST 24
Peak memory 194392 kb
Host smart-bf27c5d1-448f-4653-a98e-f406ad394e89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324741891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1324741891
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3069877112
Short name T616
Test name
Test status
Simulation time 11973966 ps
CPU time 0.67 seconds
Started Feb 21 02:54:38 PM PST 24
Finished Feb 21 02:54:39 PM PST 24
Peak memory 184196 kb
Host smart-06a0857d-1334-440f-ad98-3ca5d5adc4e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069877112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3069877112
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1459486514
Short name T710
Test name
Test status
Simulation time 56452213 ps
CPU time 0.83 seconds
Started Feb 21 02:54:35 PM PST 24
Finished Feb 21 02:54:37 PM PST 24
Peak memory 196168 kb
Host smart-18d196ad-8f89-4a40-8d42-71b29d77c49b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459486514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1459486514
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.731496005
Short name T625
Test name
Test status
Simulation time 38137902 ps
CPU time 2.16 seconds
Started Feb 21 02:54:47 PM PST 24
Finished Feb 21 02:54:49 PM PST 24
Peak memory 199132 kb
Host smart-5643dc13-1a17-4fa5-a70c-f662c137aea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731496005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.731496005
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3501008708
Short name T55
Test name
Test status
Simulation time 1168426748 ps
CPU time 1.25 seconds
Started Feb 21 02:54:35 PM PST 24
Finished Feb 21 02:54:37 PM PST 24
Peak memory 198408 kb
Host smart-566f505b-1130-4440-9073-6c4d60850dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501008708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3501008708
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1850701272
Short name T676
Test name
Test status
Simulation time 63864520 ps
CPU time 1.72 seconds
Started Feb 21 02:54:35 PM PST 24
Finished Feb 21 02:54:38 PM PST 24
Peak memory 199092 kb
Host smart-9c333595-1ab6-49fa-b997-e00c9287174f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850701272 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1850701272
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1004448880
Short name T684
Test name
Test status
Simulation time 46133618 ps
CPU time 0.65 seconds
Started Feb 21 02:54:36 PM PST 24
Finished Feb 21 02:54:37 PM PST 24
Peak memory 194436 kb
Host smart-8f725da8-e8ad-4f0a-91c1-b4a1d21b7b18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004448880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1004448880
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2875323290
Short name T612
Test name
Test status
Simulation time 16062534 ps
CPU time 0.59 seconds
Started Feb 21 02:54:31 PM PST 24
Finished Feb 21 02:54:32 PM PST 24
Peak memory 184200 kb
Host smart-fc55aa13-e3de-4785-bc4c-a0516cb9e841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875323290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2875323290
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3028286899
Short name T726
Test name
Test status
Simulation time 150596237 ps
CPU time 1.13 seconds
Started Feb 21 02:54:38 PM PST 24
Finished Feb 21 02:54:40 PM PST 24
Peak memory 192688 kb
Host smart-83cc9a66-0f7b-4da4-ad4c-8ecde92a3667
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028286899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3028286899
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3546561305
Short name T629
Test name
Test status
Simulation time 908856775 ps
CPU time 3.99 seconds
Started Feb 21 02:54:32 PM PST 24
Finished Feb 21 02:54:37 PM PST 24
Peak memory 199116 kb
Host smart-9ebce2f4-4509-4f23-98f0-5707f70b04ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546561305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3546561305
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1345365585
Short name T142
Test name
Test status
Simulation time 1079697208 ps
CPU time 1.22 seconds
Started Feb 21 02:54:32 PM PST 24
Finished Feb 21 02:54:34 PM PST 24
Peak memory 198592 kb
Host smart-b1c2f188-46c2-466b-8916-c27b4bd96e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345365585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1345365585
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3829316952
Short name T606
Test name
Test status
Simulation time 28550511 ps
CPU time 1.63 seconds
Started Feb 21 02:54:44 PM PST 24
Finished Feb 21 02:54:46 PM PST 24
Peak memory 198656 kb
Host smart-623f28d2-7f2e-466d-b7ea-d6ecbb3eda73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829316952 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3829316952
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.159879962
Short name T655
Test name
Test status
Simulation time 16215796 ps
CPU time 0.69 seconds
Started Feb 21 02:54:32 PM PST 24
Finished Feb 21 02:54:33 PM PST 24
Peak memory 194920 kb
Host smart-01d77941-fb30-40e3-b171-de872a6c5086
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159879962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.159879962
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3454633125
Short name T619
Test name
Test status
Simulation time 14428598 ps
CPU time 0.61 seconds
Started Feb 21 02:54:35 PM PST 24
Finished Feb 21 02:54:36 PM PST 24
Peak memory 184052 kb
Host smart-597dceec-0069-4b8d-b30e-989ca185e2d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454633125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3454633125
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.328492702
Short name T596
Test name
Test status
Simulation time 30813484 ps
CPU time 1.34 seconds
Started Feb 21 02:54:41 PM PST 24
Finished Feb 21 02:54:43 PM PST 24
Peak memory 192740 kb
Host smart-33a1520e-ebec-4641-81c1-0bf42d4d10bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328492702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.328492702
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4068903294
Short name T696
Test name
Test status
Simulation time 93207813 ps
CPU time 1.19 seconds
Started Feb 21 02:54:30 PM PST 24
Finished Feb 21 02:54:31 PM PST 24
Peak memory 199060 kb
Host smart-1887bbf3-b6dc-4a88-889e-a20535986f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068903294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4068903294
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2199740402
Short name T143
Test name
Test status
Simulation time 2209360409 ps
CPU time 2.89 seconds
Started Feb 21 02:54:39 PM PST 24
Finished Feb 21 02:54:42 PM PST 24
Peak memory 198948 kb
Host smart-020b6f2b-3033-4409-b7c5-a1b3c85362b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199740402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2199740402
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2722729512
Short name T634
Test name
Test status
Simulation time 120065230 ps
CPU time 2.22 seconds
Started Feb 21 02:54:32 PM PST 24
Finished Feb 21 02:54:34 PM PST 24
Peak memory 199136 kb
Host smart-8baa9a70-dc6f-4090-b8be-dae93752aed0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722729512 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2722729512
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2794507467
Short name T92
Test name
Test status
Simulation time 65415466 ps
CPU time 0.76 seconds
Started Feb 21 02:54:47 PM PST 24
Finished Feb 21 02:54:48 PM PST 24
Peak memory 194392 kb
Host smart-9da32fe3-8b3f-4e59-9110-5a3a86e5a39f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794507467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2794507467
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.4261566495
Short name T671
Test name
Test status
Simulation time 36598709 ps
CPU time 0.55 seconds
Started Feb 21 02:54:28 PM PST 24
Finished Feb 21 02:54:29 PM PST 24
Peak memory 184256 kb
Host smart-8d58cd46-067f-48f9-beef-a0f11cb2010d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261566495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4261566495
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2381410599
Short name T692
Test name
Test status
Simulation time 27752836 ps
CPU time 0.82 seconds
Started Feb 21 02:54:34 PM PST 24
Finished Feb 21 02:54:36 PM PST 24
Peak memory 195776 kb
Host smart-dd9a0e0f-c8b4-4f7c-b78b-ac3f1185aa0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381410599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2381410599
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3269151501
Short name T682
Test name
Test status
Simulation time 147039514 ps
CPU time 3.23 seconds
Started Feb 21 02:54:47 PM PST 24
Finished Feb 21 02:54:50 PM PST 24
Peak memory 198656 kb
Host smart-f28d6bff-85af-4710-bfb8-ae2339273a06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269151501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3269151501
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1523143892
Short name T723
Test name
Test status
Simulation time 324956827 ps
CPU time 1.3 seconds
Started Feb 21 02:54:42 PM PST 24
Finished Feb 21 02:54:44 PM PST 24
Peak memory 198608 kb
Host smart-993ec964-01e5-422b-8cd1-9cb4a7771c38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523143892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1523143892
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2825063604
Short name T356
Test name
Test status
Simulation time 312669034 ps
CPU time 10.17 seconds
Started Feb 21 02:12:17 PM PST 24
Finished Feb 21 02:12:27 PM PST 24
Peak memory 215864 kb
Host smart-0e3ea0ee-6415-4849-ac0e-2e05f0d8c4c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2825063604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2825063604
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1946458611
Short name T228
Test name
Test status
Simulation time 1351942074 ps
CPU time 64.6 seconds
Started Feb 21 02:12:17 PM PST 24
Finished Feb 21 02:13:22 PM PST 24
Peak memory 199544 kb
Host smart-3a99424e-c474-440c-88a7-3a64f015f45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946458611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1946458611
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3325644039
Short name T69
Test name
Test status
Simulation time 15058504388 ps
CPU time 97.87 seconds
Started Feb 21 02:12:17 PM PST 24
Finished Feb 21 02:13:55 PM PST 24
Peak memory 199648 kb
Host smart-8031e249-fd18-49c9-b527-e212ef5f1cf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325644039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3325644039
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3714295732
Short name T563
Test name
Test status
Simulation time 19703819654 ps
CPU time 123.17 seconds
Started Feb 21 02:12:30 PM PST 24
Finished Feb 21 02:14:35 PM PST 24
Peak memory 199728 kb
Host smart-5126ba5a-a687-4157-a4e8-2d18c044a6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714295732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3714295732
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.131304322
Short name T472
Test name
Test status
Simulation time 1360968962 ps
CPU time 18.36 seconds
Started Feb 21 02:12:16 PM PST 24
Finished Feb 21 02:12:35 PM PST 24
Peak memory 199512 kb
Host smart-f65824cf-a416-4469-a423-e8456f1b6085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131304322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.131304322
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2641862839
Short name T43
Test name
Test status
Simulation time 38450858 ps
CPU time 0.8 seconds
Started Feb 21 02:12:27 PM PST 24
Finished Feb 21 02:12:28 PM PST 24
Peak memory 216400 kb
Host smart-b9d50cd7-9cc7-4954-a2e6-fa5569afc937
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641862839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2641862839
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.482442265
Short name T141
Test name
Test status
Simulation time 258770458 ps
CPU time 3.57 seconds
Started Feb 21 02:12:15 PM PST 24
Finished Feb 21 02:12:19 PM PST 24
Peak memory 199560 kb
Host smart-5d8ded8d-85dd-4f40-bbc8-f1cb2cbf22f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482442265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.482442265
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.687855535
Short name T461
Test name
Test status
Simulation time 185333116463 ps
CPU time 766.46 seconds
Started Feb 21 02:12:26 PM PST 24
Finished Feb 21 02:25:13 PM PST 24
Peak memory 240672 kb
Host smart-7b1677a3-46ee-41a7-9172-dcee85586059
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687855535 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.687855535
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.802839575
Short name T433
Test name
Test status
Simulation time 42210088 ps
CPU time 0.95 seconds
Started Feb 21 02:12:23 PM PST 24
Finished Feb 21 02:12:24 PM PST 24
Peak memory 196904 kb
Host smart-7aa64029-c119-40cf-b80c-662c8c55447b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802839575 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.802839575
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2482297516
Short name T500
Test name
Test status
Simulation time 108823945045 ps
CPU time 339.85 seconds
Started Feb 21 02:12:26 PM PST 24
Finished Feb 21 02:18:06 PM PST 24
Peak memory 199508 kb
Host smart-fe1abe7c-66a3-478e-abb5-aa8fc5238e1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482297516 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.2482297516
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.347587483
Short name T454
Test name
Test status
Simulation time 317903043 ps
CPU time 4.09 seconds
Started Feb 21 02:12:23 PM PST 24
Finished Feb 21 02:12:28 PM PST 24
Peak memory 199584 kb
Host smart-dad04337-1ac3-4320-9a63-b57682a2b34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347587483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.347587483
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2077744318
Short name T511
Test name
Test status
Simulation time 42688107 ps
CPU time 0.56 seconds
Started Feb 21 02:12:25 PM PST 24
Finished Feb 21 02:12:26 PM PST 24
Peak memory 193920 kb
Host smart-feb2c2ae-b831-4e3c-8370-cf020c0408c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077744318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2077744318
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3015177731
Short name T379
Test name
Test status
Simulation time 3102962670 ps
CPU time 49.9 seconds
Started Feb 21 02:12:26 PM PST 24
Finished Feb 21 02:13:16 PM PST 24
Peak memory 224184 kb
Host smart-427ec622-cd03-4835-b3ca-bc4e3eb38d3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015177731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3015177731
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1615274303
Short name T286
Test name
Test status
Simulation time 12291319992 ps
CPU time 43.38 seconds
Started Feb 21 02:12:25 PM PST 24
Finished Feb 21 02:13:09 PM PST 24
Peak memory 199696 kb
Host smart-b4a1362f-89c5-49db-a66c-0e05686492b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615274303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1615274303
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3972502958
Short name T428
Test name
Test status
Simulation time 1276181001 ps
CPU time 67.57 seconds
Started Feb 21 02:12:32 PM PST 24
Finished Feb 21 02:13:41 PM PST 24
Peak memory 199608 kb
Host smart-4a7a568a-1d9b-4068-a548-0e4e22ed717d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972502958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3972502958
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3952938358
Short name T179
Test name
Test status
Simulation time 25211522824 ps
CPU time 80.97 seconds
Started Feb 21 02:12:25 PM PST 24
Finished Feb 21 02:13:46 PM PST 24
Peak memory 199728 kb
Host smart-a58f6c42-dac3-4e70-8cd9-a496874f22a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952938358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3952938358
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1469390413
Short name T536
Test name
Test status
Simulation time 12207362222 ps
CPU time 90.17 seconds
Started Feb 21 02:12:25 PM PST 24
Finished Feb 21 02:13:56 PM PST 24
Peak memory 199632 kb
Host smart-c1c49b65-41b1-4cf9-8a4b-9b41684e38dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469390413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1469390413
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.1206751493
Short name T245
Test name
Test status
Simulation time 668738425 ps
CPU time 2.98 seconds
Started Feb 21 02:12:25 PM PST 24
Finished Feb 21 02:12:28 PM PST 24
Peak memory 199540 kb
Host smart-34e09ba9-28cc-4fcc-afb8-0e6ce935f5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206751493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1206751493
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.869731662
Short name T130
Test name
Test status
Simulation time 31340469122 ps
CPU time 1482.44 seconds
Started Feb 21 02:12:31 PM PST 24
Finished Feb 21 02:37:14 PM PST 24
Peak memory 240680 kb
Host smart-19258bb0-b857-4572-9da5-611aa55d85e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869731662 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.869731662
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3969239331
Short name T395
Test name
Test status
Simulation time 113248920 ps
CPU time 0.88 seconds
Started Feb 21 02:12:23 PM PST 24
Finished Feb 21 02:12:24 PM PST 24
Peak memory 196864 kb
Host smart-0e159512-1292-45f6-a303-acee3bc8a6c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969239331 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.3969239331
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3402377967
Short name T201
Test name
Test status
Simulation time 28080137379 ps
CPU time 431.67 seconds
Started Feb 21 02:12:24 PM PST 24
Finished Feb 21 02:19:36 PM PST 24
Peak memory 199572 kb
Host smart-6e7de2d7-8742-49da-ad49-9491c7099deb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402377967 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.3402377967
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3392556423
Short name T224
Test name
Test status
Simulation time 2377897716 ps
CPU time 45.95 seconds
Started Feb 21 02:12:27 PM PST 24
Finished Feb 21 02:13:13 PM PST 24
Peak memory 199648 kb
Host smart-6830eb7a-3010-44a7-806f-9baf0b35bccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392556423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3392556423
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3110276975
Short name T357
Test name
Test status
Simulation time 27451215 ps
CPU time 0.58 seconds
Started Feb 21 02:13:13 PM PST 24
Finished Feb 21 02:13:15 PM PST 24
Peak memory 193912 kb
Host smart-cd681468-e920-4500-bdc0-88b1e85427cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110276975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3110276975
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4208037084
Short name T335
Test name
Test status
Simulation time 521278304 ps
CPU time 16.18 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:13:28 PM PST 24
Peak memory 209824 kb
Host smart-489c8b9b-85df-4a7c-bc2a-1dd6f5341aa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208037084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4208037084
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3518971102
Short name T10
Test name
Test status
Simulation time 1188651863 ps
CPU time 56.85 seconds
Started Feb 21 02:13:16 PM PST 24
Finished Feb 21 02:14:14 PM PST 24
Peak memory 199312 kb
Host smart-9c6e8107-07c9-4fdd-ae68-1ce15ea36291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518971102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3518971102
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.894405608
Short name T123
Test name
Test status
Simulation time 7639725226 ps
CPU time 105.58 seconds
Started Feb 21 02:13:12 PM PST 24
Finished Feb 21 02:14:58 PM PST 24
Peak memory 199644 kb
Host smart-d293db41-6ba5-4e60-85a1-b40d6dc4d4b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894405608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.894405608
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.175457352
Short name T33
Test name
Test status
Simulation time 5068387325 ps
CPU time 45.33 seconds
Started Feb 21 02:13:16 PM PST 24
Finished Feb 21 02:14:02 PM PST 24
Peak memory 199664 kb
Host smart-6aa31e54-a719-49bc-9ca1-80dd3b19eb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175457352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.175457352
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.562796216
Short name T84
Test name
Test status
Simulation time 3061756164 ps
CPU time 100.62 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:14:53 PM PST 24
Peak memory 199640 kb
Host smart-e700e514-084e-4c01-bc4b-ceae2c6be5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562796216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.562796216
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.289631013
Short name T373
Test name
Test status
Simulation time 714955133 ps
CPU time 2.56 seconds
Started Feb 21 02:13:10 PM PST 24
Finished Feb 21 02:13:13 PM PST 24
Peak memory 199660 kb
Host smart-f42e7cab-36dd-4213-82c2-13be6f7823e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289631013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.289631013
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.4248195885
Short name T440
Test name
Test status
Simulation time 194885101956 ps
CPU time 497.46 seconds
Started Feb 21 02:13:14 PM PST 24
Finished Feb 21 02:21:33 PM PST 24
Peak memory 232484 kb
Host smart-c0fffb5b-f578-4012-9fdf-097be2126c0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248195885 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.4248195885
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.4208738970
Short name T216
Test name
Test status
Simulation time 30651274 ps
CPU time 1.07 seconds
Started Feb 21 02:13:16 PM PST 24
Finished Feb 21 02:13:18 PM PST 24
Peak memory 197840 kb
Host smart-c5cb4ffc-dbfd-40de-99e4-e767764003d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208738970 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.4208738970
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.394058320
Short name T564
Test name
Test status
Simulation time 33021572745 ps
CPU time 413.67 seconds
Started Feb 21 02:13:12 PM PST 24
Finished Feb 21 02:20:06 PM PST 24
Peak memory 199580 kb
Host smart-616bc27d-2167-4183-856a-071c31c88508
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394058320 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.hmac_test_sha_vectors.394058320
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2681395765
Short name T493
Test name
Test status
Simulation time 6863349660 ps
CPU time 30.33 seconds
Started Feb 21 02:13:12 PM PST 24
Finished Feb 21 02:13:43 PM PST 24
Peak memory 199620 kb
Host smart-09ff12df-9228-42d1-94b2-67da0bc10567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681395765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2681395765
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2552663344
Short name T284
Test name
Test status
Simulation time 24498903 ps
CPU time 0.6 seconds
Started Feb 21 02:13:21 PM PST 24
Finished Feb 21 02:13:22 PM PST 24
Peak memory 193976 kb
Host smart-68604101-1e7d-45c5-8e5c-cd98474410de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552663344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2552663344
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1965874082
Short name T308
Test name
Test status
Simulation time 2334622764 ps
CPU time 42.02 seconds
Started Feb 21 02:13:14 PM PST 24
Finished Feb 21 02:13:57 PM PST 24
Peak memory 232364 kb
Host smart-775be066-00ad-46fd-a75d-f14ffa25cd2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965874082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1965874082
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3912616346
Short name T223
Test name
Test status
Simulation time 1100898699 ps
CPU time 15.24 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:13:27 PM PST 24
Peak memory 199532 kb
Host smart-d22477e2-57cb-4380-b98b-f51526b15b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912616346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3912616346
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4188983779
Short name T9
Test name
Test status
Simulation time 8597982638 ps
CPU time 87.17 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:14:39 PM PST 24
Peak memory 199652 kb
Host smart-ca2ef762-8ddb-4608-a319-241dcbd95634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188983779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4188983779
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2001521775
Short name T499
Test name
Test status
Simulation time 55257704312 ps
CPU time 149.84 seconds
Started Feb 21 02:13:22 PM PST 24
Finished Feb 21 02:15:52 PM PST 24
Peak memory 199656 kb
Host smart-7baf4295-1440-4f91-86dd-305da23fcecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001521775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2001521775
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.4031599801
Short name T204
Test name
Test status
Simulation time 2888001771 ps
CPU time 49.45 seconds
Started Feb 21 02:13:14 PM PST 24
Finished Feb 21 02:14:04 PM PST 24
Peak memory 199640 kb
Host smart-1da46304-d744-4158-a17b-4523fbab398c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031599801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.4031599801
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.299829492
Short name T298
Test name
Test status
Simulation time 409809950 ps
CPU time 2.46 seconds
Started Feb 21 02:13:14 PM PST 24
Finished Feb 21 02:13:17 PM PST 24
Peak memory 199480 kb
Host smart-afbb372b-578b-4d52-97c1-828ae4b501d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299829492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.299829492
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.755427746
Short name T497
Test name
Test status
Simulation time 11883092794 ps
CPU time 564.91 seconds
Started Feb 21 02:13:21 PM PST 24
Finished Feb 21 02:22:46 PM PST 24
Peak memory 210744 kb
Host smart-e4dd3e21-58a6-4b33-a22d-a0b2bfbdbdeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755427746 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.755427746
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2238595019
Short name T397
Test name
Test status
Simulation time 30571534 ps
CPU time 1.11 seconds
Started Feb 21 02:13:18 PM PST 24
Finished Feb 21 02:13:19 PM PST 24
Peak memory 197764 kb
Host smart-f215d1b6-7786-41bd-b0cc-f3b58e819eef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238595019 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2238595019
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2329721395
Short name T405
Test name
Test status
Simulation time 45214991693 ps
CPU time 553.31 seconds
Started Feb 21 02:13:27 PM PST 24
Finished Feb 21 02:22:41 PM PST 24
Peak memory 199572 kb
Host smart-5ed4f866-a542-419c-bfed-299ce8366cbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329721395 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.2329721395
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1076849822
Short name T112
Test name
Test status
Simulation time 23852347070 ps
CPU time 73.24 seconds
Started Feb 21 02:13:22 PM PST 24
Finished Feb 21 02:14:36 PM PST 24
Peak memory 199632 kb
Host smart-ec4d39f2-6e9e-4d67-b9b6-6628c4d0818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076849822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1076849822
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.3765862911
Short name T17
Test name
Test status
Simulation time 19511460006 ps
CPU time 651.41 seconds
Started Feb 21 02:19:16 PM PST 24
Finished Feb 21 02:30:09 PM PST 24
Peak memory 232504 kb
Host smart-9ab7b8c3-b298-4233-add9-f3ff63fdaaa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3765862911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.3765862911
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.912083218
Short name T512
Test name
Test status
Simulation time 10908548 ps
CPU time 0.55 seconds
Started Feb 21 02:13:21 PM PST 24
Finished Feb 21 02:13:22 PM PST 24
Peak memory 193800 kb
Host smart-f5082590-7bda-4ad7-949d-3ac79d200319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912083218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.912083218
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2948713557
Short name T277
Test name
Test status
Simulation time 320641513 ps
CPU time 5.54 seconds
Started Feb 21 02:13:22 PM PST 24
Finished Feb 21 02:13:28 PM PST 24
Peak memory 207740 kb
Host smart-9c37ccb7-192a-4a5b-b495-e03d84e38ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948713557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2948713557
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.993481423
Short name T85
Test name
Test status
Simulation time 2624876767 ps
CPU time 31.44 seconds
Started Feb 21 02:13:20 PM PST 24
Finished Feb 21 02:13:52 PM PST 24
Peak memory 199640 kb
Host smart-b61c5d9a-57f5-4207-a32d-d03c1835d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993481423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.993481423
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3874373184
Short name T233
Test name
Test status
Simulation time 1209266212 ps
CPU time 63.62 seconds
Started Feb 21 02:13:21 PM PST 24
Finished Feb 21 02:14:25 PM PST 24
Peak memory 199492 kb
Host smart-05cd4cfe-a28d-4e9a-a335-aa7cb787d457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874373184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3874373184
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3887194150
Short name T315
Test name
Test status
Simulation time 7649637735 ps
CPU time 95.39 seconds
Started Feb 21 02:13:27 PM PST 24
Finished Feb 21 02:15:03 PM PST 24
Peak memory 199644 kb
Host smart-f05bcbb2-d9d0-4814-a15b-c741d59b2e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887194150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3887194150
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3943640280
Short name T507
Test name
Test status
Simulation time 30487178359 ps
CPU time 79.81 seconds
Started Feb 21 02:13:21 PM PST 24
Finished Feb 21 02:14:41 PM PST 24
Peak memory 199700 kb
Host smart-838bdb9d-7846-406a-a051-8200ac13ca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943640280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3943640280
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1253122388
Short name T163
Test name
Test status
Simulation time 175822560 ps
CPU time 4.27 seconds
Started Feb 21 02:13:27 PM PST 24
Finished Feb 21 02:13:32 PM PST 24
Peak memory 199516 kb
Host smart-26a2b194-7fff-4541-b56d-5742296fd8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253122388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1253122388
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2706410783
Short name T402
Test name
Test status
Simulation time 168492062 ps
CPU time 0.92 seconds
Started Feb 21 02:13:21 PM PST 24
Finished Feb 21 02:13:22 PM PST 24
Peak memory 196628 kb
Host smart-70fdb41d-4434-4f8d-8082-d24f88108398
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706410783 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2706410783
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3628179975
Short name T325
Test name
Test status
Simulation time 59176681522 ps
CPU time 467.04 seconds
Started Feb 21 02:13:18 PM PST 24
Finished Feb 21 02:21:05 PM PST 24
Peak memory 199580 kb
Host smart-6337fa6c-eceb-40ec-b74a-4ae8ac846f7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628179975 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.3628179975
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2803309198
Short name T160
Test name
Test status
Simulation time 3204143775 ps
CPU time 59.84 seconds
Started Feb 21 02:13:23 PM PST 24
Finished Feb 21 02:14:23 PM PST 24
Peak memory 199676 kb
Host smart-e70de15f-f38a-48fb-97e8-b5364d93aee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803309198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2803309198
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1744828008
Short name T339
Test name
Test status
Simulation time 90762177 ps
CPU time 0.53 seconds
Started Feb 21 02:13:25 PM PST 24
Finished Feb 21 02:13:26 PM PST 24
Peak memory 193728 kb
Host smart-bcd93d5c-c736-4fad-8f70-9b592c90ffe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744828008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1744828008
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.228158243
Short name T261
Test name
Test status
Simulation time 1441325875 ps
CPU time 25.39 seconds
Started Feb 21 02:13:31 PM PST 24
Finished Feb 21 02:13:56 PM PST 24
Peak memory 207676 kb
Host smart-a2ed2be9-e5a8-4558-beeb-41943270ae3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228158243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.228158243
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1277485493
Short name T502
Test name
Test status
Simulation time 2348292640 ps
CPU time 8.43 seconds
Started Feb 21 02:13:25 PM PST 24
Finished Feb 21 02:13:34 PM PST 24
Peak memory 199668 kb
Host smart-0da64f0f-33d9-46c5-b688-f3355d49f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277485493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1277485493
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2741814533
Short name T309
Test name
Test status
Simulation time 5272867083 ps
CPU time 77.94 seconds
Started Feb 21 02:13:26 PM PST 24
Finished Feb 21 02:14:44 PM PST 24
Peak memory 199656 kb
Host smart-1c6ba618-dabd-4490-876b-687051c57f51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2741814533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2741814533
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.892059907
Short name T314
Test name
Test status
Simulation time 1979395026 ps
CPU time 25.56 seconds
Started Feb 21 02:13:25 PM PST 24
Finished Feb 21 02:13:51 PM PST 24
Peak memory 199608 kb
Host smart-8325b3c8-cc1a-4165-a043-7fc21a1cf83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892059907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.892059907
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1140013038
Short name T374
Test name
Test status
Simulation time 3838491405 ps
CPU time 34.51 seconds
Started Feb 21 02:13:30 PM PST 24
Finished Feb 21 02:14:05 PM PST 24
Peak memory 199892 kb
Host smart-ea00ee6a-449c-45a4-a2c4-f4fc2b6c3cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140013038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1140013038
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1438700599
Short name T169
Test name
Test status
Simulation time 297751320 ps
CPU time 4.11 seconds
Started Feb 21 02:13:21 PM PST 24
Finished Feb 21 02:13:25 PM PST 24
Peak memory 199520 kb
Host smart-9c13d7d6-52f3-48b2-9da8-454ddd1e5147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438700599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1438700599
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2594397569
Short name T421
Test name
Test status
Simulation time 152871031005 ps
CPU time 515.76 seconds
Started Feb 21 02:13:20 PM PST 24
Finished Feb 21 02:21:56 PM PST 24
Peak memory 199744 kb
Host smart-041629fc-6112-4338-abf9-7850ffac0088
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594397569 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2594397569
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2529236813
Short name T198
Test name
Test status
Simulation time 72187942 ps
CPU time 1.01 seconds
Started Feb 21 02:13:30 PM PST 24
Finished Feb 21 02:13:31 PM PST 24
Peak memory 197008 kb
Host smart-d4988b04-a056-4626-9218-2f7d76efa75c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529236813 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2529236813
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1157138084
Short name T292
Test name
Test status
Simulation time 74708223182 ps
CPU time 487.05 seconds
Started Feb 21 02:13:30 PM PST 24
Finished Feb 21 02:21:37 PM PST 24
Peak memory 199664 kb
Host smart-66e2cfbe-8ac1-46d0-904e-27dccf56c13b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157138084 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.1157138084
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3764308546
Short name T462
Test name
Test status
Simulation time 1188724972 ps
CPU time 42.86 seconds
Started Feb 21 02:13:31 PM PST 24
Finished Feb 21 02:14:14 PM PST 24
Peak memory 199808 kb
Host smart-99c60e4e-58d4-49b0-baaa-6e91d8e92348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764308546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3764308546
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1709370351
Short name T188
Test name
Test status
Simulation time 13754575 ps
CPU time 0.61 seconds
Started Feb 21 02:13:44 PM PST 24
Finished Feb 21 02:13:45 PM PST 24
Peak memory 194820 kb
Host smart-8eea83d3-b90f-4e60-8e09-e0fe8a8a7636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709370351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1709370351
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.492449451
Short name T445
Test name
Test status
Simulation time 1890850957 ps
CPU time 14.83 seconds
Started Feb 21 02:13:28 PM PST 24
Finished Feb 21 02:13:43 PM PST 24
Peak memory 215840 kb
Host smart-b8c527ef-1218-4e75-b611-75c1b2da8bf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492449451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.492449451
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3754241619
Short name T294
Test name
Test status
Simulation time 625132678 ps
CPU time 28.04 seconds
Started Feb 21 02:13:36 PM PST 24
Finished Feb 21 02:14:04 PM PST 24
Peak memory 199516 kb
Host smart-507361e3-d5ed-448d-a795-ec8dfb46fc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754241619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3754241619
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2287387170
Short name T525
Test name
Test status
Simulation time 8942311097 ps
CPU time 113.58 seconds
Started Feb 21 02:13:25 PM PST 24
Finished Feb 21 02:15:19 PM PST 24
Peak memory 199640 kb
Host smart-32018b60-7f1e-41cd-abf8-bc711245797b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287387170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2287387170
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3398406229
Short name T529
Test name
Test status
Simulation time 3054111406 ps
CPU time 15.3 seconds
Started Feb 21 02:13:37 PM PST 24
Finished Feb 21 02:13:52 PM PST 24
Peak memory 199668 kb
Host smart-df2bc818-803f-44cc-9e28-2c7b88375833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398406229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3398406229
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1864208048
Short name T469
Test name
Test status
Simulation time 13241335152 ps
CPU time 46.79 seconds
Started Feb 21 02:13:27 PM PST 24
Finished Feb 21 02:14:14 PM PST 24
Peak memory 199612 kb
Host smart-2799bbb6-4e41-468b-bc70-bc47d0f7fe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864208048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1864208048
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2173404427
Short name T176
Test name
Test status
Simulation time 211801013 ps
CPU time 1.03 seconds
Started Feb 21 02:13:25 PM PST 24
Finished Feb 21 02:13:27 PM PST 24
Peak memory 198532 kb
Host smart-32be2afa-bde1-439e-8d0a-3b05416d0435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173404427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2173404427
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1432766298
Short name T75
Test name
Test status
Simulation time 71211637463 ps
CPU time 878.7 seconds
Started Feb 21 02:13:36 PM PST 24
Finished Feb 21 02:28:15 PM PST 24
Peak memory 231380 kb
Host smart-15c77a57-67ec-4783-815b-fb6225cfcbd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432766298 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1432766298
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.2068505027
Short name T515
Test name
Test status
Simulation time 54000810613 ps
CPU time 423.55 seconds
Started Feb 21 02:13:42 PM PST 24
Finished Feb 21 02:20:46 PM PST 24
Peak memory 216420 kb
Host smart-6430ce94-c600-48d7-b8ad-548a94d9ba0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068505027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.2068505027
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.4227267920
Short name T516
Test name
Test status
Simulation time 29388604 ps
CPU time 0.92 seconds
Started Feb 21 02:13:36 PM PST 24
Finished Feb 21 02:13:37 PM PST 24
Peak memory 197324 kb
Host smart-0ed24c9b-efcb-497b-b5d2-97cba531599e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227267920 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.4227267920
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.756648822
Short name T488
Test name
Test status
Simulation time 15850455142 ps
CPU time 427.01 seconds
Started Feb 21 02:13:36 PM PST 24
Finished Feb 21 02:20:43 PM PST 24
Peak memory 199620 kb
Host smart-4969de4b-a796-4407-8a46-10fe76906cf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756648822 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.hmac_test_sha_vectors.756648822
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1222706958
Short name T562
Test name
Test status
Simulation time 3137155577 ps
CPU time 37.94 seconds
Started Feb 21 02:13:36 PM PST 24
Finished Feb 21 02:14:15 PM PST 24
Peak memory 199644 kb
Host smart-391bd451-f026-4f20-8e72-8103922e0d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222706958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1222706958
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.3571879199
Short name T59
Test name
Test status
Simulation time 35589843840 ps
CPU time 1672.47 seconds
Started Feb 21 02:19:46 PM PST 24
Finished Feb 21 02:47:39 PM PST 24
Peak memory 228360 kb
Host smart-581bdce1-f246-4323-b8f3-0e066ca7c54d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3571879199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.3571879199
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1625086452
Short name T400
Test name
Test status
Simulation time 23255612 ps
CPU time 0.58 seconds
Started Feb 21 02:13:57 PM PST 24
Finished Feb 21 02:13:58 PM PST 24
Peak memory 193752 kb
Host smart-1cb51416-8fb1-4fd2-aff9-46e85a2b35d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625086452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1625086452
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.441346267
Short name T574
Test name
Test status
Simulation time 397516405 ps
CPU time 9.65 seconds
Started Feb 21 02:13:45 PM PST 24
Finished Feb 21 02:13:55 PM PST 24
Peak memory 215404 kb
Host smart-eac20a9d-df60-4cf7-928b-0f8fd28678a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441346267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.441346267
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2645747734
Short name T167
Test name
Test status
Simulation time 1933629147 ps
CPU time 19.09 seconds
Started Feb 21 02:13:48 PM PST 24
Finished Feb 21 02:14:07 PM PST 24
Peak memory 199564 kb
Host smart-c71c48ef-f6e3-419f-b57a-4ff1f2135a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645747734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2645747734
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1116939706
Short name T437
Test name
Test status
Simulation time 266817775 ps
CPU time 13.67 seconds
Started Feb 21 02:13:54 PM PST 24
Finished Feb 21 02:14:08 PM PST 24
Peak memory 199480 kb
Host smart-d736d6af-31c9-4589-987d-2bdc1a126e80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116939706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1116939706
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3800835149
Short name T557
Test name
Test status
Simulation time 12060082962 ps
CPU time 75.65 seconds
Started Feb 21 02:13:55 PM PST 24
Finished Feb 21 02:15:11 PM PST 24
Peak memory 199700 kb
Host smart-ff5aa7f2-fbf7-4fea-81b4-f09b97169142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800835149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3800835149
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1314364814
Short name T181
Test name
Test status
Simulation time 283229796 ps
CPU time 3.86 seconds
Started Feb 21 02:13:47 PM PST 24
Finished Feb 21 02:13:52 PM PST 24
Peak memory 199424 kb
Host smart-8785b6c6-5677-4ce1-af73-c89abba9d8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314364814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1314364814
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3795524499
Short name T550
Test name
Test status
Simulation time 171043215 ps
CPU time 2.39 seconds
Started Feb 21 02:13:56 PM PST 24
Finished Feb 21 02:13:58 PM PST 24
Peak memory 199312 kb
Host smart-68fd4fce-e51e-4ba7-a273-fb5a0e6d6867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795524499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3795524499
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3500337453
Short name T316
Test name
Test status
Simulation time 44235013408 ps
CPU time 518.69 seconds
Started Feb 21 02:13:47 PM PST 24
Finished Feb 21 02:22:26 PM PST 24
Peak memory 199756 kb
Host smart-0d24f66a-927d-458d-b9d9-1b29d4061238
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500337453 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3500337453
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3920882462
Short name T213
Test name
Test status
Simulation time 193465607 ps
CPU time 0.95 seconds
Started Feb 21 02:13:56 PM PST 24
Finished Feb 21 02:13:58 PM PST 24
Peak memory 197304 kb
Host smart-1b587704-7dcc-468d-b003-c76b5450af54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920882462 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3920882462
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3916005263
Short name T161
Test name
Test status
Simulation time 1690599648 ps
CPU time 71.75 seconds
Started Feb 21 02:13:49 PM PST 24
Finished Feb 21 02:15:01 PM PST 24
Peak memory 199408 kb
Host smart-0978d5e0-828f-48c1-99e3-416c6bfa4cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916005263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3916005263
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.581069814
Short name T58
Test name
Test status
Simulation time 122762290425 ps
CPU time 1620.78 seconds
Started Feb 21 02:19:56 PM PST 24
Finished Feb 21 02:46:57 PM PST 24
Peak memory 224376 kb
Host smart-c77db86e-3a63-4812-ac85-105e95b1aa9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581069814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.581069814
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.29349794
Short name T222
Test name
Test status
Simulation time 34083487 ps
CPU time 0.56 seconds
Started Feb 21 02:13:57 PM PST 24
Finished Feb 21 02:13:58 PM PST 24
Peak memory 193984 kb
Host smart-60988d01-747a-4f39-9d9a-1178b4a15e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29349794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.29349794
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2454869643
Short name T590
Test name
Test status
Simulation time 1795255602 ps
CPU time 62.96 seconds
Started Feb 21 02:13:54 PM PST 24
Finished Feb 21 02:14:57 PM PST 24
Peak memory 224952 kb
Host smart-0a09b37b-8545-4e44-b9e0-11b8498658e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454869643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2454869643
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2563141956
Short name T187
Test name
Test status
Simulation time 7818772639 ps
CPU time 38.54 seconds
Started Feb 21 02:14:05 PM PST 24
Finished Feb 21 02:14:44 PM PST 24
Peak memory 199660 kb
Host smart-2510d076-ddb9-4e39-816c-23ae79e9e879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563141956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2563141956
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4083734776
Short name T249
Test name
Test status
Simulation time 1377692807 ps
CPU time 74.66 seconds
Started Feb 21 02:13:54 PM PST 24
Finished Feb 21 02:15:09 PM PST 24
Peak memory 199568 kb
Host smart-c2be333a-a158-4a81-9b97-6fa0a1834f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083734776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4083734776
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1803362503
Short name T435
Test name
Test status
Simulation time 2896917995 ps
CPU time 36.84 seconds
Started Feb 21 02:14:01 PM PST 24
Finished Feb 21 02:14:38 PM PST 24
Peak memory 199644 kb
Host smart-1fdd7839-4dd7-4835-956a-afdd0ea05dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803362503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1803362503
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.807098128
Short name T318
Test name
Test status
Simulation time 2523361431 ps
CPU time 33.5 seconds
Started Feb 21 02:13:55 PM PST 24
Finished Feb 21 02:14:29 PM PST 24
Peak memory 199684 kb
Host smart-cc2c311c-263a-4abf-989a-c31f6f5e2bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807098128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.807098128
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1116085829
Short name T1
Test name
Test status
Simulation time 1314174909 ps
CPU time 4.36 seconds
Started Feb 21 02:13:54 PM PST 24
Finished Feb 21 02:13:59 PM PST 24
Peak memory 199496 kb
Host smart-1628362f-e67c-42d1-965d-b9c3a676f0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116085829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1116085829
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2248276949
Short name T424
Test name
Test status
Simulation time 267989172 ps
CPU time 1.15 seconds
Started Feb 21 02:13:56 PM PST 24
Finished Feb 21 02:13:58 PM PST 24
Peak memory 198304 kb
Host smart-de6097fe-8156-4d5f-8031-f820a5648089
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248276949 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2248276949
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2008257047
Short name T186
Test name
Test status
Simulation time 7990650692 ps
CPU time 396.53 seconds
Started Feb 21 02:13:57 PM PST 24
Finished Feb 21 02:20:35 PM PST 24
Peak memory 199508 kb
Host smart-cdfdf7d1-49b7-42f2-ad63-45a641dadaf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008257047 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.2008257047
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3274289505
Short name T287
Test name
Test status
Simulation time 3750364815 ps
CPU time 40.45 seconds
Started Feb 21 02:13:57 PM PST 24
Finished Feb 21 02:14:39 PM PST 24
Peak memory 199680 kb
Host smart-27c09b34-13db-4b14-aa42-baf734e0a597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274289505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3274289505
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1016194540
Short name T239
Test name
Test status
Simulation time 31239721 ps
CPU time 0.58 seconds
Started Feb 21 02:14:01 PM PST 24
Finished Feb 21 02:14:02 PM PST 24
Peak memory 193764 kb
Host smart-d0f13d07-62c5-4209-99b9-eb7e04490802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016194540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1016194540
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1138793057
Short name T23
Test name
Test status
Simulation time 1928349974 ps
CPU time 32.3 seconds
Started Feb 21 02:13:57 PM PST 24
Finished Feb 21 02:14:30 PM PST 24
Peak memory 224140 kb
Host smart-f3266366-4603-4cbe-b552-15ecd79bf3cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1138793057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1138793057
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3556769071
Short name T266
Test name
Test status
Simulation time 1954113180 ps
CPU time 29.73 seconds
Started Feb 21 02:13:58 PM PST 24
Finished Feb 21 02:14:29 PM PST 24
Peak memory 199564 kb
Host smart-c40ba9a3-4e57-47b7-86dd-2f569867c010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556769071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3556769071
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.221885862
Short name T65
Test name
Test status
Simulation time 1494296654 ps
CPU time 76.18 seconds
Started Feb 21 02:13:58 PM PST 24
Finished Feb 21 02:15:15 PM PST 24
Peak memory 199628 kb
Host smart-2cbc3570-5dba-468b-b5ac-2358315aaf63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221885862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.221885862
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.514188064
Short name T241
Test name
Test status
Simulation time 2319503080 ps
CPU time 116.57 seconds
Started Feb 21 02:13:59 PM PST 24
Finished Feb 21 02:15:56 PM PST 24
Peak memory 199732 kb
Host smart-24b8f969-e4ac-461c-a552-c6639c41d135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514188064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.514188064
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.448057409
Short name T452
Test name
Test status
Simulation time 9310218058 ps
CPU time 71.69 seconds
Started Feb 21 02:13:56 PM PST 24
Finished Feb 21 02:15:08 PM PST 24
Peak memory 199660 kb
Host smart-4e078f01-beb1-492b-ba8a-7f6a2e464505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448057409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.448057409
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2259590073
Short name T279
Test name
Test status
Simulation time 635872722 ps
CPU time 4.33 seconds
Started Feb 21 02:14:04 PM PST 24
Finished Feb 21 02:14:09 PM PST 24
Peak memory 199536 kb
Host smart-166c0bfa-f703-4a35-9173-3c6f42f6cb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259590073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2259590073
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1845353807
Short name T83
Test name
Test status
Simulation time 105304191893 ps
CPU time 1306.58 seconds
Started Feb 21 02:14:01 PM PST 24
Finished Feb 21 02:35:48 PM PST 24
Peak memory 199652 kb
Host smart-cdddc687-adc4-4b9a-b452-a8dc1f79d1ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845353807 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1845353807
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3429740897
Short name T38
Test name
Test status
Simulation time 56493492 ps
CPU time 1.07 seconds
Started Feb 21 02:14:04 PM PST 24
Finished Feb 21 02:14:05 PM PST 24
Peak memory 198488 kb
Host smart-5e808859-883d-4964-ba37-f917ff7ef131
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429740897 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3429740897
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.246024358
Short name T378
Test name
Test status
Simulation time 3417059122 ps
CPU time 31.41 seconds
Started Feb 21 02:14:01 PM PST 24
Finished Feb 21 02:14:32 PM PST 24
Peak memory 199644 kb
Host smart-d0210f2b-9809-4ab7-a611-da84206b9436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246024358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.246024358
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2750852670
Short name T4
Test name
Test status
Simulation time 67440394728 ps
CPU time 398.9 seconds
Started Feb 21 02:20:20 PM PST 24
Finished Feb 21 02:26:59 PM PST 24
Peak memory 216208 kb
Host smart-1970eb13-f6a1-40ec-ab99-1ca66aa120f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750852670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.2750852670
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2820091630
Short name T271
Test name
Test status
Simulation time 42860484 ps
CPU time 0.57 seconds
Started Feb 21 02:14:06 PM PST 24
Finished Feb 21 02:14:07 PM PST 24
Peak memory 193800 kb
Host smart-8fe5d376-73d2-4ab8-8742-ffef4c79b68b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820091630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2820091630
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2385023153
Short name T384
Test name
Test status
Simulation time 1285767443 ps
CPU time 44.52 seconds
Started Feb 21 02:14:03 PM PST 24
Finished Feb 21 02:14:48 PM PST 24
Peak memory 232104 kb
Host smart-2eeb1acd-6a96-49ca-97e0-df26bfa5f5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385023153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2385023153
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.66545276
Short name T276
Test name
Test status
Simulation time 422261696 ps
CPU time 8.68 seconds
Started Feb 21 02:14:04 PM PST 24
Finished Feb 21 02:14:13 PM PST 24
Peak memory 199516 kb
Host smart-3a8513bd-7d59-4076-b5cb-441621c8e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66545276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.66545276
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_error.2873229533
Short name T231
Test name
Test status
Simulation time 8543810652 ps
CPU time 139.71 seconds
Started Feb 21 02:14:04 PM PST 24
Finished Feb 21 02:16:25 PM PST 24
Peak memory 199588 kb
Host smart-5fc19254-8a34-41a9-8e71-ac8f6fa50c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873229533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2873229533
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2837939851
Short name T268
Test name
Test status
Simulation time 2980229046 ps
CPU time 41.78 seconds
Started Feb 21 02:13:58 PM PST 24
Finished Feb 21 02:14:41 PM PST 24
Peak memory 199664 kb
Host smart-33027f8b-c2ba-4934-bd93-b9789e63a408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837939851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2837939851
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1012821239
Short name T495
Test name
Test status
Simulation time 1879761474 ps
CPU time 3.32 seconds
Started Feb 21 02:14:01 PM PST 24
Finished Feb 21 02:14:04 PM PST 24
Peak memory 199516 kb
Host smart-56604c95-b297-4e95-b32b-d92acb86db44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012821239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1012821239
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3320413116
Short name T492
Test name
Test status
Simulation time 23808627251 ps
CPU time 209.95 seconds
Started Feb 21 02:14:07 PM PST 24
Finished Feb 21 02:17:37 PM PST 24
Peak memory 208908 kb
Host smart-28a55577-45ac-40ec-9252-38352d947bec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320413116 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3320413116
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.4163230407
Short name T166
Test name
Test status
Simulation time 156701369 ps
CPU time 0.89 seconds
Started Feb 21 02:14:07 PM PST 24
Finished Feb 21 02:14:08 PM PST 24
Peak memory 196756 kb
Host smart-833a23eb-34d4-4b6e-b1e7-d40880e43e14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163230407 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.4163230407
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3711238744
Short name T317
Test name
Test status
Simulation time 25504498803 ps
CPU time 427.8 seconds
Started Feb 21 02:14:05 PM PST 24
Finished Feb 21 02:21:14 PM PST 24
Peak memory 199640 kb
Host smart-3ddefd95-4485-4072-a11b-86e6305ba991
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711238744 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.3711238744
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.925245950
Short name T577
Test name
Test status
Simulation time 1513074804 ps
CPU time 60.42 seconds
Started Feb 21 02:14:06 PM PST 24
Finished Feb 21 02:15:07 PM PST 24
Peak memory 199516 kb
Host smart-18a09187-a23a-4ded-a14d-aeafb9b6246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925245950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.925245950
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1415418897
Short name T288
Test name
Test status
Simulation time 17223069 ps
CPU time 0.6 seconds
Started Feb 21 02:14:14 PM PST 24
Finished Feb 21 02:14:15 PM PST 24
Peak memory 194748 kb
Host smart-4894fc55-39e2-4d59-945a-7f571da6988f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415418897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1415418897
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2499293346
Short name T496
Test name
Test status
Simulation time 1331102023 ps
CPU time 43.86 seconds
Started Feb 21 02:14:06 PM PST 24
Finished Feb 21 02:14:50 PM PST 24
Peak memory 231084 kb
Host smart-df065683-aa8d-4b02-8f3c-3d555cf1080f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499293346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2499293346
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2335821166
Short name T463
Test name
Test status
Simulation time 5264865970 ps
CPU time 41.39 seconds
Started Feb 21 02:14:03 PM PST 24
Finished Feb 21 02:14:44 PM PST 24
Peak memory 199708 kb
Host smart-d6cc8f87-4fab-4a09-a1c7-01fd1ff88e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335821166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2335821166
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1198824779
Short name T467
Test name
Test status
Simulation time 3146041184 ps
CPU time 80.9 seconds
Started Feb 21 02:14:06 PM PST 24
Finished Feb 21 02:15:28 PM PST 24
Peak memory 199672 kb
Host smart-079b5725-77d3-4084-a4f7-a4c7d485ea1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198824779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1198824779
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2265330747
Short name T293
Test name
Test status
Simulation time 13296278625 ps
CPU time 164.57 seconds
Started Feb 21 02:14:05 PM PST 24
Finished Feb 21 02:16:50 PM PST 24
Peak memory 199612 kb
Host smart-554df44f-4cc9-4dad-b135-86cab07c668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265330747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2265330747
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1638398311
Short name T236
Test name
Test status
Simulation time 1150631430 ps
CPU time 17.7 seconds
Started Feb 21 02:14:04 PM PST 24
Finished Feb 21 02:14:23 PM PST 24
Peak memory 199564 kb
Host smart-e187caed-6dc3-4f99-afb4-c16af9d7e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638398311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1638398311
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3941331396
Short name T592
Test name
Test status
Simulation time 799269316 ps
CPU time 3.83 seconds
Started Feb 21 02:14:06 PM PST 24
Finished Feb 21 02:14:10 PM PST 24
Peak memory 199476 kb
Host smart-098bb559-e2bd-47f7-941b-c48a082a6828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941331396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3941331396
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3689787678
Short name T129
Test name
Test status
Simulation time 84605212319 ps
CPU time 973.59 seconds
Started Feb 21 02:14:13 PM PST 24
Finished Feb 21 02:30:28 PM PST 24
Peak memory 240536 kb
Host smart-5798b3fc-2bc2-4280-928f-409d7f12636f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689787678 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3689787678
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2295685296
Short name T519
Test name
Test status
Simulation time 75696304 ps
CPU time 1.25 seconds
Started Feb 21 02:14:15 PM PST 24
Finished Feb 21 02:14:17 PM PST 24
Peak memory 198248 kb
Host smart-a48dd73a-9c12-47fe-b2ee-758ef0bad02b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295685296 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2295685296
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1549909291
Short name T489
Test name
Test status
Simulation time 15124992720 ps
CPU time 394.82 seconds
Started Feb 21 02:14:04 PM PST 24
Finished Feb 21 02:20:39 PM PST 24
Peak memory 199612 kb
Host smart-48f07ecd-6a5b-4753-8e46-27680ca70934
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549909291 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.1549909291
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1043480859
Short name T571
Test name
Test status
Simulation time 894586933 ps
CPU time 13.16 seconds
Started Feb 21 02:14:06 PM PST 24
Finished Feb 21 02:14:20 PM PST 24
Peak memory 199472 kb
Host smart-027b9ed8-826d-42d1-a27e-a184f0b6f03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043480859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1043480859
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.127218905
Short name T16
Test name
Test status
Simulation time 209534083521 ps
CPU time 1080.83 seconds
Started Feb 21 02:20:47 PM PST 24
Finished Feb 21 02:38:48 PM PST 24
Peak memory 215432 kb
Host smart-33c04773-835f-4334-97f3-1d50b29b62ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=127218905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.127218905
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2937572735
Short name T51
Test name
Test status
Simulation time 11091980 ps
CPU time 0.56 seconds
Started Feb 21 02:12:34 PM PST 24
Finished Feb 21 02:12:36 PM PST 24
Peak memory 193776 kb
Host smart-647cea09-b550-4789-9ab4-e6ada94b73fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937572735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2937572735
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.4138107379
Short name T426
Test name
Test status
Simulation time 1150285247 ps
CPU time 34.62 seconds
Started Feb 21 02:12:24 PM PST 24
Finished Feb 21 02:12:59 PM PST 24
Peak memory 207740 kb
Host smart-14e506d5-1fce-43f7-889e-7345f3712807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4138107379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4138107379
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1339009018
Short name T290
Test name
Test status
Simulation time 1246054204 ps
CPU time 59.77 seconds
Started Feb 21 02:12:26 PM PST 24
Finished Feb 21 02:13:26 PM PST 24
Peak memory 199588 kb
Host smart-8124da3f-dcde-485d-b826-69726c6b996b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339009018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1339009018
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3033314854
Short name T389
Test name
Test status
Simulation time 20753975500 ps
CPU time 142.35 seconds
Started Feb 21 02:12:32 PM PST 24
Finished Feb 21 02:14:56 PM PST 24
Peak memory 199704 kb
Host smart-5963d9a8-7fec-4950-ac9a-d50d6610eb7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033314854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3033314854
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1001020923
Short name T104
Test name
Test status
Simulation time 1518131104 ps
CPU time 17.09 seconds
Started Feb 21 02:12:26 PM PST 24
Finished Feb 21 02:12:43 PM PST 24
Peak memory 199396 kb
Host smart-4fb8093f-7fc8-45a4-8f32-b916a90c9acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001020923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1001020923
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.24901319
Short name T490
Test name
Test status
Simulation time 992282325 ps
CPU time 14.3 seconds
Started Feb 21 02:12:25 PM PST 24
Finished Feb 21 02:12:40 PM PST 24
Peak memory 199516 kb
Host smart-26ef1bfa-4556-4940-af51-657d1a95e6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24901319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.24901319
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1017265475
Short name T44
Test name
Test status
Simulation time 126619860 ps
CPU time 0.89 seconds
Started Feb 21 02:12:34 PM PST 24
Finished Feb 21 02:12:36 PM PST 24
Peak memory 216716 kb
Host smart-878f503d-e34f-46b2-ba43-76c94b58e445
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017265475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1017265475
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3949912680
Short name T237
Test name
Test status
Simulation time 171748341 ps
CPU time 2.59 seconds
Started Feb 21 02:12:27 PM PST 24
Finished Feb 21 02:12:30 PM PST 24
Peak memory 199548 kb
Host smart-d18fc8ed-952f-469c-8ffa-3dfee54e11d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949912680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3949912680
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2932575600
Short name T70
Test name
Test status
Simulation time 558855529846 ps
CPU time 1711.31 seconds
Started Feb 21 02:12:25 PM PST 24
Finished Feb 21 02:40:57 PM PST 24
Peak memory 199684 kb
Host smart-ee55c662-812a-4096-a832-d914a3f8deb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932575600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2932575600
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2543152907
Short name T423
Test name
Test status
Simulation time 54679868 ps
CPU time 1.13 seconds
Started Feb 21 02:12:25 PM PST 24
Finished Feb 21 02:12:27 PM PST 24
Peak memory 198332 kb
Host smart-dc4f7130-bd67-447a-8674-eb3744581257
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543152907 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2543152907
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3952954295
Short name T313
Test name
Test status
Simulation time 15937627615 ps
CPU time 399.64 seconds
Started Feb 21 02:12:25 PM PST 24
Finished Feb 21 02:19:05 PM PST 24
Peak memory 199624 kb
Host smart-3f0bc076-71c3-48d4-861c-e8086343e990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952954295 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.3952954295
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2791173736
Short name T214
Test name
Test status
Simulation time 5421414094 ps
CPU time 34.57 seconds
Started Feb 21 02:12:27 PM PST 24
Finished Feb 21 02:13:01 PM PST 24
Peak memory 199728 kb
Host smart-b7320482-b061-4595-b444-8262e9c8757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791173736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2791173736
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3459727201
Short name T459
Test name
Test status
Simulation time 46886728 ps
CPU time 0.55 seconds
Started Feb 21 02:14:38 PM PST 24
Finished Feb 21 02:14:39 PM PST 24
Peak memory 193780 kb
Host smart-876a4a2f-305e-4a8d-8af6-48ec19cd85a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459727201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3459727201
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1350067300
Short name T203
Test name
Test status
Simulation time 6133281327 ps
CPU time 43.99 seconds
Started Feb 21 02:14:14 PM PST 24
Finished Feb 21 02:14:58 PM PST 24
Peak memory 222904 kb
Host smart-98940aec-32c4-4762-bbf3-1386226f9fb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350067300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1350067300
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1400153720
Short name T162
Test name
Test status
Simulation time 485096265 ps
CPU time 11.48 seconds
Started Feb 21 02:14:19 PM PST 24
Finished Feb 21 02:14:30 PM PST 24
Peak memory 199632 kb
Host smart-5355bc78-d8c1-4423-ac07-56a4005549ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400153720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1400153720
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.231408544
Short name T226
Test name
Test status
Simulation time 32270375838 ps
CPU time 130.59 seconds
Started Feb 21 02:14:14 PM PST 24
Finished Feb 21 02:16:25 PM PST 24
Peak memory 199700 kb
Host smart-fad985f3-25b9-4717-b56f-9a4827987b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231408544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.231408544
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.31435643
Short name T388
Test name
Test status
Simulation time 938686963 ps
CPU time 46.88 seconds
Started Feb 21 02:14:19 PM PST 24
Finished Feb 21 02:15:06 PM PST 24
Peak memory 199612 kb
Host smart-45ae1e96-c0f3-4724-9641-e98f65b55a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31435643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.31435643
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3609263068
Short name T154
Test name
Test status
Simulation time 91473555 ps
CPU time 1.64 seconds
Started Feb 21 02:14:19 PM PST 24
Finished Feb 21 02:14:21 PM PST 24
Peak memory 199620 kb
Host smart-07dc5c9c-f632-4786-82e1-bcc61d160b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609263068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3609263068
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.92359392
Short name T386
Test name
Test status
Simulation time 31239639422 ps
CPU time 1515.65 seconds
Started Feb 21 02:14:34 PM PST 24
Finished Feb 21 02:39:51 PM PST 24
Peak memory 216096 kb
Host smart-34b72994-30e7-440d-8eae-72e1c4be8be6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92359392 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.92359392
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.114498722
Short name T49
Test name
Test status
Simulation time 59123417 ps
CPU time 1.17 seconds
Started Feb 21 02:14:34 PM PST 24
Finished Feb 21 02:14:36 PM PST 24
Peak memory 197072 kb
Host smart-559e1d89-ecd0-4641-a2a0-5cf396602b28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114498722 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.114498722
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3479488232
Short name T86
Test name
Test status
Simulation time 162088250488 ps
CPU time 442.62 seconds
Started Feb 21 02:14:43 PM PST 24
Finished Feb 21 02:22:06 PM PST 24
Peak memory 199572 kb
Host smart-95645d92-daa9-4304-b673-ec11ce243cd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479488232 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.3479488232
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1452189630
Short name T393
Test name
Test status
Simulation time 5171904437 ps
CPU time 17.5 seconds
Started Feb 21 02:14:34 PM PST 24
Finished Feb 21 02:14:52 PM PST 24
Peak memory 199668 kb
Host smart-aa9eb880-3cbc-46f5-ac55-9ad5b5710e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452189630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1452189630
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2230321819
Short name T582
Test name
Test status
Simulation time 38420582 ps
CPU time 0.58 seconds
Started Feb 21 02:14:41 PM PST 24
Finished Feb 21 02:14:42 PM PST 24
Peak memory 193960 kb
Host smart-220d05cf-06b3-48ad-9b7b-976e95f1cbf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230321819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2230321819
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.738787267
Short name T171
Test name
Test status
Simulation time 47860384 ps
CPU time 1.65 seconds
Started Feb 21 02:14:33 PM PST 24
Finished Feb 21 02:14:35 PM PST 24
Peak memory 199828 kb
Host smart-3c2b8e81-9edc-45e4-a654-b34c62aa0dce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738787267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.738787267
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.79169420
Short name T116
Test name
Test status
Simulation time 215574135 ps
CPU time 9.98 seconds
Started Feb 21 02:14:34 PM PST 24
Finished Feb 21 02:14:45 PM PST 24
Peak memory 199476 kb
Host smart-04aa2a2c-00db-4a1d-9b53-9aa54102b356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79169420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.79169420
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1349010522
Short name T340
Test name
Test status
Simulation time 6184747207 ps
CPU time 76.52 seconds
Started Feb 21 02:14:43 PM PST 24
Finished Feb 21 02:16:00 PM PST 24
Peak memory 199596 kb
Host smart-bc45485a-1b0c-44a5-a8e9-80070efecb57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349010522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1349010522
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3471998715
Short name T509
Test name
Test status
Simulation time 347547173 ps
CPU time 19.3 seconds
Started Feb 21 02:14:34 PM PST 24
Finished Feb 21 02:14:54 PM PST 24
Peak memory 199520 kb
Host smart-1b531c5a-9696-4651-9e6b-8072f7755740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471998715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3471998715
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.860303324
Short name T47
Test name
Test status
Simulation time 5803247549 ps
CPU time 35.71 seconds
Started Feb 21 02:14:36 PM PST 24
Finished Feb 21 02:15:12 PM PST 24
Peak memory 199696 kb
Host smart-89319ee4-fff7-4cee-ada5-d72a135fecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860303324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.860303324
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3129072466
Short name T514
Test name
Test status
Simulation time 96750251 ps
CPU time 2.39 seconds
Started Feb 21 02:14:43 PM PST 24
Finished Feb 21 02:14:46 PM PST 24
Peak memory 199484 kb
Host smart-e3fccf96-6bbd-4cbc-93ec-c4febe3078b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129072466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3129072466
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2236597327
Short name T442
Test name
Test status
Simulation time 1297874935426 ps
CPU time 1761.76 seconds
Started Feb 21 02:14:41 PM PST 24
Finished Feb 21 02:44:03 PM PST 24
Peak memory 224344 kb
Host smart-e57e0e81-f71c-4a37-be38-9daf720edae2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236597327 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2236597327
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1791973302
Short name T399
Test name
Test status
Simulation time 106657752 ps
CPU time 1.12 seconds
Started Feb 21 02:14:40 PM PST 24
Finished Feb 21 02:14:42 PM PST 24
Peak memory 197972 kb
Host smart-32952589-6217-4a70-96b4-0345c8f83ed6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791973302 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1791973302
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.4071369806
Short name T380
Test name
Test status
Simulation time 16659758364 ps
CPU time 407.97 seconds
Started Feb 21 02:14:32 PM PST 24
Finished Feb 21 02:21:21 PM PST 24
Peak memory 199548 kb
Host smart-8527fc89-de81-4b0f-9bc8-2ab42524d607
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071369806 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.4071369806
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2546552417
Short name T305
Test name
Test status
Simulation time 1245010667 ps
CPU time 22.03 seconds
Started Feb 21 02:14:33 PM PST 24
Finished Feb 21 02:14:56 PM PST 24
Peak memory 199536 kb
Host smart-bde6175d-fcb1-4735-995c-18d111b3701b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546552417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2546552417
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1558451172
Short name T211
Test name
Test status
Simulation time 13669562 ps
CPU time 0.57 seconds
Started Feb 21 02:14:40 PM PST 24
Finished Feb 21 02:14:40 PM PST 24
Peak memory 193716 kb
Host smart-0a98625a-f0f4-42b7-a97c-f4ecd0d36258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558451172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1558451172
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1200288458
Short name T273
Test name
Test status
Simulation time 11759536057 ps
CPU time 35.13 seconds
Started Feb 21 02:14:40 PM PST 24
Finished Feb 21 02:15:15 PM PST 24
Peak memory 209032 kb
Host smart-4a63f5ec-ff9f-4c25-ab71-c4d217009235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1200288458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1200288458
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.53936055
Short name T118
Test name
Test status
Simulation time 158774433 ps
CPU time 8.8 seconds
Started Feb 21 02:14:39 PM PST 24
Finished Feb 21 02:14:48 PM PST 24
Peak memory 199512 kb
Host smart-40d0fbee-d30a-4e0c-88a7-8fa2bf043da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53936055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.53936055
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3477534103
Short name T244
Test name
Test status
Simulation time 7063182470 ps
CPU time 42.56 seconds
Started Feb 21 02:14:46 PM PST 24
Finished Feb 21 02:15:30 PM PST 24
Peak memory 199704 kb
Host smart-3285aee2-b11a-4479-855a-4effbce7d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477534103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3477534103
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2403290352
Short name T456
Test name
Test status
Simulation time 3148711530 ps
CPU time 80.5 seconds
Started Feb 21 02:14:47 PM PST 24
Finished Feb 21 02:16:08 PM PST 24
Peak memory 199564 kb
Host smart-75440cbe-4208-49ba-9eff-8aa3b9bc7b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403290352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2403290352
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3852996324
Short name T257
Test name
Test status
Simulation time 2131387233 ps
CPU time 2.89 seconds
Started Feb 21 02:14:41 PM PST 24
Finished Feb 21 02:14:44 PM PST 24
Peak memory 199456 kb
Host smart-7e19000a-6579-41ad-afe0-577c44dc4418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852996324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3852996324
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2650126930
Short name T554
Test name
Test status
Simulation time 111548334768 ps
CPU time 892.34 seconds
Started Feb 21 02:14:42 PM PST 24
Finished Feb 21 02:29:35 PM PST 24
Peak memory 232376 kb
Host smart-d5492b79-331e-45d7-8d12-3baa7ff5865f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650126930 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2650126930
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.627259805
Short name T60
Test name
Test status
Simulation time 37438072545 ps
CPU time 143.31 seconds
Started Feb 21 02:14:45 PM PST 24
Finished Feb 21 02:17:09 PM PST 24
Peak memory 209340 kb
Host smart-3dcb5411-98ea-43d8-8ddb-6c48e1dadfb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=627259805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.627259805
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3886432019
Short name T229
Test name
Test status
Simulation time 46987836 ps
CPU time 0.87 seconds
Started Feb 21 02:14:43 PM PST 24
Finished Feb 21 02:14:44 PM PST 24
Peak memory 196888 kb
Host smart-dace3d27-5880-4612-8591-19dee5838c50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886432019 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3886432019
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.578264058
Short name T482
Test name
Test status
Simulation time 56518935032 ps
CPU time 459.06 seconds
Started Feb 21 02:14:40 PM PST 24
Finished Feb 21 02:22:20 PM PST 24
Peak memory 199544 kb
Host smart-2170ba43-992f-4dd3-acf3-3a2ace7de81f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578264058 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.hmac_test_sha_vectors.578264058
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3833495918
Short name T436
Test name
Test status
Simulation time 3383185638 ps
CPU time 44.08 seconds
Started Feb 21 02:14:40 PM PST 24
Finished Feb 21 02:15:25 PM PST 24
Peak memory 199644 kb
Host smart-98517353-83b0-4e6c-b127-6d900a5d89e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833495918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3833495918
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.716556883
Short name T352
Test name
Test status
Simulation time 25067379 ps
CPU time 0.58 seconds
Started Feb 21 02:14:49 PM PST 24
Finished Feb 21 02:14:50 PM PST 24
Peak memory 194088 kb
Host smart-ad47f6a5-c7c3-4f68-95d9-2b566af44686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716556883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.716556883
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2853015217
Short name T30
Test name
Test status
Simulation time 876780010 ps
CPU time 39.2 seconds
Started Feb 21 02:14:44 PM PST 24
Finished Feb 21 02:15:23 PM PST 24
Peak memory 227112 kb
Host smart-9fd93b49-a4d3-4446-9ada-48cc34c20b5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853015217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2853015217
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.95398116
Short name T341
Test name
Test status
Simulation time 641105107 ps
CPU time 12.24 seconds
Started Feb 21 02:14:46 PM PST 24
Finished Feb 21 02:14:59 PM PST 24
Peak memory 199548 kb
Host smart-c7916942-efe2-48d2-a359-a7eabdc65cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95398116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.95398116
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.542711733
Short name T382
Test name
Test status
Simulation time 2382777348 ps
CPU time 56.91 seconds
Started Feb 21 02:14:46 PM PST 24
Finished Feb 21 02:15:43 PM PST 24
Peak memory 199636 kb
Host smart-7a5ba301-9143-43ad-96a5-301494cf62fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542711733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.542711733
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1218114097
Short name T411
Test name
Test status
Simulation time 2008159651 ps
CPU time 101.16 seconds
Started Feb 21 02:14:43 PM PST 24
Finished Feb 21 02:16:25 PM PST 24
Peak memory 199508 kb
Host smart-1cbc92b2-5677-46db-85e6-72067b5a5dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218114097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1218114097
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2368616443
Short name T342
Test name
Test status
Simulation time 1806173164 ps
CPU time 91.74 seconds
Started Feb 21 02:14:45 PM PST 24
Finished Feb 21 02:16:18 PM PST 24
Peak memory 199548 kb
Host smart-71866a6f-60ea-4197-9b5f-c9de416ac704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368616443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2368616443
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1260367901
Short name T531
Test name
Test status
Simulation time 665698786 ps
CPU time 2.27 seconds
Started Feb 21 02:14:43 PM PST 24
Finished Feb 21 02:14:46 PM PST 24
Peak memory 199568 kb
Host smart-bebaea3e-1c80-4376-bf0d-4e1b230477e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260367901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1260367901
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1575931367
Short name T78
Test name
Test status
Simulation time 439721231827 ps
CPU time 934.03 seconds
Started Feb 21 02:14:43 PM PST 24
Finished Feb 21 02:30:17 PM PST 24
Peak memory 240656 kb
Host smart-c4b85e95-5b18-4e7c-8444-ef964bdeadb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575931367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1575931367
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1338844965
Short name T27
Test name
Test status
Simulation time 88657107 ps
CPU time 0.92 seconds
Started Feb 21 02:14:44 PM PST 24
Finished Feb 21 02:14:45 PM PST 24
Peak memory 197368 kb
Host smart-ef6610a1-2b7a-41bb-875b-b325dbfe0214
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338844965 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1338844965
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1726280797
Short name T383
Test name
Test status
Simulation time 52186692927 ps
CPU time 421.1 seconds
Started Feb 21 02:14:41 PM PST 24
Finished Feb 21 02:21:42 PM PST 24
Peak memory 199600 kb
Host smart-e43cdee4-eebd-4557-99dc-7624e0d92b8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726280797 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.1726280797
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2911320978
Short name T332
Test name
Test status
Simulation time 2406569421 ps
CPU time 46.04 seconds
Started Feb 21 02:14:43 PM PST 24
Finished Feb 21 02:15:30 PM PST 24
Peak memory 199636 kb
Host smart-94547beb-9077-403a-b47b-c43c994e0a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911320978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2911320978
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.109878047
Short name T575
Test name
Test status
Simulation time 81145703 ps
CPU time 0.57 seconds
Started Feb 21 02:15:05 PM PST 24
Finished Feb 21 02:15:07 PM PST 24
Peak memory 194776 kb
Host smart-bdb95cb4-ca49-4571-a0a2-9eaf983198a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109878047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.109878047
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1853482779
Short name T369
Test name
Test status
Simulation time 38345282 ps
CPU time 1.55 seconds
Started Feb 21 02:14:52 PM PST 24
Finished Feb 21 02:14:54 PM PST 24
Peak memory 199468 kb
Host smart-5e140a7d-bf44-4b47-aada-6233d74f8d3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853482779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1853482779
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.962943216
Short name T465
Test name
Test status
Simulation time 939068670 ps
CPU time 10.62 seconds
Started Feb 21 02:14:55 PM PST 24
Finished Feb 21 02:15:06 PM PST 24
Peak memory 199488 kb
Host smart-9f3dc60e-967d-4f2f-aab1-580c6b627277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962943216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.962943216
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1924041835
Short name T122
Test name
Test status
Simulation time 3223778574 ps
CPU time 44.96 seconds
Started Feb 21 02:14:54 PM PST 24
Finished Feb 21 02:15:39 PM PST 24
Peak memory 199612 kb
Host smart-3d4c6080-5afd-423b-bade-c66ec7e27a63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924041835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1924041835
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3432775312
Short name T535
Test name
Test status
Simulation time 5802649188 ps
CPU time 70.83 seconds
Started Feb 21 02:14:50 PM PST 24
Finished Feb 21 02:16:02 PM PST 24
Peak memory 199664 kb
Host smart-eb4075e4-2e4a-4c2d-ac55-0d00830b9bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432775312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3432775312
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2384280603
Short name T131
Test name
Test status
Simulation time 7784025718 ps
CPU time 69.59 seconds
Started Feb 21 02:14:49 PM PST 24
Finished Feb 21 02:16:00 PM PST 24
Peak memory 199664 kb
Host smart-a9d7ddad-a909-4345-98d1-33abf1b0464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384280603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2384280603
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2184953197
Short name T464
Test name
Test status
Simulation time 81847553 ps
CPU time 1.38 seconds
Started Feb 21 02:14:49 PM PST 24
Finished Feb 21 02:14:51 PM PST 24
Peak memory 199460 kb
Host smart-89aed456-98e7-46fd-974e-4bd22e14522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184953197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2184953197
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.279310403
Short name T46
Test name
Test status
Simulation time 60271597444 ps
CPU time 962.05 seconds
Started Feb 21 02:14:53 PM PST 24
Finished Feb 21 02:30:55 PM PST 24
Peak memory 231396 kb
Host smart-85de15b8-82ad-46fa-b3d5-da4ad5418a6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279310403 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.279310403
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1095434317
Short name T560
Test name
Test status
Simulation time 116082413 ps
CPU time 1.11 seconds
Started Feb 21 02:14:52 PM PST 24
Finished Feb 21 02:14:53 PM PST 24
Peak memory 198372 kb
Host smart-a2e13ad1-69c0-4c4a-82d5-a74065169631
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095434317 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1095434317
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2054589839
Short name T478
Test name
Test status
Simulation time 102981792958 ps
CPU time 432.76 seconds
Started Feb 21 02:14:52 PM PST 24
Finished Feb 21 02:22:06 PM PST 24
Peak memory 199572 kb
Host smart-f62dad02-e0cc-4d38-89be-83e0dd541b3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054589839 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.2054589839
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2696958311
Short name T322
Test name
Test status
Simulation time 7735853383 ps
CPU time 23.69 seconds
Started Feb 21 02:14:51 PM PST 24
Finished Feb 21 02:15:15 PM PST 24
Peak memory 199636 kb
Host smart-920d6fb2-86c7-4b97-8728-d6d98749c8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696958311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2696958311
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.399729083
Short name T306
Test name
Test status
Simulation time 52442172 ps
CPU time 0.59 seconds
Started Feb 21 02:15:04 PM PST 24
Finished Feb 21 02:15:05 PM PST 24
Peak memory 194940 kb
Host smart-8fa59eec-bbe5-45f1-b14d-faae1b04a60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399729083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.399729083
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1266233067
Short name T485
Test name
Test status
Simulation time 2067601297 ps
CPU time 59.95 seconds
Started Feb 21 02:15:05 PM PST 24
Finished Feb 21 02:16:05 PM PST 24
Peak memory 229128 kb
Host smart-07ace324-98fa-4f5b-a1fe-33a43bcf213c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266233067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1266233067
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4256515010
Short name T66
Test name
Test status
Simulation time 20098072135 ps
CPU time 26.78 seconds
Started Feb 21 02:15:06 PM PST 24
Finished Feb 21 02:15:33 PM PST 24
Peak memory 199632 kb
Host smart-38f0e9cf-ca5f-4e95-a089-f47a6e21cd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256515010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4256515010
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.82869488
Short name T121
Test name
Test status
Simulation time 2745046524 ps
CPU time 142.59 seconds
Started Feb 21 02:15:11 PM PST 24
Finished Feb 21 02:17:34 PM PST 24
Peak memory 199608 kb
Host smart-b9776ddc-b408-4333-9cca-55543bf67815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82869488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.82869488
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3873808812
Short name T177
Test name
Test status
Simulation time 17426980997 ps
CPU time 32.33 seconds
Started Feb 21 02:15:02 PM PST 24
Finished Feb 21 02:15:35 PM PST 24
Peak memory 199660 kb
Host smart-d1ce9817-bc84-4fea-9bc8-19ddd1d2e9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873808812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3873808812
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3815457149
Short name T481
Test name
Test status
Simulation time 6045041548 ps
CPU time 79.18 seconds
Started Feb 21 02:15:03 PM PST 24
Finished Feb 21 02:16:23 PM PST 24
Peak memory 199700 kb
Host smart-47f86402-6e39-4e1a-bc26-eb601430764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815457149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3815457149
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3239795376
Short name T182
Test name
Test status
Simulation time 171698605 ps
CPU time 1.92 seconds
Started Feb 21 02:15:04 PM PST 24
Finished Feb 21 02:15:07 PM PST 24
Peak memory 199552 kb
Host smart-08f8347d-95ec-44b4-ad06-357c281ca544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239795376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3239795376
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.4128483025
Short name T127
Test name
Test status
Simulation time 70810944241 ps
CPU time 638.98 seconds
Started Feb 21 02:15:04 PM PST 24
Finished Feb 21 02:25:44 PM PST 24
Peak memory 199712 kb
Host smart-fbb3a8c9-0b6a-41bb-a1e8-d23eae7fda1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128483025 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.4128483025
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1404542335
Short name T173
Test name
Test status
Simulation time 55224171 ps
CPU time 1.16 seconds
Started Feb 21 02:15:03 PM PST 24
Finished Feb 21 02:15:05 PM PST 24
Peak memory 198664 kb
Host smart-7ba040ff-2ba1-4694-96d2-99cc55176f8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404542335 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1404542335
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2218885474
Short name T487
Test name
Test status
Simulation time 29328905808 ps
CPU time 386.5 seconds
Started Feb 21 02:15:05 PM PST 24
Finished Feb 21 02:21:32 PM PST 24
Peak memory 199820 kb
Host smart-0a44edb3-ed5e-4e9d-8f49-278812edfa84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218885474 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.2218885474
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3289770303
Short name T218
Test name
Test status
Simulation time 311017714 ps
CPU time 7.57 seconds
Started Feb 21 02:15:05 PM PST 24
Finished Feb 21 02:15:13 PM PST 24
Peak memory 199508 kb
Host smart-8b838e9a-df8b-495c-b9c8-870759945ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289770303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3289770303
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.898422974
Short name T302
Test name
Test status
Simulation time 52314252 ps
CPU time 0.62 seconds
Started Feb 21 02:15:19 PM PST 24
Finished Feb 21 02:15:19 PM PST 24
Peak memory 193756 kb
Host smart-9f4a1ae2-f91a-44e3-822f-fc44162e9e10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898422974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.898422974
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1957100004
Short name T191
Test name
Test status
Simulation time 183761561 ps
CPU time 5.38 seconds
Started Feb 21 02:15:24 PM PST 24
Finished Feb 21 02:15:29 PM PST 24
Peak memory 199556 kb
Host smart-3383b102-51ef-4f8b-87d7-0753dbbbfc52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957100004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1957100004
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1376230794
Short name T434
Test name
Test status
Simulation time 1220953869 ps
CPU time 55.63 seconds
Started Feb 21 02:15:18 PM PST 24
Finished Feb 21 02:16:14 PM PST 24
Peak memory 199424 kb
Host smart-a37259b4-5ee6-4911-9485-81b1e0d98519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376230794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1376230794
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3012662802
Short name T28
Test name
Test status
Simulation time 2101572618 ps
CPU time 21.75 seconds
Started Feb 21 02:15:17 PM PST 24
Finished Feb 21 02:15:39 PM PST 24
Peak memory 199556 kb
Host smart-ce61994d-4aef-4b49-96d5-479ec09a52cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012662802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3012662802
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.4162822308
Short name T451
Test name
Test status
Simulation time 7122563702 ps
CPU time 30.1 seconds
Started Feb 21 02:15:18 PM PST 24
Finished Feb 21 02:15:48 PM PST 24
Peak memory 199704 kb
Host smart-c62e8120-742b-494e-ac5b-fcbe28d8fbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162822308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4162822308
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2194945489
Short name T175
Test name
Test status
Simulation time 18005869460 ps
CPU time 77.71 seconds
Started Feb 21 02:15:20 PM PST 24
Finished Feb 21 02:16:38 PM PST 24
Peak memory 199632 kb
Host smart-e6761831-e1e9-4b0d-b4ee-f76c246d4264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194945489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2194945489
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.957474313
Short name T275
Test name
Test status
Simulation time 115903653 ps
CPU time 2.77 seconds
Started Feb 21 02:15:20 PM PST 24
Finished Feb 21 02:15:23 PM PST 24
Peak memory 199596 kb
Host smart-6f4b4398-845f-4052-a550-e65e97d073aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957474313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.957474313
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.326438583
Short name T39
Test name
Test status
Simulation time 61055638844 ps
CPU time 693.61 seconds
Started Feb 21 02:15:17 PM PST 24
Finished Feb 21 02:26:51 PM PST 24
Peak memory 199708 kb
Host smart-18a230ba-316f-4601-93f1-074e8878ad43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326438583 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.326438583
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2059532187
Short name T329
Test name
Test status
Simulation time 136885356 ps
CPU time 0.91 seconds
Started Feb 21 02:15:26 PM PST 24
Finished Feb 21 02:15:27 PM PST 24
Peak memory 197052 kb
Host smart-5a59e9de-d3b6-4a7e-b7b3-e6f8be7c0c0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059532187 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2059532187
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.4290109985
Short name T579
Test name
Test status
Simulation time 9042921896 ps
CPU time 449.39 seconds
Started Feb 21 02:15:21 PM PST 24
Finished Feb 21 02:22:50 PM PST 24
Peak memory 199540 kb
Host smart-b95bc2a6-01b6-4a23-bb2f-93e31e7185f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290109985 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.4290109985
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3252366608
Short name T439
Test name
Test status
Simulation time 76359924 ps
CPU time 1.07 seconds
Started Feb 21 02:15:19 PM PST 24
Finished Feb 21 02:15:20 PM PST 24
Peak memory 199544 kb
Host smart-5a7cfaa4-1b51-4f5e-807c-a319accd4666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252366608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3252366608
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3986717324
Short name T289
Test name
Test status
Simulation time 71572502 ps
CPU time 0.58 seconds
Started Feb 21 02:15:30 PM PST 24
Finished Feb 21 02:15:31 PM PST 24
Peak memory 194824 kb
Host smart-08bc701b-48c9-4654-adc5-d638c3abf1d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986717324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3986717324
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2519635990
Short name T551
Test name
Test status
Simulation time 1323102118 ps
CPU time 25.85 seconds
Started Feb 21 02:15:21 PM PST 24
Finished Feb 21 02:15:47 PM PST 24
Peak memory 229264 kb
Host smart-97d6d4f9-06ab-4648-ab65-534f849abf78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519635990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2519635990
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.729515324
Short name T106
Test name
Test status
Simulation time 10754961233 ps
CPU time 38.19 seconds
Started Feb 21 02:15:28 PM PST 24
Finished Feb 21 02:16:06 PM PST 24
Peak memory 199652 kb
Host smart-2a54bb6c-814e-4b28-85b2-1283a58b7c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729515324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.729515324
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_error.2102618066
Short name T183
Test name
Test status
Simulation time 1294920368 ps
CPU time 33.53 seconds
Started Feb 21 02:15:30 PM PST 24
Finished Feb 21 02:16:04 PM PST 24
Peak memory 199548 kb
Host smart-b939ee97-4c7f-4590-a2db-6e16425a809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102618066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2102618066
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_smoke.2142498352
Short name T283
Test name
Test status
Simulation time 111631588 ps
CPU time 2.77 seconds
Started Feb 21 02:15:19 PM PST 24
Finished Feb 21 02:15:22 PM PST 24
Peak memory 199780 kb
Host smart-c971761d-1145-4936-ad94-95a8d5eafb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142498352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2142498352
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.4111281485
Short name T73
Test name
Test status
Simulation time 47638685005 ps
CPU time 563.92 seconds
Started Feb 21 02:15:23 PM PST 24
Finished Feb 21 02:24:47 PM PST 24
Peak memory 199708 kb
Host smart-040169a9-5716-4e76-bd07-36259a0cbf90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111281485 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.4111281485
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1017900128
Short name T588
Test name
Test status
Simulation time 63715334 ps
CPU time 0.92 seconds
Started Feb 21 02:15:28 PM PST 24
Finished Feb 21 02:15:29 PM PST 24
Peak memory 196920 kb
Host smart-c6c35785-9838-4112-a97a-3354ba15b4c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017900128 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1017900128
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1005410408
Short name T62
Test name
Test status
Simulation time 27342814047 ps
CPU time 442.05 seconds
Started Feb 21 02:15:19 PM PST 24
Finished Feb 21 02:22:41 PM PST 24
Peak memory 199628 kb
Host smart-96c666d7-1489-46e2-94da-253f91c67d2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005410408 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.1005410408
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3044127791
Short name T473
Test name
Test status
Simulation time 10699998681 ps
CPU time 81.51 seconds
Started Feb 21 02:15:27 PM PST 24
Finished Feb 21 02:16:49 PM PST 24
Peak memory 199692 kb
Host smart-d345ec69-45fd-4e1b-b999-a0e67962408b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044127791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3044127791
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.4168377170
Short name T36
Test name
Test status
Simulation time 13706340 ps
CPU time 0.56 seconds
Started Feb 21 02:15:36 PM PST 24
Finished Feb 21 02:15:37 PM PST 24
Peak memory 193780 kb
Host smart-1b02ae63-d5d3-4c82-8529-de69bb2f11d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168377170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.4168377170
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3906023043
Short name T570
Test name
Test status
Simulation time 3082024400 ps
CPU time 25.98 seconds
Started Feb 21 02:15:30 PM PST 24
Finished Feb 21 02:15:56 PM PST 24
Peak memory 207856 kb
Host smart-de64adf4-d091-4323-9ed6-6dc238e1eb45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906023043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3906023043
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1739048564
Short name T471
Test name
Test status
Simulation time 27256109293 ps
CPU time 23.65 seconds
Started Feb 21 02:15:27 PM PST 24
Finished Feb 21 02:15:51 PM PST 24
Peak memory 199644 kb
Host smart-705ec571-52dd-42db-86bc-3f063c487c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739048564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1739048564
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1666494275
Short name T412
Test name
Test status
Simulation time 3163810231 ps
CPU time 87.83 seconds
Started Feb 21 02:15:28 PM PST 24
Finished Feb 21 02:16:56 PM PST 24
Peak memory 199684 kb
Host smart-a9a3b6a4-17fc-4276-b1d3-417d88bc04cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666494275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1666494275
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.4283342391
Short name T407
Test name
Test status
Simulation time 871065648 ps
CPU time 44.91 seconds
Started Feb 21 02:15:27 PM PST 24
Finished Feb 21 02:16:12 PM PST 24
Peak memory 199756 kb
Host smart-1a2f7a8e-ae06-4eeb-b35f-10e6e7f5c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283342391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4283342391
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.825236019
Short name T246
Test name
Test status
Simulation time 2575229966 ps
CPU time 35.27 seconds
Started Feb 21 02:15:28 PM PST 24
Finished Feb 21 02:16:04 PM PST 24
Peak memory 199700 kb
Host smart-ca10e97a-5122-4f19-9f07-4cd926d8e096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825236019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.825236019
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.778070481
Short name T432
Test name
Test status
Simulation time 368816405 ps
CPU time 2.34 seconds
Started Feb 21 02:15:27 PM PST 24
Finished Feb 21 02:15:30 PM PST 24
Peak memory 199552 kb
Host smart-22244674-caf5-4927-a207-7259dafca8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778070481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.778070481
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4005695248
Short name T111
Test name
Test status
Simulation time 18824729492 ps
CPU time 440.8 seconds
Started Feb 21 02:15:39 PM PST 24
Finished Feb 21 02:23:00 PM PST 24
Peak memory 223836 kb
Host smart-10fe6efe-5e5c-42c8-ba96-2f0aea64471d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005695248 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4005695248
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.83447386
Short name T209
Test name
Test status
Simulation time 298247630 ps
CPU time 1.22 seconds
Started Feb 21 02:15:27 PM PST 24
Finished Feb 21 02:15:28 PM PST 24
Peak memory 198172 kb
Host smart-0227c6ff-4dc2-43bc-b356-29855f317488
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83447386 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.hmac_test_hmac_vectors.83447386
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2254334172
Short name T480
Test name
Test status
Simulation time 29799571317 ps
CPU time 492.02 seconds
Started Feb 21 02:15:29 PM PST 24
Finished Feb 21 02:23:41 PM PST 24
Peak memory 199544 kb
Host smart-783f850f-cb0a-4cf9-904b-f9e6a92ab3c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254334172 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.2254334172
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3672287843
Short name T484
Test name
Test status
Simulation time 3544599040 ps
CPU time 34.61 seconds
Started Feb 21 02:15:22 PM PST 24
Finished Feb 21 02:15:57 PM PST 24
Peak memory 199676 kb
Host smart-903deee1-80dd-46d2-b5b5-252de7013a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672287843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3672287843
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.942206777
Short name T158
Test name
Test status
Simulation time 14197798 ps
CPU time 0.55 seconds
Started Feb 21 02:15:36 PM PST 24
Finished Feb 21 02:15:37 PM PST 24
Peak memory 193780 kb
Host smart-2788a42a-2ab7-4120-9aeb-85819379adf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942206777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.942206777
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.478442788
Short name T230
Test name
Test status
Simulation time 4797691046 ps
CPU time 39.84 seconds
Started Feb 21 02:15:38 PM PST 24
Finished Feb 21 02:16:18 PM PST 24
Peak memory 224236 kb
Host smart-b6e79f16-e191-495d-aec0-bf6870b36dd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=478442788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.478442788
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1826703693
Short name T446
Test name
Test status
Simulation time 325412681 ps
CPU time 6.95 seconds
Started Feb 21 02:15:40 PM PST 24
Finished Feb 21 02:15:47 PM PST 24
Peak memory 199552 kb
Host smart-4676b8a2-cc70-47e5-a8c8-de222d0f50c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826703693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1826703693
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_error.2053955779
Short name T358
Test name
Test status
Simulation time 51331046632 ps
CPU time 148.95 seconds
Started Feb 21 02:15:38 PM PST 24
Finished Feb 21 02:18:07 PM PST 24
Peak memory 199448 kb
Host smart-d45269c9-0eb5-4ad4-8086-88ce5354514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053955779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2053955779
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2068068223
Short name T125
Test name
Test status
Simulation time 18612787626 ps
CPU time 37.62 seconds
Started Feb 21 02:15:41 PM PST 24
Finished Feb 21 02:16:19 PM PST 24
Peak memory 199704 kb
Host smart-74e80de5-12a4-4706-b932-5f665c42f3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068068223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2068068223
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3123819408
Short name T234
Test name
Test status
Simulation time 1072775975 ps
CPU time 3.78 seconds
Started Feb 21 02:15:38 PM PST 24
Finished Feb 21 02:15:42 PM PST 24
Peak memory 199520 kb
Host smart-7db3cad3-f402-42b8-bb23-e48e6f5abfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123819408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3123819408
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1205952411
Short name T40
Test name
Test status
Simulation time 1406122332 ps
CPU time 35.82 seconds
Started Feb 21 02:15:37 PM PST 24
Finished Feb 21 02:16:14 PM PST 24
Peak memory 199560 kb
Host smart-754acb83-aa36-4ac4-9af8-461756db867d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205952411 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1205952411
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3565561516
Short name T390
Test name
Test status
Simulation time 29073537 ps
CPU time 0.96 seconds
Started Feb 21 02:15:38 PM PST 24
Finished Feb 21 02:15:40 PM PST 24
Peak memory 198168 kb
Host smart-7125f4ab-7510-4132-aca2-f6b10e919348
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565561516 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3565561516
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.4277391352
Short name T391
Test name
Test status
Simulation time 41601785658 ps
CPU time 490.29 seconds
Started Feb 21 02:15:36 PM PST 24
Finished Feb 21 02:23:46 PM PST 24
Peak memory 199632 kb
Host smart-edb53739-19b6-4495-af53-bac137e4252d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277391352 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.4277391352
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2253645882
Short name T392
Test name
Test status
Simulation time 6466995109 ps
CPU time 75.48 seconds
Started Feb 21 02:15:36 PM PST 24
Finished Feb 21 02:16:52 PM PST 24
Peak memory 199652 kb
Host smart-61a8bd23-c436-4627-828f-9bcb73bb083d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253645882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2253645882
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.4281896402
Short name T200
Test name
Test status
Simulation time 35559155 ps
CPU time 0.56 seconds
Started Feb 21 02:12:33 PM PST 24
Finished Feb 21 02:12:34 PM PST 24
Peak memory 193972 kb
Host smart-faed853d-a320-4e3d-91f8-c5d2e153c28d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281896402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.4281896402
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.947170079
Short name T458
Test name
Test status
Simulation time 435295059 ps
CPU time 7.6 seconds
Started Feb 21 02:12:34 PM PST 24
Finished Feb 21 02:12:43 PM PST 24
Peak memory 215120 kb
Host smart-cb02eb10-9b62-405e-bffa-6d73312ac32c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947170079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.947170079
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.256937188
Short name T360
Test name
Test status
Simulation time 411726961 ps
CPU time 6.9 seconds
Started Feb 21 02:12:36 PM PST 24
Finished Feb 21 02:12:44 PM PST 24
Peak memory 199508 kb
Host smart-65b6354d-2640-47b7-a8d1-85f62b116a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256937188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.256937188
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3740910703
Short name T491
Test name
Test status
Simulation time 1359783911 ps
CPU time 76.2 seconds
Started Feb 21 02:12:32 PM PST 24
Finished Feb 21 02:13:48 PM PST 24
Peak memory 199576 kb
Host smart-900c104d-3aad-4f8c-8696-8b8dd160e473
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740910703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3740910703
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.767920575
Short name T238
Test name
Test status
Simulation time 2862422862 ps
CPU time 55.12 seconds
Started Feb 21 02:12:34 PM PST 24
Finished Feb 21 02:13:30 PM PST 24
Peak memory 199628 kb
Host smart-e2cf4f0f-0dcf-4855-88c1-d8cf8d4b70f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767920575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.767920575
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.42994171
Short name T45
Test name
Test status
Simulation time 79289361 ps
CPU time 0.81 seconds
Started Feb 21 02:12:35 PM PST 24
Finished Feb 21 02:12:37 PM PST 24
Peak memory 216480 kb
Host smart-7d241b07-6902-4a33-a744-3ebe81ea30e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42994171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.42994171
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2055895625
Short name T346
Test name
Test status
Simulation time 1964095767 ps
CPU time 3.24 seconds
Started Feb 21 02:12:36 PM PST 24
Finished Feb 21 02:12:39 PM PST 24
Peak memory 199556 kb
Host smart-f4d9272d-d753-4c4c-938f-35d4f157611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055895625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2055895625
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.4055619067
Short name T326
Test name
Test status
Simulation time 735549392706 ps
CPU time 2625.3 seconds
Started Feb 21 02:12:34 PM PST 24
Finished Feb 21 02:56:20 PM PST 24
Peak memory 240100 kb
Host smart-128da6b4-173f-4f83-9428-bb42e4242d0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055619067 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.4055619067
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3417506280
Short name T34
Test name
Test status
Simulation time 43802271 ps
CPU time 0.99 seconds
Started Feb 21 02:12:36 PM PST 24
Finished Feb 21 02:12:37 PM PST 24
Peak memory 197456 kb
Host smart-458a97af-936d-4fd6-8551-fa45707a15cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417506280 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3417506280
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2159299923
Short name T168
Test name
Test status
Simulation time 37216285081 ps
CPU time 444.07 seconds
Started Feb 21 02:12:31 PM PST 24
Finished Feb 21 02:19:56 PM PST 24
Peak memory 199588 kb
Host smart-0d8a6458-943d-448c-b2ff-3378923bdfc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159299923 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.2159299923
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3495782613
Short name T453
Test name
Test status
Simulation time 125844138 ps
CPU time 2.41 seconds
Started Feb 21 02:12:37 PM PST 24
Finished Feb 21 02:12:39 PM PST 24
Peak memory 199524 kb
Host smart-e54c0293-6793-446b-aef7-7c37573ae8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495782613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3495782613
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3463162305
Short name T155
Test name
Test status
Simulation time 86482174 ps
CPU time 0.55 seconds
Started Feb 21 02:15:44 PM PST 24
Finished Feb 21 02:15:45 PM PST 24
Peak memory 194008 kb
Host smart-628712a1-c308-4d0e-84cb-cc15a2d3da4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463162305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3463162305
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2167247525
Short name T419
Test name
Test status
Simulation time 1973582997 ps
CPU time 22.5 seconds
Started Feb 21 02:15:37 PM PST 24
Finished Feb 21 02:16:00 PM PST 24
Peak memory 228324 kb
Host smart-0c2068cc-4bf4-4162-9695-96ac40ca513e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167247525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2167247525
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1653289977
Short name T351
Test name
Test status
Simulation time 5704422541 ps
CPU time 71.02 seconds
Started Feb 21 02:15:40 PM PST 24
Finished Feb 21 02:16:51 PM PST 24
Peak memory 199632 kb
Host smart-f9f085e3-ee77-4401-9ffd-9e11fc07a107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653289977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1653289977
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3188335445
Short name T466
Test name
Test status
Simulation time 96611349 ps
CPU time 0.99 seconds
Started Feb 21 02:15:37 PM PST 24
Finished Feb 21 02:15:38 PM PST 24
Peak memory 198288 kb
Host smart-bf121aae-4d25-4451-b99c-3b2395547e66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188335445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3188335445
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3681209700
Short name T354
Test name
Test status
Simulation time 11867009555 ps
CPU time 161.45 seconds
Started Feb 21 02:15:44 PM PST 24
Finished Feb 21 02:18:25 PM PST 24
Peak memory 199580 kb
Host smart-f4e327a4-6ed8-40fb-b4cc-6d72006c613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681209700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3681209700
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2539389998
Short name T422
Test name
Test status
Simulation time 9928040703 ps
CPU time 98.76 seconds
Started Feb 21 02:15:38 PM PST 24
Finished Feb 21 02:17:17 PM PST 24
Peak memory 199620 kb
Host smart-f626111a-fc06-4ada-b7f6-957a25437cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539389998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2539389998
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3726725623
Short name T253
Test name
Test status
Simulation time 2917529758 ps
CPU time 3.34 seconds
Started Feb 21 02:15:42 PM PST 24
Finished Feb 21 02:15:46 PM PST 24
Peak memory 199644 kb
Host smart-cf80fc2e-14f0-47f5-8823-f27441a25f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726725623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3726725623
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2154802365
Short name T558
Test name
Test status
Simulation time 42464170101 ps
CPU time 739.4 seconds
Started Feb 21 02:15:45 PM PST 24
Finished Feb 21 02:28:05 PM PST 24
Peak memory 216064 kb
Host smart-75e9181a-f9b2-43a3-87c7-d4e3f0d21e72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154802365 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2154802365
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2747767904
Short name T539
Test name
Test status
Simulation time 33448296 ps
CPU time 1.16 seconds
Started Feb 21 02:15:46 PM PST 24
Finished Feb 21 02:15:48 PM PST 24
Peak memory 197332 kb
Host smart-3a82e89f-a84e-4007-a50d-180291ba98dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747767904 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2747767904
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.89938041
Short name T494
Test name
Test status
Simulation time 107167194629 ps
CPU time 480.15 seconds
Started Feb 21 02:15:45 PM PST 24
Finished Feb 21 02:23:46 PM PST 24
Peak memory 199580 kb
Host smart-b70ab6ec-ce11-4155-88db-43784bb027b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89938041 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.hmac_test_sha_vectors.89938041
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3417207706
Short name T79
Test name
Test status
Simulation time 4748498788 ps
CPU time 43.77 seconds
Started Feb 21 02:15:47 PM PST 24
Finished Feb 21 02:16:32 PM PST 24
Peak memory 199596 kb
Host smart-fbea6bb4-355f-4335-ab8d-6b3d4471ad1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417207706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3417207706
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3020588063
Short name T498
Test name
Test status
Simulation time 68570929 ps
CPU time 0.56 seconds
Started Feb 21 02:15:54 PM PST 24
Finished Feb 21 02:15:55 PM PST 24
Peak memory 193724 kb
Host smart-5c8d8f16-4449-43d8-94a9-14101d372e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020588063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3020588063
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2223286198
Short name T581
Test name
Test status
Simulation time 673169566 ps
CPU time 25.68 seconds
Started Feb 21 02:15:43 PM PST 24
Finished Feb 21 02:16:10 PM PST 24
Peak memory 215884 kb
Host smart-e5314e9b-c759-4b06-bc1c-2caf509e7b3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223286198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2223286198
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3442674770
Short name T105
Test name
Test status
Simulation time 1242199970 ps
CPU time 56.23 seconds
Started Feb 21 02:15:43 PM PST 24
Finished Feb 21 02:16:40 PM PST 24
Peak memory 199552 kb
Host smart-010bc892-0cc8-4dd8-86aa-ff1ba4287ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442674770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3442674770
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1766188178
Short name T29
Test name
Test status
Simulation time 416039871 ps
CPU time 21.68 seconds
Started Feb 21 02:15:44 PM PST 24
Finished Feb 21 02:16:07 PM PST 24
Peak memory 199500 kb
Host smart-34374341-8893-42af-a1f2-c9becc626a39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1766188178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1766188178
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.4211656157
Short name T540
Test name
Test status
Simulation time 1737340540 ps
CPU time 30.66 seconds
Started Feb 21 02:15:46 PM PST 24
Finished Feb 21 02:16:19 PM PST 24
Peak memory 199412 kb
Host smart-707e4312-a20a-4f3f-ba47-a9a6635d3ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211656157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.4211656157
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1109701468
Short name T556
Test name
Test status
Simulation time 1988020001 ps
CPU time 36.97 seconds
Started Feb 21 02:15:44 PM PST 24
Finished Feb 21 02:16:22 PM PST 24
Peak memory 199540 kb
Host smart-85e7ae03-fe73-4bad-88d4-4b40129de141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109701468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1109701468
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3207309974
Short name T589
Test name
Test status
Simulation time 146040013 ps
CPU time 2.94 seconds
Started Feb 21 02:15:44 PM PST 24
Finished Feb 21 02:15:47 PM PST 24
Peak memory 199468 kb
Host smart-7834974a-9530-4d31-afd8-cfd7da3cd4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207309974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3207309974
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3698209115
Short name T336
Test name
Test status
Simulation time 274520162747 ps
CPU time 1128.46 seconds
Started Feb 21 02:15:45 PM PST 24
Finished Feb 21 02:34:34 PM PST 24
Peak memory 212060 kb
Host smart-e58469e9-0c91-4db0-93af-1adce0db3fb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698209115 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3698209115
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3278938997
Short name T503
Test name
Test status
Simulation time 67967255 ps
CPU time 1.12 seconds
Started Feb 21 02:15:47 PM PST 24
Finished Feb 21 02:15:49 PM PST 24
Peak memory 197904 kb
Host smart-82f2abc9-9241-48fe-8cab-cb41058a7fb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278938997 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3278938997
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3879573660
Short name T343
Test name
Test status
Simulation time 1829833923 ps
CPU time 32.36 seconds
Started Feb 21 02:15:46 PM PST 24
Finished Feb 21 02:16:19 PM PST 24
Peak memory 199528 kb
Host smart-da2dc0f6-2682-4865-87e4-801de1d5d137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879573660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3879573660
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.431717540
Short name T532
Test name
Test status
Simulation time 45793077 ps
CPU time 0.58 seconds
Started Feb 21 02:15:55 PM PST 24
Finished Feb 21 02:15:56 PM PST 24
Peak memory 193984 kb
Host smart-447e2747-cedb-4615-b62b-2b03564911d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431717540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.431717540
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.281494207
Short name T232
Test name
Test status
Simulation time 100643807 ps
CPU time 3.11 seconds
Started Feb 21 02:15:56 PM PST 24
Finished Feb 21 02:15:59 PM PST 24
Peak memory 199512 kb
Host smart-ed6ff3d6-69f1-465d-a55b-156e10c9bb03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281494207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.281494207
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.4266992872
Short name T552
Test name
Test status
Simulation time 6183565596 ps
CPU time 48.97 seconds
Started Feb 21 02:15:56 PM PST 24
Finished Feb 21 02:16:45 PM PST 24
Peak memory 199724 kb
Host smart-5c1188db-eb0e-4b6a-95e3-80e323eb1e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266992872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.4266992872
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3029454919
Short name T235
Test name
Test status
Simulation time 2128865131 ps
CPU time 57.3 seconds
Started Feb 21 02:15:57 PM PST 24
Finished Feb 21 02:16:55 PM PST 24
Peak memory 199612 kb
Host smart-9218b051-849e-444c-b197-d916693cdd07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029454919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3029454919
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3287940314
Short name T269
Test name
Test status
Simulation time 1484390124 ps
CPU time 20.11 seconds
Started Feb 21 02:15:51 PM PST 24
Finished Feb 21 02:16:12 PM PST 24
Peak memory 199428 kb
Host smart-cc0efb40-c46d-4313-be6a-4b3d6b16c878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287940314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3287940314
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1878393118
Short name T441
Test name
Test status
Simulation time 7950142947 ps
CPU time 14.07 seconds
Started Feb 21 02:15:54 PM PST 24
Finished Feb 21 02:16:08 PM PST 24
Peak memory 199624 kb
Host smart-3f8067b5-b654-464f-b019-e6bcab3039eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878393118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1878393118
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1689990426
Short name T470
Test name
Test status
Simulation time 892343105 ps
CPU time 3.22 seconds
Started Feb 21 02:16:05 PM PST 24
Finished Feb 21 02:16:09 PM PST 24
Peak memory 199784 kb
Host smart-f7f35e39-0370-4bc0-92d1-5dc7a9820962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689990426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1689990426
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3020940335
Short name T107
Test name
Test status
Simulation time 29824864047 ps
CPU time 714.26 seconds
Started Feb 21 02:15:49 PM PST 24
Finished Feb 21 02:27:43 PM PST 24
Peak memory 199712 kb
Host smart-c60b8808-20ce-4460-8065-1206f9ea78b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020940335 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3020940335
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.647125122
Short name T431
Test name
Test status
Simulation time 32537304 ps
CPU time 1.18 seconds
Started Feb 21 02:15:56 PM PST 24
Finished Feb 21 02:15:57 PM PST 24
Peak memory 197940 kb
Host smart-de33b876-7b01-4f96-b337-8558a4b57acc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647125122 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.647125122
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2792390492
Short name T353
Test name
Test status
Simulation time 29737545448 ps
CPU time 366.87 seconds
Started Feb 21 02:15:51 PM PST 24
Finished Feb 21 02:21:58 PM PST 24
Peak memory 199672 kb
Host smart-37c070d3-eb0b-4ed8-989e-2627c46165b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792390492 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.2792390492
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3186951597
Short name T545
Test name
Test status
Simulation time 5329147207 ps
CPU time 18.26 seconds
Started Feb 21 02:15:48 PM PST 24
Finished Feb 21 02:16:07 PM PST 24
Peak memory 199680 kb
Host smart-e3763758-2037-40e1-977d-f3816eac7abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186951597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3186951597
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.99379715
Short name T475
Test name
Test status
Simulation time 11265557 ps
CPU time 0.57 seconds
Started Feb 21 02:16:12 PM PST 24
Finished Feb 21 02:16:13 PM PST 24
Peak memory 193968 kb
Host smart-d00ba3ae-ac4a-4118-9281-ca4259680f94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99379715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.99379715
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4123411497
Short name T476
Test name
Test status
Simulation time 4634040263 ps
CPU time 34.18 seconds
Started Feb 21 02:16:04 PM PST 24
Finished Feb 21 02:16:39 PM PST 24
Peak memory 211576 kb
Host smart-80c159f4-208a-4145-95d5-fa384f643a6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123411497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4123411497
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1150875365
Short name T2
Test name
Test status
Simulation time 3112139012 ps
CPU time 45.73 seconds
Started Feb 21 02:16:03 PM PST 24
Finished Feb 21 02:16:49 PM PST 24
Peak memory 199628 kb
Host smart-12211284-24c4-4b99-9a12-bd09a1714a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150875365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1150875365
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_error.1166947939
Short name T355
Test name
Test status
Simulation time 5843719144 ps
CPU time 24.85 seconds
Started Feb 21 02:16:03 PM PST 24
Finished Feb 21 02:16:28 PM PST 24
Peak memory 199608 kb
Host smart-cc2a4106-49e3-4f46-8c29-f957eac74c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166947939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1166947939
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.193967695
Short name T450
Test name
Test status
Simulation time 4419129625 ps
CPU time 77.05 seconds
Started Feb 21 02:16:01 PM PST 24
Finished Feb 21 02:17:19 PM PST 24
Peak memory 199648 kb
Host smart-521dddcb-aeef-446c-ab5a-5fc0135e6ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193967695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.193967695
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3232308427
Short name T50
Test name
Test status
Simulation time 862636620 ps
CPU time 5.01 seconds
Started Feb 21 02:15:58 PM PST 24
Finished Feb 21 02:16:03 PM PST 24
Peak memory 199632 kb
Host smart-13b3225d-4f3f-403b-94ee-89f9bc6564bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232308427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3232308427
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.52073266
Short name T299
Test name
Test status
Simulation time 42637513 ps
CPU time 0.98 seconds
Started Feb 21 02:16:04 PM PST 24
Finished Feb 21 02:16:06 PM PST 24
Peak memory 196908 kb
Host smart-5374dc33-63d3-400f-9d6f-0915bef6c236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52073266 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.hmac_test_hmac_vectors.52073266
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2728250186
Short name T174
Test name
Test status
Simulation time 101249702839 ps
CPU time 452.56 seconds
Started Feb 21 02:16:02 PM PST 24
Finished Feb 21 02:23:35 PM PST 24
Peak memory 199612 kb
Host smart-3c2aa588-9fef-486d-ad00-e10c5060d2ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728250186 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.2728250186
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.371871236
Short name T321
Test name
Test status
Simulation time 12968341183 ps
CPU time 57.36 seconds
Started Feb 21 02:16:02 PM PST 24
Finished Feb 21 02:17:00 PM PST 24
Peak memory 199728 kb
Host smart-56c98a55-00a9-49c2-a349-907023f8818b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371871236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.371871236
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3902993935
Short name T68
Test name
Test status
Simulation time 93258424 ps
CPU time 0.58 seconds
Started Feb 21 02:16:23 PM PST 24
Finished Feb 21 02:16:24 PM PST 24
Peak memory 194972 kb
Host smart-595e913c-8dbe-4b78-913b-2ee3c558d21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902993935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3902993935
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.329856362
Short name T425
Test name
Test status
Simulation time 1616083888 ps
CPU time 58.21 seconds
Started Feb 21 02:16:11 PM PST 24
Finished Feb 21 02:17:10 PM PST 24
Peak memory 232012 kb
Host smart-a5a97f53-05c5-410d-930f-108d0bc8b9f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329856362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.329856362
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2399012789
Short name T348
Test name
Test status
Simulation time 14863285337 ps
CPU time 52.1 seconds
Started Feb 21 02:16:18 PM PST 24
Finished Feb 21 02:17:10 PM PST 24
Peak memory 199760 kb
Host smart-cbc3cde6-3ea5-4cba-9799-3a2fd5b05d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399012789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2399012789
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3472848505
Short name T22
Test name
Test status
Simulation time 2962685657 ps
CPU time 76 seconds
Started Feb 21 02:16:14 PM PST 24
Finished Feb 21 02:17:31 PM PST 24
Peak memory 199856 kb
Host smart-3624fbc7-eec9-4062-b6d6-0f3a145ee674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472848505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3472848505
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1633987652
Short name T184
Test name
Test status
Simulation time 14375473374 ps
CPU time 135.51 seconds
Started Feb 21 02:16:12 PM PST 24
Finished Feb 21 02:18:29 PM PST 24
Peak memory 199688 kb
Host smart-55d892bd-fa15-444e-8512-296ada6d5ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633987652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1633987652
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.894139511
Short name T137
Test name
Test status
Simulation time 7412504290 ps
CPU time 71.11 seconds
Started Feb 21 02:16:12 PM PST 24
Finished Feb 21 02:17:24 PM PST 24
Peak memory 199676 kb
Host smart-b167dd56-e11c-47e0-8900-000a00fbfd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894139511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.894139511
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3663539915
Short name T87
Test name
Test status
Simulation time 294687331 ps
CPU time 4.2 seconds
Started Feb 21 02:16:13 PM PST 24
Finished Feb 21 02:16:19 PM PST 24
Peak memory 199540 kb
Host smart-e59d8fa3-e24b-445b-94f4-b93a0426eb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663539915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3663539915
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3801919233
Short name T72
Test name
Test status
Simulation time 567338346963 ps
CPU time 870.55 seconds
Started Feb 21 02:16:13 PM PST 24
Finished Feb 21 02:30:45 PM PST 24
Peak memory 207884 kb
Host smart-9450c3f9-2589-4cd4-bfc2-7e1e9ea4a605
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801919233 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3801919233
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.3883523484
Short name T6
Test name
Test status
Simulation time 371713999084 ps
CPU time 2553.29 seconds
Started Feb 21 02:16:24 PM PST 24
Finished Feb 21 02:58:58 PM PST 24
Peak memory 224412 kb
Host smart-94deca4c-0ca7-4cb6-ad69-7086529ac926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883523484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.3883523484
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.602685058
Short name T537
Test name
Test status
Simulation time 199721717 ps
CPU time 1.02 seconds
Started Feb 21 02:16:24 PM PST 24
Finished Feb 21 02:16:26 PM PST 24
Peak memory 196864 kb
Host smart-671a0422-f294-42a4-a8d2-b6e70f52efde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602685058 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.602685058
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.291768234
Short name T256
Test name
Test status
Simulation time 12418157039 ps
CPU time 419.79 seconds
Started Feb 21 02:16:12 PM PST 24
Finished Feb 21 02:23:12 PM PST 24
Peak memory 199564 kb
Host smart-778e77c8-b028-4b6a-884b-14d165a125ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291768234 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.hmac_test_sha_vectors.291768234
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2522314569
Short name T486
Test name
Test status
Simulation time 1595300953 ps
CPU time 7.96 seconds
Started Feb 21 02:16:15 PM PST 24
Finished Feb 21 02:16:24 PM PST 24
Peak memory 199492 kb
Host smart-385526bd-a9e3-469a-9eec-9143d070ba2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522314569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2522314569
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2390632102
Short name T165
Test name
Test status
Simulation time 38914622 ps
CPU time 0.56 seconds
Started Feb 21 02:16:25 PM PST 24
Finished Feb 21 02:16:26 PM PST 24
Peak memory 193780 kb
Host smart-668ac706-2e40-4609-84bc-9c19ae4b4ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390632102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2390632102
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1368007030
Short name T178
Test name
Test status
Simulation time 5943025640 ps
CPU time 48.28 seconds
Started Feb 21 02:16:21 PM PST 24
Finished Feb 21 02:17:10 PM PST 24
Peak memory 216116 kb
Host smart-d18cd088-428a-4e2f-ad30-911ed324cc94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368007030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1368007030
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2452649195
Short name T126
Test name
Test status
Simulation time 5705598951 ps
CPU time 39.5 seconds
Started Feb 21 02:16:24 PM PST 24
Finished Feb 21 02:17:04 PM PST 24
Peak memory 199632 kb
Host smart-3c4edfd5-a750-43a9-bfa2-e09aace1ea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452649195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2452649195
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1874414279
Short name T115
Test name
Test status
Simulation time 2013223926 ps
CPU time 61.44 seconds
Started Feb 21 02:16:21 PM PST 24
Finished Feb 21 02:17:23 PM PST 24
Peak memory 199552 kb
Host smart-8c416134-60b5-47e2-bfd0-8ce7ba52ab81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874414279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1874414279
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3259617321
Short name T281
Test name
Test status
Simulation time 1948658208 ps
CPU time 32.88 seconds
Started Feb 21 02:16:25 PM PST 24
Finished Feb 21 02:16:58 PM PST 24
Peak memory 199556 kb
Host smart-6198f7a5-964e-446a-a7db-047156b3fa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259617321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3259617321
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.636092963
Short name T338
Test name
Test status
Simulation time 19032155193 ps
CPU time 101.84 seconds
Started Feb 21 02:16:22 PM PST 24
Finished Feb 21 02:18:05 PM PST 24
Peak memory 199684 kb
Host smart-2e0c043f-c33a-43e0-a241-02910d237a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636092963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.636092963
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.293426592
Short name T296
Test name
Test status
Simulation time 744801973 ps
CPU time 2.48 seconds
Started Feb 21 02:16:24 PM PST 24
Finished Feb 21 02:16:27 PM PST 24
Peak memory 199608 kb
Host smart-255294b1-7428-4aac-af5e-eced2989fbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293426592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.293426592
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1590511441
Short name T258
Test name
Test status
Simulation time 32121897063 ps
CPU time 378.25 seconds
Started Feb 21 02:16:22 PM PST 24
Finished Feb 21 02:22:41 PM PST 24
Peak memory 199668 kb
Host smart-597433c6-4699-4e8f-b6de-4b710fc5250f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590511441 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1590511441
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3586325331
Short name T193
Test name
Test status
Simulation time 69335426 ps
CPU time 0.87 seconds
Started Feb 21 02:16:20 PM PST 24
Finished Feb 21 02:16:22 PM PST 24
Peak memory 196504 kb
Host smart-0d07f22c-84ad-4b62-a40c-963f5e373486
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586325331 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.3586325331
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3600168019
Short name T312
Test name
Test status
Simulation time 80423449122 ps
CPU time 465.66 seconds
Started Feb 21 02:16:20 PM PST 24
Finished Feb 21 02:24:07 PM PST 24
Peak memory 199632 kb
Host smart-d40b064b-d9b5-4406-a403-9257d941d70e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600168019 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_sha_vectors.3600168019
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1471977818
Short name T327
Test name
Test status
Simulation time 10248105566 ps
CPU time 74.26 seconds
Started Feb 21 02:16:23 PM PST 24
Finished Feb 21 02:17:38 PM PST 24
Peak memory 199588 kb
Host smart-24d73881-d5f7-43d9-aa33-cf15cefdf734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471977818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1471977818
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.428505688
Short name T37
Test name
Test status
Simulation time 13505343 ps
CPU time 0.59 seconds
Started Feb 21 02:16:31 PM PST 24
Finished Feb 21 02:16:32 PM PST 24
Peak memory 194792 kb
Host smart-56cb7cb3-3010-479e-ab6c-3ffc5489f242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428505688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.428505688
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1990059337
Short name T398
Test name
Test status
Simulation time 1210007780 ps
CPU time 46.46 seconds
Started Feb 21 02:16:22 PM PST 24
Finished Feb 21 02:17:09 PM PST 24
Peak memory 233356 kb
Host smart-5d5eb492-8301-4096-9e5d-729dcdbd9489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990059337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1990059337
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3477601279
Short name T304
Test name
Test status
Simulation time 3817055981 ps
CPU time 49.19 seconds
Started Feb 21 02:16:22 PM PST 24
Finished Feb 21 02:17:12 PM PST 24
Peak memory 199684 kb
Host smart-363af32d-d8a1-40bb-9fcf-ac396ceedb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477601279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3477601279
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2666875209
Short name T202
Test name
Test status
Simulation time 2084286061 ps
CPU time 113.42 seconds
Started Feb 21 02:16:21 PM PST 24
Finished Feb 21 02:18:15 PM PST 24
Peak memory 199568 kb
Host smart-976d35d8-860e-4f6a-ad40-9fde9ba02c2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666875209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2666875209
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2666152270
Short name T32
Test name
Test status
Simulation time 14709555510 ps
CPU time 171.76 seconds
Started Feb 21 02:16:23 PM PST 24
Finished Feb 21 02:19:15 PM PST 24
Peak memory 199652 kb
Host smart-072949d8-831e-4445-b509-beabe6c82f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666152270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2666152270
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.457605582
Short name T323
Test name
Test status
Simulation time 947130220 ps
CPU time 51.3 seconds
Started Feb 21 02:16:25 PM PST 24
Finished Feb 21 02:17:16 PM PST 24
Peak memory 199592 kb
Host smart-e2cb93c2-96f8-40c0-9ef5-8fd501f8ecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457605582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.457605582
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.4098921253
Short name T63
Test name
Test status
Simulation time 79841533 ps
CPU time 2.35 seconds
Started Feb 21 02:16:24 PM PST 24
Finished Feb 21 02:16:27 PM PST 24
Peak memory 199312 kb
Host smart-17f272d1-14f1-4eca-a885-ac1f62f841ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098921253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.4098921253
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1837454509
Short name T31
Test name
Test status
Simulation time 60140377192 ps
CPU time 808.61 seconds
Started Feb 21 02:16:31 PM PST 24
Finished Feb 21 02:30:00 PM PST 24
Peak memory 239844 kb
Host smart-318f02b9-7ebb-4922-a791-3e328de9a4ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837454509 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1837454509
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.2890927771
Short name T573
Test name
Test status
Simulation time 63757494558 ps
CPU time 235.22 seconds
Started Feb 21 02:16:31 PM PST 24
Finished Feb 21 02:20:27 PM PST 24
Peak memory 208012 kb
Host smart-6adc4761-fec7-4a90-b925-288b41e955d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890927771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.2890927771
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2795577620
Short name T410
Test name
Test status
Simulation time 112205098 ps
CPU time 1.09 seconds
Started Feb 21 02:16:33 PM PST 24
Finished Feb 21 02:16:34 PM PST 24
Peak memory 198648 kb
Host smart-d8687d14-8fa1-4050-a1a1-46165e9b6445
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795577620 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2795577620
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.532966151
Short name T195
Test name
Test status
Simulation time 23665718158 ps
CPU time 442.23 seconds
Started Feb 21 02:16:37 PM PST 24
Finished Feb 21 02:24:00 PM PST 24
Peak memory 199164 kb
Host smart-cd21cbb2-8c05-43ff-987d-e9159129f111
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532966151 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_sha_vectors.532966151
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.198090293
Short name T19
Test name
Test status
Simulation time 2501153923 ps
CPU time 32.85 seconds
Started Feb 21 02:16:32 PM PST 24
Finished Feb 21 02:17:06 PM PST 24
Peak memory 199632 kb
Host smart-f22d9574-3f4b-440f-9d3d-0ce446a3c14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198090293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.198090293
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1014850573
Short name T413
Test name
Test status
Simulation time 30708063 ps
CPU time 0.56 seconds
Started Feb 21 02:16:40 PM PST 24
Finished Feb 21 02:16:41 PM PST 24
Peak memory 193800 kb
Host smart-5c3b8181-7e6e-4bca-b0d9-f4d2e3e4e495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014850573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1014850573
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3190353592
Short name T260
Test name
Test status
Simulation time 2126109436 ps
CPU time 16.05 seconds
Started Feb 21 02:16:31 PM PST 24
Finished Feb 21 02:16:47 PM PST 24
Peak memory 208540 kb
Host smart-3d5734a1-faaf-4817-99a8-05ff1dcc9447
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190353592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3190353592
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2629787258
Short name T333
Test name
Test status
Simulation time 986045481 ps
CPU time 20.78 seconds
Started Feb 21 02:16:33 PM PST 24
Finished Feb 21 02:16:54 PM PST 24
Peak memory 199576 kb
Host smart-480b396c-8bd9-48a3-83d1-646c5a9ad661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629787258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2629787258
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3046724678
Short name T553
Test name
Test status
Simulation time 1834045194 ps
CPU time 102.69 seconds
Started Feb 21 02:16:34 PM PST 24
Finished Feb 21 02:18:17 PM PST 24
Peak memory 199552 kb
Host smart-fef37927-11ca-46b0-82f9-aa40a6fce0d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046724678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3046724678
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2532458458
Short name T504
Test name
Test status
Simulation time 16750008832 ps
CPU time 207.19 seconds
Started Feb 21 02:16:34 PM PST 24
Finished Feb 21 02:20:02 PM PST 24
Peak memory 199660 kb
Host smart-f8423846-d842-439f-ba00-cefe6410013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532458458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2532458458
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2334580307
Short name T7
Test name
Test status
Simulation time 7396932504 ps
CPU time 94.38 seconds
Started Feb 21 02:16:32 PM PST 24
Finished Feb 21 02:18:07 PM PST 24
Peak memory 199672 kb
Host smart-bd2942d8-3a91-469e-be14-e72479e609df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334580307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2334580307
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3054030710
Short name T11
Test name
Test status
Simulation time 491528951 ps
CPU time 1.57 seconds
Started Feb 21 02:16:33 PM PST 24
Finished Feb 21 02:16:35 PM PST 24
Peak memory 199244 kb
Host smart-4348f8b6-c3e9-4caf-aa38-6d10f7206634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054030710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3054030710
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3551868783
Short name T71
Test name
Test status
Simulation time 115698539263 ps
CPU time 376.73 seconds
Started Feb 21 02:16:42 PM PST 24
Finished Feb 21 02:22:59 PM PST 24
Peak memory 225272 kb
Host smart-d5a7ddf4-b64c-4a7e-b470-c1add1967b49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551868783 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3551868783
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1533879230
Short name T265
Test name
Test status
Simulation time 465735430 ps
CPU time 0.91 seconds
Started Feb 21 02:16:41 PM PST 24
Finished Feb 21 02:16:42 PM PST 24
Peak memory 197596 kb
Host smart-6771959d-afd3-4412-80ea-1db9347a3d42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533879230 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1533879230
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3616503590
Short name T528
Test name
Test status
Simulation time 36180415081 ps
CPU time 429.99 seconds
Started Feb 21 02:16:41 PM PST 24
Finished Feb 21 02:23:52 PM PST 24
Peak memory 199624 kb
Host smart-160433ac-640c-433b-b83e-80079776e62b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616503590 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.3616503590
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3678848984
Short name T215
Test name
Test status
Simulation time 3406480546 ps
CPU time 24.06 seconds
Started Feb 21 02:16:42 PM PST 24
Finished Feb 21 02:17:07 PM PST 24
Peak memory 199660 kb
Host smart-92bf382c-c231-46bb-91bf-770999ed84d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678848984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3678848984
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.532335068
Short name T430
Test name
Test status
Simulation time 41578701 ps
CPU time 0.58 seconds
Started Feb 21 02:16:56 PM PST 24
Finished Feb 21 02:16:57 PM PST 24
Peak memory 193912 kb
Host smart-174cd5bd-9975-4b2d-965b-44f9092dc0a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532335068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.532335068
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2979549184
Short name T319
Test name
Test status
Simulation time 1461150003 ps
CPU time 61 seconds
Started Feb 21 02:16:40 PM PST 24
Finished Feb 21 02:17:42 PM PST 24
Peak memory 231900 kb
Host smart-1542d738-5216-4731-b59d-f893710528e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979549184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2979549184
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.590382188
Short name T263
Test name
Test status
Simulation time 4990757442 ps
CPU time 63.7 seconds
Started Feb 21 02:16:42 PM PST 24
Finished Feb 21 02:17:47 PM PST 24
Peak memory 199576 kb
Host smart-dd66f12a-c147-45a6-9d78-b471da6017cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590382188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.590382188
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.999920391
Short name T110
Test name
Test status
Simulation time 10253756026 ps
CPU time 145.21 seconds
Started Feb 21 02:16:42 PM PST 24
Finished Feb 21 02:19:08 PM PST 24
Peak memory 199632 kb
Host smart-6172ebf3-e021-4e8f-bcbd-fc50f04c6f46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999920391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.999920391
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.111263388
Short name T406
Test name
Test status
Simulation time 18690945724 ps
CPU time 159.78 seconds
Started Feb 21 02:16:41 PM PST 24
Finished Feb 21 02:19:22 PM PST 24
Peak memory 199640 kb
Host smart-d8754ed4-f0ff-4075-a3c6-2f7177f1670c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111263388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.111263388
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.240570682
Short name T128
Test name
Test status
Simulation time 3941733711 ps
CPU time 53.47 seconds
Started Feb 21 02:16:41 PM PST 24
Finished Feb 21 02:17:35 PM PST 24
Peak memory 199656 kb
Host smart-ffa8a1e0-5ff4-45af-abb0-d3f85ef745d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240570682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.240570682
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1651323045
Short name T362
Test name
Test status
Simulation time 346717525 ps
CPU time 1.71 seconds
Started Feb 21 02:16:42 PM PST 24
Finished Feb 21 02:16:45 PM PST 24
Peak memory 199488 kb
Host smart-901d2756-21df-4ea5-88ee-fc7b01e3f29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651323045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1651323045
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3380131161
Short name T77
Test name
Test status
Simulation time 316368109671 ps
CPU time 1004.38 seconds
Started Feb 21 02:16:43 PM PST 24
Finished Feb 21 02:33:28 PM PST 24
Peak memory 215312 kb
Host smart-0846a746-dfd8-44b6-a87f-11ab09fd6946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380131161 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3380131161
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2681677061
Short name T583
Test name
Test status
Simulation time 199071101 ps
CPU time 1.03 seconds
Started Feb 21 02:16:43 PM PST 24
Finished Feb 21 02:16:45 PM PST 24
Peak memory 198084 kb
Host smart-78594ace-8098-4b58-b7b7-cb94347bf9bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681677061 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2681677061
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2921304272
Short name T363
Test name
Test status
Simulation time 122899422489 ps
CPU time 430.07 seconds
Started Feb 21 02:16:40 PM PST 24
Finished Feb 21 02:23:51 PM PST 24
Peak memory 199624 kb
Host smart-ab93c439-26a0-493c-bc6f-6e061f6ec4f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921304272 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.2921304272
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3831196189
Short name T586
Test name
Test status
Simulation time 190110913 ps
CPU time 2.23 seconds
Started Feb 21 02:16:45 PM PST 24
Finished Feb 21 02:16:48 PM PST 24
Peak memory 199324 kb
Host smart-470848e8-0927-42d4-a4d3-8de34325a6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831196189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3831196189
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3254361138
Short name T385
Test name
Test status
Simulation time 20590258 ps
CPU time 0.59 seconds
Started Feb 21 02:16:58 PM PST 24
Finished Feb 21 02:16:59 PM PST 24
Peak memory 193972 kb
Host smart-114d8808-0fe5-483c-b1d3-fdaa20502b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254361138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3254361138
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.669836359
Short name T8
Test name
Test status
Simulation time 1345115223 ps
CPU time 42.78 seconds
Started Feb 21 02:16:56 PM PST 24
Finished Feb 21 02:17:39 PM PST 24
Peak memory 223856 kb
Host smart-f8a89a18-9371-41e7-a2c0-d934ba10b964
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=669836359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.669836359
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1048833919
Short name T565
Test name
Test status
Simulation time 1215037686 ps
CPU time 17.67 seconds
Started Feb 21 02:16:56 PM PST 24
Finished Feb 21 02:17:14 PM PST 24
Peak memory 199528 kb
Host smart-47db2398-8de0-4f3b-b6f6-d259c4abbe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048833919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1048833919
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.4208236465
Short name T501
Test name
Test status
Simulation time 1578225117 ps
CPU time 81.74 seconds
Started Feb 21 02:16:58 PM PST 24
Finished Feb 21 02:18:20 PM PST 24
Peak memory 199436 kb
Host smart-a1faffc6-49c7-4d41-ba66-9f1f27325b4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208236465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.4208236465
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.884322337
Short name T347
Test name
Test status
Simulation time 277270963 ps
CPU time 13.91 seconds
Started Feb 21 02:16:56 PM PST 24
Finished Feb 21 02:17:10 PM PST 24
Peak memory 199620 kb
Host smart-fe6be0c6-9c44-46c2-a667-2079fd80f175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884322337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.884322337
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2828227605
Short name T301
Test name
Test status
Simulation time 5500349113 ps
CPU time 75.73 seconds
Started Feb 21 02:16:57 PM PST 24
Finished Feb 21 02:18:13 PM PST 24
Peak memory 199632 kb
Host smart-d71e093b-2d30-478a-af6e-d92aa0fe6c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828227605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2828227605
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1545566791
Short name T372
Test name
Test status
Simulation time 21268512 ps
CPU time 0.77 seconds
Started Feb 21 02:16:58 PM PST 24
Finished Feb 21 02:16:59 PM PST 24
Peak memory 196140 kb
Host smart-a327f82d-6396-4ef1-8a83-6335fb06a58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545566791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1545566791
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2079866276
Short name T80
Test name
Test status
Simulation time 110947015 ps
CPU time 1.23 seconds
Started Feb 21 02:16:56 PM PST 24
Finished Feb 21 02:16:58 PM PST 24
Peak memory 197556 kb
Host smart-980c3027-e799-4ef1-8211-b9bdce5f01ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079866276 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2079866276
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1656799195
Short name T255
Test name
Test status
Simulation time 31668042571 ps
CPU time 408.37 seconds
Started Feb 21 02:16:58 PM PST 24
Finished Feb 21 02:23:46 PM PST 24
Peak memory 199672 kb
Host smart-dea82ef5-50cc-44ef-8dde-467c0fc5a933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656799195 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_sha_vectors.1656799195
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.198500915
Short name T468
Test name
Test status
Simulation time 699407857 ps
CPU time 27.72 seconds
Started Feb 21 02:16:57 PM PST 24
Finished Feb 21 02:17:25 PM PST 24
Peak memory 199556 kb
Host smart-d1b8013c-bc66-418c-b4fe-8bedcaab3b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198500915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.198500915
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2228713497
Short name T262
Test name
Test status
Simulation time 11698688 ps
CPU time 0.56 seconds
Started Feb 21 02:12:59 PM PST 24
Finished Feb 21 02:13:00 PM PST 24
Peak memory 193752 kb
Host smart-523cca79-bb6d-4cdc-8280-19438a74ace1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228713497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2228713497
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2123811301
Short name T67
Test name
Test status
Simulation time 341209990 ps
CPU time 13.79 seconds
Started Feb 21 02:12:59 PM PST 24
Finished Feb 21 02:13:13 PM PST 24
Peak memory 224132 kb
Host smart-727279c4-83eb-4955-90a2-ce45432788ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2123811301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2123811301
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2869990126
Short name T522
Test name
Test status
Simulation time 26657081471 ps
CPU time 41.51 seconds
Started Feb 21 02:12:51 PM PST 24
Finished Feb 21 02:13:33 PM PST 24
Peak memory 199720 kb
Host smart-360d5fff-b685-4851-922a-ef1940fbf6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869990126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2869990126
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.4063044082
Short name T429
Test name
Test status
Simulation time 604432386 ps
CPU time 31.67 seconds
Started Feb 21 02:12:51 PM PST 24
Finished Feb 21 02:13:24 PM PST 24
Peak memory 199504 kb
Host smart-46070c83-8dd1-48c5-884e-4cb7670849d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063044082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.4063044082
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2671174931
Short name T324
Test name
Test status
Simulation time 7743573298 ps
CPU time 125.83 seconds
Started Feb 21 02:12:52 PM PST 24
Finished Feb 21 02:14:59 PM PST 24
Peak memory 199972 kb
Host smart-293852a0-3d94-46bb-9ea3-799aa778a9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671174931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2671174931
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1667472273
Short name T371
Test name
Test status
Simulation time 840567616 ps
CPU time 48.37 seconds
Started Feb 21 02:12:34 PM PST 24
Finished Feb 21 02:13:24 PM PST 24
Peak memory 199516 kb
Host smart-526dfd3f-83f5-4f96-ab84-a8180cf2f550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667472273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1667472273
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3669487811
Short name T42
Test name
Test status
Simulation time 63060980 ps
CPU time 0.86 seconds
Started Feb 21 02:13:01 PM PST 24
Finished Feb 21 02:13:02 PM PST 24
Peak memory 216464 kb
Host smart-7f4bc5e2-5c69-4c95-8995-9273b09695b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669487811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3669487811
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3283388222
Short name T61
Test name
Test status
Simulation time 232237861 ps
CPU time 2.06 seconds
Started Feb 21 02:12:35 PM PST 24
Finished Feb 21 02:12:37 PM PST 24
Peak memory 199792 kb
Host smart-7639f6b4-57e4-4a60-afdf-301e3bbc5174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283388222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3283388222
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.4274262172
Short name T20
Test name
Test status
Simulation time 55001369849 ps
CPU time 955.39 seconds
Started Feb 21 02:12:43 PM PST 24
Finished Feb 21 02:28:39 PM PST 24
Peak memory 199652 kb
Host smart-c2c99422-023c-4bd8-bd4e-22083960e784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274262172 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.4274262172
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.363724230
Short name T444
Test name
Test status
Simulation time 35393153 ps
CPU time 0.87 seconds
Started Feb 21 02:13:00 PM PST 24
Finished Feb 21 02:13:01 PM PST 24
Peak memory 196624 kb
Host smart-00062846-ce62-4ca0-9aa7-fbb809f49b03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363724230 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.363724230
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1695441934
Short name T366
Test name
Test status
Simulation time 8162043023 ps
CPU time 403.76 seconds
Started Feb 21 02:12:58 PM PST 24
Finished Feb 21 02:19:43 PM PST 24
Peak memory 199604 kb
Host smart-85e49c51-a84b-4b06-a00f-bee817c6518b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695441934 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.1695441934
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.429796604
Short name T330
Test name
Test status
Simulation time 3375391176 ps
CPU time 10.68 seconds
Started Feb 21 02:13:05 PM PST 24
Finished Feb 21 02:13:16 PM PST 24
Peak memory 199660 kb
Host smart-d1a9b764-583e-4523-a777-7521a7f54343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429796604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.429796604
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4255627671
Short name T375
Test name
Test status
Simulation time 30362879 ps
CPU time 0.61 seconds
Started Feb 21 02:17:10 PM PST 24
Finished Feb 21 02:17:12 PM PST 24
Peak memory 193748 kb
Host smart-c3e9ce93-750d-46b4-9d3a-b6f075aff253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255627671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4255627671
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2510164503
Short name T364
Test name
Test status
Simulation time 381577369 ps
CPU time 11.56 seconds
Started Feb 21 02:17:09 PM PST 24
Finished Feb 21 02:17:21 PM PST 24
Peak memory 199572 kb
Host smart-581c7664-464e-4d84-a141-e3e08702129e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510164503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2510164503
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2698144823
Short name T344
Test name
Test status
Simulation time 11727818214 ps
CPU time 27.45 seconds
Started Feb 21 02:17:09 PM PST 24
Finished Feb 21 02:17:37 PM PST 24
Peak memory 199668 kb
Host smart-31da9b16-3896-4075-b104-f2dea331504e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698144823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2698144823
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1663453654
Short name T506
Test name
Test status
Simulation time 927454645 ps
CPU time 50.71 seconds
Started Feb 21 02:17:10 PM PST 24
Finished Feb 21 02:18:01 PM PST 24
Peak memory 199420 kb
Host smart-2e00417f-7af8-4a03-9c99-c0e875d1b4a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663453654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1663453654
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3650569548
Short name T337
Test name
Test status
Simulation time 50176207318 ps
CPU time 164.1 seconds
Started Feb 21 02:17:10 PM PST 24
Finished Feb 21 02:19:56 PM PST 24
Peak memory 199596 kb
Host smart-841b4a5d-5c65-4476-be2a-082d7041c701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650569548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3650569548
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2979292858
Short name T533
Test name
Test status
Simulation time 20086526701 ps
CPU time 97.72 seconds
Started Feb 21 02:17:08 PM PST 24
Finished Feb 21 02:18:46 PM PST 24
Peak memory 199608 kb
Host smart-06e35354-8f53-4d78-b61c-3b52728477e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979292858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2979292858
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.557452778
Short name T567
Test name
Test status
Simulation time 50532880 ps
CPU time 1 seconds
Started Feb 21 02:16:57 PM PST 24
Finished Feb 21 02:16:59 PM PST 24
Peak memory 197396 kb
Host smart-1c068b33-14e1-4d51-b5e4-4fc52523e1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557452778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.557452778
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.1025686385
Short name T546
Test name
Test status
Simulation time 112743576 ps
CPU time 1.08 seconds
Started Feb 21 02:17:08 PM PST 24
Finished Feb 21 02:17:10 PM PST 24
Peak memory 198500 kb
Host smart-85a5e7f5-33ac-4d1a-aeb0-1dd1aa871c47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025686385 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.1025686385
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1762786091
Short name T300
Test name
Test status
Simulation time 7633142392 ps
CPU time 398.46 seconds
Started Feb 21 02:17:09 PM PST 24
Finished Feb 21 02:23:48 PM PST 24
Peak memory 199636 kb
Host smart-96171f7b-92e2-4d66-a2d4-ee654ccf9b69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762786091 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.1762786091
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1395282607
Short name T530
Test name
Test status
Simulation time 2327493497 ps
CPU time 11.46 seconds
Started Feb 21 02:17:09 PM PST 24
Finished Feb 21 02:17:20 PM PST 24
Peak memory 199612 kb
Host smart-38e8b532-4449-4f14-b7f3-898f225d0966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395282607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1395282607
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2215848388
Short name T527
Test name
Test status
Simulation time 14057329 ps
CPU time 0.56 seconds
Started Feb 21 02:17:18 PM PST 24
Finished Feb 21 02:17:19 PM PST 24
Peak memory 193936 kb
Host smart-939c0988-3905-4fd1-9a3a-a384e36862fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215848388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2215848388
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.31319927
Short name T252
Test name
Test status
Simulation time 2742223445 ps
CPU time 10.33 seconds
Started Feb 21 02:17:08 PM PST 24
Finished Feb 21 02:17:19 PM PST 24
Peak memory 199600 kb
Host smart-a9ff4213-8f83-4aab-b71d-e95b696088d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31319927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.31319927
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.331245235
Short name T474
Test name
Test status
Simulation time 3273776502 ps
CPU time 89.49 seconds
Started Feb 21 02:17:08 PM PST 24
Finished Feb 21 02:18:38 PM PST 24
Peak memory 199672 kb
Host smart-2a85c490-53bf-4f40-b00d-7426ee6f715d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331245235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.331245235
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2415513788
Short name T207
Test name
Test status
Simulation time 1510249385 ps
CPU time 25.59 seconds
Started Feb 21 02:17:10 PM PST 24
Finished Feb 21 02:17:36 PM PST 24
Peak memory 199416 kb
Host smart-03466a98-0acf-45c4-8ac3-94ff3c9f0bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415513788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2415513788
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.547963012
Short name T303
Test name
Test status
Simulation time 28248951103 ps
CPU time 67.03 seconds
Started Feb 21 02:17:08 PM PST 24
Finished Feb 21 02:18:16 PM PST 24
Peak memory 199684 kb
Host smart-f40eaf80-2c92-415b-9273-51e14ac83596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547963012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.547963012
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.661724314
Short name T505
Test name
Test status
Simulation time 74640682 ps
CPU time 1.2 seconds
Started Feb 21 02:17:08 PM PST 24
Finished Feb 21 02:17:10 PM PST 24
Peak memory 198916 kb
Host smart-a4b058f0-0bff-406a-8f52-0389b44b8e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661724314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.661724314
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.865402140
Short name T361
Test name
Test status
Simulation time 23424555642 ps
CPU time 403.21 seconds
Started Feb 21 02:17:27 PM PST 24
Finished Feb 21 02:24:11 PM PST 24
Peak memory 199640 kb
Host smart-6bad85fd-d4c7-4ec7-a7a7-0b2aa7cb14aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865402140 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.865402140
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2639991734
Short name T418
Test name
Test status
Simulation time 45968217 ps
CPU time 0.89 seconds
Started Feb 21 02:17:27 PM PST 24
Finished Feb 21 02:17:28 PM PST 24
Peak memory 197540 kb
Host smart-1aa2a8bb-ba7f-442b-b9a9-16676328ea64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639991734 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2639991734
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3356114748
Short name T477
Test name
Test status
Simulation time 7138992397 ps
CPU time 334.96 seconds
Started Feb 21 02:17:27 PM PST 24
Finished Feb 21 02:23:02 PM PST 24
Peak memory 199568 kb
Host smart-affcf996-6493-4189-8f3a-579438a9b3f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356114748 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.3356114748
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3189338181
Short name T403
Test name
Test status
Simulation time 4200093003 ps
CPU time 53.7 seconds
Started Feb 21 02:17:19 PM PST 24
Finished Feb 21 02:18:14 PM PST 24
Peak memory 199640 kb
Host smart-5a355f45-67c5-404c-a2cc-e1fed073444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189338181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3189338181
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.809892802
Short name T172
Test name
Test status
Simulation time 61159900 ps
CPU time 0.56 seconds
Started Feb 21 02:17:28 PM PST 24
Finished Feb 21 02:17:29 PM PST 24
Peak memory 193944 kb
Host smart-ddeee55e-2e45-43fb-9d45-6dd05715f5d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809892802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.809892802
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2058690510
Short name T221
Test name
Test status
Simulation time 302893144 ps
CPU time 9.78 seconds
Started Feb 21 02:17:16 PM PST 24
Finished Feb 21 02:17:26 PM PST 24
Peak memory 207736 kb
Host smart-86b03478-d003-48e8-b0dd-45cf69d885f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058690510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2058690510
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.10999027
Short name T524
Test name
Test status
Simulation time 632006954 ps
CPU time 29 seconds
Started Feb 21 02:17:28 PM PST 24
Finished Feb 21 02:17:58 PM PST 24
Peak memory 199468 kb
Host smart-dbfb043a-85e6-4f1e-96c8-7d5183be99f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10999027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.10999027
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4055483688
Short name T370
Test name
Test status
Simulation time 103418064 ps
CPU time 0.64 seconds
Started Feb 21 02:17:19 PM PST 24
Finished Feb 21 02:17:20 PM PST 24
Peak memory 194836 kb
Host smart-40ddb243-b9e0-4850-85bf-dae1fd46afd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055483688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4055483688
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.349344419
Short name T206
Test name
Test status
Simulation time 1748668596 ps
CPU time 15.16 seconds
Started Feb 21 02:17:17 PM PST 24
Finished Feb 21 02:17:32 PM PST 24
Peak memory 199644 kb
Host smart-d1d63e47-95ac-46f9-a0b7-8b3839ff634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349344419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.349344419
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.603446260
Short name T591
Test name
Test status
Simulation time 680861063 ps
CPU time 35.33 seconds
Started Feb 21 02:17:17 PM PST 24
Finished Feb 21 02:17:53 PM PST 24
Peak memory 199508 kb
Host smart-75fc5764-5a09-4ec1-a4ba-830d3cc90abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603446260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.603446260
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1305570694
Short name T82
Test name
Test status
Simulation time 179582315 ps
CPU time 1.18 seconds
Started Feb 21 02:17:15 PM PST 24
Finished Feb 21 02:17:17 PM PST 24
Peak memory 198844 kb
Host smart-a5294ee0-32e1-4f68-99aa-3a11123cf942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305570694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1305570694
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2875922294
Short name T443
Test name
Test status
Simulation time 71743818432 ps
CPU time 243.99 seconds
Started Feb 21 02:17:27 PM PST 24
Finished Feb 21 02:21:32 PM PST 24
Peak memory 219524 kb
Host smart-f77e564b-fe16-408b-a024-45fd870d36ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875922294 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2875922294
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2574888567
Short name T297
Test name
Test status
Simulation time 31792131 ps
CPU time 1.1 seconds
Started Feb 21 02:17:17 PM PST 24
Finished Feb 21 02:17:18 PM PST 24
Peak memory 197072 kb
Host smart-be8547d6-1ea9-4c44-a118-84bd4bb8b1fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574888567 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2574888567
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3468792973
Short name T566
Test name
Test status
Simulation time 7911564207 ps
CPU time 414.57 seconds
Started Feb 21 02:17:16 PM PST 24
Finished Feb 21 02:24:11 PM PST 24
Peak memory 199648 kb
Host smart-da6b9ff2-3648-4e7f-82e9-27fb0e657ab6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468792973 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.3468792973
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1733485251
Short name T585
Test name
Test status
Simulation time 1277687566 ps
CPU time 6.2 seconds
Started Feb 21 02:17:28 PM PST 24
Finished Feb 21 02:17:35 PM PST 24
Peak memory 199412 kb
Host smart-dd968943-ef2a-4d5a-8aa8-0e66d1f58886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733485251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1733485251
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1247127791
Short name T196
Test name
Test status
Simulation time 105297646 ps
CPU time 0.58 seconds
Started Feb 21 02:17:25 PM PST 24
Finished Feb 21 02:17:26 PM PST 24
Peak memory 193812 kb
Host smart-5788e965-34e1-4408-8efb-861355958bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247127791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1247127791
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1027627433
Short name T414
Test name
Test status
Simulation time 1923272309 ps
CPU time 60.8 seconds
Started Feb 21 02:17:24 PM PST 24
Finished Feb 21 02:18:25 PM PST 24
Peak memory 230328 kb
Host smart-527bb752-17ba-438c-bc3b-0a9bc1c242a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1027627433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1027627433
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3994307131
Short name T396
Test name
Test status
Simulation time 940994292 ps
CPU time 9.35 seconds
Started Feb 21 02:17:26 PM PST 24
Finished Feb 21 02:17:35 PM PST 24
Peak memory 199612 kb
Host smart-08e0bb14-0df1-4bd4-8323-8ff11eec9659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994307131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3994307131
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2093749980
Short name T580
Test name
Test status
Simulation time 2878427196 ps
CPU time 74.79 seconds
Started Feb 21 02:17:26 PM PST 24
Finished Feb 21 02:18:41 PM PST 24
Peak memory 199664 kb
Host smart-ac65be29-78dc-44fd-9cf7-17cc5240283b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093749980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2093749980
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.855086903
Short name T190
Test name
Test status
Simulation time 449125827 ps
CPU time 21.45 seconds
Started Feb 21 02:17:27 PM PST 24
Finished Feb 21 02:17:49 PM PST 24
Peak memory 199616 kb
Host smart-58abb5b0-8e5e-41c6-ab38-f786114f56d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855086903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.855086903
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1670964548
Short name T157
Test name
Test status
Simulation time 1264771966 ps
CPU time 22.7 seconds
Started Feb 21 02:17:26 PM PST 24
Finished Feb 21 02:17:49 PM PST 24
Peak memory 199536 kb
Host smart-e625d782-2be6-4d51-9de4-c2719998992d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670964548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1670964548
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1600964440
Short name T543
Test name
Test status
Simulation time 351528350 ps
CPU time 2.07 seconds
Started Feb 21 02:17:17 PM PST 24
Finished Feb 21 02:17:19 PM PST 24
Peak memory 199432 kb
Host smart-7fe76720-f814-4306-9700-2575920d4587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600964440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1600964440
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.356423774
Short name T259
Test name
Test status
Simulation time 17886838908 ps
CPU time 877.75 seconds
Started Feb 21 02:17:26 PM PST 24
Finished Feb 21 02:32:04 PM PST 24
Peak memory 240612 kb
Host smart-4dad12f4-e913-4de9-afe8-983e163719b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356423774 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.356423774
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2038135099
Short name T376
Test name
Test status
Simulation time 200956366 ps
CPU time 1.18 seconds
Started Feb 21 02:17:27 PM PST 24
Finished Feb 21 02:17:28 PM PST 24
Peak memory 198056 kb
Host smart-b2131489-1be2-4a7a-835e-f9800a37bd5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038135099 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2038135099
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.976594173
Short name T48
Test name
Test status
Simulation time 8044729224 ps
CPU time 376.25 seconds
Started Feb 21 02:17:24 PM PST 24
Finished Feb 21 02:23:41 PM PST 24
Peak memory 199524 kb
Host smart-ce60bc2d-af02-4ad7-9508-b4611d74696b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976594173 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.hmac_test_sha_vectors.976594173
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3649921605
Short name T267
Test name
Test status
Simulation time 312299556 ps
CPU time 15.41 seconds
Started Feb 21 02:17:27 PM PST 24
Finished Feb 21 02:17:43 PM PST 24
Peak memory 199560 kb
Host smart-d7cc2942-4a21-4b2d-b08d-16eb4148d403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649921605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3649921605
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2949669780
Short name T568
Test name
Test status
Simulation time 55166656 ps
CPU time 0.55 seconds
Started Feb 21 02:17:42 PM PST 24
Finished Feb 21 02:17:45 PM PST 24
Peak memory 193800 kb
Host smart-a601d506-cdc4-408e-9689-0789ea4ae748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949669780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2949669780
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1912280816
Short name T320
Test name
Test status
Simulation time 1285123280 ps
CPU time 21.56 seconds
Started Feb 21 02:17:41 PM PST 24
Finished Feb 21 02:18:05 PM PST 24
Peak memory 207736 kb
Host smart-d9a9efb9-cdb3-4c8d-8c61-1d7ea1031290
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912280816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1912280816
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2868708283
Short name T109
Test name
Test status
Simulation time 11441578272 ps
CPU time 45.46 seconds
Started Feb 21 02:17:43 PM PST 24
Finished Feb 21 02:18:30 PM PST 24
Peak memory 199620 kb
Host smart-08103a03-1d29-4509-8216-120306f6978e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868708283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2868708283
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3439391524
Short name T479
Test name
Test status
Simulation time 6957290135 ps
CPU time 91.98 seconds
Started Feb 21 02:17:42 PM PST 24
Finished Feb 21 02:19:16 PM PST 24
Peak memory 199656 kb
Host smart-ea4137e6-7839-4e1d-8d27-f2f01b6915dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439391524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3439391524
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2306213553
Short name T350
Test name
Test status
Simulation time 1536845996 ps
CPU time 80 seconds
Started Feb 21 02:17:41 PM PST 24
Finished Feb 21 02:19:02 PM PST 24
Peak memory 199520 kb
Host smart-78774d24-38fd-4b4c-b1f5-69e6ae151d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306213553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2306213553
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1736076435
Short name T192
Test name
Test status
Simulation time 988572743 ps
CPU time 57.05 seconds
Started Feb 21 02:17:42 PM PST 24
Finished Feb 21 02:18:41 PM PST 24
Peak memory 199540 kb
Host smart-1fd89a98-bb2e-46af-b58d-3140c3996f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736076435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1736076435
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2823503650
Short name T219
Test name
Test status
Simulation time 157915207 ps
CPU time 1.95 seconds
Started Feb 21 02:17:42 PM PST 24
Finished Feb 21 02:17:46 PM PST 24
Peak memory 199524 kb
Host smart-3b08bdbf-4e73-4fcb-96a3-3f6982f5613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823503650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2823503650
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3778022397
Short name T438
Test name
Test status
Simulation time 115830315316 ps
CPU time 949.83 seconds
Started Feb 21 02:17:41 PM PST 24
Finished Feb 21 02:33:32 PM PST 24
Peak memory 215396 kb
Host smart-cbdc300b-80ed-4ac2-80a6-af1d014c3177
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778022397 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3778022397
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1969344035
Short name T508
Test name
Test status
Simulation time 57798080 ps
CPU time 1.21 seconds
Started Feb 21 02:17:43 PM PST 24
Finished Feb 21 02:17:46 PM PST 24
Peak memory 198244 kb
Host smart-f50afba0-1172-461b-ae07-37ab37598ff5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969344035 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1969344035
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.153139915
Short name T205
Test name
Test status
Simulation time 30936086316 ps
CPU time 385.22 seconds
Started Feb 21 02:17:42 PM PST 24
Finished Feb 21 02:24:10 PM PST 24
Peak memory 199616 kb
Host smart-d6156d7a-97cf-4280-a4c6-aac5d777db73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153139915 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.hmac_test_sha_vectors.153139915
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.4208124338
Short name T483
Test name
Test status
Simulation time 3807898525 ps
CPU time 67.82 seconds
Started Feb 21 02:17:42 PM PST 24
Finished Feb 21 02:18:52 PM PST 24
Peak memory 199704 kb
Host smart-7762969b-760f-4531-8401-784eaf30942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208124338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.4208124338
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.4054228321
Short name T242
Test name
Test status
Simulation time 16890936 ps
CPU time 0.6 seconds
Started Feb 21 02:17:57 PM PST 24
Finished Feb 21 02:17:58 PM PST 24
Peak memory 194748 kb
Host smart-c1b85e6c-1eaf-47a2-802f-d406260e2d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054228321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.4054228321
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1285888430
Short name T25
Test name
Test status
Simulation time 1933933654 ps
CPU time 33.08 seconds
Started Feb 21 02:17:54 PM PST 24
Finished Feb 21 02:18:28 PM PST 24
Peak memory 207772 kb
Host smart-46659b96-24c6-4eed-97a5-c0a8724862d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285888430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1285888430
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2948879199
Short name T569
Test name
Test status
Simulation time 2471112893 ps
CPU time 55.42 seconds
Started Feb 21 02:17:48 PM PST 24
Finished Feb 21 02:18:44 PM PST 24
Peak memory 199636 kb
Host smart-d0d73a51-e74c-4c86-80ba-58aac8c5939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948879199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2948879199
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2634811521
Short name T199
Test name
Test status
Simulation time 879083703 ps
CPU time 43.99 seconds
Started Feb 21 02:17:54 PM PST 24
Finished Feb 21 02:18:38 PM PST 24
Peak memory 199500 kb
Host smart-9c92d77a-5d25-4554-ab65-129a00ee452a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634811521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2634811521
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3893329129
Short name T417
Test name
Test status
Simulation time 4990189230 ps
CPU time 68.85 seconds
Started Feb 21 02:17:55 PM PST 24
Finished Feb 21 02:19:05 PM PST 24
Peak memory 199612 kb
Host smart-f28fefac-01af-4536-ab74-59f386d813ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893329129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3893329129
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.179627057
Short name T64
Test name
Test status
Simulation time 1549159306 ps
CPU time 80.83 seconds
Started Feb 21 02:17:53 PM PST 24
Finished Feb 21 02:19:14 PM PST 24
Peak memory 199516 kb
Host smart-1aaa3fca-eaa0-43de-9297-b38dd00338ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179627057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.179627057
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3501238346
Short name T278
Test name
Test status
Simulation time 114865211 ps
CPU time 1.59 seconds
Started Feb 21 02:17:57 PM PST 24
Finished Feb 21 02:17:59 PM PST 24
Peak memory 199436 kb
Host smart-afa7284b-3a95-4184-9fbf-d447e8053d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501238346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3501238346
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1763922658
Short name T132
Test name
Test status
Simulation time 59420005306 ps
CPU time 490.99 seconds
Started Feb 21 02:17:54 PM PST 24
Finished Feb 21 02:26:05 PM PST 24
Peak memory 199672 kb
Host smart-7d982388-a959-4dfb-8c0b-f48ad84ea1a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763922658 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1763922658
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1990593774
Short name T541
Test name
Test status
Simulation time 112017325 ps
CPU time 1.05 seconds
Started Feb 21 02:17:54 PM PST 24
Finished Feb 21 02:17:56 PM PST 24
Peak memory 199080 kb
Host smart-86fade81-11a9-4801-8e3a-2000ce8584e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990593774 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1990593774
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2011982144
Short name T513
Test name
Test status
Simulation time 26149470881 ps
CPU time 409.69 seconds
Started Feb 21 02:17:55 PM PST 24
Finished Feb 21 02:24:46 PM PST 24
Peak memory 199688 kb
Host smart-49e88971-8709-450b-b8f9-de6f5ae3ac1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011982144 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.2011982144
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3429445976
Short name T217
Test name
Test status
Simulation time 26237912978 ps
CPU time 26.51 seconds
Started Feb 21 02:17:54 PM PST 24
Finished Feb 21 02:18:22 PM PST 24
Peak memory 199664 kb
Host smart-78ed1c7e-658b-44b1-b442-fca96893bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429445976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3429445976
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1096785937
Short name T447
Test name
Test status
Simulation time 35946989 ps
CPU time 0.56 seconds
Started Feb 21 02:17:55 PM PST 24
Finished Feb 21 02:17:56 PM PST 24
Peak memory 194008 kb
Host smart-05cd8c43-a77c-488b-b31a-733a65426296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096785937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1096785937
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3255272407
Short name T544
Test name
Test status
Simulation time 14406774715 ps
CPU time 58.72 seconds
Started Feb 21 02:17:55 PM PST 24
Finished Feb 21 02:18:55 PM PST 24
Peak memory 240664 kb
Host smart-84bf4e96-288f-4681-b25c-8989eef40050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255272407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3255272407
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.4186839972
Short name T576
Test name
Test status
Simulation time 8931664306 ps
CPU time 42.47 seconds
Started Feb 21 02:17:55 PM PST 24
Finished Feb 21 02:18:38 PM PST 24
Peak memory 199624 kb
Host smart-0e7a9c01-52f7-4217-8365-bba7a3bbecb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186839972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.4186839972
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.344190770
Short name T119
Test name
Test status
Simulation time 8095041002 ps
CPU time 106.66 seconds
Started Feb 21 02:17:57 PM PST 24
Finished Feb 21 02:19:44 PM PST 24
Peak memory 199648 kb
Host smart-6ab6f13a-fb14-4cca-9a66-484cb8a3fc95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=344190770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.344190770
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.304301737
Short name T124
Test name
Test status
Simulation time 27204753760 ps
CPU time 227.58 seconds
Started Feb 21 02:17:54 PM PST 24
Finished Feb 21 02:21:42 PM PST 24
Peak memory 199740 kb
Host smart-11b5da32-d9ea-405f-bc6e-b66fbf598797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304301737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.304301737
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3270687066
Short name T120
Test name
Test status
Simulation time 11208038862 ps
CPU time 98.63 seconds
Started Feb 21 02:17:53 PM PST 24
Finished Feb 21 02:19:33 PM PST 24
Peak memory 199660 kb
Host smart-b5f92f57-6e12-4fe1-a138-2a13a6d8aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270687066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3270687066
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3893341457
Short name T13
Test name
Test status
Simulation time 104080272 ps
CPU time 2.86 seconds
Started Feb 21 02:17:55 PM PST 24
Finished Feb 21 02:17:59 PM PST 24
Peak memory 199420 kb
Host smart-704e0a72-548c-47f3-88ed-c2d0a759effd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893341457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3893341457
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2475088906
Short name T270
Test name
Test status
Simulation time 26573075299 ps
CPU time 1252.1 seconds
Started Feb 21 02:17:55 PM PST 24
Finished Feb 21 02:38:48 PM PST 24
Peak memory 240660 kb
Host smart-4ddc0fd2-bf8f-402d-a22b-49ac223c1717
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475088906 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2475088906
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1093881752
Short name T427
Test name
Test status
Simulation time 297186214 ps
CPU time 1.16 seconds
Started Feb 21 02:17:52 PM PST 24
Finished Feb 21 02:17:54 PM PST 24
Peak memory 198208 kb
Host smart-3c5b94c6-78d8-46eb-90e7-6ea5909e7ab9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093881752 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1093881752
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1942803519
Short name T578
Test name
Test status
Simulation time 111106503088 ps
CPU time 431.15 seconds
Started Feb 21 02:17:53 PM PST 24
Finished Feb 21 02:25:06 PM PST 24
Peak memory 199604 kb
Host smart-0963a4f8-234a-49c8-89f2-8010c2cdda28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942803519 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.1942803519
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.743954026
Short name T538
Test name
Test status
Simulation time 4066384446 ps
CPU time 42.33 seconds
Started Feb 21 02:17:53 PM PST 24
Finished Feb 21 02:18:36 PM PST 24
Peak memory 199584 kb
Host smart-1a0edf29-a365-4d03-ae4a-b0b9d72c9913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743954026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.743954026
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3129536548
Short name T310
Test name
Test status
Simulation time 35311025 ps
CPU time 0.55 seconds
Started Feb 21 02:18:03 PM PST 24
Finished Feb 21 02:18:03 PM PST 24
Peak memory 193916 kb
Host smart-f0f5768d-5139-4e92-a7ff-8911143a2e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129536548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3129536548
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2720115295
Short name T274
Test name
Test status
Simulation time 5522804066 ps
CPU time 47.49 seconds
Started Feb 21 02:17:55 PM PST 24
Finished Feb 21 02:18:43 PM PST 24
Peak memory 232372 kb
Host smart-cf77ae12-ec13-4047-9fba-4e22c3e58bbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720115295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2720115295
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2756669058
Short name T561
Test name
Test status
Simulation time 872528232 ps
CPU time 10.99 seconds
Started Feb 21 02:18:02 PM PST 24
Finished Feb 21 02:18:13 PM PST 24
Peak memory 199548 kb
Host smart-102db7a9-ec55-4e5a-8fc8-52ad74011b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756669058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2756669058
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1882544806
Short name T197
Test name
Test status
Simulation time 8852456031 ps
CPU time 104.77 seconds
Started Feb 21 02:17:54 PM PST 24
Finished Feb 21 02:19:40 PM PST 24
Peak memory 199728 kb
Host smart-45e2f879-670f-488a-ab85-b381860552a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882544806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1882544806
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.4230977055
Short name T285
Test name
Test status
Simulation time 6397722665 ps
CPU time 77.52 seconds
Started Feb 21 02:18:05 PM PST 24
Finished Feb 21 02:19:22 PM PST 24
Peak memory 199704 kb
Host smart-38a01a49-9054-4188-9f27-702e079135c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230977055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4230977055
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.255320087
Short name T549
Test name
Test status
Simulation time 52093127950 ps
CPU time 81 seconds
Started Feb 21 02:17:57 PM PST 24
Finished Feb 21 02:19:18 PM PST 24
Peak memory 199600 kb
Host smart-a27da09c-1af8-4ded-a293-0aa6ace459ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255320087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.255320087
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2806073092
Short name T593
Test name
Test status
Simulation time 934392489 ps
CPU time 2.7 seconds
Started Feb 21 02:17:53 PM PST 24
Finished Feb 21 02:17:57 PM PST 24
Peak memory 199492 kb
Host smart-2d14555c-8d9f-47d1-9650-0b330ff47850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806073092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2806073092
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3846724130
Short name T510
Test name
Test status
Simulation time 133760936 ps
CPU time 1.24 seconds
Started Feb 21 02:18:05 PM PST 24
Finished Feb 21 02:18:07 PM PST 24
Peak memory 199096 kb
Host smart-2e3134d6-4a02-4195-b234-083b1ad93933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846724130 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3846724130
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2715591522
Short name T185
Test name
Test status
Simulation time 183613510199 ps
CPU time 508.51 seconds
Started Feb 21 02:18:05 PM PST 24
Finished Feb 21 02:26:34 PM PST 24
Peak memory 199848 kb
Host smart-1233793d-9aa1-4503-848f-533f5532a491
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715591522 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.2715591522
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1325135758
Short name T18
Test name
Test status
Simulation time 9977464471 ps
CPU time 71.62 seconds
Started Feb 21 02:18:05 PM PST 24
Finished Feb 21 02:19:17 PM PST 24
Peak memory 199940 kb
Host smart-da11540f-7aba-416c-97a7-81cfc3f3c878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325135758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1325135758
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.209924100
Short name T526
Test name
Test status
Simulation time 23140519 ps
CPU time 0.6 seconds
Started Feb 21 02:18:16 PM PST 24
Finished Feb 21 02:18:17 PM PST 24
Peak memory 193920 kb
Host smart-91db8e3c-aaa3-4f74-b9af-683786454e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209924100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.209924100
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1719378285
Short name T282
Test name
Test status
Simulation time 622884083 ps
CPU time 18.41 seconds
Started Feb 21 02:18:03 PM PST 24
Finished Feb 21 02:18:21 PM PST 24
Peak memory 207720 kb
Host smart-e5024994-9dfe-4800-ab15-ff5c072db5ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719378285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1719378285
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.537178110
Short name T135
Test name
Test status
Simulation time 1693907194 ps
CPU time 34.28 seconds
Started Feb 21 02:18:13 PM PST 24
Finished Feb 21 02:18:47 PM PST 24
Peak memory 199564 kb
Host smart-1200ae1b-5b4d-42e4-904f-a898b32473cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537178110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.537178110
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2885213872
Short name T264
Test name
Test status
Simulation time 125035265 ps
CPU time 5.91 seconds
Started Feb 21 02:18:02 PM PST 24
Finished Feb 21 02:18:08 PM PST 24
Peak memory 199568 kb
Host smart-753be6c0-28cc-4805-9eca-aaab9dc9b516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885213872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2885213872
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.27964434
Short name T247
Test name
Test status
Simulation time 46573089378 ps
CPU time 126.5 seconds
Started Feb 21 02:18:08 PM PST 24
Finished Feb 21 02:20:15 PM PST 24
Peak memory 199680 kb
Host smart-27261a75-7b80-4c25-a053-9a2fcf6130ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27964434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.27964434
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_smoke.4125575069
Short name T156
Test name
Test status
Simulation time 241401627 ps
CPU time 2.81 seconds
Started Feb 21 02:18:06 PM PST 24
Finished Feb 21 02:18:09 PM PST 24
Peak memory 199504 kb
Host smart-b232f051-6064-4f9b-9092-80e2aee09c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125575069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4125575069
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2449549361
Short name T521
Test name
Test status
Simulation time 108424640023 ps
CPU time 1342.11 seconds
Started Feb 21 02:18:13 PM PST 24
Finished Feb 21 02:40:36 PM PST 24
Peak memory 236560 kb
Host smart-4dcb2887-87cf-4bf3-a852-3145789c5846
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449549361 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2449549361
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.586724822
Short name T401
Test name
Test status
Simulation time 93224437 ps
CPU time 0.95 seconds
Started Feb 21 02:18:16 PM PST 24
Finished Feb 21 02:18:18 PM PST 24
Peak memory 196796 kb
Host smart-1f794554-6499-459a-9fb8-15d23894cab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586724822 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.586724822
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1077639495
Short name T448
Test name
Test status
Simulation time 34977497529 ps
CPU time 453.41 seconds
Started Feb 21 02:18:15 PM PST 24
Finished Feb 21 02:25:49 PM PST 24
Peak memory 199640 kb
Host smart-e90e4067-ebcb-4683-83d0-871ae36f10c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077639495 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.1077639495
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3243799097
Short name T81
Test name
Test status
Simulation time 4716718773 ps
CPU time 18.61 seconds
Started Feb 21 02:18:17 PM PST 24
Finished Feb 21 02:18:36 PM PST 24
Peak memory 199632 kb
Host smart-79c38283-c8e5-488c-b591-7ac8e6cc89e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243799097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3243799097
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2145223891
Short name T227
Test name
Test status
Simulation time 44450630 ps
CPU time 0.55 seconds
Started Feb 21 02:18:24 PM PST 24
Finished Feb 21 02:18:25 PM PST 24
Peak memory 193968 kb
Host smart-08a36c7c-6a3c-400c-b3a9-b70104163c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145223891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2145223891
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2364610345
Short name T26
Test name
Test status
Simulation time 1626467948 ps
CPU time 64.67 seconds
Started Feb 21 02:18:13 PM PST 24
Finished Feb 21 02:19:18 PM PST 24
Peak memory 230444 kb
Host smart-45b81221-36a8-495b-889e-8e50ca17b2e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364610345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2364610345
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4043617122
Short name T457
Test name
Test status
Simulation time 126974565 ps
CPU time 2.98 seconds
Started Feb 21 02:18:14 PM PST 24
Finished Feb 21 02:18:18 PM PST 24
Peak memory 199564 kb
Host smart-54432610-c4de-4fcd-b8e5-c2a3f628db73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043617122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4043617122
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1415314590
Short name T367
Test name
Test status
Simulation time 2241923054 ps
CPU time 30.43 seconds
Started Feb 21 02:18:23 PM PST 24
Finished Feb 21 02:18:54 PM PST 24
Peak memory 199688 kb
Host smart-fd27b81b-f6c4-4d9c-8943-2584922fac39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415314590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1415314590
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3461014536
Short name T555
Test name
Test status
Simulation time 17364467673 ps
CPU time 44.79 seconds
Started Feb 21 02:18:23 PM PST 24
Finished Feb 21 02:19:08 PM PST 24
Peak memory 199604 kb
Host smart-79951eac-ae5b-4ffd-bc12-a83cf49e3d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461014536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3461014536
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.737273772
Short name T542
Test name
Test status
Simulation time 5463905508 ps
CPU time 78.09 seconds
Started Feb 21 02:18:21 PM PST 24
Finished Feb 21 02:19:39 PM PST 24
Peak memory 199680 kb
Host smart-b902adf7-a1e5-49c1-8794-f0fde9df9a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737273772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.737273772
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3475311057
Short name T272
Test name
Test status
Simulation time 99140613 ps
CPU time 0.86 seconds
Started Feb 21 02:18:13 PM PST 24
Finished Feb 21 02:18:15 PM PST 24
Peak memory 197792 kb
Host smart-f4411ea1-92ea-4df9-b7ef-e7a54853c235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475311057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3475311057
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2171473737
Short name T254
Test name
Test status
Simulation time 3497810437 ps
CPU time 153.58 seconds
Started Feb 21 02:18:26 PM PST 24
Finished Feb 21 02:20:59 PM PST 24
Peak memory 225184 kb
Host smart-441b700c-be52-4132-beee-e724359867ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171473737 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2171473737
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1661607051
Short name T548
Test name
Test status
Simulation time 108424451 ps
CPU time 1.14 seconds
Started Feb 21 02:18:31 PM PST 24
Finished Feb 21 02:18:32 PM PST 24
Peak memory 198404 kb
Host smart-5c7d81d4-5637-416d-9442-cd0b376fa9b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661607051 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1661607051
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.280074582
Short name T523
Test name
Test status
Simulation time 6932847312 ps
CPU time 364.6 seconds
Started Feb 21 02:18:22 PM PST 24
Finished Feb 21 02:24:27 PM PST 24
Peak memory 199604 kb
Host smart-3ca3bd8a-6c62-4ea3-903c-015253949d1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280074582 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.hmac_test_sha_vectors.280074582
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2057030553
Short name T365
Test name
Test status
Simulation time 3373231742 ps
CPU time 49.16 seconds
Started Feb 21 02:18:25 PM PST 24
Finished Feb 21 02:19:14 PM PST 24
Peak memory 199660 kb
Host smart-ac5b8764-65aa-4f59-a899-397a587f7366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057030553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2057030553
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3779910407
Short name T572
Test name
Test status
Simulation time 28820682 ps
CPU time 0.54 seconds
Started Feb 21 02:12:59 PM PST 24
Finished Feb 21 02:13:00 PM PST 24
Peak memory 193644 kb
Host smart-691d5374-2300-4a08-935d-a62378bec7fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779910407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3779910407
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2058324564
Short name T415
Test name
Test status
Simulation time 885783775 ps
CPU time 30.66 seconds
Started Feb 21 02:13:24 PM PST 24
Finished Feb 21 02:13:55 PM PST 24
Peak memory 221328 kb
Host smart-663f0fd5-9c58-40fa-a4e0-e2b7c1229121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058324564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2058324564
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2432428333
Short name T225
Test name
Test status
Simulation time 10908086386 ps
CPU time 26.26 seconds
Started Feb 21 02:13:00 PM PST 24
Finished Feb 21 02:13:27 PM PST 24
Peak memory 199720 kb
Host smart-d0758d85-7218-46e1-a9c0-911993144d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432428333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2432428333
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.4172204882
Short name T220
Test name
Test status
Simulation time 3381692367 ps
CPU time 82.24 seconds
Started Feb 21 02:13:00 PM PST 24
Finished Feb 21 02:14:22 PM PST 24
Peak memory 199668 kb
Host smart-9398922c-6cba-4ad4-979c-755d84150d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172204882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.4172204882
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1394515254
Short name T409
Test name
Test status
Simulation time 4105013153 ps
CPU time 103.56 seconds
Started Feb 21 02:13:01 PM PST 24
Finished Feb 21 02:14:45 PM PST 24
Peak memory 199696 kb
Host smart-3f8d6c89-0204-4584-b549-bdcdf51b2f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394515254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1394515254
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3591155496
Short name T331
Test name
Test status
Simulation time 965721210 ps
CPU time 13.49 seconds
Started Feb 21 02:13:00 PM PST 24
Finished Feb 21 02:13:14 PM PST 24
Peak memory 199548 kb
Host smart-84ddd14f-a6fb-48f1-9d0e-d099dcf2a356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591155496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3591155496
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1215910406
Short name T248
Test name
Test status
Simulation time 203284538 ps
CPU time 1.15 seconds
Started Feb 21 02:13:00 PM PST 24
Finished Feb 21 02:13:02 PM PST 24
Peak memory 199084 kb
Host smart-3624ea35-3f1c-4f05-a734-15275112e669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215910406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1215910406
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3776627682
Short name T547
Test name
Test status
Simulation time 74920661 ps
CPU time 0.91 seconds
Started Feb 21 02:13:00 PM PST 24
Finished Feb 21 02:13:01 PM PST 24
Peak memory 196648 kb
Host smart-e5228296-2981-4670-8da7-b8d1d0328ccf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776627682 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3776627682
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1091437969
Short name T291
Test name
Test status
Simulation time 38481535639 ps
CPU time 411.85 seconds
Started Feb 21 02:13:01 PM PST 24
Finished Feb 21 02:19:53 PM PST 24
Peak memory 199608 kb
Host smart-3284a399-57f0-41de-a00d-65cb4d34a156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091437969 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.1091437969
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3748062716
Short name T449
Test name
Test status
Simulation time 494982624 ps
CPU time 26.62 seconds
Started Feb 21 02:13:00 PM PST 24
Finished Feb 21 02:13:27 PM PST 24
Peak memory 199564 kb
Host smart-55e8f8ba-5eef-4bd4-a456-de2491d7ac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748062716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3748062716
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4199172874
Short name T349
Test name
Test status
Simulation time 20725622 ps
CPU time 0.6 seconds
Started Feb 21 02:13:12 PM PST 24
Finished Feb 21 02:13:13 PM PST 24
Peak memory 193756 kb
Host smart-4f1bed48-156f-4407-838d-9d1a0689d288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199172874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4199172874
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.294121354
Short name T328
Test name
Test status
Simulation time 711905597 ps
CPU time 22.97 seconds
Started Feb 21 02:13:09 PM PST 24
Finished Feb 21 02:13:33 PM PST 24
Peak memory 225152 kb
Host smart-d8d6e751-a8b7-4b82-9d49-b56bdc175a18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=294121354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.294121354
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3409860449
Short name T455
Test name
Test status
Simulation time 1079823641 ps
CPU time 14.4 seconds
Started Feb 21 02:13:10 PM PST 24
Finished Feb 21 02:13:25 PM PST 24
Peak memory 199480 kb
Host smart-a6e6633a-d5d6-4094-9f49-37c9c5201152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409860449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3409860449
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1367934588
Short name T394
Test name
Test status
Simulation time 1804386543 ps
CPU time 97.63 seconds
Started Feb 21 02:13:10 PM PST 24
Finished Feb 21 02:14:48 PM PST 24
Peak memory 199232 kb
Host smart-ae7df44b-07a7-4cdc-aafb-b382907c0231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1367934588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1367934588
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.4175644044
Short name T334
Test name
Test status
Simulation time 67098568267 ps
CPU time 169.82 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:16:02 PM PST 24
Peak memory 199720 kb
Host smart-4191cf38-135e-4d71-b551-9756ee04a4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175644044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.4175644044
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.762009602
Short name T170
Test name
Test status
Simulation time 27917698641 ps
CPU time 40.89 seconds
Started Feb 21 02:12:59 PM PST 24
Finished Feb 21 02:13:40 PM PST 24
Peak memory 199688 kb
Host smart-bd8e26fe-73d3-4252-b454-821e64326677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762009602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.762009602
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2805509586
Short name T189
Test name
Test status
Simulation time 344002086 ps
CPU time 4.23 seconds
Started Feb 21 02:12:59 PM PST 24
Finished Feb 21 02:13:04 PM PST 24
Peak memory 199552 kb
Host smart-17f327b1-1e59-47b2-a8a6-a586dc966f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805509586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2805509586
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2803285585
Short name T74
Test name
Test status
Simulation time 77367572415 ps
CPU time 491.37 seconds
Started Feb 21 02:13:09 PM PST 24
Finished Feb 21 02:21:21 PM PST 24
Peak memory 199672 kb
Host smart-a9a4f942-1df1-4f19-9630-b0a9a9926135
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803285585 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2803285585
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.138151940
Short name T210
Test name
Test status
Simulation time 97372768 ps
CPU time 0.89 seconds
Started Feb 21 02:13:08 PM PST 24
Finished Feb 21 02:13:09 PM PST 24
Peak memory 196612 kb
Host smart-91399f17-cd45-4099-96e2-22f7fe4118ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138151940 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.138151940
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3197062076
Short name T368
Test name
Test status
Simulation time 51978378309 ps
CPU time 416.72 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:20:08 PM PST 24
Peak memory 199560 kb
Host smart-fd50fef5-ad26-48e5-b598-d5cb6abf0936
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197062076 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.3197062076
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1054653821
Short name T517
Test name
Test status
Simulation time 1222633538 ps
CPU time 30.21 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:13:42 PM PST 24
Peak memory 199756 kb
Host smart-8429e4a0-9815-47bc-b94b-8506616818cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054653821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1054653821
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3144287
Short name T15
Test name
Test status
Simulation time 24170409252 ps
CPU time 582.33 seconds
Started Feb 21 02:18:39 PM PST 24
Finished Feb 21 02:28:21 PM PST 24
Peak memory 216184 kb
Host smart-b62a1309-13f1-4a27-ab7b-3ff059af1df5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3144287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.3144287
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1791487378
Short name T280
Test name
Test status
Simulation time 23405126 ps
CPU time 0.55 seconds
Started Feb 21 02:13:12 PM PST 24
Finished Feb 21 02:13:13 PM PST 24
Peak memory 193800 kb
Host smart-5de78347-bad7-4639-bd0f-9383d54f0a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791487378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1791487378
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3874033941
Short name T250
Test name
Test status
Simulation time 1035290732 ps
CPU time 34.12 seconds
Started Feb 21 02:13:12 PM PST 24
Finished Feb 21 02:13:46 PM PST 24
Peak memory 209364 kb
Host smart-fb71ecad-40f9-4e5c-a269-d3d03c3867ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874033941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3874033941
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3993662393
Short name T377
Test name
Test status
Simulation time 1656776092 ps
CPU time 13.74 seconds
Started Feb 21 02:13:10 PM PST 24
Finished Feb 21 02:13:24 PM PST 24
Peak memory 199544 kb
Host smart-f2f40181-c8ed-47ee-b859-9b77a7a4743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993662393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3993662393
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3909251281
Short name T359
Test name
Test status
Simulation time 2506254195 ps
CPU time 132.6 seconds
Started Feb 21 02:13:08 PM PST 24
Finished Feb 21 02:15:21 PM PST 24
Peak memory 199636 kb
Host smart-734c1642-6c71-4676-8675-d60052865c10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909251281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3909251281
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2617782816
Short name T387
Test name
Test status
Simulation time 3155512190 ps
CPU time 82.86 seconds
Started Feb 21 02:13:09 PM PST 24
Finished Feb 21 02:14:32 PM PST 24
Peak memory 199716 kb
Host smart-75d587db-4c28-472c-b6bd-51b3edaa2fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617782816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2617782816
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2170179286
Short name T345
Test name
Test status
Simulation time 4483750431 ps
CPU time 27.37 seconds
Started Feb 21 02:13:12 PM PST 24
Finished Feb 21 02:13:40 PM PST 24
Peak memory 199652 kb
Host smart-893bd9aa-9ce2-4b67-bd2f-adcd2a91faa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170179286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2170179286
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1320440368
Short name T194
Test name
Test status
Simulation time 123579225 ps
CPU time 2.7 seconds
Started Feb 21 02:13:10 PM PST 24
Finished Feb 21 02:13:13 PM PST 24
Peak memory 199568 kb
Host smart-3602f89e-83a9-4ae4-b523-0176e51bd8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320440368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1320440368
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2348066146
Short name T420
Test name
Test status
Simulation time 116881244253 ps
CPU time 430.85 seconds
Started Feb 21 02:13:09 PM PST 24
Finished Feb 21 02:20:21 PM PST 24
Peak memory 199724 kb
Host smart-5a2dcf5e-7a0c-4ac7-811c-fec36d1e4441
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348066146 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2348066146
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2661804808
Short name T520
Test name
Test status
Simulation time 30997109 ps
CPU time 0.88 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:13:12 PM PST 24
Peak memory 196628 kb
Host smart-deb95376-c58a-4133-b566-b1490d9ea244
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661804808 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2661804808
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3859667430
Short name T381
Test name
Test status
Simulation time 15600684589 ps
CPU time 381.08 seconds
Started Feb 21 02:13:09 PM PST 24
Finished Feb 21 02:19:31 PM PST 24
Peak memory 199608 kb
Host smart-db0255ec-5e61-4fc0-bb80-84389521b7f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859667430 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.3859667430
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.574357068
Short name T251
Test name
Test status
Simulation time 6855126734 ps
CPU time 22.55 seconds
Started Feb 21 02:13:15 PM PST 24
Finished Feb 21 02:13:38 PM PST 24
Peak memory 199688 kb
Host smart-c784640c-15ec-4816-8f44-82a48038f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574357068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.574357068
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2064135800
Short name T518
Test name
Test status
Simulation time 27228111 ps
CPU time 0.58 seconds
Started Feb 21 02:13:09 PM PST 24
Finished Feb 21 02:13:10 PM PST 24
Peak memory 193748 kb
Host smart-ceee12b1-ddc9-4893-9d2e-dae054860373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064135800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2064135800
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.487330676
Short name T460
Test name
Test status
Simulation time 1718894459 ps
CPU time 27.78 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:13:40 PM PST 24
Peak memory 207736 kb
Host smart-53df9953-fc6f-40e4-8b58-ef7c8b4af6b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487330676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.487330676
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3894762186
Short name T52
Test name
Test status
Simulation time 6963430078 ps
CPU time 38.13 seconds
Started Feb 21 02:13:07 PM PST 24
Finished Feb 21 02:13:46 PM PST 24
Peak memory 199628 kb
Host smart-b357b926-07f7-4f65-9654-09194badde22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894762186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3894762186
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3716585239
Short name T559
Test name
Test status
Simulation time 24552404502 ps
CPU time 136.53 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:15:29 PM PST 24
Peak memory 199648 kb
Host smart-83361e0c-bc91-408d-9c4b-ae649807ccda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716585239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3716585239
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.483810923
Short name T164
Test name
Test status
Simulation time 6777313209 ps
CPU time 115.81 seconds
Started Feb 21 02:13:10 PM PST 24
Finished Feb 21 02:15:07 PM PST 24
Peak memory 199664 kb
Host smart-8f43eaff-dbf9-4c28-85bf-cdae215e4c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483810923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.483810923
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.630730788
Short name T404
Test name
Test status
Simulation time 14968858047 ps
CPU time 102.14 seconds
Started Feb 21 02:13:09 PM PST 24
Finished Feb 21 02:14:52 PM PST 24
Peak memory 199636 kb
Host smart-067b2135-fbad-41ca-88cc-86a297a07c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630730788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.630730788
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2799629624
Short name T159
Test name
Test status
Simulation time 848090630 ps
CPU time 2.95 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:13:15 PM PST 24
Peak memory 199572 kb
Host smart-e8f85224-4665-4f96-a818-7f19c099506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799629624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2799629624
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1018198834
Short name T587
Test name
Test status
Simulation time 224446278270 ps
CPU time 1344.15 seconds
Started Feb 21 02:13:08 PM PST 24
Finished Feb 21 02:35:33 PM PST 24
Peak memory 207860 kb
Host smart-f422d6bd-b7c5-4d96-adfd-bd20893ea8d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018198834 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1018198834
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1612493558
Short name T212
Test name
Test status
Simulation time 28662528 ps
CPU time 1.06 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:13:13 PM PST 24
Peak memory 197172 kb
Host smart-3a78ff11-f22a-4c65-8713-1311a33b762f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612493558 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1612493558
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1100494407
Short name T240
Test name
Test status
Simulation time 4627188154 ps
CPU time 9.49 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:13:22 PM PST 24
Peak memory 199696 kb
Host smart-accecb1e-b5ce-4e18-9577-16e24e358c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100494407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1100494407
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3130451676
Short name T243
Test name
Test status
Simulation time 14215198 ps
CPU time 0.56 seconds
Started Feb 21 02:13:09 PM PST 24
Finished Feb 21 02:13:11 PM PST 24
Peak memory 193700 kb
Host smart-b8a48441-fd7f-4a9e-b8d7-8e3280d2b2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130451676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3130451676
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3794785385
Short name T311
Test name
Test status
Simulation time 3606515730 ps
CPU time 29.81 seconds
Started Feb 21 02:13:14 PM PST 24
Finished Feb 21 02:13:45 PM PST 24
Peak memory 216040 kb
Host smart-475ace53-a43f-4132-a0ca-575e31b92781
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794785385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3794785385
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3673844845
Short name T295
Test name
Test status
Simulation time 1989244047 ps
CPU time 27.7 seconds
Started Feb 21 02:13:16 PM PST 24
Finished Feb 21 02:13:45 PM PST 24
Peak memory 199324 kb
Host smart-8f32f013-1cc7-4942-bafd-474e3334e4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673844845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3673844845
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2066845981
Short name T114
Test name
Test status
Simulation time 7338453233 ps
CPU time 90.82 seconds
Started Feb 21 02:13:10 PM PST 24
Finished Feb 21 02:14:42 PM PST 24
Peak memory 199588 kb
Host smart-9058f8ab-2b16-446b-b8b9-98725d0ffd01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066845981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2066845981
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.694532685
Short name T584
Test name
Test status
Simulation time 16898889765 ps
CPU time 58.45 seconds
Started Feb 21 02:13:23 PM PST 24
Finished Feb 21 02:14:22 PM PST 24
Peak memory 199712 kb
Host smart-0cf23215-f716-4387-948c-b8d7d6932d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694532685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.694532685
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2226671866
Short name T180
Test name
Test status
Simulation time 560375306 ps
CPU time 31.43 seconds
Started Feb 21 02:13:16 PM PST 24
Finished Feb 21 02:13:48 PM PST 24
Peak memory 199488 kb
Host smart-7d23c39d-fd92-427d-be2a-a81d1315e3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226671866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2226671866
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2563358673
Short name T416
Test name
Test status
Simulation time 53924261 ps
CPU time 1.54 seconds
Started Feb 21 02:13:10 PM PST 24
Finished Feb 21 02:13:12 PM PST 24
Peak memory 199592 kb
Host smart-5118f264-cb7e-4668-a741-123bfcafaca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563358673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2563358673
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2995709977
Short name T76
Test name
Test status
Simulation time 66960135528 ps
CPU time 212.97 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:16:44 PM PST 24
Peak memory 199652 kb
Host smart-a9f38809-a89f-4493-b1e7-4c62448db19f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995709977 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2995709977
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2319469607
Short name T208
Test name
Test status
Simulation time 279109931 ps
CPU time 1.25 seconds
Started Feb 21 02:13:10 PM PST 24
Finished Feb 21 02:13:12 PM PST 24
Peak memory 198524 kb
Host smart-f900644a-edcb-40c0-a3b1-350938501a29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319469607 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2319469607
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.2050843120
Short name T307
Test name
Test status
Simulation time 39450740228 ps
CPU time 452.07 seconds
Started Feb 21 02:13:11 PM PST 24
Finished Feb 21 02:20:44 PM PST 24
Peak memory 199780 kb
Host smart-ce59c258-0625-421e-9edb-4a6ba70e7c1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050843120 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_sha_vectors.2050843120
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.4070297281
Short name T408
Test name
Test status
Simulation time 658932051 ps
CPU time 29.82 seconds
Started Feb 21 02:13:12 PM PST 24
Finished Feb 21 02:13:42 PM PST 24
Peak memory 199576 kb
Host smart-40cae8bc-f125-4a5c-a3f0-2fd4f8498739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070297281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.4070297281
Directory /workspace/9.hmac_wipe_secret/latest
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