Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13516739	1			T1	434		T2	246		T3	3621
all_values[1]	13516739	1			T1	434		T2	246		T3	3621
all_values[2]	13516739	1			T1	434		T2	246		T3	3621

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123088

1

T1

4

T10

4

T17

440

auto[1]

40427129

1

T1

1298

T2

738

T3

10863

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28462421

1

T1

1060

T2

534

T3

9611

auto[1]

12087796

1

T1

242

T2

204

T3

1252

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	54247	1			T1	2		T17	438		T12	1
all_values[0]	auto[0]	auto[1]	438	1			T1	2		T17	2		T12	2
all_values[0]	auto[1]	auto[0]	13416491	1			T1	385		T2	191		T3	3608
all_values[0]	auto[1]	auto[1]	45563	1			T1	45		T2	55		T3	13
all_values[1]	auto[0]	auto[0]	22414	1			T38	8		T4	50		T79	3
all_values[1]	auto[0]	auto[1]	14340	1			T38	2		T4	222		T79	3
all_values[1]	auto[1]	auto[0]	7029688	1			T1	239		T2	97		T3	2382
all_values[1]	auto[1]	auto[1]	6450297	1			T1	195		T2	149		T3	1239
all_values[2]	auto[0]	auto[0]	21838	1			T10	4		T18	11		T48	516
all_values[2]	auto[0]	auto[1]	9811	1			T4	2		T6	5		T33	162
all_values[2]	auto[1]	auto[0]	7917743	1			T1	434		T2	246		T3	3621
all_values[2]	auto[1]	auto[1]	5567347	1			T7	47		T8	1572		T9	41797