Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6717705

1

T1

11065

T2

4208

T3

1736

auto[1]

2393071

1

T1

10198

T2

3186

T3

1829

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2414206

1

T1

9757

T2

4824

T3

820

auto[1]

6696570

1

T1

11506

T2

2570

T3

2745

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6032737

1

T1

9578

T2

4332

T3

1062

auto[1]

3078039

1

T1

11685

T2

3062

T3

2503

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5951441	1			T1	252		T2	6513		T3	1217
fifo_depth[1]	418822	1			T1	93		T2	322		T3	253
fifo_depth[2]	340697	1			T1	164		T2	250		T3	261
fifo_depth[3]	275517	1			T1	217		T2	92		T3	255
fifo_depth[4]	262802	1			T1	510		T2	161		T3	244
fifo_depth[5]	222715	1			T1	459		T2	31		T3	252
fifo_depth[6]	229386	1			T1	677		T2	22		T3	258
fifo_depth[7]	193770	1			T1	655		T2	1		T3	237
fifo_depth[8]	232334	1			T1	2885		T2	2		T3	204
fifo_depth[9]	136581	1			T1	1076		T3	144		T23	74
fifo_depth[10]	137219	1			T1	1792		T3	112		T10	1
fifo_depth[11]	83151	1			T1	1171		T3	67		T10	2
fifo_depth[12]	144238	1			T1	2874		T3	38		T23	16
fifo_depth[13]	63923	1			T1	1071		T3	16		T23	6
fifo_depth[14]	103076	1			T1	1766		T3	5		T10	1
fifo_depth[15]	57870	1			T1	927		T3	1		T23	1
fifo_depth[16]	257234	1			T1	4674		T3	1		T10	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3159335

1

T1

21011

T2

881

T3

2348

auto[1]

5951441

1

T1

252

T2

6513

T3

1217

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8853542

1

T1

16589

T2

7394

T3

3564

auto[1]

257234

1

T1

4674

T3

1

T10

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

224454

1

T1

1631

T2

240

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

227902

1

T1

1840

T2

38

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

953959

1

T1

2627

T2

10

T3

293

auto[0]

auto[0]

auto[1]

auto[1]

198922

1

T1

3385

T2

159

T3

372

auto[0]

auto[1]

auto[0]

auto[0]

373282

1

T1

3279

T2

102

T3

202

auto[0]

auto[1]

auto[0]

auto[1]

401837

1

T1

2840

T2

78

T3

324

auto[0]

auto[1]

auto[1]

auto[0]

406457

1

T1

3349

T2

80

T3

621

auto[0]

auto[1]

auto[1]

auto[1]

372522

1

T1

2060

T2

174

T3

536

auto[1]

auto[0]

auto[0]

auto[0]

204530

1

T1

20

T2

2748

T3

12

auto[1]

auto[0]

auto[0]

auto[1]

211854

1

T1

29

T2

251

T3

8

auto[1]

auto[0]

auto[1]

auto[0]

3787909

1

T1

19

T2

123

T3

192

auto[1]

auto[0]

auto[1]

auto[1]

223207

1

T1

27

T2

763

T3

185

auto[1]

auto[1]

auto[0]

auto[0]

389448

1

T1

104

T2

419

T3

113

auto[1]

auto[1]

auto[0]

auto[1]

380899

1

T1

14

T2

948

T3

161

auto[1]

auto[1]

auto[1]

auto[0]

377666

1

T1

36

T2

486

T3

303

auto[1]

auto[1]

auto[1]

auto[1]

375928

1

T1

3

T2

775

T3

243

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

399070

1

T1

1124

T2

2988

T3

12

auto[0]

auto[0]

auto[0]

auto[1]

405241

1

T1

1620

T2

289

T3

8

auto[0]

auto[0]

auto[1]

auto[0]

4709282

1

T1

2331

T2

133

T3

485

auto[0]

auto[0]

auto[1]

auto[1]

389262

1

T1

2732

T2

922

T3

557

auto[0]

auto[1]

auto[0]

auto[0]

731119

1

T1

3162

T2

521

T3

315

auto[0]

auto[1]

auto[0]

auto[1]

753867

1

T1

2576

T2

1026

T3

485

auto[0]

auto[1]

auto[1]

auto[0]

744175

1

T1

1802

T2

566

T3

924

auto[0]

auto[1]

auto[1]

auto[1]

721526

1

T1

1242

T2

949

T3

778

auto[1]

auto[0]

auto[0]

auto[0]

29914

1

T1

527

T38

967

T12

2

auto[1]

auto[0]

auto[0]

auto[1]

34515

1

T1

249

T38

123

T102

2314

auto[1]

auto[0]

auto[1]

auto[0]

32586

1

T1

315

T23

1

T38

300

auto[1]

auto[0]

auto[1]

auto[1]

32867

1

T1

680

T10

2

T38

1130

auto[1]

auto[1]

auto[0]

auto[0]

31611

1

T1

221

T38

2013

T12

4

auto[1]

auto[1]

auto[0]

auto[1]

28869

1

T1

278

T38

755

T42

2

auto[1]

auto[1]

auto[1]

auto[0]

39948

1

T1

1583

T38

1911

T12

1

auto[1]

auto[1]

auto[1]

auto[1]

26924

1

T1

821

T3

1

T38

1082

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	204530	1			T1	20		T2	2748		T3	12
fifo_depth[0]	auto[0]	auto[0]	auto[1]	211854	1			T1	29		T2	251		T3	8
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3787909	1			T1	19		T2	123		T3	192
fifo_depth[0]	auto[0]	auto[1]	auto[1]	223207	1			T1	27		T2	763		T3	185
fifo_depth[0]	auto[1]	auto[0]	auto[0]	389448	1			T1	104		T2	419		T3	113
fifo_depth[0]	auto[1]	auto[0]	auto[1]	380899	1			T1	14		T2	948		T3	161
fifo_depth[0]	auto[1]	auto[1]	auto[0]	377666	1			T1	36		T2	486		T3	303
fifo_depth[0]	auto[1]	auto[1]	auto[1]	375928	1			T1	3		T2	775		T3	243
fifo_depth[1]	auto[0]	auto[0]	auto[0]	16471	1			T2	147		T17	47		T38	214
fifo_depth[1]	auto[0]	auto[0]	auto[1]	17050	1			T1	4		T2	9		T17	34
fifo_depth[1]	auto[0]	auto[1]	auto[0]	207765	1			T1	10		T3	32		T23	121
fifo_depth[1]	auto[0]	auto[1]	auto[1]	16731	1			T1	10		T2	43		T3	41
fifo_depth[1]	auto[1]	auto[0]	auto[0]	39590	1			T1	41		T2	20		T3	30
fifo_depth[1]	auto[1]	auto[0]	auto[1]	42007	1			T1	9		T2	36		T3	31
fifo_depth[1]	auto[1]	auto[1]	auto[0]	39689	1			T1	19		T2	14		T3	65
fifo_depth[1]	auto[1]	auto[1]	auto[1]	39519	1			T2	53		T3	54		T16	2
fifo_depth[2]	auto[0]	auto[0]	auto[0]	15112	1			T1	11		T2	57		T17	36
fifo_depth[2]	auto[0]	auto[0]	auto[1]	14580	1			T1	16		T2	14		T17	23
fifo_depth[2]	auto[0]	auto[1]	auto[0]	151867	1			T1	9		T2	1		T3	32
fifo_depth[2]	auto[0]	auto[1]	auto[1]	14062	1			T1	11		T2	32		T3	45
fifo_depth[2]	auto[1]	auto[0]	auto[0]	35753	1			T1	59		T2	37		T3	24
fifo_depth[2]	auto[1]	auto[0]	auto[1]	38431	1			T1	24		T2	9		T3	43
fifo_depth[2]	auto[1]	auto[1]	auto[0]	35625	1			T1	19		T2	38		T3	66
fifo_depth[2]	auto[1]	auto[1]	auto[1]	35267	1			T1	15		T2	62		T3	51
fifo_depth[3]	auto[0]	auto[0]	auto[0]	12815	1			T2	8		T17	21		T38	270
fifo_depth[3]	auto[0]	auto[0]	auto[1]	12335	1			T1	5		T2	4		T17	7
fifo_depth[3]	auto[0]	auto[1]	auto[0]	112492	1			T1	40		T2	1		T3	28
fifo_depth[3]	auto[0]	auto[1]	auto[1]	11483	1			T1	42		T2	31		T3	39
fifo_depth[3]	auto[1]	auto[0]	auto[0]	30449	1			T1	41		T2	15		T3	23
fifo_depth[3]	auto[1]	auto[0]	auto[1]	33857	1			T1	63		T2	7		T3	35
fifo_depth[3]	auto[1]	auto[1]	auto[0]	31272	1			T1	26		T2	5		T3	75
fifo_depth[3]	auto[1]	auto[1]	auto[1]	30814	1			T2	21		T3	55		T17	17
fifo_depth[4]	auto[0]	auto[0]	auto[0]	15648	1			T1	28		T2	20		T17	5
fifo_depth[4]	auto[0]	auto[0]	auto[1]	14850	1			T1	30		T2	9		T17	4
fifo_depth[4]	auto[0]	auto[1]	auto[0]	86196	1			T1	37		T2	8		T3	26
fifo_depth[4]	auto[0]	auto[1]	auto[1]	13690	1			T1	67		T2	36		T3	34
fifo_depth[4]	auto[1]	auto[0]	auto[0]	32381	1			T1	52		T2	23		T3	19
fifo_depth[4]	auto[1]	auto[0]	auto[1]	34366	1			T1	158		T2	26		T3	33
fifo_depth[4]	auto[1]	auto[1]	auto[0]	33345	1			T1	72		T2	18		T3	75
fifo_depth[4]	auto[1]	auto[1]	auto[1]	32326	1			T1	66		T2	21		T3	57
fifo_depth[5]	auto[0]	auto[0]	auto[0]	12940	1			T1	33		T2	2		T17	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	11788	1			T1	48		T2	2		T17	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	70295	1			T1	38		T3	34		T23	131
fifo_depth[5]	auto[0]	auto[1]	auto[1]	10452	1			T1	70		T2	12		T3	44
fifo_depth[5]	auto[1]	auto[0]	auto[0]	27922	1			T1	70		T2	3		T3	20
fifo_depth[5]	auto[1]	auto[0]	auto[1]	31240	1			T1	137		T3	37		T38	240
fifo_depth[5]	auto[1]	auto[1]	auto[0]	29260	1			T1	42		T2	1		T3	52
fifo_depth[5]	auto[1]	auto[1]	auto[1]	28818	1			T1	21		T2	11		T3	65
fifo_depth[6]	auto[0]	auto[0]	auto[0]	14485	1			T1	39		T2	5		T10	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	14178	1			T1	106		T17	2		T38	23
fifo_depth[6]	auto[0]	auto[1]	auto[0]	64020	1			T1	32		T3	38		T23	131
fifo_depth[6]	auto[0]	auto[1]	auto[1]	12179	1			T1	146		T2	5		T3	32
fifo_depth[6]	auto[1]	auto[0]	auto[0]	29784	1			T1	103		T2	3		T3	20
fifo_depth[6]	auto[1]	auto[0]	auto[1]	32489	1			T1	110		T3	39		T38	251
fifo_depth[6]	auto[1]	auto[1]	auto[0]	31583	1			T1	56		T2	3		T3	70
fifo_depth[6]	auto[1]	auto[1]	auto[1]	30668	1			T1	85		T2	6		T3	59
fifo_depth[7]	auto[0]	auto[0]	auto[0]	12171	1			T1	26		T38	500		T12	169
fifo_depth[7]	auto[0]	auto[0]	auto[1]	11872	1			T1	91		T38	22		T12	47
fifo_depth[7]	auto[0]	auto[1]	auto[0]	51175	1			T1	55		T3	33		T23	124
fifo_depth[7]	auto[0]	auto[1]	auto[1]	9843	1			T1	154		T3	39		T38	142
fifo_depth[7]	auto[1]	auto[0]	auto[0]	25747	1			T1	119		T2	1		T3	24
fifo_depth[7]	auto[1]	auto[0]	auto[1]	28880	1			T1	150		T3	31		T38	246
fifo_depth[7]	auto[1]	auto[1]	auto[0]	27235	1			T1	60		T3	58		T38	156
fifo_depth[7]	auto[1]	auto[1]	auto[1]	26847	1			T3	52		T38	125		T12	87
fifo_depth[8]	auto[0]	auto[0]	auto[0]	20279	1			T1	263		T2	1		T38	527
fifo_depth[8]	auto[0]	auto[0]	auto[1]	20631	1			T1	351		T38	244		T12	45
fifo_depth[8]	auto[0]	auto[1]	auto[0]	50232	1			T1	466		T3	29		T23	120
fifo_depth[8]	auto[0]	auto[1]	auto[1]	17949	1			T1	528		T3	30		T38	154
fifo_depth[8]	auto[1]	auto[0]	auto[0]	29101	1			T1	556		T3	12		T38	248
fifo_depth[8]	auto[1]	auto[0]	auto[1]	31909	1			T1	429		T3	20		T38	276
fifo_depth[8]	auto[1]	auto[1]	auto[0]	32747	1			T1	211		T2	1		T3	61
fifo_depth[8]	auto[1]	auto[1]	auto[1]	29486	1			T1	81		T3	52		T38	269
fifo_depth[9]	auto[0]	auto[0]	auto[0]	9793	1			T1	34		T38	432		T12	101
fifo_depth[9]	auto[0]	auto[0]	auto[1]	9982	1			T1	65		T38	18		T12	40
fifo_depth[9]	auto[0]	auto[1]	auto[0]	29797	1			T1	131		T3	17		T23	74
fifo_depth[9]	auto[0]	auto[1]	auto[1]	7549	1			T1	148		T3	25		T38	108
fifo_depth[9]	auto[1]	auto[0]	auto[0]	18779	1			T1	366		T3	13		T38	126
fifo_depth[9]	auto[1]	auto[0]	auto[1]	21468	1			T1	120		T3	19		T38	226
fifo_depth[9]	auto[1]	auto[1]	auto[0]	20417	1			T1	177		T3	43		T38	425
fifo_depth[9]	auto[1]	auto[1]	auto[1]	18796	1			T1	35		T3	27		T38	127
fifo_depth[10]	auto[0]	auto[0]	auto[0]	13759	1			T1	196		T38	415		T12	65
fifo_depth[10]	auto[0]	auto[0]	auto[1]	12596	1			T1	260		T11	1		T38	103
fifo_depth[10]	auto[0]	auto[1]	auto[0]	25646	1			T1	256		T3	13		T23	48
fifo_depth[10]	auto[0]	auto[1]	auto[1]	10751	1			T1	237		T3	24		T38	102
fifo_depth[10]	auto[1]	auto[0]	auto[0]	17827	1			T1	421		T3	7		T10	1
fifo_depth[10]	auto[1]	auto[0]	auto[1]	19090	1			T1	206		T3	14		T38	226
fifo_depth[10]	auto[1]	auto[1]	auto[0]	20000	1			T1	115		T3	28		T38	386
fifo_depth[10]	auto[1]	auto[1]	auto[1]	17550	1			T1	101		T3	26		T38	257
fifo_depth[11]	auto[0]	auto[0]	auto[0]	7827	1			T1	39		T38	321		T12	36
fifo_depth[11]	auto[0]	auto[0]	auto[1]	8476	1			T1	59		T38	17		T12	13
fifo_depth[11]	auto[0]	auto[1]	auto[0]	15795	1			T1	224		T3	5		T23	32
fifo_depth[11]	auto[0]	auto[1]	auto[1]	6250	1			T1	226		T3	11		T10	1
fifo_depth[11]	auto[1]	auto[0]	auto[0]	10233	1			T1	248		T3	5		T38	118
fifo_depth[11]	auto[1]	auto[0]	auto[1]	12266	1			T1	204		T3	9		T38	178
fifo_depth[11]	auto[1]	auto[1]	auto[0]	12081	1			T1	143		T3	19		T38	298
fifo_depth[11]	auto[1]	auto[1]	auto[1]	10223	1			T1	28		T3	18		T10	1
fifo_depth[12]	auto[0]	auto[0]	auto[0]	17164	1			T1	210		T38	264		T12	14
fifo_depth[12]	auto[0]	auto[0]	auto[1]	17993	1			T1	230		T38	195		T12	6
fifo_depth[12]	auto[0]	auto[1]	auto[0]	22799	1			T1	503		T3	4		T23	16
fifo_depth[12]	auto[0]	auto[1]	auto[1]	14264	1			T1	525		T3	6		T38	137
fifo_depth[12]	auto[1]	auto[0]	auto[0]	17299	1			T1	322		T3	3		T38	139
fifo_depth[12]	auto[1]	auto[0]	auto[1]	17758	1			T1	473		T3	7		T38	159
fifo_depth[12]	auto[1]	auto[1]	auto[0]	19716	1			T1	213		T3	6		T38	330
fifo_depth[12]	auto[1]	auto[1]	auto[1]	17245	1			T1	398		T3	12		T38	509
fifo_depth[13]	auto[0]	auto[0]	auto[0]	7074	1			T1	33		T38	224		T12	8
fifo_depth[13]	auto[0]	auto[0]	auto[1]	8050	1			T1	64		T38	12		T12	3
fifo_depth[13]	auto[0]	auto[1]	auto[0]	10508	1			T1	194		T3	2		T23	6
fifo_depth[13]	auto[0]	auto[1]	auto[1]	5928	1			T1	201		T3	1		T38	114
fifo_depth[13]	auto[1]	auto[0]	auto[0]	6763	1			T1	202		T3	2		T38	155
fifo_depth[13]	auto[1]	auto[0]	auto[1]	8739	1			T1	190		T3	4		T38	174
fifo_depth[13]	auto[1]	auto[1]	auto[0]	9848	1			T1	141		T3	2		T38	252
fifo_depth[13]	auto[1]	auto[1]	auto[1]	7013	1			T1	46		T3	5		T38	154
fifo_depth[14]	auto[0]	auto[0]	auto[0]	12703	1			T1	168		T38	224		T12	1
fifo_depth[14]	auto[0]	auto[0]	auto[1]	11830	1			T1	230		T10	1		T38	79
fifo_depth[14]	auto[0]	auto[1]	auto[0]	14402	1			T1	174		T23	1		T38	315
fifo_depth[14]	auto[0]	auto[1]	auto[1]	9571	1			T1	184		T38	80		T12	3
fifo_depth[14]	auto[1]	auto[0]	auto[0]	13593	1			T1	280		T38	341		T12	4
fifo_depth[14]	auto[1]	auto[0]	auto[1]	12724	1			T1	172		T3	2		T38	140
fifo_depth[14]	auto[1]	auto[1]	auto[0]	14662	1			T1	234		T3	1		T38	302
fifo_depth[14]	auto[1]	auto[1]	auto[1]	13591	1			T1	324		T3	2		T38	874
fifo_depth[15]	auto[0]	auto[0]	auto[0]	6299	1			T1	24		T38	168		T102	191
fifo_depth[15]	auto[0]	auto[0]	auto[1]	7176	1			T1	32		T38	7		T12	2
fifo_depth[15]	auto[0]	auto[1]	auto[0]	8384	1			T1	143		T23	1		T38	186
fifo_depth[15]	auto[0]	auto[1]	auto[1]	5353	1			T1	156		T3	1		T38	80
fifo_depth[15]	auto[1]	auto[0]	auto[0]	6450	1			T1	178		T38	345		T42	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	7744	1			T1	117		T38	126		T42	2
fifo_depth[15]	auto[1]	auto[1]	auto[0]	9029	1			T1	238		T38	228		T42	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	7435	1			T1	39		T38	545		T12	3
fifo_depth[16]	auto[0]	auto[0]	auto[0]	29914	1			T1	527		T38	967		T12	2
fifo_depth[16]	auto[0]	auto[0]	auto[1]	34515	1			T1	249		T38	123		T102	2314
fifo_depth[16]	auto[0]	auto[1]	auto[0]	32586	1			T1	315		T23	1		T38	300
fifo_depth[16]	auto[0]	auto[1]	auto[1]	32867	1			T1	680		T10	2		T38	1130
fifo_depth[16]	auto[1]	auto[0]	auto[0]	31611	1			T1	221		T38	2013		T12	4
fifo_depth[16]	auto[1]	auto[0]	auto[1]	28869	1			T1	278		T38	755		T42	2
fifo_depth[16]	auto[1]	auto[1]	auto[0]	39948	1			T1	1583		T38	1911		T12	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	26924	1			T1	821		T3	1		T38	1082