Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13516739	1			T1	434		T2	246		T3	3621
all_pins[1]	13516739	1			T1	434		T2	246		T3	3621
all_pins[2]	13516739	1			T1	434		T2	246		T3	3621

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	28428447	1			T1	1059		T2	533		T3	9585
values[0x1]	12121770	1			T1	243		T2	205		T3	1278
transitions[0x0=>0x1]	10498140	1			T1	207		T2	166		T3	1266
transitions[0x1=>0x0]	10498156	1			T1	207		T2	167		T3	1266

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13470230	1			T1	386		T2	190		T3	3607
all_pins[0]	values[0x1]	46509	1			T1	48		T2	56		T3	14
all_pins[0]	transitions[0x0=>0x1]	46465	1			T1	48		T2	55		T3	14
all_pins[0]	transitions[0x1=>0x0]	5567319	1			T7	47		T8	1572		T9	41797
all_pins[1]	values[0x0]	7008825	1			T1	239		T2	97		T3	2357
all_pins[1]	values[0x1]	6507914	1			T1	195		T2	149		T3	1264
all_pins[1]	transitions[0x0=>0x1]	6471691	1			T1	159		T2	111		T3	1252
all_pins[1]	transitions[0x1=>0x0]	10286	1			T1	12		T2	18		T3	2
all_pins[2]	values[0x0]	7949392	1			T1	434		T2	246		T3	3621
all_pins[2]	values[0x1]	5567347	1			T7	47		T8	1572		T9	41797
all_pins[2]	transitions[0x0=>0x1]	3979984	1			T7	32		T8	1240		T9	26874
all_pins[2]	transitions[0x1=>0x0]	4920551	1			T1	195		T2	149		T3	1264