Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 636 1 T4 7 T6 17 T19 11
all_values[1] 636 1 T4 7 T6 17 T19 11
all_values[2] 636 1 T4 7 T6 17 T19 11


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 978 1 T4 13 T6 29 T19 16
auto[1] 930 1 T4 8 T6 22 T19 17


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 711 1 T4 7 T6 20 T19 10
auto[1] 1197 1 T4 14 T6 31 T19 23


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1096 1 T4 10 T6 29 T19 17
auto[1] 812 1 T4 11 T6 22 T19 16


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 141 1 T4 1 T6 4 T67 2
all_values[0] auto[0] auto[0] auto[1] 54 1 T6 2 T19 2 T67 2
all_values[0] auto[0] auto[1] auto[0] 98 1 T6 2 T19 3 T70 2
all_values[0] auto[0] auto[1] auto[1] 66 1 T4 3 T6 1 T19 1
all_values[0] auto[1] auto[0] auto[1] 140 1 T4 1 T6 4 T19 2
all_values[0] auto[1] auto[1] auto[1] 137 1 T4 2 T6 4 T19 3
all_values[1] auto[0] auto[0] auto[0] 111 1 T4 3 T6 4 T19 1
all_values[1] auto[0] auto[0] auto[1] 80 1 T6 2 T19 2 T116 3
all_values[1] auto[0] auto[1] auto[0] 91 1 T4 1 T19 2 T67 4
all_values[1] auto[0] auto[1] auto[1] 76 1 T6 2 T19 1 T70 1
all_values[1] auto[1] auto[0] auto[1] 144 1 T4 1 T6 4 T19 3
all_values[1] auto[1] auto[1] auto[1] 134 1 T4 2 T6 5 T19 2
all_values[2] auto[0] auto[0] auto[0] 132 1 T4 2 T6 5 T19 4
all_values[2] auto[0] auto[0] auto[1] 48 1 T6 1 T70 1 T116 1
all_values[2] auto[0] auto[1] auto[0] 138 1 T6 5 T70 3 T116 5
all_values[2] auto[0] auto[1] auto[1] 61 1 T6 1 T19 1 T67 3
all_values[2] auto[1] auto[0] auto[1] 128 1 T4 5 T6 3 T19 2
all_values[2] auto[1] auto[1] auto[1] 129 1 T6 2 T19 4 T67 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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