Summary for Variable digest_swap
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for digest_swap
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34116 |
1 |
|
|
T1 |
18 |
|
T2 |
24 |
|
T3 |
6 |
auto[1] |
10888 |
1 |
|
|
T1 |
20 |
|
T2 |
23 |
|
T3 |
6 |
Summary for Variable endian_swap
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for endian_swap
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10831 |
1 |
|
|
T1 |
20 |
|
T2 |
26 |
|
T3 |
6 |
auto[1] |
34173 |
1 |
|
|
T1 |
18 |
|
T2 |
21 |
|
T3 |
6 |
Summary for Variable hmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for hmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
31953 |
1 |
|
|
T1 |
20 |
|
T2 |
21 |
|
T3 |
5 |
auto[1] |
13051 |
1 |
|
|
T1 |
18 |
|
T2 |
26 |
|
T3 |
7 |
Summary for Cross cfg_cross
Samples crossed: hmac_en endian_swap digest_swap
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cfg_cross
Bins
hmac_en | endian_swap | digest_swap | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
2266 |
1 |
|
|
T1 |
4 |
|
T2 |
7 |
|
T3 |
1 |
auto[0] |
auto[0] |
auto[1] |
2353 |
1 |
|
|
T1 |
6 |
|
T2 |
5 |
|
T3 |
1 |
auto[0] |
auto[1] |
auto[0] |
25030 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T3 |
1 |
auto[0] |
auto[1] |
auto[1] |
2304 |
1 |
|
|
T1 |
6 |
|
T2 |
6 |
|
T3 |
2 |
auto[1] |
auto[0] |
auto[0] |
3097 |
1 |
|
|
T1 |
5 |
|
T2 |
8 |
|
T3 |
3 |
auto[1] |
auto[0] |
auto[1] |
3115 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T3 |
1 |
auto[1] |
auto[1] |
auto[0] |
3723 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T3 |
1 |
auto[1] |
auto[1] |
auto[1] |
3116 |
1 |
|
|
T1 |
3 |
|
T2 |
6 |
|
T3 |
2 |