Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.73 98.36 96.63 100.00 87.50 95.83 99.49 99.31


Total test records in report: 726
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T75 /workspace/coverage/default/26.hmac_stress_all.2616217615 Mar 03 02:37:34 PM PST 24 Mar 03 03:06:27 PM PST 24 139317887370 ps
T540 /workspace/coverage/default/44.hmac_smoke.3274020041 Mar 03 02:38:42 PM PST 24 Mar 03 02:38:44 PM PST 24 38064559 ps
T541 /workspace/coverage/default/39.hmac_long_msg.1634621815 Mar 03 02:38:20 PM PST 24 Mar 03 02:39:42 PM PST 24 6093596148 ps
T542 /workspace/coverage/default/34.hmac_error.35216292 Mar 03 02:38:07 PM PST 24 Mar 03 02:39:02 PM PST 24 4034145541 ps
T543 /workspace/coverage/default/28.hmac_alert_test.3989115453 Mar 03 02:37:42 PM PST 24 Mar 03 02:37:44 PM PST 24 34019611 ps
T544 /workspace/coverage/default/33.hmac_alert_test.4058315199 Mar 03 02:38:00 PM PST 24 Mar 03 02:38:01 PM PST 24 13926365 ps
T545 /workspace/coverage/default/13.hmac_smoke.1997598674 Mar 03 02:37:04 PM PST 24 Mar 03 02:37:07 PM PST 24 244934614 ps
T546 /workspace/coverage/default/13.hmac_back_pressure.4239475188 Mar 03 02:37:06 PM PST 24 Mar 03 02:37:38 PM PST 24 913168489 ps
T547 /workspace/coverage/default/6.hmac_error.3769732338 Mar 03 02:37:03 PM PST 24 Mar 03 02:38:10 PM PST 24 6057068125 ps
T548 /workspace/coverage/default/15.hmac_test_sha_vectors.3163798952 Mar 03 02:37:12 PM PST 24 Mar 03 02:43:43 PM PST 24 7568958576 ps
T549 /workspace/coverage/default/8.hmac_test_sha_vectors.421948487 Mar 03 02:37:01 PM PST 24 Mar 03 02:44:19 PM PST 24 133512838997 ps
T550 /workspace/coverage/default/25.hmac_alert_test.3370088615 Mar 03 02:37:38 PM PST 24 Mar 03 02:37:40 PM PST 24 42631210 ps
T551 /workspace/coverage/default/38.hmac_datapath_stress.799331692 Mar 03 02:38:18 PM PST 24 Mar 03 02:39:08 PM PST 24 5306582814 ps
T552 /workspace/coverage/default/7.hmac_datapath_stress.3540043832 Mar 03 02:36:55 PM PST 24 Mar 03 02:38:16 PM PST 24 3363938377 ps
T553 /workspace/coverage/default/8.hmac_back_pressure.3857397281 Mar 03 02:36:59 PM PST 24 Mar 03 02:37:13 PM PST 24 475630568 ps
T554 /workspace/coverage/default/37.hmac_alert_test.555245132 Mar 03 02:38:15 PM PST 24 Mar 03 02:38:19 PM PST 24 35207229 ps
T129 /workspace/coverage/default/33.hmac_stress_all.3885921914 Mar 03 02:38:09 PM PST 24 Mar 03 03:04:15 PM PST 24 129367412550 ps
T555 /workspace/coverage/default/46.hmac_alert_test.2866220520 Mar 03 02:38:52 PM PST 24 Mar 03 02:38:53 PM PST 24 15599580 ps
T556 /workspace/coverage/default/19.hmac_error.337371988 Mar 03 02:37:27 PM PST 24 Mar 03 02:39:05 PM PST 24 7168481866 ps
T557 /workspace/coverage/default/44.hmac_datapath_stress.68282903 Mar 03 02:38:42 PM PST 24 Mar 03 02:40:10 PM PST 24 1705075826 ps
T558 /workspace/coverage/default/7.hmac_burst_wr.3000692621 Mar 03 02:36:59 PM PST 24 Mar 03 02:37:05 PM PST 24 2640882868 ps
T559 /workspace/coverage/default/34.hmac_burst_wr.3875399569 Mar 03 02:38:08 PM PST 24 Mar 03 02:38:32 PM PST 24 483383836 ps
T560 /workspace/coverage/default/31.hmac_alert_test.197575949 Mar 03 02:37:54 PM PST 24 Mar 03 02:37:55 PM PST 24 11871932 ps
T561 /workspace/coverage/default/12.hmac_long_msg.3296322330 Mar 03 02:37:03 PM PST 24 Mar 03 02:38:44 PM PST 24 1861958253 ps
T562 /workspace/coverage/default/24.hmac_error.642060979 Mar 03 02:37:35 PM PST 24 Mar 03 02:39:14 PM PST 24 7396938587 ps
T128 /workspace/coverage/default/10.hmac_burst_wr.704015627 Mar 03 02:36:59 PM PST 24 Mar 03 02:37:23 PM PST 24 2523206043 ps
T563 /workspace/coverage/default/13.hmac_alert_test.1583157360 Mar 03 02:37:12 PM PST 24 Mar 03 02:37:13 PM PST 24 67514188 ps
T564 /workspace/coverage/default/41.hmac_alert_test.4149292570 Mar 03 02:38:36 PM PST 24 Mar 03 02:38:36 PM PST 24 20504886 ps
T565 /workspace/coverage/default/7.hmac_test_hmac_vectors.2831889200 Mar 03 02:36:58 PM PST 24 Mar 03 02:36:59 PM PST 24 57585389 ps
T566 /workspace/coverage/default/21.hmac_smoke.1433948339 Mar 03 02:37:26 PM PST 24 Mar 03 02:37:28 PM PST 24 55032660 ps
T567 /workspace/coverage/default/1.hmac_alert_test.3990295916 Mar 03 02:36:50 PM PST 24 Mar 03 02:36:51 PM PST 24 20114535 ps
T568 /workspace/coverage/default/49.hmac_burst_wr.4236769642 Mar 03 02:38:57 PM PST 24 Mar 03 02:39:45 PM PST 24 1001537156 ps
T569 /workspace/coverage/default/31.hmac_stress_all.1512549922 Mar 03 02:37:54 PM PST 24 Mar 03 02:53:08 PM PST 24 25138514340 ps
T570 /workspace/coverage/default/43.hmac_stress_all.2907456013 Mar 03 02:38:41 PM PST 24 Mar 03 03:10:25 PM PST 24 108699623144 ps
T571 /workspace/coverage/default/8.hmac_datapath_stress.947349355 Mar 03 02:37:07 PM PST 24 Mar 03 02:38:16 PM PST 24 5031708314 ps
T572 /workspace/coverage/default/35.hmac_alert_test.1707181437 Mar 03 02:38:09 PM PST 24 Mar 03 02:38:11 PM PST 24 53616583 ps
T573 /workspace/coverage/default/32.hmac_alert_test.3494723708 Mar 03 02:38:09 PM PST 24 Mar 03 02:38:10 PM PST 24 14567445 ps
T574 /workspace/coverage/default/1.hmac_smoke.301592420 Mar 03 02:36:51 PM PST 24 Mar 03 02:36:56 PM PST 24 814018584 ps
T575 /workspace/coverage/default/18.hmac_back_pressure.3927524323 Mar 03 02:37:17 PM PST 24 Mar 03 02:37:22 PM PST 24 260471387 ps
T576 /workspace/coverage/default/11.hmac_long_msg.2105793033 Mar 03 02:37:05 PM PST 24 Mar 03 02:38:09 PM PST 24 10551313752 ps
T577 /workspace/coverage/default/38.hmac_test_hmac_vectors.675818056 Mar 03 02:38:20 PM PST 24 Mar 03 02:38:23 PM PST 24 150145254 ps
T578 /workspace/coverage/default/47.hmac_test_sha_vectors.3236306394 Mar 03 02:38:52 PM PST 24 Mar 03 02:46:16 PM PST 24 27296513492 ps
T579 /workspace/coverage/default/46.hmac_datapath_stress.4220078056 Mar 03 02:38:55 PM PST 24 Mar 03 02:39:37 PM PST 24 1501068540 ps
T580 /workspace/coverage/default/6.hmac_alert_test.1093320991 Mar 03 02:36:56 PM PST 24 Mar 03 02:36:57 PM PST 24 17172572 ps
T581 /workspace/coverage/default/29.hmac_back_pressure.2977819666 Mar 03 02:37:41 PM PST 24 Mar 03 02:38:40 PM PST 24 1728864583 ps
T582 /workspace/coverage/default/6.hmac_smoke.1821613754 Mar 03 02:36:55 PM PST 24 Mar 03 02:36:59 PM PST 24 536775939 ps
T583 /workspace/coverage/default/14.hmac_datapath_stress.1103295949 Mar 03 02:37:09 PM PST 24 Mar 03 02:37:18 PM PST 24 698852634 ps
T28 /workspace/coverage/default/3.hmac_sec_cm.3162555006 Mar 03 02:36:49 PM PST 24 Mar 03 02:36:50 PM PST 24 169099979 ps
T584 /workspace/coverage/default/4.hmac_alert_test.3481397886 Mar 03 02:36:58 PM PST 24 Mar 03 02:36:59 PM PST 24 43645379 ps
T585 /workspace/coverage/default/9.hmac_test_hmac_vectors.4210959572 Mar 03 02:37:01 PM PST 24 Mar 03 02:37:02 PM PST 24 110087242 ps
T586 /workspace/coverage/default/37.hmac_error.1244988096 Mar 03 02:38:13 PM PST 24 Mar 03 02:39:31 PM PST 24 2638601021 ps
T587 /workspace/coverage/default/43.hmac_datapath_stress.3397574815 Mar 03 02:38:34 PM PST 24 Mar 03 02:40:02 PM PST 24 3438387319 ps
T588 /workspace/coverage/default/23.hmac_error.2449947886 Mar 03 02:37:29 PM PST 24 Mar 03 02:40:14 PM PST 24 12339192856 ps
T589 /workspace/coverage/default/35.hmac_datapath_stress.2681532634 Mar 03 02:38:07 PM PST 24 Mar 03 02:39:05 PM PST 24 3776296332 ps
T590 /workspace/coverage/default/6.hmac_test_hmac_vectors.3234955674 Mar 03 02:36:59 PM PST 24 Mar 03 02:37:00 PM PST 24 64245763 ps
T591 /workspace/coverage/default/28.hmac_test_sha_vectors.1045092989 Mar 03 02:37:50 PM PST 24 Mar 03 02:44:35 PM PST 24 23071838078 ps
T592 /workspace/coverage/default/19.hmac_test_sha_vectors.276136305 Mar 03 02:37:25 PM PST 24 Mar 03 02:45:09 PM PST 24 26501661003 ps
T593 /workspace/coverage/default/15.hmac_stress_all.1770589046 Mar 03 02:37:14 PM PST 24 Mar 03 02:40:30 PM PST 24 48698052207 ps
T594 /workspace/coverage/default/21.hmac_wipe_secret.2010687174 Mar 03 02:37:27 PM PST 24 Mar 03 02:38:37 PM PST 24 17243516427 ps
T595 /workspace/coverage/default/16.hmac_test_sha_vectors.2870904135 Mar 03 02:37:18 PM PST 24 Mar 03 02:45:48 PM PST 24 90058272469 ps
T596 /workspace/coverage/default/11.hmac_back_pressure.1113280635 Mar 03 02:37:02 PM PST 24 Mar 03 02:37:23 PM PST 24 8779984077 ps
T60 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4261487237 Mar 03 12:33:54 PM PST 24 Mar 03 12:33:56 PM PST 24 124430863 ps
T54 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2214346785 Mar 03 12:33:39 PM PST 24 Mar 03 12:33:40 PM PST 24 15972976 ps
T55 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4183913408 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:50 PM PST 24 52712132 ps
T49 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3591949391 Mar 03 12:33:43 PM PST 24 Mar 03 12:33:44 PM PST 24 220199014 ps
T85 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3305036161 Mar 03 12:33:28 PM PST 24 Mar 03 12:33:30 PM PST 24 128408727 ps
T597 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2472870284 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:51 PM PST 24 82327959 ps
T598 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1794828558 Mar 03 12:34:08 PM PST 24 Mar 03 12:34:09 PM PST 24 21586667 ps
T599 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2016264039 Mar 03 12:33:43 PM PST 24 Mar 03 12:33:47 PM PST 24 64641103 ps
T600 /workspace/coverage/cover_reg_top/8.hmac_intr_test.111190545 Mar 03 12:33:36 PM PST 24 Mar 03 12:33:37 PM PST 24 45825881 ps
T601 /workspace/coverage/cover_reg_top/21.hmac_intr_test.171264042 Mar 03 12:33:59 PM PST 24 Mar 03 12:34:00 PM PST 24 13869621 ps
T602 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.275400062 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:52 PM PST 24 62027684 ps
T76 /workspace/coverage/cover_reg_top/19.hmac_intr_test.275728200 Mar 03 12:34:05 PM PST 24 Mar 03 12:34:07 PM PST 24 48949671 ps
T603 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3139216190 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:55 PM PST 24 45688814 ps
T604 /workspace/coverage/cover_reg_top/34.hmac_intr_test.472515057 Mar 03 12:34:08 PM PST 24 Mar 03 12:34:09 PM PST 24 46523249 ps
T605 /workspace/coverage/cover_reg_top/31.hmac_intr_test.631604892 Mar 03 12:33:51 PM PST 24 Mar 03 12:33:52 PM PST 24 50963671 ps
T606 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3641159038 Mar 03 12:33:48 PM PST 24 Mar 03 12:33:49 PM PST 24 49857829 ps
T607 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.84319513 Mar 03 12:33:35 PM PST 24 Mar 03 12:33:36 PM PST 24 23966521 ps
T608 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2359791452 Mar 03 12:33:51 PM PST 24 Mar 03 12:33:51 PM PST 24 44746812 ps
T50 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1309260992 Mar 03 12:33:39 PM PST 24 Mar 03 12:33:41 PM PST 24 48940548 ps
T77 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2729356315 Mar 03 12:33:47 PM PST 24 Mar 03 12:33:53 PM PST 24 656765830 ps
T609 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3299618248 Mar 03 12:33:39 PM PST 24 Mar 03 12:33:40 PM PST 24 22473207 ps
T610 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2326021656 Mar 03 12:34:10 PM PST 24 Mar 03 12:34:13 PM PST 24 191550960 ps
T611 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2793314890 Mar 03 12:33:19 PM PST 24 Mar 03 12:38:01 PM PST 24 156876239736 ps
T612 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1597108322 Mar 03 12:33:51 PM PST 24 Mar 03 12:33:52 PM PST 24 11697752 ps
T613 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1987201331 Mar 03 12:33:14 PM PST 24 Mar 03 12:33:18 PM PST 24 445146769 ps
T614 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3332757741 Mar 03 12:33:35 PM PST 24 Mar 03 12:33:36 PM PST 24 45317710 ps
T615 /workspace/coverage/cover_reg_top/43.hmac_intr_test.87455847 Mar 03 12:33:46 PM PST 24 Mar 03 12:33:47 PM PST 24 72682191 ps
T86 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.529240960 Mar 03 12:33:19 PM PST 24 Mar 03 12:33:25 PM PST 24 37534431 ps
T616 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3492453033 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:51 PM PST 24 15501396 ps
T87 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2570887480 Mar 03 12:33:46 PM PST 24 Mar 03 12:33:46 PM PST 24 19475422 ps
T88 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2848585981 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:50 PM PST 24 13801726 ps
T51 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3646848280 Mar 03 12:34:51 PM PST 24 Mar 03 12:34:53 PM PST 24 202261806 ps
T617 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.459855713 Mar 03 12:33:20 PM PST 24 Mar 03 12:33:23 PM PST 24 82797480 ps
T89 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.415475424 Mar 03 12:34:48 PM PST 24 Mar 03 12:34:50 PM PST 24 144518495 ps
T618 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3741514287 Mar 03 12:33:53 PM PST 24 Mar 03 12:33:54 PM PST 24 104334092 ps
T136 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2129915280 Mar 03 12:33:29 PM PST 24 Mar 03 12:33:31 PM PST 24 232461497 ps
T619 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3415203879 Mar 03 12:34:06 PM PST 24 Mar 03 12:34:07 PM PST 24 30739347 ps
T620 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1317707246 Mar 03 12:33:51 PM PST 24 Mar 03 12:33:53 PM PST 24 655094390 ps
T621 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4292236460 Mar 03 12:33:41 PM PST 24 Mar 03 12:33:43 PM PST 24 30120624 ps
T622 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3914960798 Mar 03 12:33:34 PM PST 24 Mar 03 12:33:36 PM PST 24 421505429 ps
T623 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3759384532 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:52 PM PST 24 330167762 ps
T624 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2615557956 Mar 03 12:34:08 PM PST 24 Mar 03 12:34:09 PM PST 24 46715112 ps
T625 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1610456424 Mar 03 12:33:42 PM PST 24 Mar 03 12:33:43 PM PST 24 159666324 ps
T90 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3729024591 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:50 PM PST 24 25873532 ps
T91 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3701038966 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:50 PM PST 24 18912438 ps
T626 /workspace/coverage/cover_reg_top/2.hmac_intr_test.4238694362 Mar 03 12:33:16 PM PST 24 Mar 03 12:33:17 PM PST 24 15822890 ps
T56 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3307831418 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:52 PM PST 24 268748890 ps
T627 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2918215420 Mar 03 12:33:22 PM PST 24 Mar 03 12:33:25 PM PST 24 43521409 ps
T628 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.889290524 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:52 PM PST 24 82217359 ps
T629 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.668580264 Mar 03 12:33:20 PM PST 24 Mar 03 12:33:22 PM PST 24 124940283 ps
T630 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2322434647 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:51 PM PST 24 41596637 ps
T92 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3729864126 Mar 03 12:33:46 PM PST 24 Mar 03 12:33:49 PM PST 24 189235554 ps
T93 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1455196687 Mar 03 12:33:29 PM PST 24 Mar 03 12:33:30 PM PST 24 75432268 ps
T631 /workspace/coverage/cover_reg_top/42.hmac_intr_test.986422241 Mar 03 12:34:03 PM PST 24 Mar 03 12:34:03 PM PST 24 22594641 ps
T137 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3698426053 Mar 03 12:33:48 PM PST 24 Mar 03 12:33:52 PM PST 24 267677744 ps
T139 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1161216550 Mar 03 12:37:29 PM PST 24 Mar 03 12:37:31 PM PST 24 359411358 ps
T632 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3223206195 Mar 03 12:33:46 PM PST 24 Mar 03 12:33:48 PM PST 24 220443819 ps
T633 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1177591597 Mar 03 12:33:56 PM PST 24 Mar 03 12:33:57 PM PST 24 244794851 ps
T634 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1080112907 Mar 03 12:33:38 PM PST 24 Mar 03 12:33:40 PM PST 24 37313375 ps
T635 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4078654689 Mar 03 12:34:07 PM PST 24 Mar 03 12:34:08 PM PST 24 20023810 ps
T138 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.331768632 Mar 03 12:33:48 PM PST 24 Mar 03 12:33:50 PM PST 24 43081911 ps
T636 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1553763359 Mar 03 12:33:42 PM PST 24 Mar 03 12:33:43 PM PST 24 17561081 ps
T140 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2990976856 Mar 03 12:33:19 PM PST 24 Mar 03 12:33:21 PM PST 24 74046034 ps
T637 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3212653566 Mar 03 12:33:34 PM PST 24 Mar 03 12:33:36 PM PST 24 138673734 ps
T638 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2788185552 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:51 PM PST 24 72861236 ps
T639 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3930696202 Mar 03 12:33:43 PM PST 24 Mar 03 12:33:45 PM PST 24 12624387 ps
T142 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2705643462 Mar 03 12:33:39 PM PST 24 Mar 03 12:33:40 PM PST 24 156832233 ps
T640 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2489631090 Mar 03 12:34:03 PM PST 24 Mar 03 12:34:04 PM PST 24 18745026 ps
T641 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.345169639 Mar 03 12:33:30 PM PST 24 Mar 03 12:33:32 PM PST 24 136258536 ps
T642 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.650112654 Mar 03 12:33:56 PM PST 24 Mar 03 12:33:59 PM PST 24 528301931 ps
T643 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3799534305 Mar 03 12:33:16 PM PST 24 Mar 03 12:33:18 PM PST 24 94698336 ps
T644 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3841421707 Mar 03 12:33:15 PM PST 24 Mar 03 12:33:16 PM PST 24 49066892 ps
T645 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3304319506 Mar 03 12:33:48 PM PST 24 Mar 03 12:33:49 PM PST 24 11435560 ps
T646 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1517787050 Mar 03 12:33:57 PM PST 24 Mar 03 12:33:59 PM PST 24 171534519 ps
T647 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.460906912 Mar 03 12:33:18 PM PST 24 Mar 03 12:33:20 PM PST 24 76530401 ps
T648 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3596823349 Mar 03 12:34:04 PM PST 24 Mar 03 12:34:04 PM PST 24 13414436 ps
T97 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1430000670 Mar 03 12:33:53 PM PST 24 Mar 03 12:33:54 PM PST 24 12842309 ps
T649 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2067527273 Mar 03 12:33:45 PM PST 24 Mar 03 12:33:45 PM PST 24 34112287 ps
T650 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3928218640 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:51 PM PST 24 112380937 ps
T651 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2720977044 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:51 PM PST 24 39723423 ps
T652 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2271427376 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:54 PM PST 24 341729472 ps
T653 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.698935002 Mar 03 12:33:15 PM PST 24 Mar 03 12:33:18 PM PST 24 102105239 ps
T654 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.810564907 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:54 PM PST 24 68419507 ps
T655 /workspace/coverage/cover_reg_top/32.hmac_intr_test.445826748 Mar 03 12:34:10 PM PST 24 Mar 03 12:34:11 PM PST 24 16864621 ps
T143 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1810481390 Mar 03 12:33:35 PM PST 24 Mar 03 12:33:37 PM PST 24 417167114 ps
T98 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1070354080 Mar 03 12:34:46 PM PST 24 Mar 03 12:34:48 PM PST 24 89983772 ps
T656 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4102238649 Mar 03 12:33:20 PM PST 24 Mar 03 12:33:21 PM PST 24 40435700 ps
T657 /workspace/coverage/cover_reg_top/23.hmac_intr_test.4199349840 Mar 03 12:33:58 PM PST 24 Mar 03 12:33:58 PM PST 24 155917541 ps
T658 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3839812309 Mar 03 12:33:21 PM PST 24 Mar 03 12:33:27 PM PST 24 52506960 ps
T659 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2690989596 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:50 PM PST 24 15860013 ps
T94 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4226947421 Mar 03 12:33:48 PM PST 24 Mar 03 12:33:56 PM PST 24 190793154 ps
T660 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3903732578 Mar 03 12:33:54 PM PST 24 Mar 03 12:33:56 PM PST 24 413659849 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.746942516 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:51 PM PST 24 87250863 ps
T661 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3168259364 Mar 03 12:37:27 PM PST 24 Mar 03 12:37:28 PM PST 24 15418167 ps
T662 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2556777966 Mar 03 12:33:52 PM PST 24 Mar 03 12:33:54 PM PST 24 130221238 ps
T99 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3215292845 Mar 03 12:33:30 PM PST 24 Mar 03 12:33:31 PM PST 24 21479441 ps
T663 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1399929607 Mar 03 12:33:21 PM PST 24 Mar 03 12:39:03 PM PST 24 67645281000 ps
T664 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2529925929 Mar 03 12:33:14 PM PST 24 Mar 03 12:33:16 PM PST 24 66004818 ps
T665 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.4152893721 Mar 03 12:33:43 PM PST 24 Mar 03 12:33:44 PM PST 24 100031834 ps
T666 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3270118871 Mar 03 12:33:54 PM PST 24 Mar 03 12:33:56 PM PST 24 533489530 ps
T667 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2783477208 Mar 03 12:33:56 PM PST 24 Mar 03 12:33:57 PM PST 24 43388966 ps
T96 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1647710587 Mar 03 12:33:35 PM PST 24 Mar 03 12:33:36 PM PST 24 55131770 ps
T668 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3196794079 Mar 03 12:33:43 PM PST 24 Mar 03 12:33:43 PM PST 24 26938173 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1573921386 Mar 03 12:33:53 PM PST 24 Mar 03 12:33:54 PM PST 24 67656914 ps
T669 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1621539769 Mar 03 12:33:19 PM PST 24 Mar 03 12:33:21 PM PST 24 58164234 ps
T670 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1088514704 Mar 03 12:34:01 PM PST 24 Mar 03 12:34:02 PM PST 24 118268106 ps
T671 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1935589760 Mar 03 12:33:53 PM PST 24 Mar 03 12:33:54 PM PST 24 59027119 ps
T672 /workspace/coverage/cover_reg_top/29.hmac_intr_test.45517139 Mar 03 12:33:58 PM PST 24 Mar 03 12:33:59 PM PST 24 45867635 ps
T673 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1682877507 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:50 PM PST 24 42254020 ps
T674 /workspace/coverage/cover_reg_top/15.hmac_intr_test.797211681 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:51 PM PST 24 37891152 ps
T675 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2040806037 Mar 03 12:33:48 PM PST 24 Mar 03 12:33:53 PM PST 24 331132089 ps
T676 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1930851116 Mar 03 12:33:44 PM PST 24 Mar 03 12:33:44 PM PST 24 19756778 ps
T677 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3355425404 Mar 03 12:37:27 PM PST 24 Mar 03 12:37:28 PM PST 24 136226414 ps
T678 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2487048500 Mar 03 12:33:51 PM PST 24 Mar 03 12:33:53 PM PST 24 45555893 ps
T679 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4278710325 Mar 03 12:33:46 PM PST 24 Mar 03 12:33:50 PM PST 24 242585394 ps
T680 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2542574025 Mar 03 12:34:02 PM PST 24 Mar 03 12:34:03 PM PST 24 26242818 ps
T681 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3985074784 Mar 03 12:33:44 PM PST 24 Mar 03 12:49:09 PM PST 24 176725872325 ps
T682 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.469315366 Mar 03 12:33:29 PM PST 24 Mar 03 12:33:30 PM PST 24 27353288 ps
T683 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4196731248 Mar 03 12:33:53 PM PST 24 Mar 03 12:34:00 PM PST 24 119848346 ps
T684 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3462972995 Mar 03 12:33:46 PM PST 24 Mar 03 12:33:47 PM PST 24 255084440 ps
T685 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3669773222 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:52 PM PST 24 71790423 ps
T686 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3650357674 Mar 03 12:33:24 PM PST 24 Mar 03 12:33:25 PM PST 24 18020375 ps
T687 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2399748851 Mar 03 12:33:44 PM PST 24 Mar 03 12:33:45 PM PST 24 25049893 ps
T688 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2123258170 Mar 03 12:33:25 PM PST 24 Mar 03 12:33:26 PM PST 24 19460467 ps
T141 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1388613654 Mar 03 12:33:54 PM PST 24 Mar 03 12:33:56 PM PST 24 102767768 ps
T689 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2880768901 Mar 03 12:37:29 PM PST 24 Mar 03 12:37:30 PM PST 24 14950546 ps
T690 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1956333538 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:51 PM PST 24 13561101 ps
T691 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1859958947 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:53 PM PST 24 193446849 ps
T692 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2241183300 Mar 03 12:34:03 PM PST 24 Mar 03 12:34:03 PM PST 24 21193657 ps
T693 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1423686438 Mar 03 12:33:35 PM PST 24 Mar 03 12:33:36 PM PST 24 28092359 ps
T694 /workspace/coverage/cover_reg_top/38.hmac_intr_test.736600260 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:50 PM PST 24 49344719 ps
T695 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1609757192 Mar 03 12:33:38 PM PST 24 Mar 03 12:33:42 PM PST 24 153181777 ps
T696 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1895403544 Mar 03 12:33:46 PM PST 24 Mar 03 12:33:47 PM PST 24 16863852 ps
T697 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.373496088 Mar 03 12:34:29 PM PST 24 Mar 03 12:34:36 PM PST 24 193132626 ps
T698 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1870754323 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:50 PM PST 24 35630220 ps
T699 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3429777036 Mar 03 12:33:38 PM PST 24 Mar 03 12:33:40 PM PST 24 18097052 ps
T700 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.134333129 Mar 03 12:33:19 PM PST 24 Mar 03 12:33:20 PM PST 24 168316904 ps
T701 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3192243779 Mar 03 12:33:52 PM PST 24 Mar 03 12:33:54 PM PST 24 39335769 ps
T702 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1364417717 Mar 03 12:33:48 PM PST 24 Mar 03 12:33:48 PM PST 24 99760562 ps
T703 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2222751658 Mar 03 12:33:43 PM PST 24 Mar 03 12:33:44 PM PST 24 35722480 ps
T144 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4057253616 Mar 03 12:33:19 PM PST 24 Mar 03 12:33:20 PM PST 24 41820529 ps
T704 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3406434181 Mar 03 12:33:21 PM PST 24 Mar 03 12:33:23 PM PST 24 24282198 ps
T705 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.690932309 Mar 03 12:33:52 PM PST 24 Mar 03 12:33:54 PM PST 24 96859132 ps
T101 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3880530535 Mar 03 12:33:52 PM PST 24 Mar 03 12:33:53 PM PST 24 59207490 ps
T706 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2359796292 Mar 03 12:33:57 PM PST 24 Mar 03 12:33:58 PM PST 24 12140329 ps
T707 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.869160539 Mar 03 12:33:35 PM PST 24 Mar 03 12:33:37 PM PST 24 66595049 ps
T708 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4066209430 Mar 03 12:34:02 PM PST 24 Mar 03 12:34:08 PM PST 24 17768741 ps
T709 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1078937959 Mar 03 12:33:38 PM PST 24 Mar 03 12:33:40 PM PST 24 22645222 ps
T710 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3217014452 Mar 03 12:33:52 PM PST 24 Mar 03 12:33:53 PM PST 24 24271018 ps
T711 /workspace/coverage/cover_reg_top/30.hmac_intr_test.890716660 Mar 03 12:33:57 PM PST 24 Mar 03 12:33:58 PM PST 24 79579554 ps
T712 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.679919253 Mar 03 12:33:58 PM PST 24 Mar 03 12:34:00 PM PST 24 104824055 ps
T713 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1166029610 Mar 03 12:33:37 PM PST 24 Mar 03 12:33:38 PM PST 24 86124627 ps
T714 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2015195548 Mar 03 12:33:52 PM PST 24 Mar 03 12:33:53 PM PST 24 34618668 ps
T715 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2496655417 Mar 03 12:33:55 PM PST 24 Mar 03 12:33:56 PM PST 24 48890439 ps
T716 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1678859172 Mar 03 12:33:35 PM PST 24 Mar 03 12:33:36 PM PST 24 63526419 ps
T717 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4012989121 Mar 03 12:33:36 PM PST 24 Mar 03 12:33:37 PM PST 24 44442973 ps
T718 /workspace/coverage/cover_reg_top/47.hmac_intr_test.889023030 Mar 03 12:33:46 PM PST 24 Mar 03 12:33:47 PM PST 24 21924087 ps
T719 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4202819116 Mar 03 12:33:45 PM PST 24 Mar 03 12:33:46 PM PST 24 78695095 ps
T720 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1576993922 Mar 03 12:33:45 PM PST 24 Mar 03 12:33:47 PM PST 24 76405033 ps
T721 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3845134648 Mar 03 12:33:49 PM PST 24 Mar 03 12:33:50 PM PST 24 12859976 ps
T722 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3714238586 Mar 03 12:34:45 PM PST 24 Mar 03 12:34:48 PM PST 24 229999790 ps
T723 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.929848600 Mar 03 12:33:39 PM PST 24 Mar 03 12:33:41 PM PST 24 448142618 ps
T724 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.496905277 Mar 03 12:33:50 PM PST 24 Mar 03 12:33:51 PM PST 24 112485081 ps
T725 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1578724284 Mar 03 12:33:17 PM PST 24 Mar 03 12:33:27 PM PST 24 4009560203 ps
T726 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2107192617 Mar 03 12:33:58 PM PST 24 Mar 03 12:33:58 PM PST 24 15727918 ps

Test location /workspace/coverage/default/19.hmac_wipe_secret.24668725
Short name T17
Test name
Test status
Simulation time 1908970398 ps
CPU time 34.13 seconds
Started Mar 03 02:37:24 PM PST 24
Finished Mar 03 02:37:58 PM PST 24
Peak memory 199848 kb
Host smart-51df0cb2-0c27-4cbd-a0ac-d96162c93b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24668725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.24668725
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.3728787409
Short name T19
Test name
Test status
Simulation time 40950626018 ps
CPU time 675.39 seconds
Started Mar 03 02:39:17 PM PST 24
Finished Mar 03 02:50:34 PM PST 24
Peak memory 224772 kb
Host smart-07c9ea6f-410a-4acc-af5f-e02aa54cf295
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728787409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.3728787409
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2109019362
Short name T102
Test name
Test status
Simulation time 1661429234 ps
CPU time 80.23 seconds
Started Mar 03 02:38:41 PM PST 24
Finished Mar 03 02:40:01 PM PST 24
Peak memory 199844 kb
Host smart-18401730-d3b8-4a66-b2d2-e9f8b16c2747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109019362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2109019362
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1469627523
Short name T6
Test name
Test status
Simulation time 8485949498 ps
CPU time 426.08 seconds
Started Mar 03 02:37:39 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 215984 kb
Host smart-cb952a9c-b515-48f9-ac1d-819ca2a09eaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469627523 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1469627523
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3354789208
Short name T24
Test name
Test status
Simulation time 134379951 ps
CPU time 0.9 seconds
Started Mar 03 02:36:53 PM PST 24
Finished Mar 03 02:36:54 PM PST 24
Peak memory 216968 kb
Host smart-6fee54f2-7c20-4860-96cc-165461a49823
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354789208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3354789208
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3591949391
Short name T49
Test name
Test status
Simulation time 220199014 ps
CPU time 1.21 seconds
Started Mar 03 12:33:43 PM PST 24
Finished Mar 03 12:33:44 PM PST 24
Peak memory 198892 kb
Host smart-7fd2f0c2-d323-4994-b89c-6f197aba0407
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591949391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3591949391
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.1829647756
Short name T41
Test name
Test status
Simulation time 45342014591 ps
CPU time 1142.83 seconds
Started Mar 03 02:39:15 PM PST 24
Finished Mar 03 02:58:18 PM PST 24
Peak memory 251328 kb
Host smart-8b3e7c86-8d03-491d-8c65-5fd796bf8994
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829647756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.1829647756
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1724901073
Short name T2
Test name
Test status
Simulation time 6985627980 ps
CPU time 51.78 seconds
Started Mar 03 02:37:25 PM PST 24
Finished Mar 03 02:38:18 PM PST 24
Peak memory 199932 kb
Host smart-970b862e-2073-44e7-9093-cb9514e96b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724901073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1724901073
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2729356315
Short name T77
Test name
Test status
Simulation time 656765830 ps
CPU time 6.37 seconds
Started Mar 03 12:33:47 PM PST 24
Finished Mar 03 12:33:53 PM PST 24
Peak memory 192932 kb
Host smart-ff9a3bd4-51ad-4351-ba04-90cb67fea1cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729356315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2729356315
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3594629213
Short name T106
Test name
Test status
Simulation time 110484841591 ps
CPU time 1924.76 seconds
Started Mar 03 02:36:56 PM PST 24
Finished Mar 03 03:09:01 PM PST 24
Peak memory 199932 kb
Host smart-3c109560-099a-4786-a784-6833e5312532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594629213 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3594629213
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3698426053
Short name T137
Test name
Test status
Simulation time 267677744 ps
CPU time 2.27 seconds
Started Mar 03 12:33:48 PM PST 24
Finished Mar 03 12:33:52 PM PST 24
Peak memory 199136 kb
Host smart-0b445563-a49c-4f1d-ae85-309b2329f02c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698426053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3698426053
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2736010043
Short name T110
Test name
Test status
Simulation time 35670790256 ps
CPU time 1792.89 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 03:07:21 PM PST 24
Peak memory 234308 kb
Host smart-1cdb7462-dab4-4afc-8f3b-56580350f93c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736010043 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2736010043
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3305234603
Short name T107
Test name
Test status
Simulation time 15799594720 ps
CPU time 44.63 seconds
Started Mar 03 02:38:28 PM PST 24
Finished Mar 03 02:39:13 PM PST 24
Peak memory 200028 kb
Host smart-bcc69a2f-d47b-4052-83dd-39d6de9fbb0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3305234603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3305234603
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_stress_all.443575572
Short name T4
Test name
Test status
Simulation time 75675369368 ps
CPU time 880.93 seconds
Started Mar 03 02:38:54 PM PST 24
Finished Mar 03 02:53:36 PM PST 24
Peak memory 229752 kb
Host smart-d3e05e69-3e57-4143-9a2d-7fff7a5e739a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443575572 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.443575572
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2634067379
Short name T148
Test name
Test status
Simulation time 31849143 ps
CPU time 0.57 seconds
Started Mar 03 02:37:06 PM PST 24
Finished Mar 03 02:37:06 PM PST 24
Peak memory 194444 kb
Host smart-454098ad-279d-416d-b8cc-1dcf4fbb2d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634067379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2634067379
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4057253616
Short name T144
Test name
Test status
Simulation time 41820529 ps
CPU time 1.17 seconds
Started Mar 03 12:33:19 PM PST 24
Finished Mar 03 12:33:20 PM PST 24
Peak memory 199336 kb
Host smart-b8971756-b8a0-4714-913b-42a1fb5c20a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057253616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.4057253616
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3217698071
Short name T126
Test name
Test status
Simulation time 136429753160 ps
CPU time 1735.24 seconds
Started Mar 03 02:38:41 PM PST 24
Finished Mar 03 03:07:37 PM PST 24
Peak memory 199944 kb
Host smart-d379e6d5-cf3c-4b99-8240-32005b653de4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217698071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3217698071
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3698027067
Short name T112
Test name
Test status
Simulation time 1505218471 ps
CPU time 77.63 seconds
Started Mar 03 02:36:58 PM PST 24
Finished Mar 03 02:38:16 PM PST 24
Peak memory 200068 kb
Host smart-bbb67565-b781-4f2b-9743-887ebbc3ab66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698027067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3698027067
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.415475424
Short name T89
Test name
Test status
Simulation time 144518495 ps
CPU time 2.41 seconds
Started Mar 03 12:34:48 PM PST 24
Finished Mar 03 12:34:50 PM PST 24
Peak memory 192900 kb
Host smart-1462428e-d911-4d7f-bc52-843b4d82527c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415475424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.415475424
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3307831418
Short name T56
Test name
Test status
Simulation time 268748890 ps
CPU time 1.88 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:52 PM PST 24
Peak memory 198928 kb
Host smart-1cdb46d1-3957-4272-bb37-51eeae50fb29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307831418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3307831418
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1810481390
Short name T143
Test name
Test status
Simulation time 417167114 ps
CPU time 1.76 seconds
Started Mar 03 12:33:35 PM PST 24
Finished Mar 03 12:33:37 PM PST 24
Peak memory 198852 kb
Host smart-351f7f84-2442-40e0-bc75-f2e8a0d2cca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810481390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1810481390
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2499468852
Short name T1
Test name
Test status
Simulation time 934056316 ps
CPU time 44.1 seconds
Started Mar 03 02:37:12 PM PST 24
Finished Mar 03 02:37:57 PM PST 24
Peak memory 199884 kb
Host smart-44777e77-ed1e-43a3-aaae-722b66dcec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499468852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2499468852
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_stress_all.943909119
Short name T67
Test name
Test status
Simulation time 26977956170 ps
CPU time 1287.85 seconds
Started Mar 03 02:36:50 PM PST 24
Finished Mar 03 02:58:18 PM PST 24
Peak memory 208276 kb
Host smart-c0a8d274-76e3-447d-9cd1-fab18bba34bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943909119 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.943909119
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.4039739979
Short name T40
Test name
Test status
Simulation time 131362727286 ps
CPU time 993.29 seconds
Started Mar 03 02:38:30 PM PST 24
Finished Mar 03 02:55:04 PM PST 24
Peak memory 249348 kb
Host smart-8583fdea-392e-47bd-9cca-7875ca6b49d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039739979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.4039739979
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2699821694
Short name T124
Test name
Test status
Simulation time 2721731877 ps
CPU time 73.73 seconds
Started Mar 03 02:36:58 PM PST 24
Finished Mar 03 02:38:12 PM PST 24
Peak memory 199972 kb
Host smart-94053c18-d7fa-44d2-a1ab-b9522a4186b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699821694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2699821694
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3729864126
Short name T92
Test name
Test status
Simulation time 189235554 ps
CPU time 2.33 seconds
Started Mar 03 12:33:46 PM PST 24
Finished Mar 03 12:33:49 PM PST 24
Peak memory 184756 kb
Host smart-ac494924-beb4-44be-9a19-64e7b29745fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729864126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3729864126
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1455196687
Short name T93
Test name
Test status
Simulation time 75432268 ps
CPU time 0.71 seconds
Started Mar 03 12:33:29 PM PST 24
Finished Mar 03 12:33:30 PM PST 24
Peak memory 195376 kb
Host smart-d477fe96-e812-45d5-8b90-551de50d7e8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455196687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1455196687
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2793314890
Short name T611
Test name
Test status
Simulation time 156876239736 ps
CPU time 281.19 seconds
Started Mar 03 12:33:19 PM PST 24
Finished Mar 03 12:38:01 PM PST 24
Peak memory 210080 kb
Host smart-c01afaf0-e6c9-4e12-994f-949b80f09c8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793314890 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2793314890
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1647710587
Short name T96
Test name
Test status
Simulation time 55131770 ps
CPU time 0.66 seconds
Started Mar 03 12:33:35 PM PST 24
Finished Mar 03 12:33:36 PM PST 24
Peak memory 194928 kb
Host smart-80f70d97-8134-4aa9-a034-97a3ba19199b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647710587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1647710587
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3429777036
Short name T699
Test name
Test status
Simulation time 18097052 ps
CPU time 0.6 seconds
Started Mar 03 12:33:38 PM PST 24
Finished Mar 03 12:33:40 PM PST 24
Peak memory 184492 kb
Host smart-d84e3f74-000d-404e-88cd-0043c052112a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429777036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3429777036
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1678859172
Short name T716
Test name
Test status
Simulation time 63526419 ps
CPU time 1.18 seconds
Started Mar 03 12:33:35 PM PST 24
Finished Mar 03 12:33:36 PM PST 24
Peak memory 192960 kb
Host smart-84607c2b-b327-42a1-9c4c-e4e7214f1373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678859172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1678859172
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1609757192
Short name T695
Test name
Test status
Simulation time 153181777 ps
CPU time 3.39 seconds
Started Mar 03 12:33:38 PM PST 24
Finished Mar 03 12:33:42 PM PST 24
Peak memory 199396 kb
Host smart-cfe9aa1f-37ed-4e98-a101-2c5ea033ffbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609757192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1609757192
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1578724284
Short name T725
Test name
Test status
Simulation time 4009560203 ps
CPU time 9.12 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:27 PM PST 24
Peak memory 193096 kb
Host smart-464fc181-ee06-408c-bd1f-edab663df70c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578724284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1578724284
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3332757741
Short name T614
Test name
Test status
Simulation time 45317710 ps
CPU time 0.73 seconds
Started Mar 03 12:33:35 PM PST 24
Finished Mar 03 12:33:36 PM PST 24
Peak memory 195020 kb
Host smart-f5fe40af-c5d1-4fb4-9351-742e86ca9c32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332757741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3332757741
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.698935002
Short name T653
Test name
Test status
Simulation time 102105239 ps
CPU time 2.15 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:33:18 PM PST 24
Peak memory 199392 kb
Host smart-03214114-7c86-4614-ab9b-4c4ffdabba51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698935002 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.698935002
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4012989121
Short name T717
Test name
Test status
Simulation time 44442973 ps
CPU time 0.63 seconds
Started Mar 03 12:33:36 PM PST 24
Finished Mar 03 12:33:37 PM PST 24
Peak memory 195260 kb
Host smart-a124dbf0-e1c0-4fed-b35b-b88519c6775d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012989121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4012989121
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1166029610
Short name T713
Test name
Test status
Simulation time 86124627 ps
CPU time 0.66 seconds
Started Mar 03 12:33:37 PM PST 24
Finished Mar 03 12:33:38 PM PST 24
Peak memory 184492 kb
Host smart-73f78197-1621-4f8a-a168-b33d02152d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166029610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1166029610
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.869160539
Short name T707
Test name
Test status
Simulation time 66595049 ps
CPU time 1.43 seconds
Started Mar 03 12:33:35 PM PST 24
Finished Mar 03 12:33:37 PM PST 24
Peak memory 192924 kb
Host smart-415af35b-772a-4955-b490-6db6425fe3f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869160539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.869160539
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2040806037
Short name T675
Test name
Test status
Simulation time 331132089 ps
CPU time 3.63 seconds
Started Mar 03 12:33:48 PM PST 24
Finished Mar 03 12:33:53 PM PST 24
Peak memory 199452 kb
Host smart-d9036cd7-ec40-4538-baed-bee355124231
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040806037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2040806037
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3714238586
Short name T722
Test name
Test status
Simulation time 229999790 ps
CPU time 1.19 seconds
Started Mar 03 12:34:45 PM PST 24
Finished Mar 03 12:34:48 PM PST 24
Peak memory 198468 kb
Host smart-6624581b-9a29-4073-a5f8-317bb0d69572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714238586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3714238586
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1399929607
Short name T663
Test name
Test status
Simulation time 67645281000 ps
CPU time 341.82 seconds
Started Mar 03 12:33:21 PM PST 24
Finished Mar 03 12:39:03 PM PST 24
Peak memory 201800 kb
Host smart-0820a1c5-89b2-4ae2-9b5e-b09d62fe1504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399929607 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1399929607
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1430000670
Short name T97
Test name
Test status
Simulation time 12842309 ps
CPU time 0.67 seconds
Started Mar 03 12:33:53 PM PST 24
Finished Mar 03 12:33:54 PM PST 24
Peak memory 195000 kb
Host smart-151cd718-d9ab-4057-a7b8-ed89dd405fdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430000670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1430000670
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1080112907
Short name T634
Test name
Test status
Simulation time 37313375 ps
CPU time 0.58 seconds
Started Mar 03 12:33:38 PM PST 24
Finished Mar 03 12:33:40 PM PST 24
Peak memory 184500 kb
Host smart-437beb13-2a1c-4c8d-b173-6ff0a2e60027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080112907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1080112907
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2214346785
Short name T54
Test name
Test status
Simulation time 15972976 ps
CPU time 0.73 seconds
Started Mar 03 12:33:39 PM PST 24
Finished Mar 03 12:33:40 PM PST 24
Peak memory 192712 kb
Host smart-2774f18e-0a62-421c-9b89-e006199aba34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214346785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2214346785
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3192243779
Short name T701
Test name
Test status
Simulation time 39335769 ps
CPU time 2.18 seconds
Started Mar 03 12:33:52 PM PST 24
Finished Mar 03 12:33:54 PM PST 24
Peak memory 199452 kb
Host smart-57914074-33fd-4328-933a-c52c2b34d474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192243779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3192243779
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3985074784
Short name T681
Test name
Test status
Simulation time 176725872325 ps
CPU time 924.79 seconds
Started Mar 03 12:33:44 PM PST 24
Finished Mar 03 12:49:09 PM PST 24
Peak memory 211276 kb
Host smart-5534029d-0561-4a26-a79f-59d69f694d20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985074784 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3985074784
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3930696202
Short name T639
Test name
Test status
Simulation time 12624387 ps
CPU time 0.67 seconds
Started Mar 03 12:33:43 PM PST 24
Finished Mar 03 12:33:45 PM PST 24
Peak memory 193964 kb
Host smart-97816951-8060-4879-83a5-56c6bd92fbe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930696202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3930696202
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1682877507
Short name T673
Test name
Test status
Simulation time 42254020 ps
CPU time 0.63 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 184504 kb
Host smart-5f66ba65-c865-4bd6-ac1a-e41fa8bfffc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682877507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1682877507
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2556777966
Short name T662
Test name
Test status
Simulation time 130221238 ps
CPU time 1.39 seconds
Started Mar 03 12:33:52 PM PST 24
Finished Mar 03 12:33:54 PM PST 24
Peak memory 193248 kb
Host smart-63f297aa-7b14-4bd6-ad28-5dece6f09e5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556777966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2556777966
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3462972995
Short name T684
Test name
Test status
Simulation time 255084440 ps
CPU time 1.39 seconds
Started Mar 03 12:33:46 PM PST 24
Finished Mar 03 12:33:47 PM PST 24
Peak memory 199320 kb
Host smart-7d85f85c-0097-41e9-ab5c-464ce6700a45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462972995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3462972995
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2129915280
Short name T136
Test name
Test status
Simulation time 232461497 ps
CPU time 1.79 seconds
Started Mar 03 12:33:29 PM PST 24
Finished Mar 03 12:33:31 PM PST 24
Peak memory 199104 kb
Host smart-2366f316-5206-4b3c-88f3-24d0856021f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129915280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2129915280
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2529925929
Short name T664
Test name
Test status
Simulation time 66004818 ps
CPU time 1.24 seconds
Started Mar 03 12:33:14 PM PST 24
Finished Mar 03 12:33:16 PM PST 24
Peak memory 198392 kb
Host smart-02032537-c677-4bec-bc4c-527d895c7c97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529925929 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2529925929
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2241183300
Short name T692
Test name
Test status
Simulation time 21193657 ps
CPU time 0.64 seconds
Started Mar 03 12:34:03 PM PST 24
Finished Mar 03 12:34:03 PM PST 24
Peak memory 194916 kb
Host smart-60eb1ee4-ba98-4374-8319-d105502df3a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241183300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2241183300
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2123258170
Short name T688
Test name
Test status
Simulation time 19460467 ps
CPU time 0.58 seconds
Started Mar 03 12:33:25 PM PST 24
Finished Mar 03 12:33:26 PM PST 24
Peak memory 184532 kb
Host smart-9dc8f6bf-8a81-44ef-880f-c6ab8913ada6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123258170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2123258170
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1517787050
Short name T646
Test name
Test status
Simulation time 171534519 ps
CPU time 1.05 seconds
Started Mar 03 12:33:57 PM PST 24
Finished Mar 03 12:33:59 PM PST 24
Peak memory 197712 kb
Host smart-629f3309-f3d5-4421-9334-d3947c0af51d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517787050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1517787050
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.4152893721
Short name T665
Test name
Test status
Simulation time 100031834 ps
CPU time 1.23 seconds
Started Mar 03 12:33:43 PM PST 24
Finished Mar 03 12:33:44 PM PST 24
Peak memory 199284 kb
Host smart-2974f264-cbd0-47dd-9ac8-02ccbb1acd82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152893721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.4152893721
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.929848600
Short name T723
Test name
Test status
Simulation time 448142618 ps
CPU time 1.88 seconds
Started Mar 03 12:33:39 PM PST 24
Finished Mar 03 12:33:41 PM PST 24
Peak memory 199140 kb
Host smart-926430c2-ae70-4668-bdf1-dd635d438759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929848600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.929848600
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2472870284
Short name T597
Test name
Test status
Simulation time 82327959 ps
CPU time 1.26 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 199320 kb
Host smart-6969e978-669d-4ca0-9a80-5dc257be5459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472870284 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2472870284
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3196794079
Short name T668
Test name
Test status
Simulation time 26938173 ps
CPU time 0.71 seconds
Started Mar 03 12:33:43 PM PST 24
Finished Mar 03 12:33:43 PM PST 24
Peak memory 195360 kb
Host smart-08222273-7f0f-4857-8662-6507837aba95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196794079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3196794079
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2359796292
Short name T706
Test name
Test status
Simulation time 12140329 ps
CPU time 0.57 seconds
Started Mar 03 12:33:57 PM PST 24
Finished Mar 03 12:33:58 PM PST 24
Peak memory 184572 kb
Host smart-b3068808-7fff-436b-9561-1b640850f673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359796292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2359796292
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1610456424
Short name T625
Test name
Test status
Simulation time 159666324 ps
CPU time 0.93 seconds
Started Mar 03 12:33:42 PM PST 24
Finished Mar 03 12:33:43 PM PST 24
Peak memory 192780 kb
Host smart-fd5ac414-6d4e-4894-8f01-04b123a4da5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610456424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1610456424
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2271427376
Short name T652
Test name
Test status
Simulation time 341729472 ps
CPU time 3.71 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:54 PM PST 24
Peak memory 199456 kb
Host smart-8799eb70-9168-413f-bee8-0a76f3256f46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271427376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2271427376
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.496905277
Short name T724
Test name
Test status
Simulation time 112485081 ps
CPU time 1.04 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 199164 kb
Host smart-d3a554f3-7e22-4422-b900-54f519d27314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496905277 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.496905277
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1078937959
Short name T709
Test name
Test status
Simulation time 22645222 ps
CPU time 0.75 seconds
Started Mar 03 12:33:38 PM PST 24
Finished Mar 03 12:33:40 PM PST 24
Peak memory 195224 kb
Host smart-98247d35-8145-47e3-b1c1-3b3a001f452d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078937959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1078937959
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1553763359
Short name T636
Test name
Test status
Simulation time 17561081 ps
CPU time 0.63 seconds
Started Mar 03 12:33:42 PM PST 24
Finished Mar 03 12:33:43 PM PST 24
Peak memory 184576 kb
Host smart-04a87e7f-cc7f-4998-bd87-55eda868f050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553763359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1553763359
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2399748851
Short name T687
Test name
Test status
Simulation time 25049893 ps
CPU time 1.11 seconds
Started Mar 03 12:33:44 PM PST 24
Finished Mar 03 12:33:45 PM PST 24
Peak memory 197064 kb
Host smart-b05d8103-b2f9-42d2-bf4e-3c1d46359879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399748851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2399748851
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4261487237
Short name T60
Test name
Test status
Simulation time 124430863 ps
CPU time 1.85 seconds
Started Mar 03 12:33:54 PM PST 24
Finished Mar 03 12:33:56 PM PST 24
Peak memory 199336 kb
Host smart-3ed11d9d-496f-451b-a38c-c2c834ef8d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261487237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.4261487237
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1576993922
Short name T720
Test name
Test status
Simulation time 76405033 ps
CPU time 1.72 seconds
Started Mar 03 12:33:45 PM PST 24
Finished Mar 03 12:33:47 PM PST 24
Peak memory 199384 kb
Host smart-c7fe524d-0976-4d9e-8b25-2f32e07c4103
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576993922 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1576993922
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3701038966
Short name T91
Test name
Test status
Simulation time 18912438 ps
CPU time 0.65 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 194812 kb
Host smart-be5e0698-1259-409f-a1b7-7ac1c6b53a5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701038966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3701038966
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.797211681
Short name T674
Test name
Test status
Simulation time 37891152 ps
CPU time 0.55 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 184576 kb
Host smart-d45bdbd7-4404-4c1a-a461-a47aafd8b56e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797211681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.797211681
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4292236460
Short name T621
Test name
Test status
Simulation time 30120624 ps
CPU time 1.34 seconds
Started Mar 03 12:33:41 PM PST 24
Finished Mar 03 12:33:43 PM PST 24
Peak memory 197284 kb
Host smart-038508d2-aec9-4131-a2bf-4d19b11407bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292236460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.4292236460
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3759384532
Short name T623
Test name
Test status
Simulation time 330167762 ps
CPU time 2.16 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:52 PM PST 24
Peak memory 199404 kb
Host smart-992e7497-ce99-47f3-9807-4e0265d1eea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759384532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3759384532
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.275400062
Short name T602
Test name
Test status
Simulation time 62027684 ps
CPU time 1.64 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:52 PM PST 24
Peak memory 199444 kb
Host smart-adf3080f-1dab-42ed-aecd-855bef5a07c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275400062 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.275400062
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3217014452
Short name T710
Test name
Test status
Simulation time 24271018 ps
CPU time 0.66 seconds
Started Mar 03 12:33:52 PM PST 24
Finished Mar 03 12:33:53 PM PST 24
Peak memory 195232 kb
Host smart-72a10b81-734e-4ef0-a94b-5d7afa155d9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217014452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3217014452
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2359791452
Short name T608
Test name
Test status
Simulation time 44746812 ps
CPU time 0.59 seconds
Started Mar 03 12:33:51 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 184656 kb
Host smart-accc1fec-dd3a-42bd-9461-d6caf72286a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359791452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2359791452
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3928218640
Short name T650
Test name
Test status
Simulation time 112380937 ps
CPU time 1.31 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 197860 kb
Host smart-21a3b062-f948-48a8-a752-494fb77e89e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928218640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3928218640
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4278710325
Short name T679
Test name
Test status
Simulation time 242585394 ps
CPU time 3.5 seconds
Started Mar 03 12:33:46 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 199452 kb
Host smart-818a68c0-341a-4d3c-8b24-38b38c0827de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278710325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.4278710325
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.331768632
Short name T138
Test name
Test status
Simulation time 43081911 ps
CPU time 1.14 seconds
Started Mar 03 12:33:48 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 198820 kb
Host smart-f9f7ea8a-9ade-48bb-8d59-3d920605ef57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331768632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.331768632
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4202819116
Short name T719
Test name
Test status
Simulation time 78695095 ps
CPU time 1.28 seconds
Started Mar 03 12:33:45 PM PST 24
Finished Mar 03 12:33:46 PM PST 24
Peak memory 199236 kb
Host smart-5673f4d4-382a-41de-9798-724200dfad55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202819116 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4202819116
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3880530535
Short name T101
Test name
Test status
Simulation time 59207490 ps
CPU time 0.7 seconds
Started Mar 03 12:33:52 PM PST 24
Finished Mar 03 12:33:53 PM PST 24
Peak memory 195288 kb
Host smart-6fc49209-682e-4a31-8d0a-7e2fa213952f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880530535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3880530535
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3492453033
Short name T616
Test name
Test status
Simulation time 15501396 ps
CPU time 0.57 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 184480 kb
Host smart-055a77c0-82fb-49e7-96fe-2a70663c1d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492453033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3492453033
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4196731248
Short name T683
Test name
Test status
Simulation time 119848346 ps
CPU time 1.38 seconds
Started Mar 03 12:33:53 PM PST 24
Finished Mar 03 12:34:00 PM PST 24
Peak memory 193044 kb
Host smart-36f5257b-5fab-4a41-8e2f-6e354df4d8cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196731248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4196731248
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2326021656
Short name T610
Test name
Test status
Simulation time 191550960 ps
CPU time 2.61 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:13 PM PST 24
Peak memory 199336 kb
Host smart-40486e55-2f86-4ece-8d06-5a91d8c5b4c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326021656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2326021656
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.679919253
Short name T712
Test name
Test status
Simulation time 104824055 ps
CPU time 1.71 seconds
Started Mar 03 12:33:58 PM PST 24
Finished Mar 03 12:34:00 PM PST 24
Peak memory 199012 kb
Host smart-36d63b3a-70ec-4baf-a7f5-eb926463a514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679919253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.679919253
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2788185552
Short name T638
Test name
Test status
Simulation time 72861236 ps
CPU time 1.17 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 199232 kb
Host smart-2b0481e5-2ec0-4c65-8683-ad70dba34afb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788185552 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2788185552
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1895403544
Short name T696
Test name
Test status
Simulation time 16863852 ps
CPU time 0.69 seconds
Started Mar 03 12:33:46 PM PST 24
Finished Mar 03 12:33:47 PM PST 24
Peak memory 195432 kb
Host smart-998e1c9a-9970-4aaa-a5cd-aca61b702892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895403544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1895403544
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1930851116
Short name T676
Test name
Test status
Simulation time 19756778 ps
CPU time 0.58 seconds
Started Mar 03 12:33:44 PM PST 24
Finished Mar 03 12:33:44 PM PST 24
Peak memory 184940 kb
Host smart-d822478d-830d-48d8-86f2-02c966d179f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930851116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1930851116
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.889290524
Short name T628
Test name
Test status
Simulation time 82217359 ps
CPU time 1.02 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:52 PM PST 24
Peak memory 192952 kb
Host smart-9c98685a-d523-4a09-97a2-1717054e1192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889290524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.889290524
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.810564907
Short name T654
Test name
Test status
Simulation time 68419507 ps
CPU time 3.73 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:54 PM PST 24
Peak memory 199320 kb
Host smart-d8aa2930-0a6e-4ea6-b6e7-3e82093deb27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810564907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.810564907
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3903732578
Short name T660
Test name
Test status
Simulation time 413659849 ps
CPU time 1.96 seconds
Started Mar 03 12:33:54 PM PST 24
Finished Mar 03 12:33:56 PM PST 24
Peak memory 199024 kb
Host smart-782e6250-8551-4c7b-829e-ef0104256389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903732578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3903732578
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1423686438
Short name T693
Test name
Test status
Simulation time 28092359 ps
CPU time 1.52 seconds
Started Mar 03 12:33:35 PM PST 24
Finished Mar 03 12:33:36 PM PST 24
Peak memory 199524 kb
Host smart-6ee781e6-3d34-4f80-a7dd-102adb40da23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423686438 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1423686438
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3729024591
Short name T90
Test name
Test status
Simulation time 25873532 ps
CPU time 0.72 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 195428 kb
Host smart-1101466e-c4e5-421c-b8b4-34cc3d54a589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729024591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3729024591
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.275728200
Short name T76
Test name
Test status
Simulation time 48949671 ps
CPU time 0.6 seconds
Started Mar 03 12:34:05 PM PST 24
Finished Mar 03 12:34:07 PM PST 24
Peak memory 184544 kb
Host smart-1259fa5d-1623-4cf2-8acc-b40ca5ae5366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275728200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.275728200
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4066209430
Short name T708
Test name
Test status
Simulation time 17768741 ps
CPU time 0.78 seconds
Started Mar 03 12:34:02 PM PST 24
Finished Mar 03 12:34:08 PM PST 24
Peak memory 192812 kb
Host smart-8ba1b68c-61bb-4176-bfef-87385ac48538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066209430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4066209430
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2016264039
Short name T599
Test name
Test status
Simulation time 64641103 ps
CPU time 3.62 seconds
Started Mar 03 12:33:43 PM PST 24
Finished Mar 03 12:33:47 PM PST 24
Peak memory 199392 kb
Host smart-f99bbf10-305e-4f69-9a69-39b666947898
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016264039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2016264039
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1388613654
Short name T141
Test name
Test status
Simulation time 102767768 ps
CPU time 1.79 seconds
Started Mar 03 12:33:54 PM PST 24
Finished Mar 03 12:33:56 PM PST 24
Peak memory 198736 kb
Host smart-3c85da38-b99e-462b-9490-c16faf0fd5f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388613654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1388613654
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.746942516
Short name T95
Test name
Test status
Simulation time 87250863 ps
CPU time 1.15 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 184820 kb
Host smart-32da9d4d-8acd-4fc6-acab-4e265adb1c47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746942516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.746942516
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.373496088
Short name T697
Test name
Test status
Simulation time 193132626 ps
CPU time 7.41 seconds
Started Mar 03 12:34:29 PM PST 24
Finished Mar 03 12:34:36 PM PST 24
Peak memory 192652 kb
Host smart-ff025dd4-9e40-415c-b6e9-f31b561d471d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373496088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.373496088
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.469315366
Short name T682
Test name
Test status
Simulation time 27353288 ps
CPU time 0.64 seconds
Started Mar 03 12:33:29 PM PST 24
Finished Mar 03 12:33:30 PM PST 24
Peak memory 194240 kb
Host smart-f69293fb-a410-4e06-8636-4abdeda89767
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469315366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.469315366
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3914960798
Short name T622
Test name
Test status
Simulation time 421505429 ps
CPU time 2.13 seconds
Started Mar 03 12:33:34 PM PST 24
Finished Mar 03 12:33:36 PM PST 24
Peak memory 199348 kb
Host smart-ca2f71f1-c55e-4fba-848b-fb623359625f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914960798 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3914960798
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2570887480
Short name T87
Test name
Test status
Simulation time 19475422 ps
CPU time 0.75 seconds
Started Mar 03 12:33:46 PM PST 24
Finished Mar 03 12:33:46 PM PST 24
Peak memory 195384 kb
Host smart-975d1a0e-ec42-4051-a93f-e36e31e6a786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570887480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2570887480
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.4238694362
Short name T626
Test name
Test status
Simulation time 15822890 ps
CPU time 0.6 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:33:17 PM PST 24
Peak memory 184520 kb
Host smart-dce51270-c97c-4ef8-a460-fc3117b475db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238694362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.4238694362
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.84319513
Short name T607
Test name
Test status
Simulation time 23966521 ps
CPU time 1.06 seconds
Started Mar 03 12:33:35 PM PST 24
Finished Mar 03 12:33:36 PM PST 24
Peak memory 192988 kb
Host smart-06bd6b1a-7f47-4340-952a-c26e8a6098a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84319513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_o
utstanding.84319513
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3799534305
Short name T643
Test name
Test status
Simulation time 94698336 ps
CPU time 1.34 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:33:18 PM PST 24
Peak memory 199268 kb
Host smart-73f3e8ea-d7f7-4f72-962a-4c1d1fe28795
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799534305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3799534305
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.650112654
Short name T642
Test name
Test status
Simulation time 528301931 ps
CPU time 1.72 seconds
Started Mar 03 12:33:56 PM PST 24
Finished Mar 03 12:33:59 PM PST 24
Peak memory 199044 kb
Host smart-16f338ea-be42-4179-ae1c-4641d1445b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650112654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.650112654
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1364417717
Short name T702
Test name
Test status
Simulation time 99760562 ps
CPU time 0.58 seconds
Started Mar 03 12:33:48 PM PST 24
Finished Mar 03 12:33:48 PM PST 24
Peak memory 184572 kb
Host smart-3226f6d4-21ba-44f0-816f-042817a05109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364417717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1364417717
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.171264042
Short name T601
Test name
Test status
Simulation time 13869621 ps
CPU time 0.54 seconds
Started Mar 03 12:33:59 PM PST 24
Finished Mar 03 12:34:00 PM PST 24
Peak memory 184516 kb
Host smart-7ee799c8-46fb-4339-991e-67605ba77e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171264042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.171264042
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3596823349
Short name T648
Test name
Test status
Simulation time 13414436 ps
CPU time 0.61 seconds
Started Mar 03 12:34:04 PM PST 24
Finished Mar 03 12:34:04 PM PST 24
Peak memory 184460 kb
Host smart-741b91d2-88b4-4a45-bd87-c04add90dcd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596823349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3596823349
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.4199349840
Short name T657
Test name
Test status
Simulation time 155917541 ps
CPU time 0.55 seconds
Started Mar 03 12:33:58 PM PST 24
Finished Mar 03 12:33:58 PM PST 24
Peak memory 184460 kb
Host smart-ddedc7f3-dcb9-46a1-ac7e-589dfe91079c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199349840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.4199349840
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2720977044
Short name T651
Test name
Test status
Simulation time 39723423 ps
CPU time 0.54 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 184576 kb
Host smart-ce31a867-da0a-47e5-8c43-efd6302be195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720977044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2720977044
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2067527273
Short name T649
Test name
Test status
Simulation time 34112287 ps
CPU time 0.53 seconds
Started Mar 03 12:33:45 PM PST 24
Finished Mar 03 12:33:45 PM PST 24
Peak memory 184476 kb
Host smart-52ede8c8-0017-45af-9227-6e5ba387a78f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067527273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2067527273
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2615557956
Short name T624
Test name
Test status
Simulation time 46715112 ps
CPU time 0.65 seconds
Started Mar 03 12:34:08 PM PST 24
Finished Mar 03 12:34:09 PM PST 24
Peak memory 184572 kb
Host smart-67af7f49-72f8-4371-be31-ebca417be290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615557956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2615557956
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3304319506
Short name T645
Test name
Test status
Simulation time 11435560 ps
CPU time 0.58 seconds
Started Mar 03 12:33:48 PM PST 24
Finished Mar 03 12:33:49 PM PST 24
Peak memory 184504 kb
Host smart-0a2b1850-7093-4694-99a6-09b1dd1b2d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304319506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3304319506
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3415203879
Short name T619
Test name
Test status
Simulation time 30739347 ps
CPU time 0.64 seconds
Started Mar 03 12:34:06 PM PST 24
Finished Mar 03 12:34:07 PM PST 24
Peak memory 184504 kb
Host smart-0969abd2-0048-49c5-94ff-4dd767ce1cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415203879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3415203879
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.45517139
Short name T672
Test name
Test status
Simulation time 45867635 ps
CPU time 0.57 seconds
Started Mar 03 12:33:58 PM PST 24
Finished Mar 03 12:33:59 PM PST 24
Peak memory 184656 kb
Host smart-b022d8ec-41a3-4e09-9973-9c66548e8f07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45517139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.45517139
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3305036161
Short name T85
Test name
Test status
Simulation time 128408727 ps
CPU time 2.47 seconds
Started Mar 03 12:33:28 PM PST 24
Finished Mar 03 12:33:30 PM PST 24
Peak memory 196668 kb
Host smart-132190bb-416d-4313-99f8-547a8382c9c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305036161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3305036161
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1987201331
Short name T613
Test name
Test status
Simulation time 445146769 ps
CPU time 3.35 seconds
Started Mar 03 12:33:14 PM PST 24
Finished Mar 03 12:33:18 PM PST 24
Peak memory 193000 kb
Host smart-12ee9983-4998-4312-b9ab-7611066c8499
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987201331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1987201331
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3215292845
Short name T99
Test name
Test status
Simulation time 21479441 ps
CPU time 0.73 seconds
Started Mar 03 12:33:30 PM PST 24
Finished Mar 03 12:33:31 PM PST 24
Peak memory 195212 kb
Host smart-666eee01-4b8b-48ca-8fbf-81f09d13952d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215292845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3215292845
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3406434181
Short name T704
Test name
Test status
Simulation time 24282198 ps
CPU time 1.41 seconds
Started Mar 03 12:33:21 PM PST 24
Finished Mar 03 12:33:23 PM PST 24
Peak memory 199268 kb
Host smart-5920e7a2-6398-432a-b604-9423c0299cc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406434181 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3406434181
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.529240960
Short name T86
Test name
Test status
Simulation time 37534431 ps
CPU time 0.6 seconds
Started Mar 03 12:33:19 PM PST 24
Finished Mar 03 12:33:25 PM PST 24
Peak memory 194788 kb
Host smart-ad9c456b-786d-4dc8-863e-ee5e048255ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529240960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.529240960
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3839812309
Short name T658
Test name
Test status
Simulation time 52506960 ps
CPU time 0.57 seconds
Started Mar 03 12:33:21 PM PST 24
Finished Mar 03 12:33:27 PM PST 24
Peak memory 184508 kb
Host smart-e18a8ee5-ba5d-4344-89a6-813087c5881e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839812309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3839812309
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.460906912
Short name T647
Test name
Test status
Simulation time 76530401 ps
CPU time 1.32 seconds
Started Mar 03 12:33:18 PM PST 24
Finished Mar 03 12:33:20 PM PST 24
Peak memory 197948 kb
Host smart-f764322a-8b4c-40fc-93b3-1110cab2a4bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460906912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.460906912
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.134333129
Short name T700
Test name
Test status
Simulation time 168316904 ps
CPU time 1.23 seconds
Started Mar 03 12:33:19 PM PST 24
Finished Mar 03 12:33:20 PM PST 24
Peak memory 199340 kb
Host smart-8a00f2a2-b332-402b-9f03-651550cb6983
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134333129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.134333129
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3355425404
Short name T677
Test name
Test status
Simulation time 136226414 ps
CPU time 1.65 seconds
Started Mar 03 12:37:27 PM PST 24
Finished Mar 03 12:37:28 PM PST 24
Peak memory 198780 kb
Host smart-65633b7c-cad3-4e58-b042-67cbc6843b08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355425404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3355425404
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.890716660
Short name T711
Test name
Test status
Simulation time 79579554 ps
CPU time 0.56 seconds
Started Mar 03 12:33:57 PM PST 24
Finished Mar 03 12:33:58 PM PST 24
Peak memory 184568 kb
Host smart-7bb3d8d1-7638-4ad8-904d-5ab9cd1dcf41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890716660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.890716660
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.631604892
Short name T605
Test name
Test status
Simulation time 50963671 ps
CPU time 0.61 seconds
Started Mar 03 12:33:51 PM PST 24
Finished Mar 03 12:33:52 PM PST 24
Peak memory 184920 kb
Host smart-e5e54ad9-9fa5-4639-9087-d38ba64bdee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631604892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.631604892
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.445826748
Short name T655
Test name
Test status
Simulation time 16864621 ps
CPU time 0.58 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:11 PM PST 24
Peak memory 184464 kb
Host smart-e3d18735-91ec-4507-8fd9-e4be9d325778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445826748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.445826748
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3845134648
Short name T721
Test name
Test status
Simulation time 12859976 ps
CPU time 0.57 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 184568 kb
Host smart-e84c8008-2249-42a7-9c16-c0355091bcfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845134648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3845134648
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.472515057
Short name T604
Test name
Test status
Simulation time 46523249 ps
CPU time 0.57 seconds
Started Mar 03 12:34:08 PM PST 24
Finished Mar 03 12:34:09 PM PST 24
Peak memory 184568 kb
Host smart-13b3e8bb-77a9-40e5-9680-c35dd761467c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472515057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.472515057
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3741514287
Short name T618
Test name
Test status
Simulation time 104334092 ps
CPU time 0.58 seconds
Started Mar 03 12:33:53 PM PST 24
Finished Mar 03 12:33:54 PM PST 24
Peak memory 184480 kb
Host smart-95b6953f-3ddd-497f-ba39-58e8c1ba6166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741514287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3741514287
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1597108322
Short name T612
Test name
Test status
Simulation time 11697752 ps
CPU time 0.62 seconds
Started Mar 03 12:33:51 PM PST 24
Finished Mar 03 12:33:52 PM PST 24
Peak memory 184496 kb
Host smart-dd7a1e69-60df-4d8a-951b-036f9ae57b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597108322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1597108322
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1177591597
Short name T633
Test name
Test status
Simulation time 244794851 ps
CPU time 0.61 seconds
Started Mar 03 12:33:56 PM PST 24
Finished Mar 03 12:33:57 PM PST 24
Peak memory 184516 kb
Host smart-e35b299a-1b1d-4ace-ba47-f842b104a4d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177591597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1177591597
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.736600260
Short name T694
Test name
Test status
Simulation time 49344719 ps
CPU time 0.55 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 184528 kb
Host smart-f48f3ebb-5468-4c15-bbf7-1b861172a5c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736600260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.736600260
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1956333538
Short name T690
Test name
Test status
Simulation time 13561101 ps
CPU time 0.55 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 184572 kb
Host smart-8f808d5e-9422-4abf-a321-72d9a369545f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956333538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1956333538
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3841421707
Short name T644
Test name
Test status
Simulation time 49066892 ps
CPU time 1.09 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:33:16 PM PST 24
Peak memory 192868 kb
Host smart-809e2198-06f9-4071-8cb0-4ad8895a4999
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841421707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3841421707
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4226947421
Short name T94
Test name
Test status
Simulation time 190793154 ps
CPU time 7.74 seconds
Started Mar 03 12:33:48 PM PST 24
Finished Mar 03 12:33:56 PM PST 24
Peak memory 193004 kb
Host smart-669dfeb0-32fd-44f8-89ec-eaff0418db02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226947421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4226947421
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1573921386
Short name T100
Test name
Test status
Simulation time 67656914 ps
CPU time 0.72 seconds
Started Mar 03 12:33:53 PM PST 24
Finished Mar 03 12:33:54 PM PST 24
Peak memory 195104 kb
Host smart-b68ba41d-8124-4c5e-b11b-7d72f2b39f2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573921386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1573921386
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.459855713
Short name T617
Test name
Test status
Simulation time 82797480 ps
CPU time 2.47 seconds
Started Mar 03 12:33:20 PM PST 24
Finished Mar 03 12:33:23 PM PST 24
Peak memory 199304 kb
Host smart-17564f6b-287f-4225-976a-26ad25dfdd68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459855713 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.459855713
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1070354080
Short name T98
Test name
Test status
Simulation time 89983772 ps
CPU time 0.66 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:48 PM PST 24
Peak memory 195252 kb
Host smart-3fce9177-e8a9-46c9-a85f-deb5027818bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070354080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1070354080
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3299618248
Short name T609
Test name
Test status
Simulation time 22473207 ps
CPU time 0.66 seconds
Started Mar 03 12:33:39 PM PST 24
Finished Mar 03 12:33:40 PM PST 24
Peak memory 184652 kb
Host smart-1926d813-d65a-4acb-98cf-440044f1ed1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299618248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3299618248
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3270118871
Short name T666
Test name
Test status
Simulation time 533489530 ps
CPU time 1.07 seconds
Started Mar 03 12:33:54 PM PST 24
Finished Mar 03 12:33:56 PM PST 24
Peak memory 192984 kb
Host smart-669c6048-c3ad-4a5e-ae86-42ca9107157c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270118871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3270118871
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3212653566
Short name T637
Test name
Test status
Simulation time 138673734 ps
CPU time 2.13 seconds
Started Mar 03 12:33:34 PM PST 24
Finished Mar 03 12:33:36 PM PST 24
Peak memory 199348 kb
Host smart-9d6830b3-2bc2-4d4f-8471-5e5eff4fca7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212653566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3212653566
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3646848280
Short name T51
Test name
Test status
Simulation time 202261806 ps
CPU time 1.66 seconds
Started Mar 03 12:34:51 PM PST 24
Finished Mar 03 12:34:53 PM PST 24
Peak memory 198924 kb
Host smart-24dad25d-3410-437f-b516-4ddf63b5c391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646848280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3646848280
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1088514704
Short name T670
Test name
Test status
Simulation time 118268106 ps
CPU time 0.6 seconds
Started Mar 03 12:34:01 PM PST 24
Finished Mar 03 12:34:02 PM PST 24
Peak memory 184652 kb
Host smart-d633b327-f815-47c7-a404-a57e8ed8060b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088514704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1088514704
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2690989596
Short name T659
Test name
Test status
Simulation time 15860013 ps
CPU time 0.59 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 184516 kb
Host smart-88346087-1b9c-4f1d-be56-686b9870464c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690989596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2690989596
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.986422241
Short name T631
Test name
Test status
Simulation time 22594641 ps
CPU time 0.59 seconds
Started Mar 03 12:34:03 PM PST 24
Finished Mar 03 12:34:03 PM PST 24
Peak memory 184504 kb
Host smart-b8ca9489-8d92-4e7c-906c-6cbe0af6d050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986422241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.986422241
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.87455847
Short name T615
Test name
Test status
Simulation time 72682191 ps
CPU time 0.57 seconds
Started Mar 03 12:33:46 PM PST 24
Finished Mar 03 12:33:47 PM PST 24
Peak memory 184460 kb
Host smart-3b0d506f-6dd4-4448-81c5-94adf0fadba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87455847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.87455847
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2783477208
Short name T667
Test name
Test status
Simulation time 43388966 ps
CPU time 0.6 seconds
Started Mar 03 12:33:56 PM PST 24
Finished Mar 03 12:33:57 PM PST 24
Peak memory 184576 kb
Host smart-7254f2be-61a8-4023-90d8-ca7ba1740222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783477208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2783477208
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2107192617
Short name T726
Test name
Test status
Simulation time 15727918 ps
CPU time 0.62 seconds
Started Mar 03 12:33:58 PM PST 24
Finished Mar 03 12:33:58 PM PST 24
Peak memory 184652 kb
Host smart-d09905ee-00ba-42a3-9353-903ef0eaebf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107192617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2107192617
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1794828558
Short name T598
Test name
Test status
Simulation time 21586667 ps
CPU time 0.54 seconds
Started Mar 03 12:34:08 PM PST 24
Finished Mar 03 12:34:09 PM PST 24
Peak memory 184436 kb
Host smart-36e3f060-a6b2-4917-a894-71a14c18f97a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794828558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1794828558
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.889023030
Short name T718
Test name
Test status
Simulation time 21924087 ps
CPU time 0.57 seconds
Started Mar 03 12:33:46 PM PST 24
Finished Mar 03 12:33:47 PM PST 24
Peak memory 184620 kb
Host smart-421b3078-398b-4a24-8ef4-fc367cfd39a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889023030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.889023030
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1870754323
Short name T698
Test name
Test status
Simulation time 35630220 ps
CPU time 0.54 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 184536 kb
Host smart-9933fec5-ca09-4d8b-b1d2-62bc43673e42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870754323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1870754323
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2489631090
Short name T640
Test name
Test status
Simulation time 18745026 ps
CPU time 0.58 seconds
Started Mar 03 12:34:03 PM PST 24
Finished Mar 03 12:34:04 PM PST 24
Peak memory 184516 kb
Host smart-e5deb52d-9027-433b-ba40-f16293708bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489631090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2489631090
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1621539769
Short name T669
Test name
Test status
Simulation time 58164234 ps
CPU time 1.53 seconds
Started Mar 03 12:33:19 PM PST 24
Finished Mar 03 12:33:21 PM PST 24
Peak memory 199696 kb
Host smart-4ad44a91-a216-454a-b5f5-f463864144c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621539769 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1621539769
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3168259364
Short name T661
Test name
Test status
Simulation time 15418167 ps
CPU time 0.59 seconds
Started Mar 03 12:37:27 PM PST 24
Finished Mar 03 12:37:28 PM PST 24
Peak memory 194516 kb
Host smart-d1cd7564-574b-47b5-b8ab-cd2d0fa75fab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168259364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3168259364
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2880768901
Short name T689
Test name
Test status
Simulation time 14950546 ps
CPU time 0.61 seconds
Started Mar 03 12:37:29 PM PST 24
Finished Mar 03 12:37:30 PM PST 24
Peak memory 184584 kb
Host smart-b4f4cb08-3091-42d0-9452-1329cfe556dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880768901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2880768901
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.668580264
Short name T629
Test name
Test status
Simulation time 124940283 ps
CPU time 1.29 seconds
Started Mar 03 12:33:20 PM PST 24
Finished Mar 03 12:33:22 PM PST 24
Peak memory 197276 kb
Host smart-a0d20cb7-78cc-4821-a6ce-82099bbacd4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668580264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.668580264
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.345169639
Short name T641
Test name
Test status
Simulation time 136258536 ps
CPU time 2.55 seconds
Started Mar 03 12:33:30 PM PST 24
Finished Mar 03 12:33:32 PM PST 24
Peak memory 199384 kb
Host smart-c2bc8760-f549-4645-af28-042028e5d91e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345169639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.345169639
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1161216550
Short name T139
Test name
Test status
Simulation time 359411358 ps
CPU time 1.63 seconds
Started Mar 03 12:37:29 PM PST 24
Finished Mar 03 12:37:31 PM PST 24
Peak memory 199068 kb
Host smart-592c07dd-13e9-43ca-b484-7e89ba529927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161216550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1161216550
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3223206195
Short name T632
Test name
Test status
Simulation time 220443819 ps
CPU time 1.82 seconds
Started Mar 03 12:33:46 PM PST 24
Finished Mar 03 12:33:48 PM PST 24
Peak memory 199444 kb
Host smart-435e7546-6963-4962-ae94-e6bf4bc1846c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223206195 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3223206195
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4183913408
Short name T55
Test name
Test status
Simulation time 52712132 ps
CPU time 0.6 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 194576 kb
Host smart-558f1bbe-70e5-4d40-bdbc-84b881f86a5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183913408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4183913408
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3139216190
Short name T603
Test name
Test status
Simulation time 45688814 ps
CPU time 0.6 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:55 PM PST 24
Peak memory 184460 kb
Host smart-9d0ab0d7-c863-42aa-a58d-863f23aecf3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139216190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3139216190
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2222751658
Short name T703
Test name
Test status
Simulation time 35722480 ps
CPU time 0.84 seconds
Started Mar 03 12:33:43 PM PST 24
Finished Mar 03 12:33:44 PM PST 24
Peak memory 196392 kb
Host smart-5dcb71d1-0b16-4588-9e7d-258b9325cfba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222751658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2222751658
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2918215420
Short name T627
Test name
Test status
Simulation time 43521409 ps
CPU time 2.27 seconds
Started Mar 03 12:33:22 PM PST 24
Finished Mar 03 12:33:25 PM PST 24
Peak memory 199428 kb
Host smart-b7e42c2b-be74-4f5d-aef1-782327239eb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918215420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2918215420
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2705643462
Short name T142
Test name
Test status
Simulation time 156832233 ps
CPU time 1.17 seconds
Started Mar 03 12:33:39 PM PST 24
Finished Mar 03 12:33:40 PM PST 24
Peak memory 198804 kb
Host smart-c73a42f6-b422-46af-a881-97f5e468b0a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705643462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2705643462
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2322434647
Short name T630
Test name
Test status
Simulation time 41596637 ps
CPU time 1.2 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:51 PM PST 24
Peak memory 199244 kb
Host smart-8d2853be-a873-4536-9823-c1791869a76e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322434647 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2322434647
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3650357674
Short name T686
Test name
Test status
Simulation time 18020375 ps
CPU time 0.6 seconds
Started Mar 03 12:33:24 PM PST 24
Finished Mar 03 12:33:25 PM PST 24
Peak memory 194548 kb
Host smart-b031aacd-a513-458c-92ef-5b705cbc4db3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650357674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3650357674
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2015195548
Short name T714
Test name
Test status
Simulation time 34618668 ps
CPU time 0.62 seconds
Started Mar 03 12:33:52 PM PST 24
Finished Mar 03 12:33:53 PM PST 24
Peak memory 184572 kb
Host smart-32ea9741-b986-40f8-aba8-36e302fe30cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015195548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2015195548
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4078654689
Short name T635
Test name
Test status
Simulation time 20023810 ps
CPU time 0.83 seconds
Started Mar 03 12:34:07 PM PST 24
Finished Mar 03 12:34:08 PM PST 24
Peak memory 196168 kb
Host smart-84ca8b11-c250-4de2-b30a-360b265d9e49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078654689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.4078654689
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2487048500
Short name T678
Test name
Test status
Simulation time 45555893 ps
CPU time 1.87 seconds
Started Mar 03 12:33:51 PM PST 24
Finished Mar 03 12:33:53 PM PST 24
Peak memory 199428 kb
Host smart-9a81191d-a573-4c74-8136-88a66f713884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487048500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2487048500
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2496655417
Short name T715
Test name
Test status
Simulation time 48890439 ps
CPU time 1.25 seconds
Started Mar 03 12:33:55 PM PST 24
Finished Mar 03 12:33:56 PM PST 24
Peak memory 198752 kb
Host smart-72c59eee-3104-48e7-a29d-3d1601f51acb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496655417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2496655417
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1317707246
Short name T620
Test name
Test status
Simulation time 655094390 ps
CPU time 1.77 seconds
Started Mar 03 12:33:51 PM PST 24
Finished Mar 03 12:33:53 PM PST 24
Peak memory 199384 kb
Host smart-4deaedd8-eb55-494d-a2d6-ea88cfcd8a7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317707246 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1317707246
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2848585981
Short name T88
Test name
Test status
Simulation time 13801726 ps
CPU time 0.62 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 194792 kb
Host smart-5f436015-812a-4fbd-96c0-371320bfbabb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848585981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2848585981
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.111190545
Short name T600
Test name
Test status
Simulation time 45825881 ps
CPU time 0.6 seconds
Started Mar 03 12:33:36 PM PST 24
Finished Mar 03 12:33:37 PM PST 24
Peak memory 184456 kb
Host smart-c21eafb5-59e0-45d5-bcf5-06643c4985cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111190545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.111190545
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4102238649
Short name T656
Test name
Test status
Simulation time 40435700 ps
CPU time 0.97 seconds
Started Mar 03 12:33:20 PM PST 24
Finished Mar 03 12:33:21 PM PST 24
Peak memory 197420 kb
Host smart-d9789c6f-a0b9-4153-83ff-b65d7b8653e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102238649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.4102238649
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3669773222
Short name T685
Test name
Test status
Simulation time 71790423 ps
CPU time 1.64 seconds
Started Mar 03 12:33:50 PM PST 24
Finished Mar 03 12:33:52 PM PST 24
Peak memory 199388 kb
Host smart-e08314fc-3d14-4f10-9b8b-dd8c6530136c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669773222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3669773222
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1309260992
Short name T50
Test name
Test status
Simulation time 48940548 ps
CPU time 1.15 seconds
Started Mar 03 12:33:39 PM PST 24
Finished Mar 03 12:33:41 PM PST 24
Peak memory 198540 kb
Host smart-246ce1fa-d6a3-4bb4-9f5e-e6edfa7c0197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309260992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1309260992
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.690932309
Short name T705
Test name
Test status
Simulation time 96859132 ps
CPU time 1.79 seconds
Started Mar 03 12:33:52 PM PST 24
Finished Mar 03 12:33:54 PM PST 24
Peak memory 199404 kb
Host smart-c1c3cf95-69b7-4ab3-a65c-069237a0c588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690932309 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.690932309
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2542574025
Short name T680
Test name
Test status
Simulation time 26242818 ps
CPU time 0.66 seconds
Started Mar 03 12:34:02 PM PST 24
Finished Mar 03 12:34:03 PM PST 24
Peak memory 194904 kb
Host smart-7a677536-6f9d-4934-9148-1366e86eb5ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542574025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2542574025
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3641159038
Short name T606
Test name
Test status
Simulation time 49857829 ps
CPU time 0.56 seconds
Started Mar 03 12:33:48 PM PST 24
Finished Mar 03 12:33:49 PM PST 24
Peak memory 184652 kb
Host smart-44e2d00e-3619-4226-98c8-236b0dca7d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641159038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3641159038
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1935589760
Short name T671
Test name
Test status
Simulation time 59027119 ps
CPU time 1.12 seconds
Started Mar 03 12:33:53 PM PST 24
Finished Mar 03 12:33:54 PM PST 24
Peak memory 192916 kb
Host smart-d54e4c87-9d67-4d78-9f0b-991609f834c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935589760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1935589760
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1859958947
Short name T691
Test name
Test status
Simulation time 193446849 ps
CPU time 3.46 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:33:53 PM PST 24
Peak memory 199392 kb
Host smart-878f1d66-fb54-4413-a1c9-34fb1a6a82f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859958947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1859958947
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2990976856
Short name T140
Test name
Test status
Simulation time 74046034 ps
CPU time 1.62 seconds
Started Mar 03 12:33:19 PM PST 24
Finished Mar 03 12:33:21 PM PST 24
Peak memory 199056 kb
Host smart-4b946b44-ec2c-4acd-ac9f-35d5f2ad00f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990976856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2990976856
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4159954572
Short name T417
Test name
Test status
Simulation time 51395652 ps
CPU time 0.58 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:36:49 PM PST 24
Peak memory 195288 kb
Host smart-d25cce60-52c8-42fa-a33a-237bea923e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159954572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4159954572
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.4231492147
Short name T298
Test name
Test status
Simulation time 200481979 ps
CPU time 6.85 seconds
Started Mar 03 02:36:46 PM PST 24
Finished Mar 03 02:36:53 PM PST 24
Peak memory 208100 kb
Host smart-fc3744fb-8311-4345-ab94-612a60733ef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231492147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.4231492147
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.429200588
Short name T286
Test name
Test status
Simulation time 156263225 ps
CPU time 2.9 seconds
Started Mar 03 02:36:53 PM PST 24
Finished Mar 03 02:36:56 PM PST 24
Peak memory 199920 kb
Host smart-319e28f6-de42-409b-9d55-4fceffa0a0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429200588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.429200588
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.825306681
Short name T310
Test name
Test status
Simulation time 4567487030 ps
CPU time 63.28 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:37:53 PM PST 24
Peak memory 200000 kb
Host smart-8caec376-385e-4831-a112-c66d4af1ea46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825306681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.825306681
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.4073562425
Short name T465
Test name
Test status
Simulation time 100561713 ps
CPU time 1.2 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:36:51 PM PST 24
Peak memory 199860 kb
Host smart-3f72a561-6687-4548-8712-a1206652d2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073562425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.4073562425
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3176503562
Short name T31
Test name
Test status
Simulation time 7570596019 ps
CPU time 99.73 seconds
Started Mar 03 02:36:51 PM PST 24
Finished Mar 03 02:38:31 PM PST 24
Peak memory 199952 kb
Host smart-1d5b7fe0-162a-4bc6-8e4c-4bffd2beef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176503562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3176503562
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.996867611
Short name T368
Test name
Test status
Simulation time 95644883 ps
CPU time 1.78 seconds
Started Mar 03 02:36:50 PM PST 24
Finished Mar 03 02:36:52 PM PST 24
Peak memory 199796 kb
Host smart-7a477409-ccd4-42de-9284-95314e43442a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996867611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.996867611
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3310613366
Short name T469
Test name
Test status
Simulation time 229829252428 ps
CPU time 1058.29 seconds
Started Mar 03 02:36:51 PM PST 24
Finished Mar 03 02:54:29 PM PST 24
Peak memory 236928 kb
Host smart-0f1fc9f9-dea6-413d-a60b-7f4944293baa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310613366 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3310613366
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.415771200
Short name T357
Test name
Test status
Simulation time 44211353 ps
CPU time 1.03 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:36:50 PM PST 24
Peak memory 198604 kb
Host smart-33b07755-4875-4243-9866-d9bf5a493c87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415771200 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.415771200
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.495531181
Short name T328
Test name
Test status
Simulation time 138371632242 ps
CPU time 466.11 seconds
Started Mar 03 02:36:50 PM PST 24
Finished Mar 03 02:44:37 PM PST 24
Peak memory 199924 kb
Host smart-3268bb46-efe9-40dc-82c7-1b4d712a9535
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495531181 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.hmac_test_sha_vectors.495531181
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1219731901
Short name T440
Test name
Test status
Simulation time 561037297 ps
CPU time 28.29 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:37:17 PM PST 24
Peak memory 199864 kb
Host smart-d7ce9641-e0fe-492e-b45f-0706f6b7bea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219731901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1219731901
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3990295916
Short name T567
Test name
Test status
Simulation time 20114535 ps
CPU time 0.61 seconds
Started Mar 03 02:36:50 PM PST 24
Finished Mar 03 02:36:51 PM PST 24
Peak memory 194488 kb
Host smart-2e96711e-b594-4dba-aeef-8481cb61742c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990295916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3990295916
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3550036009
Short name T536
Test name
Test status
Simulation time 1416320643 ps
CPU time 50.65 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:37:40 PM PST 24
Peak memory 219360 kb
Host smart-1e1f2df8-5df0-449c-bd3b-cd761c51b594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3550036009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3550036009
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2148216770
Short name T282
Test name
Test status
Simulation time 18226448905 ps
CPU time 23.33 seconds
Started Mar 03 02:36:50 PM PST 24
Finished Mar 03 02:37:13 PM PST 24
Peak memory 199996 kb
Host smart-1e53881e-f67a-4c26-ae74-dac6e3df6ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148216770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2148216770
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2577464802
Short name T211
Test name
Test status
Simulation time 71014685 ps
CPU time 3.47 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:36:52 PM PST 24
Peak memory 199896 kb
Host smart-2a263092-33b8-475a-8496-3e70282263fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577464802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2577464802
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.346274406
Short name T456
Test name
Test status
Simulation time 13596069864 ps
CPU time 113.69 seconds
Started Mar 03 02:36:47 PM PST 24
Finished Mar 03 02:38:42 PM PST 24
Peak memory 200036 kb
Host smart-ea1435ce-0cb0-465a-a491-695e97a2b62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346274406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.346274406
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3419659015
Short name T149
Test name
Test status
Simulation time 9907071354 ps
CPU time 122.51 seconds
Started Mar 03 02:36:47 PM PST 24
Finished Mar 03 02:38:51 PM PST 24
Peak memory 200036 kb
Host smart-6d714497-6613-42bd-b9b2-0f1c5f08307e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419659015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3419659015
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.191656814
Short name T25
Test name
Test status
Simulation time 61487580 ps
CPU time 0.78 seconds
Started Mar 03 02:36:56 PM PST 24
Finished Mar 03 02:36:57 PM PST 24
Peak memory 216904 kb
Host smart-46d97adf-0d27-4885-a8ec-aadd9c9205d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191656814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.191656814
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.301592420
Short name T574
Test name
Test status
Simulation time 814018584 ps
CPU time 4.15 seconds
Started Mar 03 02:36:51 PM PST 24
Finished Mar 03 02:36:56 PM PST 24
Peak memory 199776 kb
Host smart-ecbb1580-a4fe-465d-8c06-668d67bc87af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301592420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.301592420
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3851761034
Short name T463
Test name
Test status
Simulation time 69420314768 ps
CPU time 985.36 seconds
Started Mar 03 02:36:56 PM PST 24
Finished Mar 03 02:53:21 PM PST 24
Peak memory 214452 kb
Host smart-d758c015-8909-47e0-8eab-8d1d2c97d08d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851761034 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3851761034
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2929318900
Short name T171
Test name
Test status
Simulation time 47037787 ps
CPU time 1.01 seconds
Started Mar 03 02:36:50 PM PST 24
Finished Mar 03 02:36:51 PM PST 24
Peak memory 197204 kb
Host smart-ae717f1a-e404-4bfc-87eb-cfec75a60956
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929318900 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2929318900
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.794040122
Short name T299
Test name
Test status
Simulation time 72638509710 ps
CPU time 435.24 seconds
Started Mar 03 02:36:48 PM PST 24
Finished Mar 03 02:44:04 PM PST 24
Peak memory 199936 kb
Host smart-afeaeaa6-49eb-4720-9072-6cb39a29e54d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794040122 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.hmac_test_sha_vectors.794040122
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2996990886
Short name T302
Test name
Test status
Simulation time 7420375279 ps
CPU time 14.82 seconds
Started Mar 03 02:36:47 PM PST 24
Finished Mar 03 02:37:03 PM PST 24
Peak memory 199976 kb
Host smart-7bb15cd9-591b-418f-9043-585b3e0e03eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996990886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2996990886
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3439334435
Short name T483
Test name
Test status
Simulation time 26823468 ps
CPU time 0.55 seconds
Started Mar 03 02:37:07 PM PST 24
Finished Mar 03 02:37:08 PM PST 24
Peak memory 194236 kb
Host smart-6bacf2e0-d1ab-4172-b5f4-f2d1eb5171b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439334435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3439334435
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1043915024
Short name T44
Test name
Test status
Simulation time 328212869 ps
CPU time 11.72 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:37:17 PM PST 24
Peak memory 216056 kb
Host smart-511ad2fe-4926-4a77-9f74-0dd4f3f13653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043915024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1043915024
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.704015627
Short name T128
Test name
Test status
Simulation time 2523206043 ps
CPU time 24.46 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:37:23 PM PST 24
Peak memory 200000 kb
Host smart-8495c310-ed07-42f7-b2a2-41538ab8db60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704015627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.704015627
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3878132719
Short name T436
Test name
Test status
Simulation time 2178040131 ps
CPU time 47.87 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:37:53 PM PST 24
Peak memory 200008 kb
Host smart-74fe6fc8-5ae2-48d4-b219-8e07bb3dc265
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3878132719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3878132719
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3928082933
Short name T285
Test name
Test status
Simulation time 8518147063 ps
CPU time 127.68 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:39:18 PM PST 24
Peak memory 200008 kb
Host smart-300df2f8-2b2b-4d64-a8d3-47d03f7784f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928082933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3928082933
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1291654383
Short name T156
Test name
Test status
Simulation time 635710996 ps
CPU time 4.45 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:37:04 PM PST 24
Peak memory 199748 kb
Host smart-efb00819-3afa-45a1-9ba2-f8cb316abdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291654383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1291654383
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1315494778
Short name T441
Test name
Test status
Simulation time 1707726614 ps
CPU time 4.57 seconds
Started Mar 03 02:37:00 PM PST 24
Finished Mar 03 02:37:05 PM PST 24
Peak memory 199828 kb
Host smart-485b8482-85a7-4247-8c2a-35d6c2fb749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315494778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1315494778
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3502386193
Short name T73
Test name
Test status
Simulation time 113168848105 ps
CPU time 1513.67 seconds
Started Mar 03 02:37:04 PM PST 24
Finished Mar 03 03:02:18 PM PST 24
Peak memory 230676 kb
Host smart-8bbc80b0-de40-4cf6-a122-161bf89bbe44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502386193 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3502386193
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2390537450
Short name T284
Test name
Test status
Simulation time 104817789 ps
CPU time 1.17 seconds
Started Mar 03 02:37:06 PM PST 24
Finished Mar 03 02:37:07 PM PST 24
Peak memory 198820 kb
Host smart-702b8be5-c56b-4264-a08e-9894ada9e107
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390537450 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2390537450
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.178469263
Short name T300
Test name
Test status
Simulation time 7371389544 ps
CPU time 372.76 seconds
Started Mar 03 02:37:01 PM PST 24
Finished Mar 03 02:43:14 PM PST 24
Peak memory 199804 kb
Host smart-c41a1558-e58d-4c5e-8260-7d552f63f850
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178469263 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.hmac_test_sha_vectors.178469263
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1957286124
Short name T218
Test name
Test status
Simulation time 1844921564 ps
CPU time 33.78 seconds
Started Mar 03 02:37:00 PM PST 24
Finished Mar 03 02:37:34 PM PST 24
Peak memory 199864 kb
Host smart-113ed1ba-a3a7-4069-a4cb-a7f0cd907bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957286124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1957286124
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.973488652
Short name T480
Test name
Test status
Simulation time 21459511 ps
CPU time 0.54 seconds
Started Mar 03 02:37:08 PM PST 24
Finished Mar 03 02:37:11 PM PST 24
Peak memory 194452 kb
Host smart-df284281-1054-4328-a605-5de495ede649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973488652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.973488652
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1113280635
Short name T596
Test name
Test status
Simulation time 8779984077 ps
CPU time 20.94 seconds
Started Mar 03 02:37:02 PM PST 24
Finished Mar 03 02:37:23 PM PST 24
Peak memory 221536 kb
Host smart-f11243cc-1fb3-445c-87a5-db9484922f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113280635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1113280635
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1851098368
Short name T324
Test name
Test status
Simulation time 842900480 ps
CPU time 16.08 seconds
Started Mar 03 02:37:03 PM PST 24
Finished Mar 03 02:37:19 PM PST 24
Peak memory 199916 kb
Host smart-b049a461-4ffe-4d66-b487-4b79bdd4a693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851098368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1851098368
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.261526705
Short name T213
Test name
Test status
Simulation time 13532823079 ps
CPU time 107.59 seconds
Started Mar 03 02:37:08 PM PST 24
Finished Mar 03 02:38:55 PM PST 24
Peak memory 200000 kb
Host smart-33a6399c-dde4-439d-80b9-e407c9a8cadc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261526705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.261526705
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1972819653
Short name T478
Test name
Test status
Simulation time 8055441182 ps
CPU time 48.99 seconds
Started Mar 03 02:37:07 PM PST 24
Finished Mar 03 02:37:57 PM PST 24
Peak memory 199896 kb
Host smart-bec45197-a6b3-421e-b3aa-b22d0598fcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972819653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1972819653
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2105793033
Short name T576
Test name
Test status
Simulation time 10551313752 ps
CPU time 64.04 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:38:09 PM PST 24
Peak memory 199984 kb
Host smart-f23578a2-52b7-4367-82d4-4013e66cda03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105793033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2105793033
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1407168995
Short name T244
Test name
Test status
Simulation time 257370082 ps
CPU time 1.4 seconds
Started Mar 03 02:37:04 PM PST 24
Finished Mar 03 02:37:06 PM PST 24
Peak memory 199532 kb
Host smart-ba61262a-a3e7-4c45-99de-bb346bd105a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407168995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1407168995
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3063844217
Short name T464
Test name
Test status
Simulation time 139881864886 ps
CPU time 1137.21 seconds
Started Mar 03 02:37:08 PM PST 24
Finished Mar 03 02:56:05 PM PST 24
Peak memory 200036 kb
Host smart-94c035ff-08a1-44ad-b9b5-c869b072b7c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063844217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3063844217
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1114393668
Short name T509
Test name
Test status
Simulation time 128909283 ps
CPU time 1.16 seconds
Started Mar 03 02:37:07 PM PST 24
Finished Mar 03 02:37:09 PM PST 24
Peak memory 198424 kb
Host smart-ca48e5f6-cf97-4fb1-be1f-572c12a88bab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114393668 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1114393668
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.416266554
Short name T312
Test name
Test status
Simulation time 9043508299 ps
CPU time 429.54 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:44:14 PM PST 24
Peak memory 199988 kb
Host smart-000f773e-4df4-49b9-b574-86fde850fd97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416266554 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.hmac_test_sha_vectors.416266554
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2577193568
Short name T147
Test name
Test status
Simulation time 23285822940 ps
CPU time 72.87 seconds
Started Mar 03 02:37:04 PM PST 24
Finished Mar 03 02:38:17 PM PST 24
Peak memory 199988 kb
Host smart-56016223-8eb0-4705-9665-ee3f39eb2384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577193568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2577193568
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.2702152972
Short name T21
Test name
Test status
Simulation time 97251975091 ps
CPU time 566.71 seconds
Started Mar 03 02:39:24 PM PST 24
Finished Mar 03 02:48:51 PM PST 24
Peak memory 208392 kb
Host smart-c3362943-c898-4f7f-b229-1e78c29b4647
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702152972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.2702152972
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.917146258
Short name T468
Test name
Test status
Simulation time 1425572445 ps
CPU time 10.06 seconds
Started Mar 03 02:37:09 PM PST 24
Finished Mar 03 02:37:21 PM PST 24
Peak memory 199888 kb
Host smart-057424a8-aa4a-4863-bd2c-afe0480cf2d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917146258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.917146258
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.89610414
Short name T164
Test name
Test status
Simulation time 3689353972 ps
CPU time 3.93 seconds
Started Mar 03 02:37:06 PM PST 24
Finished Mar 03 02:37:10 PM PST 24
Peak memory 199948 kb
Host smart-7758d457-1e90-4e66-a282-7baf9d7a63a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89610414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.89610414
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3324000873
Short name T260
Test name
Test status
Simulation time 1484676858 ps
CPU time 79.93 seconds
Started Mar 03 02:37:06 PM PST 24
Finished Mar 03 02:38:27 PM PST 24
Peak memory 199844 kb
Host smart-0a253e2a-a671-4134-b321-1afb98451666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324000873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3324000873
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2898709777
Short name T318
Test name
Test status
Simulation time 15652914254 ps
CPU time 69.4 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:38:15 PM PST 24
Peak memory 199888 kb
Host smart-eddeabdc-7170-4923-b1a4-c425bfbed142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898709777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2898709777
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3296322330
Short name T561
Test name
Test status
Simulation time 1861958253 ps
CPU time 100.34 seconds
Started Mar 03 02:37:03 PM PST 24
Finished Mar 03 02:38:44 PM PST 24
Peak memory 199924 kb
Host smart-ffcb27c6-7321-4e83-8360-6150577a931d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296322330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3296322330
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1373819156
Short name T18
Test name
Test status
Simulation time 336480044 ps
CPU time 4.76 seconds
Started Mar 03 02:37:02 PM PST 24
Finished Mar 03 02:37:07 PM PST 24
Peak memory 199900 kb
Host smart-b2777a20-1413-4730-b6f2-dcdda0062186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373819156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1373819156
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1402514492
Short name T114
Test name
Test status
Simulation time 193119815008 ps
CPU time 2343.27 seconds
Started Mar 03 02:37:09 PM PST 24
Finished Mar 03 03:16:14 PM PST 24
Peak memory 216224 kb
Host smart-42073853-1ba9-4bad-89c2-82f42722921b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402514492 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1402514492
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.4146735586
Short name T83
Test name
Test status
Simulation time 140889086 ps
CPU time 1.1 seconds
Started Mar 03 02:37:08 PM PST 24
Finished Mar 03 02:37:11 PM PST 24
Peak memory 198512 kb
Host smart-5652cd90-d89b-4d57-a4ef-cd17ea7e5690
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146735586 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.4146735586
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3744416138
Short name T82
Test name
Test status
Simulation time 8003854163 ps
CPU time 423.52 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:44:09 PM PST 24
Peak memory 199892 kb
Host smart-5a17f2d7-4ec5-4426-a228-90add58c813b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744416138 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.3744416138
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3041654374
Short name T269
Test name
Test status
Simulation time 6258095961 ps
CPU time 85.08 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:38:30 PM PST 24
Peak memory 200052 kb
Host smart-6936623b-d997-4845-90b8-317ff33f11cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041654374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3041654374
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.328026412
Short name T20
Test name
Test status
Simulation time 27004173375 ps
CPU time 755.12 seconds
Started Mar 03 02:39:25 PM PST 24
Finished Mar 03 02:52:02 PM PST 24
Peak memory 228568 kb
Host smart-aaf324e7-da41-4cca-9340-ba3b826fba1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328026412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.328026412
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1583157360
Short name T563
Test name
Test status
Simulation time 67514188 ps
CPU time 0.58 seconds
Started Mar 03 02:37:12 PM PST 24
Finished Mar 03 02:37:13 PM PST 24
Peak memory 194244 kb
Host smart-77b53a5f-226b-413c-aa20-d83f21ef45df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583157360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1583157360
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.4239475188
Short name T546
Test name
Test status
Simulation time 913168489 ps
CPU time 32.28 seconds
Started Mar 03 02:37:06 PM PST 24
Finished Mar 03 02:37:38 PM PST 24
Peak memory 225476 kb
Host smart-8fd2f7e1-40eb-42b1-9c9a-a27c29198b0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239475188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.4239475188
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2731064278
Short name T428
Test name
Test status
Simulation time 2400662756 ps
CPU time 11.68 seconds
Started Mar 03 02:37:09 PM PST 24
Finished Mar 03 02:37:22 PM PST 24
Peak memory 199860 kb
Host smart-2781de1d-4b18-43a9-9c35-5679e8ce97a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731064278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2731064278
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2618915616
Short name T353
Test name
Test status
Simulation time 8539947875 ps
CPU time 37.74 seconds
Started Mar 03 02:37:09 PM PST 24
Finished Mar 03 02:37:48 PM PST 24
Peak memory 199952 kb
Host smart-7c2bf7d5-4169-41b8-b12f-2d60c378c731
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618915616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2618915616
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.289533561
Short name T504
Test name
Test status
Simulation time 29416420095 ps
CPU time 125.21 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:39:11 PM PST 24
Peak memory 200000 kb
Host smart-ea106095-9ed6-41a1-a5cc-43d15a69a71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289533561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.289533561
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2075230176
Short name T61
Test name
Test status
Simulation time 2847047470 ps
CPU time 34.29 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:37:39 PM PST 24
Peak memory 200028 kb
Host smart-b062e428-b231-488b-9d4e-ee3d8d228a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075230176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2075230176
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1997598674
Short name T545
Test name
Test status
Simulation time 244934614 ps
CPU time 3.47 seconds
Started Mar 03 02:37:04 PM PST 24
Finished Mar 03 02:37:07 PM PST 24
Peak memory 199852 kb
Host smart-c7b3f6c7-41f1-4095-8661-03aeabb832f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997598674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1997598674
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2250295602
Short name T178
Test name
Test status
Simulation time 71963730803 ps
CPU time 187.4 seconds
Started Mar 03 02:37:14 PM PST 24
Finished Mar 03 02:40:21 PM PST 24
Peak memory 200024 kb
Host smart-2e79e551-05b7-4977-b43f-9d95f91cc920
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250295602 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2250295602
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.548030333
Short name T181
Test name
Test status
Simulation time 158030644 ps
CPU time 0.92 seconds
Started Mar 03 02:37:10 PM PST 24
Finished Mar 03 02:37:12 PM PST 24
Peak memory 198012 kb
Host smart-a0f1fd7e-6bc7-4b00-b7bb-4752f552ce58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548030333 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.548030333
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.464085792
Short name T423
Test name
Test status
Simulation time 7678730593 ps
CPU time 374.35 seconds
Started Mar 03 02:37:14 PM PST 24
Finished Mar 03 02:43:28 PM PST 24
Peak memory 199928 kb
Host smart-61bfce78-6e43-4c7c-a89e-035d42ff4bc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464085792 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.hmac_test_sha_vectors.464085792
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3304402703
Short name T22
Test name
Test status
Simulation time 3689035416 ps
CPU time 29.75 seconds
Started Mar 03 02:37:04 PM PST 24
Finished Mar 03 02:37:34 PM PST 24
Peak memory 200008 kb
Host smart-595edfbb-03f2-43ed-b74c-bbb8e7bc2569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304402703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3304402703
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1914113420
Short name T237
Test name
Test status
Simulation time 26140512 ps
CPU time 0.57 seconds
Started Mar 03 02:37:13 PM PST 24
Finished Mar 03 02:37:13 PM PST 24
Peak memory 194244 kb
Host smart-5ff1dda9-ec7b-4cff-b10e-51250252645d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914113420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1914113420
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3706619888
Short name T343
Test name
Test status
Simulation time 578892673 ps
CPU time 18.79 seconds
Started Mar 03 02:37:11 PM PST 24
Finished Mar 03 02:37:30 PM PST 24
Peak memory 199868 kb
Host smart-fb0916e5-f089-4b92-979f-8b2d54654c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706619888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3706619888
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1103295949
Short name T583
Test name
Test status
Simulation time 698852634 ps
CPU time 7.76 seconds
Started Mar 03 02:37:09 PM PST 24
Finished Mar 03 02:37:18 PM PST 24
Peak memory 199908 kb
Host smart-a00965d4-2680-4201-8445-e182524f86d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103295949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1103295949
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1166107043
Short name T444
Test name
Test status
Simulation time 13746928225 ps
CPU time 231.75 seconds
Started Mar 03 02:37:16 PM PST 24
Finished Mar 03 02:41:08 PM PST 24
Peak memory 199872 kb
Host smart-cad218b1-48a4-4c17-be96-9cf7892bd77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166107043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1166107043
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1837568595
Short name T263
Test name
Test status
Simulation time 13028593095 ps
CPU time 86.08 seconds
Started Mar 03 02:37:12 PM PST 24
Finished Mar 03 02:38:38 PM PST 24
Peak memory 199888 kb
Host smart-6f37a53d-90e6-42ef-a0c8-a67251f70666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837568595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1837568595
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1720441449
Short name T430
Test name
Test status
Simulation time 399825199 ps
CPU time 4.45 seconds
Started Mar 03 02:37:09 PM PST 24
Finished Mar 03 02:37:15 PM PST 24
Peak memory 199884 kb
Host smart-05b51fe0-b7b6-4408-a5c2-7dee15917e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720441449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1720441449
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.602168163
Short name T122
Test name
Test status
Simulation time 66843199798 ps
CPU time 554.68 seconds
Started Mar 03 02:37:11 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 208276 kb
Host smart-c3acb7ea-a900-41bf-bb60-30786b02aafd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602168163 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.602168163
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1751312561
Short name T175
Test name
Test status
Simulation time 109883268 ps
CPU time 0.97 seconds
Started Mar 03 02:37:09 PM PST 24
Finished Mar 03 02:37:12 PM PST 24
Peak memory 197352 kb
Host smart-13c21d46-7216-4e1c-a81f-8e155c8b4aa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751312561 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1751312561
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.470500306
Short name T9
Test name
Test status
Simulation time 29688390886 ps
CPU time 474.39 seconds
Started Mar 03 02:37:12 PM PST 24
Finished Mar 03 02:45:06 PM PST 24
Peak memory 199936 kb
Host smart-b02b21d3-549c-4404-990c-5468726b143c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470500306 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.hmac_test_sha_vectors.470500306
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1363335448
Short name T279
Test name
Test status
Simulation time 1528038806 ps
CPU time 61.53 seconds
Started Mar 03 02:37:15 PM PST 24
Finished Mar 03 02:38:17 PM PST 24
Peak memory 199912 kb
Host smart-9c3a44e7-53ce-4c29-a901-b250819b734b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363335448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1363335448
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1217371186
Short name T394
Test name
Test status
Simulation time 14025965 ps
CPU time 0.55 seconds
Started Mar 03 02:37:14 PM PST 24
Finished Mar 03 02:37:15 PM PST 24
Peak memory 194240 kb
Host smart-65821e4e-be7d-4c59-8d59-905646050386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217371186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1217371186
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1434743383
Short name T433
Test name
Test status
Simulation time 5339459918 ps
CPU time 45.88 seconds
Started Mar 03 02:37:15 PM PST 24
Finished Mar 03 02:38:01 PM PST 24
Peak memory 216132 kb
Host smart-ad746d67-85f6-4f94-b25c-e1c8fd5ba3e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434743383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1434743383
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3842535142
Short name T350
Test name
Test status
Simulation time 569424215 ps
CPU time 25.68 seconds
Started Mar 03 02:37:11 PM PST 24
Finished Mar 03 02:37:37 PM PST 24
Peak memory 199828 kb
Host smart-2f72c907-92db-4ff4-b25c-a6cd67895cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842535142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3842535142
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2612259672
Short name T113
Test name
Test status
Simulation time 4752230432 ps
CPU time 86.49 seconds
Started Mar 03 02:37:11 PM PST 24
Finished Mar 03 02:38:38 PM PST 24
Peak memory 199980 kb
Host smart-f7d8fcac-7eb9-4c0e-9cc5-863ed9d51583
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612259672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2612259672
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2073543517
Short name T163
Test name
Test status
Simulation time 2817795354 ps
CPU time 73.23 seconds
Started Mar 03 02:37:12 PM PST 24
Finished Mar 03 02:38:26 PM PST 24
Peak memory 200000 kb
Host smart-8b16ef68-e293-48f4-98b1-df9bc825640c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073543517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2073543517
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.802044426
Short name T23
Test name
Test status
Simulation time 417738068 ps
CPU time 11.79 seconds
Started Mar 03 02:37:12 PM PST 24
Finished Mar 03 02:37:24 PM PST 24
Peak memory 199892 kb
Host smart-e285f103-a926-4a75-9979-3fe5a037ad29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802044426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.802044426
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.4014444200
Short name T34
Test name
Test status
Simulation time 146746060 ps
CPU time 1.76 seconds
Started Mar 03 02:37:11 PM PST 24
Finished Mar 03 02:37:13 PM PST 24
Peak memory 199760 kb
Host smart-d8b31f1c-e8bc-4533-b97f-1b5377e2bbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014444200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4014444200
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1770589046
Short name T593
Test name
Test status
Simulation time 48698052207 ps
CPU time 195.88 seconds
Started Mar 03 02:37:14 PM PST 24
Finished Mar 03 02:40:30 PM PST 24
Peak memory 200028 kb
Host smart-b7bd4048-ffe1-48e3-a368-9d5ae2a49a01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770589046 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1770589046
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.414323203
Short name T7
Test name
Test status
Simulation time 56350910 ps
CPU time 1.18 seconds
Started Mar 03 02:37:11 PM PST 24
Finished Mar 03 02:37:12 PM PST 24
Peak memory 199676 kb
Host smart-dd46c4af-12d2-45ad-99eb-ea9245b079be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414323203 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.414323203
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.3163798952
Short name T548
Test name
Test status
Simulation time 7568958576 ps
CPU time 391.26 seconds
Started Mar 03 02:37:12 PM PST 24
Finished Mar 03 02:43:43 PM PST 24
Peak memory 199932 kb
Host smart-d51b5f7c-5cf5-45e8-b14a-0943cdc0272e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163798952 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_sha_vectors.3163798952
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4235845516
Short name T401
Test name
Test status
Simulation time 5162342016 ps
CPU time 63.46 seconds
Started Mar 03 02:37:14 PM PST 24
Finished Mar 03 02:38:17 PM PST 24
Peak memory 199944 kb
Host smart-b798a6cb-bc41-4799-b071-ae5be47fc751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235845516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4235845516
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1672720622
Short name T13
Test name
Test status
Simulation time 28274628 ps
CPU time 0.54 seconds
Started Mar 03 02:37:18 PM PST 24
Finished Mar 03 02:37:19 PM PST 24
Peak memory 194248 kb
Host smart-105d155f-de4d-4712-b74d-d18b9d747d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672720622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1672720622
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2876314982
Short name T127
Test name
Test status
Simulation time 5411237055 ps
CPU time 36.96 seconds
Started Mar 03 02:37:12 PM PST 24
Finished Mar 03 02:37:50 PM PST 24
Peak memory 200036 kb
Host smart-6a344fd1-29b3-42a4-9ab0-3ab65865a528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876314982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2876314982
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.4153050809
Short name T209
Test name
Test status
Simulation time 2638865044 ps
CPU time 23.14 seconds
Started Mar 03 02:37:19 PM PST 24
Finished Mar 03 02:37:43 PM PST 24
Peak memory 199936 kb
Host smart-3cce6cab-16a7-494d-852f-0d0d92037068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153050809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4153050809
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2328547592
Short name T118
Test name
Test status
Simulation time 8838542774 ps
CPU time 154.74 seconds
Started Mar 03 02:37:17 PM PST 24
Finished Mar 03 02:39:52 PM PST 24
Peak memory 199984 kb
Host smart-feae9ea7-9af1-4e3a-9fe7-550ce1ebda2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2328547592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2328547592
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2413594919
Short name T514
Test name
Test status
Simulation time 17990526927 ps
CPU time 230.63 seconds
Started Mar 03 02:37:17 PM PST 24
Finished Mar 03 02:41:07 PM PST 24
Peak memory 199984 kb
Host smart-16b5c9b9-7f59-4a9f-959a-2305910a3f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413594919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2413594919
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2371715144
Short name T448
Test name
Test status
Simulation time 234893514 ps
CPU time 2.46 seconds
Started Mar 03 02:37:12 PM PST 24
Finished Mar 03 02:37:15 PM PST 24
Peak memory 199880 kb
Host smart-b3bc2484-3405-4b58-95ec-7253d8df1aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371715144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2371715144
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1193709301
Short name T322
Test name
Test status
Simulation time 332822127 ps
CPU time 3.86 seconds
Started Mar 03 02:37:11 PM PST 24
Finished Mar 03 02:37:15 PM PST 24
Peak memory 199856 kb
Host smart-984f2ac5-5664-446d-8bec-e988400f61d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193709301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1193709301
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3032959008
Short name T358
Test name
Test status
Simulation time 61718830430 ps
CPU time 432.54 seconds
Started Mar 03 02:37:19 PM PST 24
Finished Mar 03 02:44:31 PM PST 24
Peak memory 200116 kb
Host smart-d71124c6-6a10-4dae-ab0a-daed116efd8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032959008 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3032959008
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.878809096
Short name T446
Test name
Test status
Simulation time 34196516 ps
CPU time 1.17 seconds
Started Mar 03 02:37:17 PM PST 24
Finished Mar 03 02:37:18 PM PST 24
Peak memory 198492 kb
Host smart-1e4586a9-fedd-4cdf-becb-616d5adbcd58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878809096 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_hmac_vectors.878809096
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2870904135
Short name T595
Test name
Test status
Simulation time 90058272469 ps
CPU time 509.94 seconds
Started Mar 03 02:37:18 PM PST 24
Finished Mar 03 02:45:48 PM PST 24
Peak memory 199972 kb
Host smart-21895541-d5a4-4b25-a4fe-757fbef981d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870904135 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.2870904135
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3805068609
Short name T192
Test name
Test status
Simulation time 4351956351 ps
CPU time 75.6 seconds
Started Mar 03 02:37:16 PM PST 24
Finished Mar 03 02:38:32 PM PST 24
Peak memory 199908 kb
Host smart-c2d9e2cc-cee8-4265-8d63-9372f2b91c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805068609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3805068609
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3216776208
Short name T221
Test name
Test status
Simulation time 20752007 ps
CPU time 0.59 seconds
Started Mar 03 02:37:16 PM PST 24
Finished Mar 03 02:37:17 PM PST 24
Peak memory 194444 kb
Host smart-1d4a0cae-ee37-452f-a274-d231e2a59d38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216776208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3216776208
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2046434079
Short name T522
Test name
Test status
Simulation time 4382220701 ps
CPU time 41.3 seconds
Started Mar 03 02:37:18 PM PST 24
Finished Mar 03 02:37:59 PM PST 24
Peak memory 221636 kb
Host smart-bec65863-10d1-44d3-ba51-cdd3446111ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046434079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2046434079
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.743694375
Short name T206
Test name
Test status
Simulation time 1334706429 ps
CPU time 16.12 seconds
Started Mar 03 02:37:21 PM PST 24
Finished Mar 03 02:37:37 PM PST 24
Peak memory 199788 kb
Host smart-7b3d522e-9cac-43f5-b844-2d3cc4f6a0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743694375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.743694375
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.4242379581
Short name T409
Test name
Test status
Simulation time 1070662173 ps
CPU time 61.83 seconds
Started Mar 03 02:37:24 PM PST 24
Finished Mar 03 02:38:26 PM PST 24
Peak memory 199844 kb
Host smart-5b32eee8-1c93-49a2-97c3-7969ca8247ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4242379581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.4242379581
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.880463634
Short name T391
Test name
Test status
Simulation time 88808007684 ps
CPU time 134.04 seconds
Started Mar 03 02:37:17 PM PST 24
Finished Mar 03 02:39:31 PM PST 24
Peak memory 199944 kb
Host smart-c74ebca4-6d10-4538-bd6e-187a926625ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880463634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.880463634
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2668551106
Short name T215
Test name
Test status
Simulation time 18074451693 ps
CPU time 38.56 seconds
Started Mar 03 02:37:19 PM PST 24
Finished Mar 03 02:37:58 PM PST 24
Peak memory 199944 kb
Host smart-d000ade3-da72-4625-95fd-6ff9b0697771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668551106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2668551106
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.35223880
Short name T470
Test name
Test status
Simulation time 129053299 ps
CPU time 3.33 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 02:37:30 PM PST 24
Peak memory 199904 kb
Host smart-a2558abb-3a86-4edb-a854-2c1600097731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35223880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.35223880
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2010903944
Short name T71
Test name
Test status
Simulation time 98585532256 ps
CPU time 1358.63 seconds
Started Mar 03 02:37:18 PM PST 24
Finished Mar 03 02:59:57 PM PST 24
Peak memory 240244 kb
Host smart-5535d9e9-d6cb-4cda-aab3-976d9c3af126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010903944 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2010903944
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.4121653802
Short name T248
Test name
Test status
Simulation time 54824876 ps
CPU time 1.08 seconds
Started Mar 03 02:37:17 PM PST 24
Finished Mar 03 02:37:19 PM PST 24
Peak memory 198376 kb
Host smart-2a603ec5-f3f0-40a7-8303-427f0819edbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121653802 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.4121653802
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.31374159
Short name T518
Test name
Test status
Simulation time 104136436817 ps
CPU time 458.02 seconds
Started Mar 03 02:37:22 PM PST 24
Finished Mar 03 02:45:01 PM PST 24
Peak memory 199912 kb
Host smart-fd7436b1-3663-4666-a230-5acfc5ea42eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31374159 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.hmac_test_sha_vectors.31374159
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1136151138
Short name T434
Test name
Test status
Simulation time 1582818913 ps
CPU time 33.57 seconds
Started Mar 03 02:37:17 PM PST 24
Finished Mar 03 02:37:51 PM PST 24
Peak memory 199920 kb
Host smart-501ca203-34c9-4108-9fb9-64a37d07722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136151138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1136151138
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1632389028
Short name T424
Test name
Test status
Simulation time 35016576 ps
CPU time 0.57 seconds
Started Mar 03 02:37:24 PM PST 24
Finished Mar 03 02:37:25 PM PST 24
Peak memory 194200 kb
Host smart-fe0bb19e-54ed-4b80-a552-fbb183db1afe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632389028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1632389028
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3927524323
Short name T575
Test name
Test status
Simulation time 260471387 ps
CPU time 4.57 seconds
Started Mar 03 02:37:17 PM PST 24
Finished Mar 03 02:37:22 PM PST 24
Peak memory 215212 kb
Host smart-72cdea7a-53c0-4b01-b207-9721db5d56bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927524323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3927524323
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.4065890151
Short name T373
Test name
Test status
Simulation time 5356257975 ps
CPU time 43.15 seconds
Started Mar 03 02:37:23 PM PST 24
Finished Mar 03 02:38:06 PM PST 24
Peak memory 199980 kb
Host smart-7589821f-83a2-430c-9227-5112c3150d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065890151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.4065890151
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3811290027
Short name T360
Test name
Test status
Simulation time 4815635988 ps
CPU time 64.16 seconds
Started Mar 03 02:37:25 PM PST 24
Finished Mar 03 02:38:30 PM PST 24
Peak memory 199988 kb
Host smart-a68e08db-9db6-41a5-8623-4134716ff671
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3811290027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3811290027
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2090618396
Short name T293
Test name
Test status
Simulation time 939437004 ps
CPU time 47.08 seconds
Started Mar 03 02:37:16 PM PST 24
Finished Mar 03 02:38:04 PM PST 24
Peak memory 199856 kb
Host smart-bb0cac77-a7e7-4965-847a-07fee2b6da73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090618396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2090618396
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1258776875
Short name T326
Test name
Test status
Simulation time 462438462 ps
CPU time 12.18 seconds
Started Mar 03 02:37:22 PM PST 24
Finished Mar 03 02:37:34 PM PST 24
Peak memory 199848 kb
Host smart-63092178-fe4b-4d38-a86f-4d4ec4d52f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258776875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1258776875
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1610094430
Short name T81
Test name
Test status
Simulation time 644196302 ps
CPU time 4.43 seconds
Started Mar 03 02:37:16 PM PST 24
Finished Mar 03 02:37:20 PM PST 24
Peak memory 199868 kb
Host smart-bef7e6f5-f97f-44c3-8718-de9d18c5a935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610094430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1610094430
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.4105390900
Short name T400
Test name
Test status
Simulation time 18869241879 ps
CPU time 989.38 seconds
Started Mar 03 02:37:24 PM PST 24
Finished Mar 03 02:53:54 PM PST 24
Peak memory 200072 kb
Host smart-61ee69aa-f175-4250-9a6c-ce2f35155733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105390900 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.4105390900
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3037678966
Short name T151
Test name
Test status
Simulation time 737886759 ps
CPU time 1.17 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:37:33 PM PST 24
Peak memory 198996 kb
Host smart-c2f88e7f-b842-4181-bf1d-2fb0e4ad5044
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037678966 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3037678966
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1669371555
Short name T287
Test name
Test status
Simulation time 42804432867 ps
CPU time 503 seconds
Started Mar 03 02:37:28 PM PST 24
Finished Mar 03 02:45:51 PM PST 24
Peak memory 199844 kb
Host smart-18aed59a-75c6-44f5-9e0d-715d431f1d40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669371555 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.1669371555
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.42569478
Short name T162
Test name
Test status
Simulation time 5136083808 ps
CPU time 69.9 seconds
Started Mar 03 02:37:30 PM PST 24
Finished Mar 03 02:38:41 PM PST 24
Peak memory 199960 kb
Host smart-12ba15f3-a0bf-4c25-ac35-11530eb94ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42569478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.42569478
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4222689807
Short name T321
Test name
Test status
Simulation time 13998817 ps
CPU time 0.58 seconds
Started Mar 03 02:37:30 PM PST 24
Finished Mar 03 02:37:32 PM PST 24
Peak memory 194156 kb
Host smart-f68ce03f-fa63-4455-978b-0663aa7dc2a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222689807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4222689807
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3994005828
Short name T317
Test name
Test status
Simulation time 1577926485 ps
CPU time 55.25 seconds
Started Mar 03 02:37:26 PM PST 24
Finished Mar 03 02:38:22 PM PST 24
Peak memory 232692 kb
Host smart-feb455a0-b924-4402-8fef-7288b55720c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994005828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3994005828
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3731088454
Short name T134
Test name
Test status
Simulation time 2873123298 ps
CPU time 79.7 seconds
Started Mar 03 02:37:26 PM PST 24
Finished Mar 03 02:38:46 PM PST 24
Peak memory 200004 kb
Host smart-264fcfb5-2ac7-4a80-8707-308f7bc10b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731088454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3731088454
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.337371988
Short name T556
Test name
Test status
Simulation time 7168481866 ps
CPU time 97.66 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 02:39:05 PM PST 24
Peak memory 199932 kb
Host smart-5ee56ddc-909b-4651-b30a-2153cd1fe062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337371988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.337371988
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4065859702
Short name T123
Test name
Test status
Simulation time 1739164045 ps
CPU time 48.15 seconds
Started Mar 03 02:37:24 PM PST 24
Finished Mar 03 02:38:13 PM PST 24
Peak memory 199892 kb
Host smart-7bfe200c-6c18-40b3-b08c-e6b6e71a3492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065859702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4065859702
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2891007155
Short name T176
Test name
Test status
Simulation time 164981113 ps
CPU time 3.95 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 02:37:31 PM PST 24
Peak memory 199816 kb
Host smart-6432b1e6-9432-4864-a532-6833a4ce5d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891007155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2891007155
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2443410313
Short name T513
Test name
Test status
Simulation time 56086241247 ps
CPU time 252.63 seconds
Started Mar 03 02:37:20 PM PST 24
Finished Mar 03 02:41:33 PM PST 24
Peak memory 200048 kb
Host smart-63708528-7983-4406-806e-832aae5146eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443410313 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2443410313
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.281196087
Short name T161
Test name
Test status
Simulation time 211543113 ps
CPU time 1.2 seconds
Started Mar 03 02:37:24 PM PST 24
Finished Mar 03 02:37:26 PM PST 24
Peak memory 198828 kb
Host smart-9cab2194-6472-44a9-a094-a1e63c2c193e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281196087 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.281196087
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.276136305
Short name T592
Test name
Test status
Simulation time 26501661003 ps
CPU time 462.58 seconds
Started Mar 03 02:37:25 PM PST 24
Finished Mar 03 02:45:09 PM PST 24
Peak memory 199932 kb
Host smart-04d799c3-ce73-4905-b7fb-309e0508239b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276136305 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.hmac_test_sha_vectors.276136305
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_alert_test.268242858
Short name T236
Test name
Test status
Simulation time 23752529 ps
CPU time 0.58 seconds
Started Mar 03 02:36:51 PM PST 24
Finished Mar 03 02:36:51 PM PST 24
Peak memory 195220 kb
Host smart-418ea7b5-b242-470c-ad92-5d909169c97c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268242858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.268242858
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1179624290
Short name T341
Test name
Test status
Simulation time 3721376759 ps
CPU time 65.26 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:37:54 PM PST 24
Peak memory 228612 kb
Host smart-2c51293a-b5c9-4164-a8a7-45941a9fe816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179624290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1179624290
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.296506198
Short name T380
Test name
Test status
Simulation time 1928271902 ps
CPU time 18.25 seconds
Started Mar 03 02:36:54 PM PST 24
Finished Mar 03 02:37:13 PM PST 24
Peak memory 199856 kb
Host smart-1aa6df12-6e2c-47fc-ae61-cae7fb2b9a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296506198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.296506198
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1658388746
Short name T304
Test name
Test status
Simulation time 9270194856 ps
CPU time 123.01 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:38:52 PM PST 24
Peak memory 199992 kb
Host smart-f19d7edc-2b39-4e46-bb42-aa6d1f119ea7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1658388746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1658388746
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1424883450
Short name T418
Test name
Test status
Simulation time 3116777271 ps
CPU time 155.42 seconds
Started Mar 03 02:36:48 PM PST 24
Finished Mar 03 02:39:24 PM PST 24
Peak memory 199960 kb
Host smart-0dbe884c-001a-404f-b19c-6b25494c623d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424883450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1424883450
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2229227803
Short name T42
Test name
Test status
Simulation time 918388894 ps
CPU time 50.08 seconds
Started Mar 03 02:36:51 PM PST 24
Finished Mar 03 02:37:41 PM PST 24
Peak memory 199880 kb
Host smart-4ad1338d-05e3-4eac-8d67-fabcb0ea4dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229227803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2229227803
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2111597496
Short name T26
Test name
Test status
Simulation time 99932138 ps
CPU time 0.95 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:36:50 PM PST 24
Peak memory 218196 kb
Host smart-7c489149-776b-47ab-99ca-71680a346633
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111597496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2111597496
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2040217165
Short name T339
Test name
Test status
Simulation time 471578436 ps
CPU time 1.55 seconds
Started Mar 03 02:36:48 PM PST 24
Finished Mar 03 02:36:50 PM PST 24
Peak memory 199732 kb
Host smart-e8eadcf1-7091-4f22-a5cb-46adbc03aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040217165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2040217165
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3187072414
Short name T364
Test name
Test status
Simulation time 29439373828 ps
CPU time 736.13 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:49:05 PM PST 24
Peak memory 209896 kb
Host smart-8641ad0a-fb10-483e-8d9c-55978fb87abe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187072414 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3187072414
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.185607893
Short name T195
Test name
Test status
Simulation time 95856863 ps
CPU time 1.09 seconds
Started Mar 03 02:36:50 PM PST 24
Finished Mar 03 02:36:51 PM PST 24
Peak memory 198348 kb
Host smart-318b96e6-9b97-4c84-9993-a31d40754f4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185607893 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.185607893
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.686553864
Short name T393
Test name
Test status
Simulation time 24635774598 ps
CPU time 398.11 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:43:27 PM PST 24
Peak memory 199924 kb
Host smart-ba9bca3f-8364-4bb0-afcf-87bdd765f939
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686553864 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.hmac_test_sha_vectors.686553864
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.457345866
Short name T313
Test name
Test status
Simulation time 7501423385 ps
CPU time 27.82 seconds
Started Mar 03 02:36:53 PM PST 24
Finished Mar 03 02:37:21 PM PST 24
Peak memory 200008 kb
Host smart-9c1ab70d-5f9a-46a7-9a5b-7091a869b302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457345866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.457345866
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2087787920
Short name T340
Test name
Test status
Simulation time 13950545 ps
CPU time 0.6 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:37:31 PM PST 24
Peak memory 194356 kb
Host smart-4c1ff63f-46a5-40d7-b0ac-ca9a6f1bd3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087787920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2087787920
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3781616923
Short name T158
Test name
Test status
Simulation time 1408745761 ps
CPU time 47.74 seconds
Started Mar 03 02:37:24 PM PST 24
Finished Mar 03 02:38:12 PM PST 24
Peak memory 222084 kb
Host smart-a4dd4c43-370a-4b7f-9a11-4741adecde0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781616923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3781616923
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3461437140
Short name T271
Test name
Test status
Simulation time 4354131093 ps
CPU time 31.48 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:38:02 PM PST 24
Peak memory 200188 kb
Host smart-cd118b00-89f1-49fe-8fa6-88e092571527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461437140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3461437140
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1499983352
Short name T184
Test name
Test status
Simulation time 1245816471 ps
CPU time 37.03 seconds
Started Mar 03 02:37:25 PM PST 24
Finished Mar 03 02:38:02 PM PST 24
Peak memory 199844 kb
Host smart-fcece7b7-eed1-427c-8c95-67ab0f49fc2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499983352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1499983352
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.4022503244
Short name T408
Test name
Test status
Simulation time 168175404 ps
CPU time 8.25 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 02:37:36 PM PST 24
Peak memory 199728 kb
Host smart-39f4915a-f4cf-408b-8417-ab282a1665f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022503244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.4022503244
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.4105453688
Short name T535
Test name
Test status
Simulation time 4709998956 ps
CPU time 52.02 seconds
Started Mar 03 02:37:26 PM PST 24
Finished Mar 03 02:38:18 PM PST 24
Peak memory 199984 kb
Host smart-38ddd5a8-06aa-40f4-ae84-c606af7223c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105453688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.4105453688
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4090449243
Short name T16
Test name
Test status
Simulation time 446610672 ps
CPU time 1.62 seconds
Started Mar 03 02:37:28 PM PST 24
Finished Mar 03 02:37:31 PM PST 24
Peak memory 199872 kb
Host smart-6e0b8309-0c2a-4f45-9214-c858fa838ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090449243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4090449243
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.624825990
Short name T458
Test name
Test status
Simulation time 7862495847 ps
CPU time 108.31 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 02:39:16 PM PST 24
Peak memory 200036 kb
Host smart-d5123df5-2d3e-444b-9876-716bde9e1e3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624825990 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.624825990
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3746447810
Short name T242
Test name
Test status
Simulation time 43674279 ps
CPU time 1.01 seconds
Started Mar 03 02:37:28 PM PST 24
Finished Mar 03 02:37:29 PM PST 24
Peak memory 198432 kb
Host smart-bf30a49c-ec5b-4c75-8185-76dd951841c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746447810 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3746447810
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1759028886
Short name T439
Test name
Test status
Simulation time 6894543968 ps
CPU time 354.7 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 02:43:22 PM PST 24
Peak memory 199988 kb
Host smart-ff80636d-f73a-4bb3-a904-5bb26616e194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759028886 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.1759028886
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1393486221
Short name T35
Test name
Test status
Simulation time 2087521132 ps
CPU time 65.71 seconds
Started Mar 03 02:37:23 PM PST 24
Finished Mar 03 02:38:30 PM PST 24
Peak memory 199852 kb
Host smart-e467f1a7-cab5-4630-a51d-38b516c2b90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393486221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1393486221
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2516102688
Short name T283
Test name
Test status
Simulation time 46101114 ps
CPU time 0.58 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:37:31 PM PST 24
Peak memory 194148 kb
Host smart-a512c45f-f486-4dcb-b61f-c0f0eb00d2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516102688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2516102688
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3670874510
Short name T431
Test name
Test status
Simulation time 415754682 ps
CPU time 13.9 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 02:37:42 PM PST 24
Peak memory 208132 kb
Host smart-50940b4e-d37f-4702-be71-ef498bb6a104
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3670874510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3670874510
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1357685757
Short name T154
Test name
Test status
Simulation time 2183907032 ps
CPU time 55.59 seconds
Started Mar 03 02:37:26 PM PST 24
Finished Mar 03 02:38:22 PM PST 24
Peak memory 200000 kb
Host smart-efb5d3c4-d261-426e-aa03-ac2c69c0ff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357685757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1357685757
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1386099203
Short name T474
Test name
Test status
Simulation time 2389554204 ps
CPU time 122.13 seconds
Started Mar 03 02:37:30 PM PST 24
Finished Mar 03 02:39:34 PM PST 24
Peak memory 199864 kb
Host smart-9c512441-6d6e-4b6f-a14b-3325801875e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386099203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1386099203
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.4272446832
Short name T222
Test name
Test status
Simulation time 13312162294 ps
CPU time 174.45 seconds
Started Mar 03 02:37:24 PM PST 24
Finished Mar 03 02:40:19 PM PST 24
Peak memory 199896 kb
Host smart-577bef85-7fb3-4a2c-9e5c-199efd015d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272446832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.4272446832
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2666580054
Short name T241
Test name
Test status
Simulation time 220666557 ps
CPU time 12.35 seconds
Started Mar 03 02:37:28 PM PST 24
Finished Mar 03 02:37:40 PM PST 24
Peak memory 199924 kb
Host smart-65ec7286-c04b-425b-be26-d527a3b64fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666580054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2666580054
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1433948339
Short name T566
Test name
Test status
Simulation time 55032660 ps
CPU time 1.5 seconds
Started Mar 03 02:37:26 PM PST 24
Finished Mar 03 02:37:28 PM PST 24
Peak memory 199704 kb
Host smart-46489e03-e36c-4d5c-bfff-57c450a65ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433948339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1433948339
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.218485604
Short name T291
Test name
Test status
Simulation time 58849042991 ps
CPU time 264.31 seconds
Started Mar 03 02:37:24 PM PST 24
Finished Mar 03 02:41:49 PM PST 24
Peak memory 200060 kb
Host smart-69106305-2325-4a04-8c9d-75b386f7d33f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218485604 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.218485604
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2731512841
Short name T203
Test name
Test status
Simulation time 268940985 ps
CPU time 1.22 seconds
Started Mar 03 02:37:30 PM PST 24
Finished Mar 03 02:37:33 PM PST 24
Peak memory 198660 kb
Host smart-07cf45bd-2836-4977-8f37-719b0ab05999
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731512841 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2731512841
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2062875973
Short name T337
Test name
Test status
Simulation time 47096871696 ps
CPU time 407.27 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:44:18 PM PST 24
Peak memory 200124 kb
Host smart-d1f9c8ec-c34d-4ca9-9912-e3df9cfcb935
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062875973 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.2062875973
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2010687174
Short name T594
Test name
Test status
Simulation time 17243516427 ps
CPU time 69.69 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 02:38:37 PM PST 24
Peak memory 200000 kb
Host smart-f7422907-40fd-4f45-83aa-085f34d9b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010687174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2010687174
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3168703762
Short name T29
Test name
Test status
Simulation time 16587141 ps
CPU time 0.54 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 02:37:28 PM PST 24
Peak memory 194388 kb
Host smart-f00fd29d-a25e-4e16-81c6-ffde21b4b331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168703762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3168703762
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3955493413
Short name T266
Test name
Test status
Simulation time 4849328273 ps
CPU time 49.25 seconds
Started Mar 03 02:37:33 PM PST 24
Finished Mar 03 02:38:23 PM PST 24
Peak memory 230472 kb
Host smart-aeee824e-7092-46e2-9855-8f506b525719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955493413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3955493413
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1588048668
Short name T443
Test name
Test status
Simulation time 1694599115 ps
CPU time 20.57 seconds
Started Mar 03 02:37:28 PM PST 24
Finished Mar 03 02:37:49 PM PST 24
Peak memory 199868 kb
Host smart-642f918d-a296-4962-aa0a-a06ef4f19fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588048668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1588048668
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.274091229
Short name T379
Test name
Test status
Simulation time 9117712616 ps
CPU time 118.03 seconds
Started Mar 03 02:37:38 PM PST 24
Finished Mar 03 02:39:37 PM PST 24
Peak memory 199928 kb
Host smart-298dae24-a591-4413-867e-e133f5d42979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=274091229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.274091229
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2883768979
Short name T204
Test name
Test status
Simulation time 366674368 ps
CPU time 19.47 seconds
Started Mar 03 02:37:31 PM PST 24
Finished Mar 03 02:37:51 PM PST 24
Peak memory 199708 kb
Host smart-a12ea898-d8fa-44a4-9e15-9d5b0cf1b68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883768979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2883768979
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.4097616592
Short name T517
Test name
Test status
Simulation time 3365739135 ps
CPU time 67.02 seconds
Started Mar 03 02:37:33 PM PST 24
Finished Mar 03 02:38:41 PM PST 24
Peak memory 200076 kb
Host smart-b283d284-b2a7-4091-833d-69a1ecdc79c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097616592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.4097616592
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1676876434
Short name T349
Test name
Test status
Simulation time 43081895 ps
CPU time 0.95 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:37:31 PM PST 24
Peak memory 198708 kb
Host smart-0902c875-17a6-442e-b35a-8b89aff155a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676876434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1676876434
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.4186368156
Short name T407
Test name
Test status
Simulation time 70053074 ps
CPU time 1.19 seconds
Started Mar 03 02:37:28 PM PST 24
Finished Mar 03 02:37:29 PM PST 24
Peak memory 199420 kb
Host smart-3350c90e-fa14-4e84-88a2-28cc9c4bc947
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186368156 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.4186368156
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2705000631
Short name T381
Test name
Test status
Simulation time 10487143554 ps
CPU time 73.31 seconds
Started Mar 03 02:37:30 PM PST 24
Finished Mar 03 02:38:45 PM PST 24
Peak memory 200240 kb
Host smart-34e1cf5d-9c30-4bdb-80ef-0cf9e89ae416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705000631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2705000631
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.4154360870
Short name T316
Test name
Test status
Simulation time 11593144 ps
CPU time 0.55 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:37:32 PM PST 24
Peak memory 194432 kb
Host smart-6753e0b2-8657-4af2-8444-feb981d88f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154360870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4154360870
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1892915055
Short name T477
Test name
Test status
Simulation time 8338538742 ps
CPU time 56.05 seconds
Started Mar 03 02:37:33 PM PST 24
Finished Mar 03 02:38:30 PM PST 24
Peak memory 222560 kb
Host smart-951e654d-f452-4ef7-b6fd-dc35159c35ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892915055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1892915055
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.450924934
Short name T537
Test name
Test status
Simulation time 1281024796 ps
CPU time 41.04 seconds
Started Mar 03 02:37:32 PM PST 24
Finished Mar 03 02:38:13 PM PST 24
Peak memory 199796 kb
Host smart-fda624c8-4c3e-4d5f-a0c4-f8b9b3899fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450924934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.450924934
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2013196722
Short name T377
Test name
Test status
Simulation time 1176381387 ps
CPU time 61.1 seconds
Started Mar 03 02:37:28 PM PST 24
Finished Mar 03 02:38:29 PM PST 24
Peak memory 199860 kb
Host smart-900791eb-4774-4999-b023-274940aaeb57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013196722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2013196722
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2449947886
Short name T588
Test name
Test status
Simulation time 12339192856 ps
CPU time 163.54 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:40:14 PM PST 24
Peak memory 200024 kb
Host smart-b49585ea-2951-4cbc-920f-1fab9e7702fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449947886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2449947886
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2836260469
Short name T496
Test name
Test status
Simulation time 1725807406 ps
CPU time 97.09 seconds
Started Mar 03 02:37:33 PM PST 24
Finished Mar 03 02:39:10 PM PST 24
Peak memory 199836 kb
Host smart-a2d3c09e-d39c-4c88-a7ed-54a0fd0aaf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836260469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2836260469
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.443692222
Short name T384
Test name
Test status
Simulation time 27651984 ps
CPU time 0.65 seconds
Started Mar 03 02:37:31 PM PST 24
Finished Mar 03 02:37:33 PM PST 24
Peak memory 195184 kb
Host smart-0829d3a4-31c3-48cc-8b98-618716a9b3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443692222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.443692222
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.7136875
Short name T104
Test name
Test status
Simulation time 53565182724 ps
CPU time 674.22 seconds
Started Mar 03 02:37:33 PM PST 24
Finished Mar 03 02:48:48 PM PST 24
Peak memory 215844 kb
Host smart-05448635-e09e-4e30-90d7-1040d456a1d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7136875 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.7136875
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.701096657
Short name T297
Test name
Test status
Simulation time 59843604 ps
CPU time 1.13 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:37:32 PM PST 24
Peak memory 198480 kb
Host smart-88e5fe89-c76b-4c6b-b714-0eec7ead2ec8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701096657 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.701096657
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.2566857171
Short name T290
Test name
Test status
Simulation time 42182936296 ps
CPU time 513.25 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 199916 kb
Host smart-dfee3040-99db-4731-8da6-698f7475652b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566857171 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.2566857171
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3296714723
Short name T232
Test name
Test status
Simulation time 6019226736 ps
CPU time 63.95 seconds
Started Mar 03 02:37:34 PM PST 24
Finished Mar 03 02:38:39 PM PST 24
Peak memory 199988 kb
Host smart-c04cdbcb-9840-4ea2-a171-bcb21d7fd9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296714723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3296714723
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2074918918
Short name T183
Test name
Test status
Simulation time 13692453 ps
CPU time 0.58 seconds
Started Mar 03 02:37:30 PM PST 24
Finished Mar 03 02:37:32 PM PST 24
Peak memory 194428 kb
Host smart-50b6edda-dced-4dab-bf1d-99b70d6edf37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074918918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2074918918
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.449842736
Short name T524
Test name
Test status
Simulation time 2365663099 ps
CPU time 39.9 seconds
Started Mar 03 02:37:31 PM PST 24
Finished Mar 03 02:38:12 PM PST 24
Peak memory 210124 kb
Host smart-9f7b5a3b-b49d-4dff-bdf9-2a0d331e905d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449842736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.449842736
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1825780697
Short name T475
Test name
Test status
Simulation time 3607825983 ps
CPU time 17.79 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:37:48 PM PST 24
Peak memory 199980 kb
Host smart-78f114c4-7a6b-4427-8ba5-d7530f4d515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825780697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1825780697
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3522627045
Short name T361
Test name
Test status
Simulation time 19112616 ps
CPU time 0.72 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:37:32 PM PST 24
Peak memory 195608 kb
Host smart-31bb5ab6-16e4-47db-8236-c0c799e88ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522627045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3522627045
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.642060979
Short name T562
Test name
Test status
Simulation time 7396938587 ps
CPU time 99.21 seconds
Started Mar 03 02:37:35 PM PST 24
Finished Mar 03 02:39:14 PM PST 24
Peak memory 199940 kb
Host smart-1615d3a2-16d0-44c2-abd0-539aa94a4eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642060979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.642060979
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2395793555
Short name T246
Test name
Test status
Simulation time 28037001098 ps
CPU time 43.82 seconds
Started Mar 03 02:37:32 PM PST 24
Finished Mar 03 02:38:17 PM PST 24
Peak memory 199956 kb
Host smart-abfe6131-8859-4746-86bc-e573917ad66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395793555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2395793555
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1089957768
Short name T150
Test name
Test status
Simulation time 849384074 ps
CPU time 2.21 seconds
Started Mar 03 02:37:28 PM PST 24
Finished Mar 03 02:37:30 PM PST 24
Peak memory 199844 kb
Host smart-6c2d322f-d761-4732-909f-cc81304cf5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089957768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1089957768
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1018791549
Short name T70
Test name
Test status
Simulation time 113206277475 ps
CPU time 1314.1 seconds
Started Mar 03 02:37:33 PM PST 24
Finished Mar 03 02:59:27 PM PST 24
Peak memory 215532 kb
Host smart-bfd976cf-df66-4c37-aa5a-bde1b8e4973f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018791549 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1018791549
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1575079885
Short name T398
Test name
Test status
Simulation time 28609921 ps
CPU time 1.05 seconds
Started Mar 03 02:37:28 PM PST 24
Finished Mar 03 02:37:29 PM PST 24
Peak memory 198528 kb
Host smart-90c422f2-0316-43ce-a415-e71700b65801
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575079885 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1575079885
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3994639609
Short name T78
Test name
Test status
Simulation time 222937239 ps
CPU time 11.71 seconds
Started Mar 03 02:37:29 PM PST 24
Finished Mar 03 02:37:43 PM PST 24
Peak memory 199840 kb
Host smart-3682dcd8-4ba1-43f8-a371-e01bbd785203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994639609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3994639609
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3370088615
Short name T550
Test name
Test status
Simulation time 42631210 ps
CPU time 0.59 seconds
Started Mar 03 02:37:38 PM PST 24
Finished Mar 03 02:37:40 PM PST 24
Peak memory 195512 kb
Host smart-0fc29fe2-5c6e-466b-910c-b7ba255bac18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370088615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3370088615
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1944755244
Short name T488
Test name
Test status
Simulation time 196133683 ps
CPU time 3.38 seconds
Started Mar 03 02:37:35 PM PST 24
Finished Mar 03 02:37:39 PM PST 24
Peak memory 199932 kb
Host smart-75262ec3-04fa-49b7-8305-b33e8984fa27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944755244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1944755244
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2670665433
Short name T278
Test name
Test status
Simulation time 4134296814 ps
CPU time 48.6 seconds
Started Mar 03 02:37:37 PM PST 24
Finished Mar 03 02:38:26 PM PST 24
Peak memory 200000 kb
Host smart-66364273-7f55-40bd-9e88-66ab4322b14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670665433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2670665433
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.703216726
Short name T461
Test name
Test status
Simulation time 10280863963 ps
CPU time 138.47 seconds
Started Mar 03 02:37:36 PM PST 24
Finished Mar 03 02:39:55 PM PST 24
Peak memory 200028 kb
Host smart-2d5702b5-d65c-4c48-8bdb-829fa2aaef66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=703216726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.703216726
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.860102905
Short name T392
Test name
Test status
Simulation time 10543239551 ps
CPU time 131.67 seconds
Started Mar 03 02:37:35 PM PST 24
Finished Mar 03 02:39:47 PM PST 24
Peak memory 200036 kb
Host smart-53a690dc-94eb-4410-a0f0-d98ecdfeaa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860102905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.860102905
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2505857885
Short name T383
Test name
Test status
Simulation time 15468082764 ps
CPU time 13.27 seconds
Started Mar 03 02:37:39 PM PST 24
Finished Mar 03 02:37:55 PM PST 24
Peak memory 200016 kb
Host smart-7e8731f9-1220-457d-a5db-570323c2ad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505857885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2505857885
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1216359175
Short name T308
Test name
Test status
Simulation time 30659489 ps
CPU time 0.81 seconds
Started Mar 03 02:37:27 PM PST 24
Finished Mar 03 02:37:28 PM PST 24
Peak memory 196556 kb
Host smart-cbf19533-0497-42c2-93e1-bbe00cf7b542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216359175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1216359175
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2900554724
Short name T219
Test name
Test status
Simulation time 35302438988 ps
CPU time 861.15 seconds
Started Mar 03 02:37:36 PM PST 24
Finished Mar 03 02:51:58 PM PST 24
Peak memory 228728 kb
Host smart-cb266460-3c2a-4a6f-81a6-ba4693e68458
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900554724 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2900554724
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.4197104312
Short name T395
Test name
Test status
Simulation time 50895697 ps
CPU time 1.14 seconds
Started Mar 03 02:37:37 PM PST 24
Finished Mar 03 02:37:38 PM PST 24
Peak memory 199336 kb
Host smart-6f234289-def7-44fc-8ee4-785368f818c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197104312 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.4197104312
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.190692942
Short name T190
Test name
Test status
Simulation time 152957228855 ps
CPU time 458.58 seconds
Started Mar 03 02:37:34 PM PST 24
Finished Mar 03 02:45:13 PM PST 24
Peak memory 199964 kb
Host smart-46737f6c-036d-4ca0-9373-9e82d7f08c28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190692942 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.hmac_test_sha_vectors.190692942
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3007531694
Short name T495
Test name
Test status
Simulation time 106874448 ps
CPU time 3.09 seconds
Started Mar 03 02:37:37 PM PST 24
Finished Mar 03 02:37:40 PM PST 24
Peak memory 199848 kb
Host smart-ecd9d122-16a2-4688-8c13-bf5f02b95422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007531694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3007531694
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.325659131
Short name T14
Test name
Test status
Simulation time 12402056 ps
CPU time 0.61 seconds
Started Mar 03 02:37:37 PM PST 24
Finished Mar 03 02:37:39 PM PST 24
Peak memory 194240 kb
Host smart-da2a48b1-eb36-4946-bcc9-78dbdf8c4a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325659131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.325659131
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.306330235
Short name T202
Test name
Test status
Simulation time 768602526 ps
CPU time 28.69 seconds
Started Mar 03 02:37:36 PM PST 24
Finished Mar 03 02:38:05 PM PST 24
Peak memory 223400 kb
Host smart-30b0953b-3841-46e2-a385-35bcbb99ed2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306330235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.306330235
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1076144423
Short name T342
Test name
Test status
Simulation time 390962950 ps
CPU time 4.49 seconds
Started Mar 03 02:37:39 PM PST 24
Finished Mar 03 02:37:45 PM PST 24
Peak memory 199892 kb
Host smart-6ac2e694-9211-44da-83e1-33437faf5e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076144423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1076144423
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3475399215
Short name T45
Test name
Test status
Simulation time 10813459646 ps
CPU time 79.85 seconds
Started Mar 03 02:37:39 PM PST 24
Finished Mar 03 02:39:00 PM PST 24
Peak memory 199980 kb
Host smart-58b13030-589b-4e42-a90e-ef982041ecc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3475399215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3475399215
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1513245170
Short name T489
Test name
Test status
Simulation time 7940942243 ps
CPU time 101.24 seconds
Started Mar 03 02:37:34 PM PST 24
Finished Mar 03 02:39:16 PM PST 24
Peak memory 200004 kb
Host smart-89a3704d-0286-4cdc-9979-b5b426f7f4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513245170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1513245170
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1056770760
Short name T207
Test name
Test status
Simulation time 1502413114 ps
CPU time 13.89 seconds
Started Mar 03 02:37:36 PM PST 24
Finished Mar 03 02:37:51 PM PST 24
Peak memory 199888 kb
Host smart-3cce8469-413d-4559-aba7-07d8d8c2153f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056770760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1056770760
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3156230566
Short name T420
Test name
Test status
Simulation time 305886051 ps
CPU time 1.95 seconds
Started Mar 03 02:37:36 PM PST 24
Finished Mar 03 02:37:38 PM PST 24
Peak memory 199752 kb
Host smart-df117342-6133-47a7-837c-43a0647427ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156230566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3156230566
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2616217615
Short name T75
Test name
Test status
Simulation time 139317887370 ps
CPU time 1732.33 seconds
Started Mar 03 02:37:34 PM PST 24
Finished Mar 03 03:06:27 PM PST 24
Peak memory 200052 kb
Host smart-8d69ba09-9c4a-4793-9a1c-6719457964c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616217615 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2616217615
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2277969013
Short name T289
Test name
Test status
Simulation time 27776614 ps
CPU time 0.95 seconds
Started Mar 03 02:37:35 PM PST 24
Finished Mar 03 02:37:36 PM PST 24
Peak memory 197296 kb
Host smart-f2911161-9283-49a6-ad01-1341cc207f85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277969013 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2277969013
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2064658841
Short name T532
Test name
Test status
Simulation time 43450472106 ps
CPU time 433.79 seconds
Started Mar 03 02:37:35 PM PST 24
Finished Mar 03 02:44:49 PM PST 24
Peak memory 199976 kb
Host smart-bbe145cb-5994-4f10-90f1-5b5b7c28bd5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064658841 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.2064658841
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.737613785
Short name T303
Test name
Test status
Simulation time 1137379382 ps
CPU time 41.96 seconds
Started Mar 03 02:37:37 PM PST 24
Finished Mar 03 02:38:19 PM PST 24
Peak memory 199928 kb
Host smart-a855c1ec-1c1d-4b4f-84c7-42e6987f1209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737613785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.737613785
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3800449198
Short name T471
Test name
Test status
Simulation time 55814096 ps
CPU time 0.57 seconds
Started Mar 03 02:37:40 PM PST 24
Finished Mar 03 02:37:44 PM PST 24
Peak memory 194456 kb
Host smart-bbc9846e-0a97-4600-b7c3-7d6e0d9880da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800449198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3800449198
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.610365865
Short name T217
Test name
Test status
Simulation time 432118594 ps
CPU time 12.66 seconds
Started Mar 03 02:37:41 PM PST 24
Finished Mar 03 02:37:56 PM PST 24
Peak memory 215692 kb
Host smart-6b1694a1-d3ae-4f4b-ab0d-a38cb11d89e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=610365865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.610365865
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1936151085
Short name T367
Test name
Test status
Simulation time 1948000548 ps
CPU time 27.53 seconds
Started Mar 03 02:37:40 PM PST 24
Finished Mar 03 02:38:10 PM PST 24
Peak memory 199876 kb
Host smart-d3b74f0f-5a68-4ec0-a3b2-3f79cce9fa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936151085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1936151085
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3836817917
Short name T65
Test name
Test status
Simulation time 582175605 ps
CPU time 15.93 seconds
Started Mar 03 02:37:42 PM PST 24
Finished Mar 03 02:38:00 PM PST 24
Peak memory 199780 kb
Host smart-08b1478f-c315-4d7e-a169-e06ffc9b6c4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836817917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3836817917
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3554673395
Short name T33
Test name
Test status
Simulation time 1562205268 ps
CPU time 73.41 seconds
Started Mar 03 02:37:49 PM PST 24
Finished Mar 03 02:39:04 PM PST 24
Peak memory 199828 kb
Host smart-c444706d-4b1e-46aa-be86-85118420877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554673395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3554673395
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3234649320
Short name T197
Test name
Test status
Simulation time 6213184325 ps
CPU time 110.36 seconds
Started Mar 03 02:37:40 PM PST 24
Finished Mar 03 02:39:33 PM PST 24
Peak memory 200004 kb
Host smart-0f7ce73d-003b-4c9c-a3f1-efa214997d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234649320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3234649320
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3913396597
Short name T429
Test name
Test status
Simulation time 239551932 ps
CPU time 1.7 seconds
Started Mar 03 02:37:40 PM PST 24
Finished Mar 03 02:37:45 PM PST 24
Peak memory 199732 kb
Host smart-844e17cd-ac58-418a-9c8e-4f18c1008df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913396597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3913396597
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1182192799
Short name T194
Test name
Test status
Simulation time 789476262 ps
CPU time 1.11 seconds
Started Mar 03 02:37:49 PM PST 24
Finished Mar 03 02:37:51 PM PST 24
Peak memory 198904 kb
Host smart-b80e3025-314d-4ead-8fb6-75731c138071
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182192799 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1182192799
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3654782339
Short name T36
Test name
Test status
Simulation time 109251217957 ps
CPU time 458.03 seconds
Started Mar 03 02:37:40 PM PST 24
Finished Mar 03 02:45:21 PM PST 24
Peak memory 199908 kb
Host smart-105dc67d-6eb8-46d6-9aee-73b11cc3127a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654782339 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.3654782339
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3433630005
Short name T245
Test name
Test status
Simulation time 22550943213 ps
CPU time 79.14 seconds
Started Mar 03 02:37:49 PM PST 24
Finished Mar 03 02:39:09 PM PST 24
Peak memory 199956 kb
Host smart-2e6fa409-9b57-4bc0-b9dc-cd3983574bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433630005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3433630005
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3989115453
Short name T543
Test name
Test status
Simulation time 34019611 ps
CPU time 0.57 seconds
Started Mar 03 02:37:42 PM PST 24
Finished Mar 03 02:37:44 PM PST 24
Peak memory 194312 kb
Host smart-ba25be48-c9c0-45a5-9e7c-f42a5ce6e574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989115453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3989115453
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2969445341
Short name T426
Test name
Test status
Simulation time 1230472198 ps
CPU time 53.88 seconds
Started Mar 03 02:37:39 PM PST 24
Finished Mar 03 02:38:34 PM PST 24
Peak memory 232624 kb
Host smart-759fbfbb-b60a-4f5b-9508-f87ab26384cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969445341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2969445341
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.871381441
Short name T467
Test name
Test status
Simulation time 14408818348 ps
CPU time 64.15 seconds
Started Mar 03 02:37:41 PM PST 24
Finished Mar 03 02:38:47 PM PST 24
Peak memory 199920 kb
Host smart-5ea96954-18f5-42e9-9179-19d7b722bd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871381441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.871381441
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1426498960
Short name T119
Test name
Test status
Simulation time 758476899 ps
CPU time 42.3 seconds
Started Mar 03 02:37:49 PM PST 24
Finished Mar 03 02:38:32 PM PST 24
Peak memory 199848 kb
Host smart-23e4881a-832b-4277-badb-51fd419b133a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426498960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1426498960
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.312489649
Short name T253
Test name
Test status
Simulation time 15587514971 ps
CPU time 51.6 seconds
Started Mar 03 02:37:40 PM PST 24
Finished Mar 03 02:38:34 PM PST 24
Peak memory 200036 kb
Host smart-1ac0144a-31c7-436f-91e7-6455117a89db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312489649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.312489649
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2654439679
Short name T224
Test name
Test status
Simulation time 2087220064 ps
CPU time 114.73 seconds
Started Mar 03 02:37:40 PM PST 24
Finished Mar 03 02:39:36 PM PST 24
Peak memory 199896 kb
Host smart-dd7b6ba8-2853-40d0-94f3-ecc971032b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654439679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2654439679
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.766287459
Short name T459
Test name
Test status
Simulation time 48330133 ps
CPU time 1.06 seconds
Started Mar 03 02:37:39 PM PST 24
Finished Mar 03 02:37:41 PM PST 24
Peak memory 199084 kb
Host smart-3b9ace89-5065-4c31-b74c-67386a6fba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766287459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.766287459
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1343562952
Short name T494
Test name
Test status
Simulation time 9501459188 ps
CPU time 469.15 seconds
Started Mar 03 02:37:49 PM PST 24
Finished Mar 03 02:45:39 PM PST 24
Peak memory 200004 kb
Host smart-7100418e-d589-41ff-a726-3d90d9eb40b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343562952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1343562952
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2804013845
Short name T399
Test name
Test status
Simulation time 29252471 ps
CPU time 0.96 seconds
Started Mar 03 02:37:40 PM PST 24
Finished Mar 03 02:37:44 PM PST 24
Peak memory 197856 kb
Host smart-51de4e36-edbd-4c9f-bb20-9457339111ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804013845 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2804013845
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1045092989
Short name T591
Test name
Test status
Simulation time 23071838078 ps
CPU time 405 seconds
Started Mar 03 02:37:50 PM PST 24
Finished Mar 03 02:44:35 PM PST 24
Peak memory 199944 kb
Host smart-bb70322b-bd9d-4f1e-80f8-c9b0116555ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045092989 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.1045092989
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3658916040
Short name T180
Test name
Test status
Simulation time 978358145 ps
CPU time 33.76 seconds
Started Mar 03 02:37:42 PM PST 24
Finished Mar 03 02:38:19 PM PST 24
Peak memory 199812 kb
Host smart-50cb32c9-ef0e-43d8-8576-48cf91026ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658916040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3658916040
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.750932736
Short name T370
Test name
Test status
Simulation time 58706327 ps
CPU time 0.58 seconds
Started Mar 03 02:37:48 PM PST 24
Finished Mar 03 02:37:50 PM PST 24
Peak memory 194452 kb
Host smart-28745c5c-20a6-4a40-ac6f-b986e206bf54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750932736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.750932736
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2977819666
Short name T581
Test name
Test status
Simulation time 1728864583 ps
CPU time 57.11 seconds
Started Mar 03 02:37:41 PM PST 24
Finished Mar 03 02:38:40 PM PST 24
Peak memory 230660 kb
Host smart-87910006-2e9f-4796-88e8-a2de1d695315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977819666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2977819666
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1108144874
Short name T228
Test name
Test status
Simulation time 12473932261 ps
CPU time 50.4 seconds
Started Mar 03 02:37:41 PM PST 24
Finished Mar 03 02:38:33 PM PST 24
Peak memory 200028 kb
Host smart-1a05ac05-580e-4009-a44b-e50d265c54c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108144874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1108144874
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1841542174
Short name T268
Test name
Test status
Simulation time 157893425 ps
CPU time 7.97 seconds
Started Mar 03 02:37:39 PM PST 24
Finished Mar 03 02:37:49 PM PST 24
Peak memory 199804 kb
Host smart-7a02a9e2-b66e-4e34-9faa-04b26f42dcea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1841542174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1841542174
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2666517384
Short name T506
Test name
Test status
Simulation time 3275482777 ps
CPU time 32.76 seconds
Started Mar 03 02:37:47 PM PST 24
Finished Mar 03 02:38:20 PM PST 24
Peak memory 199940 kb
Host smart-093c1a3b-737d-4f75-9956-947213061a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666517384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2666517384
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4266041561
Short name T199
Test name
Test status
Simulation time 1229784714 ps
CPU time 18 seconds
Started Mar 03 02:37:42 PM PST 24
Finished Mar 03 02:38:03 PM PST 24
Peak memory 199916 kb
Host smart-67d08c7f-1045-43ce-a170-b2b308210c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266041561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4266041561
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2002097436
Short name T155
Test name
Test status
Simulation time 621894113 ps
CPU time 4.49 seconds
Started Mar 03 02:37:40 PM PST 24
Finished Mar 03 02:37:46 PM PST 24
Peak memory 199848 kb
Host smart-f67b0e03-5be4-4ca4-9e24-0f1f0a454a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002097436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2002097436
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2581036138
Short name T116
Test name
Test status
Simulation time 22942860094 ps
CPU time 188.74 seconds
Started Mar 03 02:37:50 PM PST 24
Finished Mar 03 02:40:59 PM PST 24
Peak memory 234820 kb
Host smart-57b5b401-d124-476c-a196-449e4c82dfeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581036138 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2581036138
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2792419392
Short name T528
Test name
Test status
Simulation time 26692865 ps
CPU time 0.87 seconds
Started Mar 03 02:37:48 PM PST 24
Finished Mar 03 02:37:51 PM PST 24
Peak memory 197560 kb
Host smart-a173ac7a-7460-4123-ac44-6475b65b8221
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792419392 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2792419392
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1684151674
Short name T333
Test name
Test status
Simulation time 44457034948 ps
CPU time 523.77 seconds
Started Mar 03 02:37:51 PM PST 24
Finished Mar 03 02:46:35 PM PST 24
Peak memory 199936 kb
Host smart-dc25acef-d66d-4086-aff5-666747e8855a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684151674 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.1684151674
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.4141590224
Short name T262
Test name
Test status
Simulation time 835967632 ps
CPU time 10.4 seconds
Started Mar 03 02:37:50 PM PST 24
Finished Mar 03 02:38:01 PM PST 24
Peak memory 199872 kb
Host smart-a384592d-bf44-43c2-befa-9c3d2a614e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141590224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.4141590224
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3365272239
Short name T411
Test name
Test status
Simulation time 14101333 ps
CPU time 0.58 seconds
Started Mar 03 02:36:53 PM PST 24
Finished Mar 03 02:36:54 PM PST 24
Peak memory 194472 kb
Host smart-2c646bb9-6477-41dc-bbb5-d3fc374ded57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365272239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3365272239
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.911647680
Short name T387
Test name
Test status
Simulation time 543073255 ps
CPU time 4.69 seconds
Started Mar 03 02:36:53 PM PST 24
Finished Mar 03 02:36:58 PM PST 24
Peak memory 199888 kb
Host smart-b0b33cdb-2c0d-4b99-88a3-0f2a0b300814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=911647680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.911647680
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2217780230
Short name T216
Test name
Test status
Simulation time 2024782337 ps
CPU time 23.94 seconds
Started Mar 03 02:36:53 PM PST 24
Finished Mar 03 02:37:18 PM PST 24
Peak memory 199916 kb
Host smart-0341c321-8d97-4010-a6ea-d41f7ac586c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217780230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2217780230
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1166151564
Short name T292
Test name
Test status
Simulation time 9163312423 ps
CPU time 126.95 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:38:56 PM PST 24
Peak memory 200020 kb
Host smart-bd196ad0-1f0b-4b09-85e5-28e27e090985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166151564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1166151564
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1608873018
Short name T261
Test name
Test status
Simulation time 26374153890 ps
CPU time 81.36 seconds
Started Mar 03 02:36:53 PM PST 24
Finished Mar 03 02:38:14 PM PST 24
Peak memory 199952 kb
Host smart-093732b3-6fe7-4153-a11b-88ea41a6d5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608873018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1608873018
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1400018319
Short name T48
Test name
Test status
Simulation time 841994326 ps
CPU time 12.54 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:37:02 PM PST 24
Peak memory 199908 kb
Host smart-f6268d08-56db-428e-a9d0-fab7f3116f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400018319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1400018319
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3162555006
Short name T28
Test name
Test status
Simulation time 169099979 ps
CPU time 0.9 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:36:50 PM PST 24
Peak memory 216992 kb
Host smart-3d264c51-4de0-4bcf-a59d-6cec757cc6b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162555006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3162555006
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3951494283
Short name T515
Test name
Test status
Simulation time 86268884 ps
CPU time 2.41 seconds
Started Mar 03 02:36:48 PM PST 24
Finished Mar 03 02:36:50 PM PST 24
Peak memory 199884 kb
Host smart-532cb4f7-c013-4dc4-8488-8f02410136da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951494283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3951494283
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3720169626
Short name T356
Test name
Test status
Simulation time 25399597994 ps
CPU time 383.97 seconds
Started Mar 03 02:36:51 PM PST 24
Finished Mar 03 02:43:15 PM PST 24
Peak memory 215612 kb
Host smart-5edfc306-c850-4c6c-9cb1-dcb1c63623cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720169626 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3720169626
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.820271955
Short name T250
Test name
Test status
Simulation time 42701947 ps
CPU time 0.98 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:36:50 PM PST 24
Peak memory 197596 kb
Host smart-4de5168f-cab0-4ede-99f3-8e92245e3063
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820271955 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_hmac_vectors.820271955
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1346284399
Short name T247
Test name
Test status
Simulation time 109896626671 ps
CPU time 441.69 seconds
Started Mar 03 02:36:52 PM PST 24
Finished Mar 03 02:44:14 PM PST 24
Peak memory 199988 kb
Host smart-776eca42-c14f-44ef-b757-0232295e826b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346284399 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.1346284399
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.4265132059
Short name T264
Test name
Test status
Simulation time 284600144 ps
CPU time 11.67 seconds
Started Mar 03 02:36:51 PM PST 24
Finished Mar 03 02:37:02 PM PST 24
Peak memory 199848 kb
Host smart-c861b1a7-70a3-417a-a959-8c27465f13ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265132059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.4265132059
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.883869487
Short name T200
Test name
Test status
Simulation time 27379425 ps
CPU time 0.6 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:37:55 PM PST 24
Peak memory 195272 kb
Host smart-bf15cb4a-e892-4feb-91bc-4a01ad0c6835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883869487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.883869487
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.4147992413
Short name T347
Test name
Test status
Simulation time 414988534 ps
CPU time 7.14 seconds
Started Mar 03 02:37:49 PM PST 24
Finished Mar 03 02:37:57 PM PST 24
Peak memory 215832 kb
Host smart-223daf4d-62bc-4206-ac54-b78a270fb910
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147992413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.4147992413
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.535333399
Short name T485
Test name
Test status
Simulation time 34448550659 ps
CPU time 44.49 seconds
Started Mar 03 02:37:48 PM PST 24
Finished Mar 03 02:38:34 PM PST 24
Peak memory 200052 kb
Host smart-97116a3e-9063-4462-a345-9377ec47a050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535333399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.535333399
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2815132129
Short name T105
Test name
Test status
Simulation time 4143784320 ps
CPU time 58.22 seconds
Started Mar 03 02:37:48 PM PST 24
Finished Mar 03 02:38:47 PM PST 24
Peak memory 199916 kb
Host smart-0148b4ce-2bd8-40ef-b1ea-bf43f4b0b849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815132129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2815132129
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1665355294
Short name T188
Test name
Test status
Simulation time 19954260795 ps
CPU time 86.54 seconds
Started Mar 03 02:37:55 PM PST 24
Finished Mar 03 02:39:21 PM PST 24
Peak memory 200032 kb
Host smart-8f738492-691c-42e9-a712-68de35d391d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665355294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1665355294
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.4138852417
Short name T52
Test name
Test status
Simulation time 116140177 ps
CPU time 5.96 seconds
Started Mar 03 02:37:47 PM PST 24
Finished Mar 03 02:37:53 PM PST 24
Peak memory 199816 kb
Host smart-fdc5f22b-fd41-4382-af25-a8813b4ddb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138852417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.4138852417
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1032201630
Short name T186
Test name
Test status
Simulation time 150142632 ps
CPU time 1.23 seconds
Started Mar 03 02:37:48 PM PST 24
Finished Mar 03 02:37:49 PM PST 24
Peak memory 199424 kb
Host smart-ac43b34f-fcfe-433f-b558-0c7c1c4964c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032201630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1032201630
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1983852754
Short name T62
Test name
Test status
Simulation time 54633013655 ps
CPU time 653.07 seconds
Started Mar 03 02:37:48 PM PST 24
Finished Mar 03 02:48:43 PM PST 24
Peak memory 208224 kb
Host smart-81deb909-b760-4f7d-ab60-3aca0a2588dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983852754 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1983852754
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3116141801
Short name T273
Test name
Test status
Simulation time 74459760 ps
CPU time 0.98 seconds
Started Mar 03 02:37:51 PM PST 24
Finished Mar 03 02:37:52 PM PST 24
Peak memory 198420 kb
Host smart-9fc52197-841e-4b2c-b425-89a693cc3bbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116141801 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3116141801
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1351173669
Short name T323
Test name
Test status
Simulation time 122855077001 ps
CPU time 430.9 seconds
Started Mar 03 02:37:50 PM PST 24
Finished Mar 03 02:45:02 PM PST 24
Peak memory 199908 kb
Host smart-1b8078cc-6bfa-439a-a1f6-76640fe32be0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351173669 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.1351173669
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1427699465
Short name T453
Test name
Test status
Simulation time 3031348858 ps
CPU time 32.69 seconds
Started Mar 03 02:37:50 PM PST 24
Finished Mar 03 02:38:23 PM PST 24
Peak memory 200032 kb
Host smart-42b4d0f7-b6eb-46fd-8c2e-14475f2e1f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427699465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1427699465
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.197575949
Short name T560
Test name
Test status
Simulation time 11871932 ps
CPU time 0.58 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:37:55 PM PST 24
Peak memory 195272 kb
Host smart-2aae8ef1-658d-40e1-9059-791ae25e6f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197575949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.197575949
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.308616927
Short name T296
Test name
Test status
Simulation time 13987499247 ps
CPU time 53.18 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:38:48 PM PST 24
Peak memory 234544 kb
Host smart-1c113274-9169-4781-966b-04611640ad0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308616927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.308616927
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3332875537
Short name T233
Test name
Test status
Simulation time 336718133 ps
CPU time 7.93 seconds
Started Mar 03 02:37:56 PM PST 24
Finished Mar 03 02:38:04 PM PST 24
Peak memory 199884 kb
Host smart-e8d13a56-18ec-4a4c-8cb1-9adfa33cd44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332875537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3332875537
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.22148739
Short name T511
Test name
Test status
Simulation time 4040938217 ps
CPU time 114.07 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:39:48 PM PST 24
Peak memory 200052 kb
Host smart-3d7634c2-f365-4b31-b3ac-50b59138bd3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22148739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.22148739
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1716658279
Short name T422
Test name
Test status
Simulation time 37845893 ps
CPU time 2.12 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:37:57 PM PST 24
Peak memory 199788 kb
Host smart-50c2c321-e398-4bff-b795-6b270c33f0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716658279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1716658279
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3837467193
Short name T481
Test name
Test status
Simulation time 49415835915 ps
CPU time 91.48 seconds
Started Mar 03 02:38:03 PM PST 24
Finished Mar 03 02:39:35 PM PST 24
Peak memory 200044 kb
Host smart-6dbf3062-3a3e-4c47-b081-cbaaacaf1be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837467193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3837467193
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3761005974
Short name T227
Test name
Test status
Simulation time 260105449 ps
CPU time 3.97 seconds
Started Mar 03 02:37:55 PM PST 24
Finished Mar 03 02:37:59 PM PST 24
Peak memory 199820 kb
Host smart-fadf7fed-8f3e-4b62-b17e-1b22544ba018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761005974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3761005974
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1512549922
Short name T569
Test name
Test status
Simulation time 25138514340 ps
CPU time 913.49 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:53:08 PM PST 24
Peak memory 235016 kb
Host smart-fbcf9775-a576-4bc7-9529-1d5bc6e5d9d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512549922 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1512549922
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2683927610
Short name T254
Test name
Test status
Simulation time 140305296 ps
CPU time 0.96 seconds
Started Mar 03 02:37:55 PM PST 24
Finished Mar 03 02:37:56 PM PST 24
Peak memory 197272 kb
Host smart-df7c6bd5-1f76-4747-9543-3051f5db1dfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683927610 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2683927610
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.4265878860
Short name T330
Test name
Test status
Simulation time 102783722161 ps
CPU time 421.1 seconds
Started Mar 03 02:37:53 PM PST 24
Finished Mar 03 02:44:54 PM PST 24
Peak memory 199916 kb
Host smart-4d184f07-6568-485c-a520-ad21e99d2c03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265878860 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.4265878860
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2430851801
Short name T490
Test name
Test status
Simulation time 1374797091 ps
CPU time 29.59 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:38:23 PM PST 24
Peak memory 199872 kb
Host smart-7ba39ccd-16d9-40e4-a98d-14195016668d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430851801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2430851801
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3494723708
Short name T573
Test name
Test status
Simulation time 14567445 ps
CPU time 0.59 seconds
Started Mar 03 02:38:09 PM PST 24
Finished Mar 03 02:38:10 PM PST 24
Peak memory 194456 kb
Host smart-2b43633f-1f94-4f84-866d-9177fa53551f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494723708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3494723708
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2288793052
Short name T46
Test name
Test status
Simulation time 874388948 ps
CPU time 1.77 seconds
Started Mar 03 02:37:53 PM PST 24
Finished Mar 03 02:37:55 PM PST 24
Peak memory 199788 kb
Host smart-1beb43b2-a086-4a5d-ace8-45cf09c4e91d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288793052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2288793052
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2463630352
Short name T187
Test name
Test status
Simulation time 6485874406 ps
CPU time 77.92 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:39:12 PM PST 24
Peak memory 199972 kb
Host smart-eea0da5e-ec64-43df-a5ae-233931097f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463630352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2463630352
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3427639502
Short name T121
Test name
Test status
Simulation time 1393648535 ps
CPU time 60.26 seconds
Started Mar 03 02:37:53 PM PST 24
Finished Mar 03 02:38:53 PM PST 24
Peak memory 199916 kb
Host smart-f2d7897a-08eb-487b-9548-cd3213dec5d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3427639502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3427639502
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2004027552
Short name T346
Test name
Test status
Simulation time 2026124963 ps
CPU time 25.51 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:38:19 PM PST 24
Peak memory 199860 kb
Host smart-4a107266-f404-4d0e-ba92-0913957b7fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004027552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2004027552
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.446086446
Short name T68
Test name
Test status
Simulation time 6957423350 ps
CPU time 64.41 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:38:59 PM PST 24
Peak memory 200004 kb
Host smart-f6baf1e5-1bdf-4e03-bec6-065afb3a93ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446086446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.446086446
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1746432096
Short name T502
Test name
Test status
Simulation time 43573150 ps
CPU time 1.27 seconds
Started Mar 03 02:37:53 PM PST 24
Finished Mar 03 02:37:54 PM PST 24
Peak memory 198420 kb
Host smart-88f96ed2-deb3-48f7-b336-20cfb7293e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746432096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1746432096
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.544748476
Short name T454
Test name
Test status
Simulation time 6432266515 ps
CPU time 305.16 seconds
Started Mar 03 02:37:53 PM PST 24
Finished Mar 03 02:42:58 PM PST 24
Peak memory 240796 kb
Host smart-75ddf53a-12a4-4482-9d01-5fce20a7d073
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544748476 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.544748476
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3322130576
Short name T348
Test name
Test status
Simulation time 790974371 ps
CPU time 1.15 seconds
Started Mar 03 02:37:54 PM PST 24
Finished Mar 03 02:37:55 PM PST 24
Peak memory 198820 kb
Host smart-25db7071-3a5d-4a72-8aeb-e4a1e8faba07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322130576 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3322130576
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1491703949
Short name T311
Test name
Test status
Simulation time 71726059879 ps
CPU time 511.37 seconds
Started Mar 03 02:37:55 PM PST 24
Finished Mar 03 02:46:27 PM PST 24
Peak memory 199936 kb
Host smart-4c4271ca-fb06-40ff-a7ad-e6eca8579584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491703949 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.1491703949
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2939889483
Short name T472
Test name
Test status
Simulation time 3741382164 ps
CPU time 37.83 seconds
Started Mar 03 02:37:55 PM PST 24
Finished Mar 03 02:38:33 PM PST 24
Peak memory 199976 kb
Host smart-28c56761-6ef7-4307-8baf-99aec8990c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939889483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2939889483
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4058315199
Short name T544
Test name
Test status
Simulation time 13926365 ps
CPU time 0.56 seconds
Started Mar 03 02:38:00 PM PST 24
Finished Mar 03 02:38:01 PM PST 24
Peak memory 194176 kb
Host smart-ed4d2c59-40d8-48a0-a1e4-37493e7e9220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058315199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4058315199
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.527024961
Short name T239
Test name
Test status
Simulation time 1334757866 ps
CPU time 21.7 seconds
Started Mar 03 02:38:08 PM PST 24
Finished Mar 03 02:38:31 PM PST 24
Peak memory 215396 kb
Host smart-c7497820-12ac-4181-939b-52886822a573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=527024961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.527024961
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3730573353
Short name T325
Test name
Test status
Simulation time 941366482 ps
CPU time 32.48 seconds
Started Mar 03 02:38:09 PM PST 24
Finished Mar 03 02:38:43 PM PST 24
Peak memory 199860 kb
Host smart-b5c41540-fa48-44cd-977f-e8b814da16b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730573353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3730573353
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.89131932
Short name T109
Test name
Test status
Simulation time 2295762050 ps
CPU time 129.78 seconds
Started Mar 03 02:38:01 PM PST 24
Finished Mar 03 02:40:11 PM PST 24
Peak memory 199948 kb
Host smart-73489345-84da-4679-b7fc-b534ed585272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89131932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.89131932
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1147818746
Short name T371
Test name
Test status
Simulation time 8688732964 ps
CPU time 145.86 seconds
Started Mar 03 02:38:00 PM PST 24
Finished Mar 03 02:40:27 PM PST 24
Peak memory 199992 kb
Host smart-273c5723-e5ec-4da0-8a0b-36df03acbba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147818746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1147818746
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.922152605
Short name T487
Test name
Test status
Simulation time 15363461350 ps
CPU time 98.83 seconds
Started Mar 03 02:38:01 PM PST 24
Finished Mar 03 02:39:40 PM PST 24
Peak memory 200028 kb
Host smart-16ed157a-236b-4630-8b1b-fc56526f2738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922152605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.922152605
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2578969609
Short name T223
Test name
Test status
Simulation time 459156767 ps
CPU time 4.62 seconds
Started Mar 03 02:38:00 PM PST 24
Finished Mar 03 02:38:05 PM PST 24
Peak memory 200104 kb
Host smart-6719374c-043b-47e1-b4ad-ed72ebcf821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578969609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2578969609
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3885921914
Short name T129
Test name
Test status
Simulation time 129367412550 ps
CPU time 1564.33 seconds
Started Mar 03 02:38:09 PM PST 24
Finished Mar 03 03:04:15 PM PST 24
Peak memory 200076 kb
Host smart-1eccbedf-481b-4fb1-b63f-492cb08958e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885921914 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3885921914
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2831381566
Short name T220
Test name
Test status
Simulation time 179416436 ps
CPU time 1.14 seconds
Started Mar 03 02:38:02 PM PST 24
Finished Mar 03 02:38:03 PM PST 24
Peak memory 197808 kb
Host smart-a87d00f7-8063-435d-85c8-b53018d5e7d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831381566 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2831381566
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2294327827
Short name T335
Test name
Test status
Simulation time 28907362491 ps
CPU time 492.03 seconds
Started Mar 03 02:38:02 PM PST 24
Finished Mar 03 02:46:14 PM PST 24
Peak memory 199932 kb
Host smart-dc09c330-1965-4269-ba1e-a568480c2f71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294327827 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.2294327827
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3972296473
Short name T214
Test name
Test status
Simulation time 12009727376 ps
CPU time 88.19 seconds
Started Mar 03 02:38:09 PM PST 24
Finished Mar 03 02:39:39 PM PST 24
Peak memory 200012 kb
Host smart-d81d1a93-dbcc-4859-b51e-f1eb5db6f17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972296473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3972296473
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.4157055609
Short name T389
Test name
Test status
Simulation time 14056354 ps
CPU time 0.58 seconds
Started Mar 03 02:38:08 PM PST 24
Finished Mar 03 02:38:10 PM PST 24
Peak memory 194456 kb
Host smart-8e97778b-ad8d-407e-983c-91d6f8f10df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157055609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.4157055609
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1460583898
Short name T466
Test name
Test status
Simulation time 1203066150 ps
CPU time 41.65 seconds
Started Mar 03 02:38:10 PM PST 24
Finished Mar 03 02:38:53 PM PST 24
Peak memory 224504 kb
Host smart-6ec3c1e2-26af-4ca4-a5af-e6555aa8bba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1460583898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1460583898
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3875399569
Short name T559
Test name
Test status
Simulation time 483383836 ps
CPU time 22.2 seconds
Started Mar 03 02:38:08 PM PST 24
Finished Mar 03 02:38:32 PM PST 24
Peak memory 199832 kb
Host smart-6dc0784f-c917-48f9-aee7-26bd838ddfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875399569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3875399569
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.889464590
Short name T182
Test name
Test status
Simulation time 4470524893 ps
CPU time 59.92 seconds
Started Mar 03 02:38:07 PM PST 24
Finished Mar 03 02:39:08 PM PST 24
Peak memory 200048 kb
Host smart-f7fbe5bb-4b6c-4cc9-a6db-e6f1d4638476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889464590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.889464590
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.35216292
Short name T542
Test name
Test status
Simulation time 4034145541 ps
CPU time 53.64 seconds
Started Mar 03 02:38:07 PM PST 24
Finished Mar 03 02:39:02 PM PST 24
Peak memory 200192 kb
Host smart-2d0b197f-8914-4b61-89e5-6a93e21b974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35216292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.35216292
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.544710188
Short name T432
Test name
Test status
Simulation time 1398267768 ps
CPU time 20.13 seconds
Started Mar 03 02:38:01 PM PST 24
Finished Mar 03 02:38:21 PM PST 24
Peak memory 199792 kb
Host smart-603c4802-e072-423b-8152-6283beab1d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544710188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.544710188
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3536008605
Short name T275
Test name
Test status
Simulation time 568681186 ps
CPU time 3.62 seconds
Started Mar 03 02:38:01 PM PST 24
Finished Mar 03 02:38:05 PM PST 24
Peak memory 199840 kb
Host smart-50723107-5f43-49b3-91f6-a2c40cb5d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536008605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3536008605
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1208395641
Short name T133
Test name
Test status
Simulation time 299398122176 ps
CPU time 816.06 seconds
Started Mar 03 02:38:07 PM PST 24
Finished Mar 03 02:51:45 PM PST 24
Peak memory 200096 kb
Host smart-ea18e8f4-16e9-48fe-b2f6-f085bb983f2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208395641 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1208395641
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3647892400
Short name T288
Test name
Test status
Simulation time 33183213 ps
CPU time 1.12 seconds
Started Mar 03 02:38:08 PM PST 24
Finished Mar 03 02:38:11 PM PST 24
Peak memory 198764 kb
Host smart-fd6cb8bc-1c78-45bf-af63-46a041cb4e78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647892400 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3647892400
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.943965995
Short name T208
Test name
Test status
Simulation time 106797230005 ps
CPU time 444.4 seconds
Started Mar 03 02:38:08 PM PST 24
Finished Mar 03 02:45:34 PM PST 24
Peak memory 199928 kb
Host smart-39641749-94b9-40cb-a98c-519f01d242fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943965995 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.hmac_test_sha_vectors.943965995
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1805362164
Short name T198
Test name
Test status
Simulation time 4317040032 ps
CPU time 16.57 seconds
Started Mar 03 02:38:12 PM PST 24
Finished Mar 03 02:38:31 PM PST 24
Peak memory 200012 kb
Host smart-42af61ea-0309-4929-9d62-a0b9f200e854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805362164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1805362164
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1707181437
Short name T572
Test name
Test status
Simulation time 53616583 ps
CPU time 0.56 seconds
Started Mar 03 02:38:09 PM PST 24
Finished Mar 03 02:38:11 PM PST 24
Peak memory 194252 kb
Host smart-4948eb4b-b221-46ff-9aca-223a1614a0c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707181437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1707181437
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2409955038
Short name T538
Test name
Test status
Simulation time 554534953 ps
CPU time 21.55 seconds
Started Mar 03 02:38:08 PM PST 24
Finished Mar 03 02:38:31 PM PST 24
Peak memory 233364 kb
Host smart-19997703-6848-44b4-9a8f-fd3fee4ba85b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409955038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2409955038
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2591556388
Short name T486
Test name
Test status
Simulation time 892040076 ps
CPU time 41.32 seconds
Started Mar 03 02:38:07 PM PST 24
Finished Mar 03 02:38:49 PM PST 24
Peak memory 199876 kb
Host smart-962c2c6a-e060-4167-ac91-a0c931a42994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591556388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2591556388
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2681532634
Short name T589
Test name
Test status
Simulation time 3776296332 ps
CPU time 57.33 seconds
Started Mar 03 02:38:07 PM PST 24
Finished Mar 03 02:39:05 PM PST 24
Peak memory 199980 kb
Host smart-dc13a70f-620d-4bfd-8f02-569a65aa5a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2681532634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2681532634
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3356103910
Short name T414
Test name
Test status
Simulation time 5788485997 ps
CPU time 103.33 seconds
Started Mar 03 02:38:07 PM PST 24
Finished Mar 03 02:39:52 PM PST 24
Peak memory 200044 kb
Host smart-1bc432ad-8b37-41ef-b29b-601b092dd184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356103910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3356103910
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3115784927
Short name T249
Test name
Test status
Simulation time 341682477 ps
CPU time 18.74 seconds
Started Mar 03 02:38:07 PM PST 24
Finished Mar 03 02:38:26 PM PST 24
Peak memory 199916 kb
Host smart-ef9a0d27-c3fb-45f7-84d9-dbd64e4f332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115784927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3115784927
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.786750012
Short name T374
Test name
Test status
Simulation time 316668086 ps
CPU time 3.51 seconds
Started Mar 03 02:38:11 PM PST 24
Finished Mar 03 02:38:15 PM PST 24
Peak memory 199920 kb
Host smart-e64c4b4c-299e-4980-a4d3-cbc6d2d8f219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786750012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.786750012
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1779374969
Short name T427
Test name
Test status
Simulation time 83992034172 ps
CPU time 1455.89 seconds
Started Mar 03 02:38:11 PM PST 24
Finished Mar 03 03:02:30 PM PST 24
Peak memory 208292 kb
Host smart-351a7b80-6f06-417b-a5b2-9c798cf03df8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779374969 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1779374969
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.833319480
Short name T238
Test name
Test status
Simulation time 269615768 ps
CPU time 1.14 seconds
Started Mar 03 02:38:09 PM PST 24
Finished Mar 03 02:38:12 PM PST 24
Peak memory 198416 kb
Host smart-8c1b5d7d-ad48-4ae8-a341-49c40c33409c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833319480 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.833319480
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3560560271
Short name T309
Test name
Test status
Simulation time 35096788968 ps
CPU time 401.26 seconds
Started Mar 03 02:38:09 PM PST 24
Finished Mar 03 02:44:52 PM PST 24
Peak memory 199908 kb
Host smart-57eeeada-08c0-4b00-bd76-c63c8377a7b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560560271 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_sha_vectors.3560560271
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.342082551
Short name T165
Test name
Test status
Simulation time 5608684734 ps
CPU time 77.6 seconds
Started Mar 03 02:38:08 PM PST 24
Finished Mar 03 02:39:27 PM PST 24
Peak memory 199920 kb
Host smart-b2b8e76d-dc42-4d88-990e-9ec36fd2a4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342082551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.342082551
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3160064996
Short name T352
Test name
Test status
Simulation time 26322522 ps
CPU time 0.59 seconds
Started Mar 03 02:38:18 PM PST 24
Finished Mar 03 02:38:20 PM PST 24
Peak memory 194356 kb
Host smart-a62b728a-97e6-4056-99c2-dfd343e81867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160064996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3160064996
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.559371090
Short name T66
Test name
Test status
Simulation time 811230159 ps
CPU time 27.88 seconds
Started Mar 03 02:38:10 PM PST 24
Finished Mar 03 02:38:39 PM PST 24
Peak memory 222436 kb
Host smart-65ff6228-8c9f-45b7-9cf4-a3bc741431eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559371090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.559371090
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2050899256
Short name T258
Test name
Test status
Simulation time 15630538947 ps
CPU time 57.05 seconds
Started Mar 03 02:38:09 PM PST 24
Finished Mar 03 02:39:08 PM PST 24
Peak memory 200008 kb
Host smart-65fa7ebd-1460-4725-bd5e-f6dff7eb7e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050899256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2050899256
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1406627347
Short name T451
Test name
Test status
Simulation time 2241164094 ps
CPU time 121.65 seconds
Started Mar 03 02:38:10 PM PST 24
Finished Mar 03 02:40:13 PM PST 24
Peak memory 200032 kb
Host smart-ac955a67-438a-4717-b4ab-e7c0881e16cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406627347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1406627347
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.396555909
Short name T8
Test name
Test status
Simulation time 17108220249 ps
CPU time 18.42 seconds
Started Mar 03 02:38:08 PM PST 24
Finished Mar 03 02:38:28 PM PST 24
Peak memory 199952 kb
Host smart-36734b2e-53ff-4e9f-8d15-a9a7e7f2e043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396555909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.396555909
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.608180658
Short name T476
Test name
Test status
Simulation time 618509478 ps
CPU time 11.47 seconds
Started Mar 03 02:38:08 PM PST 24
Finished Mar 03 02:38:21 PM PST 24
Peak memory 199904 kb
Host smart-fb2ae997-0fb1-450c-a5e1-3182969e6217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608180658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.608180658
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2118166040
Short name T435
Test name
Test status
Simulation time 295006708 ps
CPU time 3.44 seconds
Started Mar 03 02:38:11 PM PST 24
Finished Mar 03 02:38:18 PM PST 24
Peak memory 199884 kb
Host smart-825dc74b-0c41-41c1-b60a-7c8674c59681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118166040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2118166040
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1316760164
Short name T5
Test name
Test status
Simulation time 36568625176 ps
CPU time 216.98 seconds
Started Mar 03 02:38:13 PM PST 24
Finished Mar 03 02:41:54 PM PST 24
Peak memory 200088 kb
Host smart-7294558c-f907-411c-9975-0709263f2155
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316760164 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1316760164
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.4283739038
Short name T416
Test name
Test status
Simulation time 81493664 ps
CPU time 0.93 seconds
Started Mar 03 02:38:15 PM PST 24
Finished Mar 03 02:38:19 PM PST 24
Peak memory 197060 kb
Host smart-9e115382-6f5c-4899-9bdd-d89e68e06745
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283739038 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.4283739038
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2544052861
Short name T519
Test name
Test status
Simulation time 36417267757 ps
CPU time 446.9 seconds
Started Mar 03 02:38:17 PM PST 24
Finished Mar 03 02:45:46 PM PST 24
Peak memory 199948 kb
Host smart-521e1f45-d45f-4eee-9a6d-c8c0e84726fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544052861 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_sha_vectors.2544052861
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1165378082
Short name T482
Test name
Test status
Simulation time 3503618802 ps
CPU time 31.1 seconds
Started Mar 03 02:38:08 PM PST 24
Finished Mar 03 02:38:41 PM PST 24
Peak memory 200024 kb
Host smart-6d7aa69c-4bd3-4c8f-8cd2-1c34a58069a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165378082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1165378082
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.555245132
Short name T554
Test name
Test status
Simulation time 35207229 ps
CPU time 0.58 seconds
Started Mar 03 02:38:15 PM PST 24
Finished Mar 03 02:38:19 PM PST 24
Peak memory 194072 kb
Host smart-431a4c24-9076-4ca5-aaf1-e1881e0085ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555245132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.555245132
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2632878780
Short name T493
Test name
Test status
Simulation time 2592781214 ps
CPU time 44.28 seconds
Started Mar 03 02:38:21 PM PST 24
Finished Mar 03 02:39:06 PM PST 24
Peak memory 231960 kb
Host smart-d0ee3ef1-9b21-477d-afa0-181c9bf3d88d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632878780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2632878780
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.665339484
Short name T267
Test name
Test status
Simulation time 1524225964 ps
CPU time 36.3 seconds
Started Mar 03 02:38:21 PM PST 24
Finished Mar 03 02:38:58 PM PST 24
Peak memory 199876 kb
Host smart-52d7d502-c1a3-4c8c-b898-91c9ec676be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665339484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.665339484
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3715621339
Short name T168
Test name
Test status
Simulation time 57803374 ps
CPU time 0.61 seconds
Started Mar 03 02:38:12 PM PST 24
Finished Mar 03 02:38:15 PM PST 24
Peak memory 195156 kb
Host smart-b1efb30d-8ce5-4dba-979a-935504aadf30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3715621339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3715621339
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1244988096
Short name T586
Test name
Test status
Simulation time 2638601021 ps
CPU time 74.13 seconds
Started Mar 03 02:38:13 PM PST 24
Finished Mar 03 02:39:31 PM PST 24
Peak memory 199988 kb
Host smart-606c1891-7936-4cb8-bea5-a6a38702317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244988096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1244988096
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3339601277
Short name T376
Test name
Test status
Simulation time 2498393794 ps
CPU time 12.98 seconds
Started Mar 03 02:38:12 PM PST 24
Finished Mar 03 02:38:27 PM PST 24
Peak memory 200020 kb
Host smart-a14e010d-f01f-4a5f-be43-36e993e590ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339601277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3339601277
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.4220221819
Short name T301
Test name
Test status
Simulation time 1663292143 ps
CPU time 4.84 seconds
Started Mar 03 02:38:15 PM PST 24
Finished Mar 03 02:38:24 PM PST 24
Peak memory 199868 kb
Host smart-39e944ef-09d2-44dd-af67-eb47ebdfe856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220221819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.4220221819
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2589550131
Short name T191
Test name
Test status
Simulation time 28841622473 ps
CPU time 193.04 seconds
Started Mar 03 02:38:15 PM PST 24
Finished Mar 03 02:41:31 PM PST 24
Peak memory 215692 kb
Host smart-a6120dc7-0b60-4845-9f0c-d66a40197659
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589550131 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2589550131
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1493570306
Short name T445
Test name
Test status
Simulation time 279621444 ps
CPU time 1.4 seconds
Started Mar 03 02:38:21 PM PST 24
Finished Mar 03 02:38:23 PM PST 24
Peak memory 199896 kb
Host smart-6e67e05d-c9b1-4f71-9c3c-0bc2be452863
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493570306 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1493570306
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1938607686
Short name T382
Test name
Test status
Simulation time 147843159741 ps
CPU time 420 seconds
Started Mar 03 02:38:12 PM PST 24
Finished Mar 03 02:45:15 PM PST 24
Peak memory 199852 kb
Host smart-441d70e8-8850-48f5-8dcc-3f2a12e2417b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938607686 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.1938607686
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.242781922
Short name T497
Test name
Test status
Simulation time 328734714 ps
CPU time 4.18 seconds
Started Mar 03 02:38:13 PM PST 24
Finished Mar 03 02:38:21 PM PST 24
Peak memory 199856 kb
Host smart-55bb3431-4fcb-4ff3-bae7-83823215cf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242781922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.242781922
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.96217073
Short name T388
Test name
Test status
Simulation time 19972173 ps
CPU time 0.56 seconds
Started Mar 03 02:38:21 PM PST 24
Finished Mar 03 02:38:22 PM PST 24
Peak memory 194280 kb
Host smart-ed0af21f-c005-45fa-981a-580e932d3bc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96217073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.96217073
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3458310574
Short name T307
Test name
Test status
Simulation time 103581809 ps
CPU time 3.54 seconds
Started Mar 03 02:38:17 PM PST 24
Finished Mar 03 02:38:23 PM PST 24
Peak memory 199872 kb
Host smart-2da257e9-bcb3-4960-8664-9894606886fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458310574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3458310574
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3238992193
Short name T103
Test name
Test status
Simulation time 4394250841 ps
CPU time 53.99 seconds
Started Mar 03 02:38:19 PM PST 24
Finished Mar 03 02:39:15 PM PST 24
Peak memory 200004 kb
Host smart-1f780595-a79a-4778-8c01-a3f9f2c059bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238992193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3238992193
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.799331692
Short name T551
Test name
Test status
Simulation time 5306582814 ps
CPU time 49.22 seconds
Started Mar 03 02:38:18 PM PST 24
Finished Mar 03 02:39:08 PM PST 24
Peak memory 199912 kb
Host smart-3ad3623c-7801-4630-97fe-df61e9855a65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=799331692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.799331692
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.462472600
Short name T265
Test name
Test status
Simulation time 1198854864 ps
CPU time 60.86 seconds
Started Mar 03 02:38:22 PM PST 24
Finished Mar 03 02:39:23 PM PST 24
Peak memory 199784 kb
Host smart-4b57565c-04dc-406f-bdbe-733cc62ca1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462472600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.462472600
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.635427596
Short name T179
Test name
Test status
Simulation time 3784060757 ps
CPU time 48.11 seconds
Started Mar 03 02:38:15 PM PST 24
Finished Mar 03 02:39:06 PM PST 24
Peak memory 199724 kb
Host smart-6ccc6c7a-1cf0-4297-aa04-d0ac9233c0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635427596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.635427596
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3173040198
Short name T243
Test name
Test status
Simulation time 50188538 ps
CPU time 0.95 seconds
Started Mar 03 02:38:13 PM PST 24
Finished Mar 03 02:38:18 PM PST 24
Peak memory 197632 kb
Host smart-d4b4f5fd-e015-4305-91b2-7fc1f660b772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173040198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3173040198
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.278702384
Short name T402
Test name
Test status
Simulation time 4039316632 ps
CPU time 180.64 seconds
Started Mar 03 02:38:20 PM PST 24
Finished Mar 03 02:41:22 PM PST 24
Peak memory 200056 kb
Host smart-d6b98334-3031-46a7-ab5a-25071380a96b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278702384 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.278702384
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.675818056
Short name T577
Test name
Test status
Simulation time 150145254 ps
CPU time 1.01 seconds
Started Mar 03 02:38:20 PM PST 24
Finished Mar 03 02:38:23 PM PST 24
Peak memory 197500 kb
Host smart-9c5c53c5-6e1b-43fb-9242-98348d5fb4f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675818056 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_hmac_vectors.675818056
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.170170972
Short name T362
Test name
Test status
Simulation time 49640423984 ps
CPU time 389.9 seconds
Started Mar 03 02:38:22 PM PST 24
Finished Mar 03 02:44:52 PM PST 24
Peak memory 200168 kb
Host smart-d7c7244b-b2e0-4109-8168-4d3c66946f74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170170972 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.hmac_test_sha_vectors.170170972
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3280045187
Short name T521
Test name
Test status
Simulation time 2285825393 ps
CPU time 21.88 seconds
Started Mar 03 02:38:19 PM PST 24
Finished Mar 03 02:38:42 PM PST 24
Peak memory 199988 kb
Host smart-6d24f5ef-daab-412c-bc54-f70c9c0da60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280045187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3280045187
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3598825508
Short name T460
Test name
Test status
Simulation time 51344906 ps
CPU time 0.56 seconds
Started Mar 03 02:38:21 PM PST 24
Finished Mar 03 02:38:22 PM PST 24
Peak memory 195272 kb
Host smart-9a4fb7c1-dd11-4dce-9a04-3ec9fa779f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598825508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3598825508
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2988344810
Short name T314
Test name
Test status
Simulation time 2100615840 ps
CPU time 16.46 seconds
Started Mar 03 02:38:22 PM PST 24
Finished Mar 03 02:38:39 PM PST 24
Peak memory 228548 kb
Host smart-7dab1b27-4d09-476f-8c0f-25a5a641f83e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988344810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2988344810
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3301178456
Short name T369
Test name
Test status
Simulation time 632059804 ps
CPU time 13.02 seconds
Started Mar 03 02:38:21 PM PST 24
Finished Mar 03 02:38:35 PM PST 24
Peak memory 199816 kb
Host smart-c0c846c6-0529-4a59-a41a-3d4fe26d2355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301178456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3301178456
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1417249312
Short name T372
Test name
Test status
Simulation time 889395578 ps
CPU time 49.2 seconds
Started Mar 03 02:38:19 PM PST 24
Finished Mar 03 02:39:10 PM PST 24
Peak memory 199868 kb
Host smart-bb78e427-19b7-4908-b663-5ac300264f21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417249312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1417249312
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2176132111
Short name T526
Test name
Test status
Simulation time 1479790479 ps
CPU time 71.82 seconds
Started Mar 03 02:38:20 PM PST 24
Finished Mar 03 02:39:33 PM PST 24
Peak memory 199848 kb
Host smart-50a0ba98-dfa9-47fd-8ba4-9df7b67a95c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176132111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2176132111
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1634621815
Short name T541
Test name
Test status
Simulation time 6093596148 ps
CPU time 80.43 seconds
Started Mar 03 02:38:20 PM PST 24
Finished Mar 03 02:39:42 PM PST 24
Peak memory 199912 kb
Host smart-2f3dcc2f-9437-4377-9fb6-117d6c36b0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634621815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1634621815
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1407802365
Short name T80
Test name
Test status
Simulation time 260090560 ps
CPU time 3.56 seconds
Started Mar 03 02:38:20 PM PST 24
Finished Mar 03 02:38:25 PM PST 24
Peak memory 199896 kb
Host smart-d92ff47d-b7b8-4acb-ba2b-90541d6c2ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407802365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1407802365
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.34051112
Short name T259
Test name
Test status
Simulation time 13427992302 ps
CPU time 631.57 seconds
Started Mar 03 02:38:19 PM PST 24
Finished Mar 03 02:48:53 PM PST 24
Peak memory 200096 kb
Host smart-d07cb2c8-9c26-44d9-8013-add1c83a1a05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34051112 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.34051112
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3747024992
Short name T533
Test name
Test status
Simulation time 115844484 ps
CPU time 1.19 seconds
Started Mar 03 02:38:22 PM PST 24
Finished Mar 03 02:38:23 PM PST 24
Peak memory 198584 kb
Host smart-3845609f-0026-4ba9-ac1a-5b5392bccd90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747024992 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3747024992
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2513452365
Short name T378
Test name
Test status
Simulation time 4365506615 ps
CPU time 63.33 seconds
Started Mar 03 02:38:20 PM PST 24
Finished Mar 03 02:39:25 PM PST 24
Peak memory 199996 kb
Host smart-d749e134-3ec5-4734-81a2-6ae7809b45b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513452365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2513452365
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3481397886
Short name T584
Test name
Test status
Simulation time 43645379 ps
CPU time 0.57 seconds
Started Mar 03 02:36:58 PM PST 24
Finished Mar 03 02:36:59 PM PST 24
Peak memory 194436 kb
Host smart-d45e588b-cc3f-40da-8970-daa84d4e794f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481397886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3481397886
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1147981676
Short name T500
Test name
Test status
Simulation time 1951635850 ps
CPU time 15.23 seconds
Started Mar 03 02:36:52 PM PST 24
Finished Mar 03 02:37:07 PM PST 24
Peak memory 199832 kb
Host smart-c0ecb209-3c2d-4009-af0d-5c97d1cd7ad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1147981676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1147981676
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.665837907
Short name T450
Test name
Test status
Simulation time 1346689370 ps
CPU time 19.29 seconds
Started Mar 03 02:36:52 PM PST 24
Finished Mar 03 02:37:12 PM PST 24
Peak memory 199864 kb
Host smart-11341128-e1dc-476a-8845-a6c6ac018fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665837907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.665837907
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2965857077
Short name T111
Test name
Test status
Simulation time 12233794705 ps
CPU time 114.96 seconds
Started Mar 03 02:36:51 PM PST 24
Finished Mar 03 02:38:46 PM PST 24
Peak memory 199984 kb
Host smart-bce70290-e4b3-433c-98b7-121abf6bdd37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965857077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2965857077
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.4147070817
Short name T169
Test name
Test status
Simulation time 12654898766 ps
CPU time 34.93 seconds
Started Mar 03 02:36:50 PM PST 24
Finished Mar 03 02:37:25 PM PST 24
Peak memory 200012 kb
Host smart-eb3676e4-6b32-4703-bef7-1aa43ff29c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147070817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.4147070817
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1030653122
Short name T131
Test name
Test status
Simulation time 1239073210 ps
CPU time 64.42 seconds
Started Mar 03 02:36:52 PM PST 24
Finished Mar 03 02:37:57 PM PST 24
Peak memory 199936 kb
Host smart-d5e30460-d9e9-4944-b19c-625a0593273c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030653122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1030653122
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.234147717
Short name T27
Test name
Test status
Simulation time 329263763 ps
CPU time 0.97 seconds
Started Mar 03 02:36:50 PM PST 24
Finished Mar 03 02:36:51 PM PST 24
Peak memory 218100 kb
Host smart-5e42301b-8381-4c6e-a44a-148d95744e56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234147717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.234147717
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1563835757
Short name T505
Test name
Test status
Simulation time 522444721 ps
CPU time 3.03 seconds
Started Mar 03 02:36:51 PM PST 24
Finished Mar 03 02:36:54 PM PST 24
Peak memory 199784 kb
Host smart-608ee70d-eef8-4873-af62-2f3ecead6afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563835757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1563835757
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2192773257
Short name T531
Test name
Test status
Simulation time 40707402 ps
CPU time 0.95 seconds
Started Mar 03 02:36:52 PM PST 24
Finished Mar 03 02:36:53 PM PST 24
Peak memory 197376 kb
Host smart-986296bf-4b92-478d-8db4-43e87ee3320b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192773257 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2192773257
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2971176551
Short name T508
Test name
Test status
Simulation time 198272951622 ps
CPU time 466.45 seconds
Started Mar 03 02:36:49 PM PST 24
Finished Mar 03 02:44:36 PM PST 24
Peak memory 199956 kb
Host smart-b1bd653d-5049-4980-affd-1dcfb4bb50a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971176551 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.2971176551
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1757872124
Short name T64
Test name
Test status
Simulation time 2353002822 ps
CPU time 39.42 seconds
Started Mar 03 02:36:50 PM PST 24
Finished Mar 03 02:37:29 PM PST 24
Peak memory 200004 kb
Host smart-1a09fd98-3604-47e8-9887-5a008b4beacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757872124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1757872124
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3229830720
Short name T332
Test name
Test status
Simulation time 92107247 ps
CPU time 0.56 seconds
Started Mar 03 02:38:28 PM PST 24
Finished Mar 03 02:38:29 PM PST 24
Peak memory 194208 kb
Host smart-e08f08c2-5701-44b4-ae65-f17ed6ae5be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229830720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3229830720
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.630044270
Short name T315
Test name
Test status
Simulation time 4953945432 ps
CPU time 36.72 seconds
Started Mar 03 02:38:27 PM PST 24
Finished Mar 03 02:39:04 PM PST 24
Peak memory 208176 kb
Host smart-adf2808d-7c6b-4f03-8f18-f6ffd22a9778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=630044270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.630044270
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3975237737
Short name T331
Test name
Test status
Simulation time 5420769003 ps
CPU time 26.27 seconds
Started Mar 03 02:38:30 PM PST 24
Finished Mar 03 02:38:56 PM PST 24
Peak memory 200016 kb
Host smart-48add9f6-f58b-40d8-b5cf-97b8dbd319fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975237737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3975237737
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_error.3074573864
Short name T344
Test name
Test status
Simulation time 30027638798 ps
CPU time 130 seconds
Started Mar 03 02:38:30 PM PST 24
Finished Mar 03 02:40:40 PM PST 24
Peak memory 199988 kb
Host smart-08282883-d638-4cb1-86d7-39b027b4db16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074573864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3074573864
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.62930930
Short name T172
Test name
Test status
Simulation time 4066980697 ps
CPU time 75.54 seconds
Started Mar 03 02:38:27 PM PST 24
Finished Mar 03 02:39:43 PM PST 24
Peak memory 199988 kb
Host smart-8e8af275-0bd4-474d-8c98-87a70fa62012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62930930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.62930930
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2334284622
Short name T177
Test name
Test status
Simulation time 360808353 ps
CPU time 1.59 seconds
Started Mar 03 02:38:20 PM PST 24
Finished Mar 03 02:38:23 PM PST 24
Peak memory 199892 kb
Host smart-97c000ba-3c05-463c-bfe7-4009a0528f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334284622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2334284622
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2930710430
Short name T438
Test name
Test status
Simulation time 9650059119 ps
CPU time 165.03 seconds
Started Mar 03 02:38:26 PM PST 24
Finished Mar 03 02:41:11 PM PST 24
Peak memory 200056 kb
Host smart-b9689f76-b6bd-40fb-bc1c-cecdfd09a739
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930710430 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2930710430
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3015172247
Short name T185
Test name
Test status
Simulation time 55495886 ps
CPU time 1.19 seconds
Started Mar 03 02:38:38 PM PST 24
Finished Mar 03 02:38:39 PM PST 24
Peak memory 198888 kb
Host smart-c58e9c22-5f41-4afe-94fd-585e329d3216
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015172247 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3015172247
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1829209108
Short name T447
Test name
Test status
Simulation time 28769786522 ps
CPU time 457.01 seconds
Started Mar 03 02:38:27 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 199968 kb
Host smart-9ab05fb3-d6fd-41b0-bc54-76c04dfaed39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829209108 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.1829209108
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1382449011
Short name T529
Test name
Test status
Simulation time 7539356855 ps
CPU time 60.12 seconds
Started Mar 03 02:38:28 PM PST 24
Finished Mar 03 02:39:28 PM PST 24
Peak memory 199976 kb
Host smart-dc5110c9-80c6-4376-b5ed-731b7c63c28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382449011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1382449011
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.4149292570
Short name T564
Test name
Test status
Simulation time 20504886 ps
CPU time 0.59 seconds
Started Mar 03 02:38:36 PM PST 24
Finished Mar 03 02:38:36 PM PST 24
Peak memory 194448 kb
Host smart-759b3984-8b44-46e0-9bad-70fca522c2ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149292570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.4149292570
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2389023308
Short name T527
Test name
Test status
Simulation time 3606882225 ps
CPU time 36.11 seconds
Started Mar 03 02:38:29 PM PST 24
Finished Mar 03 02:39:06 PM PST 24
Peak memory 222452 kb
Host smart-d5ebd854-e55e-416b-965b-db6a426b1cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2389023308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2389023308
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.513135559
Short name T336
Test name
Test status
Simulation time 1412268077 ps
CPU time 27.99 seconds
Started Mar 03 02:38:27 PM PST 24
Finished Mar 03 02:38:55 PM PST 24
Peak memory 199848 kb
Host smart-6d0c418e-18d6-4ef8-8555-745c90cae64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513135559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.513135559
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2207844306
Short name T226
Test name
Test status
Simulation time 224054643 ps
CPU time 1.81 seconds
Started Mar 03 02:38:38 PM PST 24
Finished Mar 03 02:38:40 PM PST 24
Peak memory 199872 kb
Host smart-8824d46b-7714-4478-ab4a-4f0b412d0837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2207844306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2207844306
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2671610559
Short name T539
Test name
Test status
Simulation time 55918310709 ps
CPU time 77.08 seconds
Started Mar 03 02:38:26 PM PST 24
Finished Mar 03 02:39:44 PM PST 24
Peak memory 199988 kb
Host smart-c9364c98-1d08-4b78-9bf8-e00b568291bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671610559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2671610559
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.164556851
Short name T230
Test name
Test status
Simulation time 760594800 ps
CPU time 42.57 seconds
Started Mar 03 02:38:30 PM PST 24
Finished Mar 03 02:39:12 PM PST 24
Peak memory 199896 kb
Host smart-981f498d-1688-4a25-922c-5d536af75517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164556851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.164556851
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.821895604
Short name T365
Test name
Test status
Simulation time 2666826351 ps
CPU time 2.09 seconds
Started Mar 03 02:38:30 PM PST 24
Finished Mar 03 02:38:32 PM PST 24
Peak memory 199992 kb
Host smart-d2a4cd85-ab69-4d34-aa4f-b13850a7ad53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821895604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.821895604
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3564767500
Short name T410
Test name
Test status
Simulation time 23647438568 ps
CPU time 1165.41 seconds
Started Mar 03 02:38:28 PM PST 24
Finished Mar 03 02:57:53 PM PST 24
Peak memory 241036 kb
Host smart-fa9a5785-addd-444a-b64d-28ccbd0feac7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564767500 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3564767500
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2830295562
Short name T442
Test name
Test status
Simulation time 30576654 ps
CPU time 1.12 seconds
Started Mar 03 02:38:27 PM PST 24
Finished Mar 03 02:38:28 PM PST 24
Peak memory 198852 kb
Host smart-c480da0e-b3f8-416f-af5d-830a5a47b24c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830295562 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2830295562
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.278728880
Short name T255
Test name
Test status
Simulation time 31907095497 ps
CPU time 411.79 seconds
Started Mar 03 02:38:29 PM PST 24
Finished Mar 03 02:45:22 PM PST 24
Peak memory 199680 kb
Host smart-17ffa81e-9c7f-44c7-a2cd-7533b07154ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278728880 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.hmac_test_sha_vectors.278728880
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3122067846
Short name T306
Test name
Test status
Simulation time 140389245 ps
CPU time 3.78 seconds
Started Mar 03 02:38:30 PM PST 24
Finished Mar 03 02:38:34 PM PST 24
Peak memory 199904 kb
Host smart-1f3fbda6-0b49-4a25-b26e-b076387ca071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122067846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3122067846
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1758797813
Short name T280
Test name
Test status
Simulation time 13354494 ps
CPU time 0.57 seconds
Started Mar 03 02:38:35 PM PST 24
Finished Mar 03 02:38:35 PM PST 24
Peak memory 194156 kb
Host smart-de6f9f99-fd6b-464d-9273-9d5ea30db23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758797813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1758797813
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1214420400
Short name T240
Test name
Test status
Simulation time 1290493617 ps
CPU time 43.96 seconds
Started Mar 03 02:38:39 PM PST 24
Finished Mar 03 02:39:23 PM PST 24
Peak memory 230364 kb
Host smart-b59d0b2c-ec8b-411a-bab1-34b5343fd869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214420400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1214420400
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.649237382
Short name T491
Test name
Test status
Simulation time 5276175546 ps
CPU time 26.35 seconds
Started Mar 03 02:38:33 PM PST 24
Finished Mar 03 02:39:00 PM PST 24
Peak memory 200040 kb
Host smart-ac2c76f2-fc6e-4c28-b2ca-0a353b4595aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649237382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.649237382
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3360990826
Short name T174
Test name
Test status
Simulation time 4777812735 ps
CPU time 64.31 seconds
Started Mar 03 02:38:34 PM PST 24
Finished Mar 03 02:39:39 PM PST 24
Peak memory 199964 kb
Host smart-7d824a10-b2d6-4b1d-81be-2d0a7acfe33d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360990826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3360990826
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.647620259
Short name T351
Test name
Test status
Simulation time 2652778836 ps
CPU time 43.49 seconds
Started Mar 03 02:38:37 PM PST 24
Finished Mar 03 02:39:21 PM PST 24
Peak memory 199884 kb
Host smart-effbd755-c837-452e-8b5b-18493c4a9e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647620259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.647620259
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.948773900
Short name T3
Test name
Test status
Simulation time 840149948 ps
CPU time 22.03 seconds
Started Mar 03 02:38:34 PM PST 24
Finished Mar 03 02:38:56 PM PST 24
Peak memory 199820 kb
Host smart-92a0842c-aa94-48dc-82a1-30d167428913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948773900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.948773900
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2495865767
Short name T503
Test name
Test status
Simulation time 48227627 ps
CPU time 0.98 seconds
Started Mar 03 02:38:38 PM PST 24
Finished Mar 03 02:38:40 PM PST 24
Peak memory 197524 kb
Host smart-a4899aa5-3beb-4353-95d2-2ebf109a09fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495865767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2495865767
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3275966779
Short name T305
Test name
Test status
Simulation time 25049880167 ps
CPU time 1271.39 seconds
Started Mar 03 02:38:32 PM PST 24
Finished Mar 03 02:59:44 PM PST 24
Peak memory 199940 kb
Host smart-b10d63f5-f77f-4316-b96a-33858fbdeb5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275966779 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3275966779
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2205574669
Short name T437
Test name
Test status
Simulation time 188709076 ps
CPU time 1.01 seconds
Started Mar 03 02:38:31 PM PST 24
Finished Mar 03 02:38:32 PM PST 24
Peak memory 197712 kb
Host smart-6aad3805-5a4e-4d4b-a63d-e6f2f2521733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205574669 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2205574669
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1907492193
Short name T196
Test name
Test status
Simulation time 39613858258 ps
CPU time 435.33 seconds
Started Mar 03 02:38:35 PM PST 24
Finished Mar 03 02:45:50 PM PST 24
Peak memory 199912 kb
Host smart-708b26f3-8493-4ea9-8a68-76f004414e92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907492193 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.1907492193
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.61867736
Short name T152
Test name
Test status
Simulation time 1012716673 ps
CPU time 27.21 seconds
Started Mar 03 02:38:35 PM PST 24
Finished Mar 03 02:39:02 PM PST 24
Peak memory 199784 kb
Host smart-1c87e5ae-6ed8-4a71-a36e-70f1fb8f2758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61867736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.61867736
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3300619702
Short name T272
Test name
Test status
Simulation time 26972588 ps
CPU time 0.59 seconds
Started Mar 03 02:38:39 PM PST 24
Finished Mar 03 02:38:40 PM PST 24
Peak memory 194260 kb
Host smart-5a3751bd-f62b-4ea2-bd0c-b98f09405c7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300619702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3300619702
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3542967230
Short name T252
Test name
Test status
Simulation time 1048160895 ps
CPU time 7.99 seconds
Started Mar 03 02:38:34 PM PST 24
Finished Mar 03 02:38:42 PM PST 24
Peak memory 199820 kb
Host smart-3674f159-71f9-4318-81c2-007e63963dac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542967230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3542967230
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1391326553
Short name T38
Test name
Test status
Simulation time 5725063203 ps
CPU time 71.7 seconds
Started Mar 03 02:38:33 PM PST 24
Finished Mar 03 02:39:45 PM PST 24
Peak memory 199988 kb
Host smart-ab8cb3a1-3f0b-4a7d-b87c-cfeb37d5a03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391326553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1391326553
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3397574815
Short name T587
Test name
Test status
Simulation time 3438387319 ps
CPU time 88.03 seconds
Started Mar 03 02:38:34 PM PST 24
Finished Mar 03 02:40:02 PM PST 24
Peak memory 199968 kb
Host smart-357eb625-9379-49f8-91b2-c4ee018b658a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397574815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3397574815
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.33545931
Short name T492
Test name
Test status
Simulation time 5847010060 ps
CPU time 46.44 seconds
Started Mar 03 02:38:32 PM PST 24
Finished Mar 03 02:39:19 PM PST 24
Peak memory 200028 kb
Host smart-0bc8a906-e4f5-4a83-a0ae-83f650c1d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33545931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.33545931
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3671304651
Short name T53
Test name
Test status
Simulation time 12186579655 ps
CPU time 44.42 seconds
Started Mar 03 02:38:39 PM PST 24
Finished Mar 03 02:39:24 PM PST 24
Peak memory 200012 kb
Host smart-202e298a-0fb9-4b7b-97ce-a9ae2d45cd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671304651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3671304651
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1456399555
Short name T294
Test name
Test status
Simulation time 383455864 ps
CPU time 1.19 seconds
Started Mar 03 02:38:33 PM PST 24
Finished Mar 03 02:38:34 PM PST 24
Peak memory 199772 kb
Host smart-89160eec-4fd4-47d0-8de5-92c5a7c362df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456399555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1456399555
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2907456013
Short name T570
Test name
Test status
Simulation time 108699623144 ps
CPU time 1903.89 seconds
Started Mar 03 02:38:41 PM PST 24
Finished Mar 03 03:10:25 PM PST 24
Peak memory 200024 kb
Host smart-adfd3bb0-7104-4393-ad4e-cbeb06a9e822
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907456013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2907456013
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1300165571
Short name T421
Test name
Test status
Simulation time 60708695 ps
CPU time 0.95 seconds
Started Mar 03 02:38:40 PM PST 24
Finished Mar 03 02:38:41 PM PST 24
Peak memory 197576 kb
Host smart-33dce0c9-e882-4e32-a4a9-394dec16cb8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300165571 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1300165571
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.656206780
Short name T212
Test name
Test status
Simulation time 153824477246 ps
CPU time 427.6 seconds
Started Mar 03 02:38:34 PM PST 24
Finished Mar 03 02:45:42 PM PST 24
Peak memory 199884 kb
Host smart-8ed3255f-2b3c-4ef3-8dae-1ec062b72f70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656206780 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.hmac_test_sha_vectors.656206780
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.689202863
Short name T30
Test name
Test status
Simulation time 2591229735 ps
CPU time 32.11 seconds
Started Mar 03 02:38:35 PM PST 24
Finished Mar 03 02:39:07 PM PST 24
Peak memory 200036 kb
Host smart-d156eda4-e936-4d7c-b151-ed2858bbc819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689202863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.689202863
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3657736438
Short name T512
Test name
Test status
Simulation time 10960328 ps
CPU time 0.56 seconds
Started Mar 03 02:38:44 PM PST 24
Finished Mar 03 02:38:45 PM PST 24
Peak memory 194436 kb
Host smart-2e4ef37e-7763-42f7-ad3c-8bbd31d8c752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657736438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3657736438
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1585340034
Short name T11
Test name
Test status
Simulation time 40604622 ps
CPU time 1.73 seconds
Started Mar 03 02:38:43 PM PST 24
Finished Mar 03 02:38:45 PM PST 24
Peak memory 199812 kb
Host smart-7d728b3d-bc88-4f16-a952-798198a4b89f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585340034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1585340034
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.68282903
Short name T557
Test name
Test status
Simulation time 1705075826 ps
CPU time 88.28 seconds
Started Mar 03 02:38:42 PM PST 24
Finished Mar 03 02:40:10 PM PST 24
Peak memory 199776 kb
Host smart-360752a5-43cf-42bc-9cde-4f6f018b5df9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68282903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.68282903
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1550464847
Short name T153
Test name
Test status
Simulation time 8078403932 ps
CPU time 93.36 seconds
Started Mar 03 02:38:41 PM PST 24
Finished Mar 03 02:40:15 PM PST 24
Peak memory 200172 kb
Host smart-73e6fe8c-b047-467b-8989-7d19e359ce70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550464847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1550464847
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.158236760
Short name T276
Test name
Test status
Simulation time 4070056895 ps
CPU time 71.35 seconds
Started Mar 03 02:38:40 PM PST 24
Finished Mar 03 02:39:52 PM PST 24
Peak memory 200000 kb
Host smart-c57e9706-0760-431c-9ea8-9e3d91f767ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158236760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.158236760
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3274020041
Short name T540
Test name
Test status
Simulation time 38064559 ps
CPU time 1.25 seconds
Started Mar 03 02:38:42 PM PST 24
Finished Mar 03 02:38:44 PM PST 24
Peak memory 199628 kb
Host smart-3639962d-6ac7-4bac-964d-28b021fc3013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274020041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3274020041
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.2526131675
Short name T39
Test name
Test status
Simulation time 24352018226 ps
CPU time 1079.66 seconds
Started Mar 03 02:38:45 PM PST 24
Finished Mar 03 02:56:45 PM PST 24
Peak memory 208372 kb
Host smart-06edd03f-9d94-4dc5-8cf5-4ae24a6c5c21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526131675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.2526131675
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3752589188
Short name T523
Test name
Test status
Simulation time 99515651 ps
CPU time 1.19 seconds
Started Mar 03 02:38:42 PM PST 24
Finished Mar 03 02:38:43 PM PST 24
Peak memory 198512 kb
Host smart-fa76e627-5dbd-4037-8942-759fc101cf0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752589188 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3752589188
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2378764994
Short name T375
Test name
Test status
Simulation time 73272769054 ps
CPU time 481.94 seconds
Started Mar 03 02:38:41 PM PST 24
Finished Mar 03 02:46:43 PM PST 24
Peak memory 199936 kb
Host smart-9a1e80f9-23d7-4e42-ab74-8e09cee539c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378764994 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.2378764994
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.4052086282
Short name T167
Test name
Test status
Simulation time 1702118125 ps
CPU time 22.83 seconds
Started Mar 03 02:38:41 PM PST 24
Finished Mar 03 02:39:04 PM PST 24
Peak memory 199864 kb
Host smart-f449adc5-3045-49a9-936f-438c9c4e7d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052086282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.4052086282
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1566498057
Short name T452
Test name
Test status
Simulation time 46779489 ps
CPU time 0.55 seconds
Started Mar 03 02:38:52 PM PST 24
Finished Mar 03 02:38:53 PM PST 24
Peak memory 194148 kb
Host smart-3a7e7036-5e9c-44e1-8856-c95631898b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566498057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1566498057
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.8847718
Short name T10
Test name
Test status
Simulation time 751455542 ps
CPU time 12.07 seconds
Started Mar 03 02:38:48 PM PST 24
Finished Mar 03 02:39:01 PM PST 24
Peak memory 232500 kb
Host smart-d85e869e-3949-43cf-9a24-9a44d1c14767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8847718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.8847718
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.97371659
Short name T295
Test name
Test status
Simulation time 1030146883 ps
CPU time 14.51 seconds
Started Mar 03 02:38:44 PM PST 24
Finished Mar 03 02:38:59 PM PST 24
Peak memory 199848 kb
Host smart-0f05fb7e-19cd-43ea-9900-90fbe75cb714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97371659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.97371659
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2125463198
Short name T189
Test name
Test status
Simulation time 5335598466 ps
CPU time 71.55 seconds
Started Mar 03 02:38:49 PM PST 24
Finished Mar 03 02:40:00 PM PST 24
Peak memory 199944 kb
Host smart-d879d4a8-0cbb-4894-9a99-5ac0e1e2dd0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2125463198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2125463198
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.124866399
Short name T419
Test name
Test status
Simulation time 4612687039 ps
CPU time 106.75 seconds
Started Mar 03 02:38:50 PM PST 24
Finished Mar 03 02:40:37 PM PST 24
Peak memory 199988 kb
Host smart-3c65388b-53fa-40b2-89ac-2ec8d69c5fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124866399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.124866399
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3340708664
Short name T412
Test name
Test status
Simulation time 292169120 ps
CPU time 1.37 seconds
Started Mar 03 02:38:52 PM PST 24
Finished Mar 03 02:38:53 PM PST 24
Peak memory 199772 kb
Host smart-e956847a-3a27-40fb-8642-71bfbf148df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340708664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3340708664
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1983689334
Short name T455
Test name
Test status
Simulation time 191855308 ps
CPU time 1.85 seconds
Started Mar 03 02:38:46 PM PST 24
Finished Mar 03 02:38:48 PM PST 24
Peak memory 199812 kb
Host smart-448e3a90-6b63-4c03-9125-982ef03f435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983689334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1983689334
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3837339120
Short name T117
Test name
Test status
Simulation time 9081640003 ps
CPU time 460.67 seconds
Started Mar 03 02:38:45 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 199984 kb
Host smart-99f60b00-d3fc-4130-b39a-a5dd3be6fa87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837339120 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3837339120
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3085438920
Short name T281
Test name
Test status
Simulation time 84688063 ps
CPU time 1.13 seconds
Started Mar 03 02:38:44 PM PST 24
Finished Mar 03 02:38:46 PM PST 24
Peak memory 198716 kb
Host smart-b25ad614-21c5-4a4e-bfc6-8f9ee02e8d32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085438920 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3085438920
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.512164547
Short name T32
Test name
Test status
Simulation time 174050058631 ps
CPU time 472.37 seconds
Started Mar 03 02:38:46 PM PST 24
Finished Mar 03 02:46:39 PM PST 24
Peak memory 199928 kb
Host smart-27925f3c-2ca0-4ec7-93bf-c0d4fecbaa7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512164547 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.hmac_test_sha_vectors.512164547
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1147342027
Short name T234
Test name
Test status
Simulation time 122768903 ps
CPU time 0.61 seconds
Started Mar 03 02:38:49 PM PST 24
Finished Mar 03 02:38:49 PM PST 24
Peak memory 194704 kb
Host smart-b1c3dbd1-2544-441a-a478-21c534425e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147342027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1147342027
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2866220520
Short name T555
Test name
Test status
Simulation time 15599580 ps
CPU time 0.6 seconds
Started Mar 03 02:38:52 PM PST 24
Finished Mar 03 02:38:53 PM PST 24
Peak memory 194244 kb
Host smart-316efe9c-6418-4422-be0e-f9dfdbd6b969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866220520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2866220520
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.831161954
Short name T501
Test name
Test status
Simulation time 2471657119 ps
CPU time 39.04 seconds
Started Mar 03 02:38:50 PM PST 24
Finished Mar 03 02:39:30 PM PST 24
Peak memory 216216 kb
Host smart-44427435-a27b-44e7-a69e-2ccf9ba53c4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831161954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.831161954
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3252514687
Short name T413
Test name
Test status
Simulation time 994457256 ps
CPU time 45.81 seconds
Started Mar 03 02:38:54 PM PST 24
Finished Mar 03 02:39:39 PM PST 24
Peak memory 199916 kb
Host smart-f639d8e8-aa20-4f09-9f9a-b2c20ba85feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252514687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3252514687
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.4220078056
Short name T579
Test name
Test status
Simulation time 1501068540 ps
CPU time 40.84 seconds
Started Mar 03 02:38:55 PM PST 24
Finished Mar 03 02:39:37 PM PST 24
Peak memory 199904 kb
Host smart-e13c7b9a-16a9-4fa3-9fe7-1d347ce2614f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220078056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.4220078056
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3997743361
Short name T329
Test name
Test status
Simulation time 16516538589 ps
CPU time 94.65 seconds
Started Mar 03 02:38:52 PM PST 24
Finished Mar 03 02:40:26 PM PST 24
Peak memory 199896 kb
Host smart-9699d2b7-4e6c-4396-9965-f2abe51c6e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997743361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3997743361
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1344609191
Short name T37
Test name
Test status
Simulation time 1387731136 ps
CPU time 9.7 seconds
Started Mar 03 02:38:52 PM PST 24
Finished Mar 03 02:39:02 PM PST 24
Peak memory 199868 kb
Host smart-bbd24857-dd25-49fa-a088-5694c4a53d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344609191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1344609191
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3110460937
Short name T425
Test name
Test status
Simulation time 529219985 ps
CPU time 1.76 seconds
Started Mar 03 02:38:59 PM PST 24
Finished Mar 03 02:39:01 PM PST 24
Peak memory 199608 kb
Host smart-ade10332-330c-4524-a773-fef82a88feb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110460937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3110460937
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.4259644366
Short name T135
Test name
Test status
Simulation time 2439559089751 ps
CPU time 1765.72 seconds
Started Mar 03 02:38:54 PM PST 24
Finished Mar 03 03:08:20 PM PST 24
Peak memory 232768 kb
Host smart-f6971a50-06ed-4b16-9b28-058547c6901b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259644366 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.4259644366
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1343281414
Short name T473
Test name
Test status
Simulation time 64798599 ps
CPU time 1.28 seconds
Started Mar 03 02:38:56 PM PST 24
Finished Mar 03 02:38:58 PM PST 24
Peak memory 199524 kb
Host smart-cbace0db-3368-420b-b14a-926c91e262a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343281414 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1343281414
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2295579495
Short name T363
Test name
Test status
Simulation time 70228068335 ps
CPU time 384.85 seconds
Started Mar 03 02:38:54 PM PST 24
Finished Mar 03 02:45:19 PM PST 24
Peak memory 199912 kb
Host smart-d672f025-df5d-484c-9027-409332dc4134
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295579495 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.2295579495
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.960801702
Short name T277
Test name
Test status
Simulation time 2992063400 ps
CPU time 13.21 seconds
Started Mar 03 02:38:52 PM PST 24
Finished Mar 03 02:39:05 PM PST 24
Peak memory 200004 kb
Host smart-960e82c6-fa04-47ab-a5d9-2011306ed0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960801702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.960801702
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.755360110
Short name T397
Test name
Test status
Simulation time 27184916 ps
CPU time 0.55 seconds
Started Mar 03 02:38:57 PM PST 24
Finished Mar 03 02:38:57 PM PST 24
Peak memory 194360 kb
Host smart-ad9865f2-9845-4517-94d6-726efd06cbfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755360110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.755360110
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.163964638
Short name T534
Test name
Test status
Simulation time 66765553 ps
CPU time 1.69 seconds
Started Mar 03 02:38:59 PM PST 24
Finished Mar 03 02:39:01 PM PST 24
Peak memory 199912 kb
Host smart-65c2bb08-3e12-4e65-9e91-91be783bd0d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163964638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.163964638
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3850190785
Short name T79
Test name
Test status
Simulation time 1067042834 ps
CPU time 12.67 seconds
Started Mar 03 02:38:53 PM PST 24
Finished Mar 03 02:39:06 PM PST 24
Peak memory 199820 kb
Host smart-0eb9b2cd-b22c-4b83-abf4-7a2bd783afe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850190785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3850190785
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3713702711
Short name T406
Test name
Test status
Simulation time 4110044374 ps
CPU time 130.52 seconds
Started Mar 03 02:38:52 PM PST 24
Finished Mar 03 02:41:03 PM PST 24
Peak memory 200040 kb
Host smart-4baf2db4-d275-4504-a81b-1785138c0071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713702711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3713702711
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2118876266
Short name T157
Test name
Test status
Simulation time 7367596785 ps
CPU time 30.16 seconds
Started Mar 03 02:38:52 PM PST 24
Finished Mar 03 02:39:23 PM PST 24
Peak memory 199968 kb
Host smart-7c654cb4-0af4-4985-8244-a46e7f43d860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118876266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2118876266
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1913421625
Short name T12
Test name
Test status
Simulation time 9418129740 ps
CPU time 76.98 seconds
Started Mar 03 02:38:59 PM PST 24
Finished Mar 03 02:40:16 PM PST 24
Peak memory 199996 kb
Host smart-d76796b7-4160-45f5-bedd-0339fd384fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913421625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1913421625
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.404691798
Short name T145
Test name
Test status
Simulation time 900463014 ps
CPU time 2.2 seconds
Started Mar 03 02:38:51 PM PST 24
Finished Mar 03 02:38:53 PM PST 24
Peak memory 199860 kb
Host smart-91701214-0ca8-4483-9729-16b020d80fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404691798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.404691798
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3639659682
Short name T498
Test name
Test status
Simulation time 69206046 ps
CPU time 1.21 seconds
Started Mar 03 02:38:51 PM PST 24
Finished Mar 03 02:38:52 PM PST 24
Peak memory 198648 kb
Host smart-eabbe0ff-9294-4505-a87c-63699a4e8816
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639659682 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3639659682
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3236306394
Short name T578
Test name
Test status
Simulation time 27296513492 ps
CPU time 443.96 seconds
Started Mar 03 02:38:52 PM PST 24
Finished Mar 03 02:46:16 PM PST 24
Peak memory 199956 kb
Host smart-7aae094a-d6f4-4355-8ee1-216736664761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236306394 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.3236306394
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1635393550
Short name T484
Test name
Test status
Simulation time 19793177364 ps
CPU time 61.58 seconds
Started Mar 03 02:38:51 PM PST 24
Finished Mar 03 02:39:53 PM PST 24
Peak memory 200024 kb
Host smart-f55293a6-a501-4d93-9bc2-631eea97f8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635393550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1635393550
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3843268383
Short name T160
Test name
Test status
Simulation time 71147867 ps
CPU time 0.59 seconds
Started Mar 03 02:38:57 PM PST 24
Finished Mar 03 02:38:58 PM PST 24
Peak memory 194448 kb
Host smart-18175dcf-f286-47b2-86c4-5f0da199c32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843268383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3843268383
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2788135851
Short name T47
Test name
Test status
Simulation time 4731194481 ps
CPU time 42.56 seconds
Started Mar 03 02:38:56 PM PST 24
Finished Mar 03 02:39:39 PM PST 24
Peak memory 228324 kb
Host smart-16247fef-fd93-4086-bb2c-df8daccf63e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788135851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2788135851
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3591825316
Short name T231
Test name
Test status
Simulation time 786869992 ps
CPU time 2.91 seconds
Started Mar 03 02:38:56 PM PST 24
Finished Mar 03 02:39:00 PM PST 24
Peak memory 199872 kb
Host smart-fded7000-c75d-4e1c-a416-41706f2103bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591825316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3591825316
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3814343717
Short name T193
Test name
Test status
Simulation time 11364861130 ps
CPU time 144.02 seconds
Started Mar 03 02:38:58 PM PST 24
Finished Mar 03 02:41:22 PM PST 24
Peak memory 199932 kb
Host smart-d578f3ba-ab2c-4163-be1d-a44b987ceca5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814343717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3814343717
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.126855303
Short name T405
Test name
Test status
Simulation time 8314280553 ps
CPU time 112.41 seconds
Started Mar 03 02:38:57 PM PST 24
Finished Mar 03 02:40:50 PM PST 24
Peak memory 199996 kb
Host smart-da13dbb7-340e-49e9-81cf-9c10e0eb710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126855303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.126855303
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2541919710
Short name T130
Test name
Test status
Simulation time 5098117303 ps
CPU time 71.73 seconds
Started Mar 03 02:38:58 PM PST 24
Finished Mar 03 02:40:10 PM PST 24
Peak memory 200020 kb
Host smart-4fe079d7-8dbc-4622-adec-68843da13838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541919710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2541919710
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2952711799
Short name T457
Test name
Test status
Simulation time 685784812 ps
CPU time 2.24 seconds
Started Mar 03 02:38:58 PM PST 24
Finished Mar 03 02:39:00 PM PST 24
Peak memory 199832 kb
Host smart-4c4568f8-923d-48bd-9f1e-de73bf278d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952711799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2952711799
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3658153592
Short name T108
Test name
Test status
Simulation time 12436158625 ps
CPU time 603.66 seconds
Started Mar 03 02:38:58 PM PST 24
Finished Mar 03 02:49:01 PM PST 24
Peak memory 231820 kb
Host smart-490950f2-b0f0-42cd-b884-75666f47c0bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658153592 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3658153592
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.1330210882
Short name T59
Test name
Test status
Simulation time 191547299674 ps
CPU time 193.84 seconds
Started Mar 03 02:38:57 PM PST 24
Finished Mar 03 02:42:12 PM PST 24
Peak memory 230296 kb
Host smart-41cfbbff-b6c1-4f31-9ccc-93168598271a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330210882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.1330210882
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.4150762579
Short name T201
Test name
Test status
Simulation time 55448776 ps
CPU time 1.1 seconds
Started Mar 03 02:38:59 PM PST 24
Finished Mar 03 02:39:00 PM PST 24
Peak memory 198376 kb
Host smart-a2df3d6c-23dd-4c6e-8e1b-63447ff48a9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150762579 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.4150762579
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3753532381
Short name T385
Test name
Test status
Simulation time 27910377062 ps
CPU time 456.89 seconds
Started Mar 03 02:38:57 PM PST 24
Finished Mar 03 02:46:34 PM PST 24
Peak memory 199920 kb
Host smart-15bb439c-af14-4519-a625-e747f0e52413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753532381 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.3753532381
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2258275809
Short name T404
Test name
Test status
Simulation time 11431427273 ps
CPU time 79.98 seconds
Started Mar 03 02:38:56 PM PST 24
Finished Mar 03 02:40:17 PM PST 24
Peak memory 199944 kb
Host smart-a9a342e7-3421-4a90-834b-91c63eaed442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258275809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2258275809
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1717173802
Short name T15
Test name
Test status
Simulation time 40515444 ps
CPU time 0.56 seconds
Started Mar 03 02:38:57 PM PST 24
Finished Mar 03 02:38:57 PM PST 24
Peak memory 194168 kb
Host smart-f3c54f21-e21d-4ae7-8238-008d10bc9198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717173802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1717173802
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3175806883
Short name T345
Test name
Test status
Simulation time 1341017732 ps
CPU time 22.82 seconds
Started Mar 03 02:38:57 PM PST 24
Finished Mar 03 02:39:20 PM PST 24
Peak memory 208012 kb
Host smart-9a1190d8-25fa-421e-8acc-fccb07cbc4f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175806883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3175806883
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4236769642
Short name T568
Test name
Test status
Simulation time 1001537156 ps
CPU time 47.56 seconds
Started Mar 03 02:38:57 PM PST 24
Finished Mar 03 02:39:45 PM PST 24
Peak memory 199888 kb
Host smart-1fbba25c-9f4c-4a9b-b2fc-85ce53048097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236769642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4236769642
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3113903766
Short name T166
Test name
Test status
Simulation time 8717697384 ps
CPU time 112.62 seconds
Started Mar 03 02:38:56 PM PST 24
Finished Mar 03 02:40:49 PM PST 24
Peak memory 199936 kb
Host smart-c05a3ef2-89ee-4e7c-952b-fe38e5cad8dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113903766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3113903766
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.275248608
Short name T146
Test name
Test status
Simulation time 116577159 ps
CPU time 5.85 seconds
Started Mar 03 02:38:58 PM PST 24
Finished Mar 03 02:39:04 PM PST 24
Peak memory 199864 kb
Host smart-ed103288-f67c-4072-abb1-81aec3e70af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275248608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.275248608
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3863500351
Short name T354
Test name
Test status
Simulation time 16678112972 ps
CPU time 31.16 seconds
Started Mar 03 02:39:00 PM PST 24
Finished Mar 03 02:39:31 PM PST 24
Peak memory 199976 kb
Host smart-89781cf1-2aa1-4d04-a2f6-bb439debbe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863500351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3863500351
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3082015104
Short name T403
Test name
Test status
Simulation time 1350647750 ps
CPU time 4.93 seconds
Started Mar 03 02:38:58 PM PST 24
Finished Mar 03 02:39:03 PM PST 24
Peak memory 199824 kb
Host smart-bc761619-86fd-41cb-af2c-8ee943758822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082015104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3082015104
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3184441905
Short name T170
Test name
Test status
Simulation time 40218721443 ps
CPU time 861.24 seconds
Started Mar 03 02:39:00 PM PST 24
Finished Mar 03 02:53:21 PM PST 24
Peak memory 208284 kb
Host smart-5ae6a790-3153-4097-a19a-f6d3039d24cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184441905 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3184441905
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3148765662
Short name T205
Test name
Test status
Simulation time 207918570 ps
CPU time 1.03 seconds
Started Mar 03 02:38:58 PM PST 24
Finished Mar 03 02:38:59 PM PST 24
Peak memory 198432 kb
Host smart-013856e6-120d-4a64-8c43-977c71d4607c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148765662 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3148765662
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1463321487
Short name T334
Test name
Test status
Simulation time 13757733134 ps
CPU time 433.01 seconds
Started Mar 03 02:38:56 PM PST 24
Finished Mar 03 02:46:10 PM PST 24
Peak memory 199984 kb
Host smart-8cc34566-a199-4f54-9943-a12003394ddd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463321487 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_sha_vectors.1463321487
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1299720278
Short name T338
Test name
Test status
Simulation time 9220098146 ps
CPU time 77.66 seconds
Started Mar 03 02:38:58 PM PST 24
Finished Mar 03 02:40:16 PM PST 24
Peak memory 199904 kb
Host smart-10c4e283-d6cd-4a5f-8f63-7456bd7ac73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299720278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1299720278
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1070262324
Short name T479
Test name
Test status
Simulation time 77224681 ps
CPU time 0.55 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:37:00 PM PST 24
Peak memory 194644 kb
Host smart-1682f3f4-bfc2-4555-a577-abffc225304c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070262324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1070262324
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2145167794
Short name T43
Test name
Test status
Simulation time 914367111 ps
CPU time 27.2 seconds
Started Mar 03 02:36:52 PM PST 24
Finished Mar 03 02:37:19 PM PST 24
Peak memory 216312 kb
Host smart-914d91f2-899d-4e29-9fa0-58a9196e48cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145167794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2145167794
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.884341865
Short name T449
Test name
Test status
Simulation time 3568209429 ps
CPU time 51.28 seconds
Started Mar 03 02:36:58 PM PST 24
Finished Mar 03 02:37:49 PM PST 24
Peak memory 200004 kb
Host smart-e1fb3fc5-fbba-4c9f-90cf-27355d5599df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884341865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.884341865
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.959529142
Short name T120
Test name
Test status
Simulation time 728477729 ps
CPU time 41.32 seconds
Started Mar 03 02:36:53 PM PST 24
Finished Mar 03 02:37:35 PM PST 24
Peak memory 199912 kb
Host smart-8e00db72-b49d-491e-8378-14121d8e3c30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=959529142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.959529142
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3615707216
Short name T63
Test name
Test status
Simulation time 4615516790 ps
CPU time 74.21 seconds
Started Mar 03 02:36:53 PM PST 24
Finished Mar 03 02:38:07 PM PST 24
Peak memory 199996 kb
Host smart-f769a3b1-359d-4a4a-9e09-d7a8e495f23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615707216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3615707216
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2289803645
Short name T355
Test name
Test status
Simulation time 6507922792 ps
CPU time 84.74 seconds
Started Mar 03 02:36:56 PM PST 24
Finished Mar 03 02:38:21 PM PST 24
Peak memory 200036 kb
Host smart-9106f880-9923-4eed-bae3-a2b180a5d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289803645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2289803645
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.376444856
Short name T84
Test name
Test status
Simulation time 6438503217 ps
CPU time 4.53 seconds
Started Mar 03 02:36:58 PM PST 24
Finished Mar 03 02:37:03 PM PST 24
Peak memory 200012 kb
Host smart-01164d76-574d-472a-91df-8b1d29b24822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376444856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.376444856
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1401453021
Short name T115
Test name
Test status
Simulation time 745401438348 ps
CPU time 2156.68 seconds
Started Mar 03 02:36:56 PM PST 24
Finished Mar 03 03:12:53 PM PST 24
Peak memory 228736 kb
Host smart-7fc26240-7e31-420e-81c0-4fa365a8fce2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401453021 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1401453021
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.411560409
Short name T510
Test name
Test status
Simulation time 141156630 ps
CPU time 1.23 seconds
Started Mar 03 02:36:52 PM PST 24
Finished Mar 03 02:36:53 PM PST 24
Peak memory 198688 kb
Host smart-2e52be4e-461a-4b55-a54c-c502200d1823
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411560409 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.411560409
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3451346177
Short name T520
Test name
Test status
Simulation time 51254505199 ps
CPU time 524.13 seconds
Started Mar 03 02:36:57 PM PST 24
Finished Mar 03 02:45:42 PM PST 24
Peak memory 199876 kb
Host smart-b2fe6b35-a2bb-4661-9a17-9a703e02260c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451346177 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.3451346177
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.972233137
Short name T251
Test name
Test status
Simulation time 2343687039 ps
CPU time 43.69 seconds
Started Mar 03 02:36:57 PM PST 24
Finished Mar 03 02:37:42 PM PST 24
Peak memory 199988 kb
Host smart-680dfcf5-5c91-455e-84ec-326acfac8620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972233137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.972233137
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1093320991
Short name T580
Test name
Test status
Simulation time 17172572 ps
CPU time 0.57 seconds
Started Mar 03 02:36:56 PM PST 24
Finished Mar 03 02:36:57 PM PST 24
Peak memory 194444 kb
Host smart-8cf84b1b-d6e8-416d-bf9e-bc02b378468c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093320991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1093320991
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2380833181
Short name T462
Test name
Test status
Simulation time 12356599324 ps
CPU time 47.56 seconds
Started Mar 03 02:36:58 PM PST 24
Finished Mar 03 02:37:46 PM PST 24
Peak memory 211228 kb
Host smart-d5b2430f-d663-4a9e-8df1-5d33c386390c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2380833181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2380833181
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.138983894
Short name T235
Test name
Test status
Simulation time 4328355118 ps
CPU time 26.58 seconds
Started Mar 03 02:36:57 PM PST 24
Finished Mar 03 02:37:25 PM PST 24
Peak memory 199984 kb
Host smart-550f452c-0647-4ea3-8106-f94fc1eed948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138983894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.138983894
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_error.3769732338
Short name T547
Test name
Test status
Simulation time 6057068125 ps
CPU time 66.76 seconds
Started Mar 03 02:37:03 PM PST 24
Finished Mar 03 02:38:10 PM PST 24
Peak memory 199936 kb
Host smart-ee0b23e8-6218-4842-a973-3ca9ece309c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769732338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3769732338
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.130952462
Short name T516
Test name
Test status
Simulation time 4202403778 ps
CPU time 57.09 seconds
Started Mar 03 02:36:56 PM PST 24
Finished Mar 03 02:37:53 PM PST 24
Peak memory 199976 kb
Host smart-37a71af7-71c3-41ca-9ffb-46352acea658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130952462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.130952462
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1821613754
Short name T582
Test name
Test status
Simulation time 536775939 ps
CPU time 3.76 seconds
Started Mar 03 02:36:55 PM PST 24
Finished Mar 03 02:36:59 PM PST 24
Peak memory 199864 kb
Host smart-6729bb68-186e-4cea-917f-9840b98fd073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821613754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1821613754
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3767913386
Short name T366
Test name
Test status
Simulation time 31681242299 ps
CPU time 759.9 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:49:39 PM PST 24
Peak memory 226864 kb
Host smart-5ec4a66c-403b-4229-bdf2-357da81d3de4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767913386 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3767913386
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1042746601
Short name T58
Test name
Test status
Simulation time 55449119918 ps
CPU time 1010.17 seconds
Started Mar 03 02:37:02 PM PST 24
Finished Mar 03 02:53:52 PM PST 24
Peak memory 241016 kb
Host smart-890dbd4b-b253-4a4d-b4fa-f3cb199bd149
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1042746601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1042746601
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3234955674
Short name T590
Test name
Test status
Simulation time 64245763 ps
CPU time 0.92 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:37:00 PM PST 24
Peak memory 197460 kb
Host smart-07f1dac4-56fb-4821-84f8-5816fb676014
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234955674 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3234955674
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.936420723
Short name T320
Test name
Test status
Simulation time 88247396473 ps
CPU time 498.89 seconds
Started Mar 03 02:37:02 PM PST 24
Finished Mar 03 02:45:21 PM PST 24
Peak memory 199828 kb
Host smart-27e85a66-ce28-498e-9db0-46281275b9a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936420723 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.hmac_test_sha_vectors.936420723
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.768331552
Short name T507
Test name
Test status
Simulation time 2332645280 ps
CPU time 40.91 seconds
Started Mar 03 02:36:53 PM PST 24
Finished Mar 03 02:37:34 PM PST 24
Peak memory 200036 kb
Host smart-cc89dcb8-562e-4540-a59e-ceb7b86c3a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768331552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.768331552
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.3824798850
Short name T57
Test name
Test status
Simulation time 5613915095 ps
CPU time 46.2 seconds
Started Mar 03 02:39:05 PM PST 24
Finished Mar 03 02:39:52 PM PST 24
Peak memory 200292 kb
Host smart-488953f2-fb25-4bd7-b2ad-d2981c4ab934
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3824798850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.3824798850
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2776077410
Short name T396
Test name
Test status
Simulation time 47469933 ps
CPU time 0.57 seconds
Started Mar 03 02:37:03 PM PST 24
Finished Mar 03 02:37:03 PM PST 24
Peak memory 193188 kb
Host smart-61aa643c-3238-4414-9b21-17d99dba2bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776077410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2776077410
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3442804880
Short name T210
Test name
Test status
Simulation time 1177277459 ps
CPU time 21.9 seconds
Started Mar 03 02:36:52 PM PST 24
Finished Mar 03 02:37:14 PM PST 24
Peak memory 216264 kb
Host smart-7d846be7-c741-45d3-99fe-54444d34dc0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3442804880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3442804880
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3000692621
Short name T558
Test name
Test status
Simulation time 2640882868 ps
CPU time 5.63 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:37:05 PM PST 24
Peak memory 200168 kb
Host smart-e17bf541-d0df-4ee7-b2c0-a000858c78a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000692621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3000692621
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3540043832
Short name T552
Test name
Test status
Simulation time 3363938377 ps
CPU time 80 seconds
Started Mar 03 02:36:55 PM PST 24
Finished Mar 03 02:38:16 PM PST 24
Peak memory 199992 kb
Host smart-8805affb-49ea-4235-8cbe-59587de12092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3540043832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3540043832
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3956788505
Short name T229
Test name
Test status
Simulation time 6690687647 ps
CPU time 80.25 seconds
Started Mar 03 02:36:56 PM PST 24
Finished Mar 03 02:38:17 PM PST 24
Peak memory 199996 kb
Host smart-dd29e676-004d-4977-85c8-dab0a4e95374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956788505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3956788505
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_smoke.3289468960
Short name T225
Test name
Test status
Simulation time 25622095 ps
CPU time 0.84 seconds
Started Mar 03 02:36:57 PM PST 24
Finished Mar 03 02:36:59 PM PST 24
Peak memory 196000 kb
Host smart-c5e266b0-845e-4c97-a3cd-92bb0839f35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289468960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3289468960
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2831889200
Short name T565
Test name
Test status
Simulation time 57585389 ps
CPU time 0.92 seconds
Started Mar 03 02:36:58 PM PST 24
Finished Mar 03 02:36:59 PM PST 24
Peak memory 197560 kb
Host smart-ac9d056c-5944-45b1-ba1b-d3487c73d86e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831889200 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2831889200
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.674247972
Short name T359
Test name
Test status
Simulation time 7542858104 ps
CPU time 402.57 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:43:41 PM PST 24
Peak memory 199964 kb
Host smart-65fbdb0d-ac78-4ded-a984-90a8d1b9154d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674247972 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.hmac_test_sha_vectors.674247972
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1837583120
Short name T159
Test name
Test status
Simulation time 923370075 ps
CPU time 31.52 seconds
Started Mar 03 02:36:52 PM PST 24
Finished Mar 03 02:37:24 PM PST 24
Peak memory 199824 kb
Host smart-9dcc4efb-ef38-4469-bad0-82bd740993c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837583120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1837583120
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.4062944185
Short name T530
Test name
Test status
Simulation time 15001878 ps
CPU time 0.59 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:36:59 PM PST 24
Peak memory 194472 kb
Host smart-21407e70-3d94-48ba-a29b-2544385b1bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062944185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.4062944185
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3857397281
Short name T553
Test name
Test status
Simulation time 475630568 ps
CPU time 14.23 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:37:13 PM PST 24
Peak memory 208128 kb
Host smart-00b8dcb2-ab69-46be-9874-2170ee8b22b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857397281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3857397281
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.431311541
Short name T390
Test name
Test status
Simulation time 6172668676 ps
CPU time 23.81 seconds
Started Mar 03 02:37:02 PM PST 24
Finished Mar 03 02:37:26 PM PST 24
Peak memory 199992 kb
Host smart-e588fe7d-1afa-4774-9a1e-4a4a6e17ba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431311541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.431311541
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.947349355
Short name T571
Test name
Test status
Simulation time 5031708314 ps
CPU time 69.3 seconds
Started Mar 03 02:37:07 PM PST 24
Finished Mar 03 02:38:16 PM PST 24
Peak memory 200016 kb
Host smart-2392ad61-7ac7-46e8-a611-39534bcb5625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947349355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.947349355
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.763207971
Short name T69
Test name
Test status
Simulation time 3527383408 ps
CPU time 48.68 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:37:49 PM PST 24
Peak memory 199992 kb
Host smart-bd7af5f7-e589-4654-b48c-40cec28497b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763207971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.763207971
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2958189573
Short name T270
Test name
Test status
Simulation time 4954884653 ps
CPU time 85.75 seconds
Started Mar 03 02:37:03 PM PST 24
Finished Mar 03 02:38:28 PM PST 24
Peak memory 198816 kb
Host smart-bb8a5e7d-e060-4f6a-bdf7-244eabd74a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958189573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2958189573
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3361153376
Short name T256
Test name
Test status
Simulation time 92791667 ps
CPU time 0.92 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:37:00 PM PST 24
Peak memory 197924 kb
Host smart-0bf9856d-b6e2-4238-bcc1-66e33bf9b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361153376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3361153376
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2035917039
Short name T74
Test name
Test status
Simulation time 37650432481 ps
CPU time 547.9 seconds
Started Mar 03 02:37:01 PM PST 24
Finished Mar 03 02:46:09 PM PST 24
Peak memory 248376 kb
Host smart-bcb03fa5-7408-47ce-b658-398a8343e8a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035917039 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2035917039
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2514164029
Short name T415
Test name
Test status
Simulation time 54633117 ps
CPU time 1.19 seconds
Started Mar 03 02:36:58 PM PST 24
Finished Mar 03 02:36:59 PM PST 24
Peak memory 198904 kb
Host smart-1635c461-2f41-4d3f-af2f-ba08520c3b9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514164029 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2514164029
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.421948487
Short name T549
Test name
Test status
Simulation time 133512838997 ps
CPU time 437.38 seconds
Started Mar 03 02:37:01 PM PST 24
Finished Mar 03 02:44:19 PM PST 24
Peak memory 199864 kb
Host smart-aec8830f-9ead-4a6c-a51f-b73cef163b75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421948487 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.hmac_test_sha_vectors.421948487
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.841081582
Short name T319
Test name
Test status
Simulation time 1496471010 ps
CPU time 25.1 seconds
Started Mar 03 02:37:05 PM PST 24
Finished Mar 03 02:37:30 PM PST 24
Peak memory 199924 kb
Host smart-3e25e2c8-a0f7-488b-8318-09fbf1115ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841081582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.841081582
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1161597228
Short name T499
Test name
Test status
Simulation time 18610816 ps
CPU time 0.59 seconds
Started Mar 03 02:37:06 PM PST 24
Finished Mar 03 02:37:07 PM PST 24
Peak memory 194444 kb
Host smart-2caeaf67-0e44-43b0-9c01-99c6a52f8748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161597228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1161597228
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3515884232
Short name T125
Test name
Test status
Simulation time 3921721482 ps
CPU time 32.25 seconds
Started Mar 03 02:37:02 PM PST 24
Finished Mar 03 02:37:35 PM PST 24
Peak memory 216388 kb
Host smart-076dcfe6-d06b-4d9c-b75e-f42b65cbefbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515884232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3515884232
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1630959619
Short name T525
Test name
Test status
Simulation time 1008414425 ps
CPU time 20.05 seconds
Started Mar 03 02:37:00 PM PST 24
Finished Mar 03 02:37:20 PM PST 24
Peak memory 200044 kb
Host smart-555e46e9-babc-4719-9c23-f6b647695685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630959619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1630959619
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2917550786
Short name T173
Test name
Test status
Simulation time 701689843 ps
CPU time 25.15 seconds
Started Mar 03 02:36:58 PM PST 24
Finished Mar 03 02:37:23 PM PST 24
Peak memory 199912 kb
Host smart-99699b5a-7353-4d2d-8bc1-9abd551c8bff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2917550786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2917550786
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.643313708
Short name T386
Test name
Test status
Simulation time 19689764505 ps
CPU time 174.94 seconds
Started Mar 03 02:37:00 PM PST 24
Finished Mar 03 02:39:55 PM PST 24
Peak memory 199992 kb
Host smart-e1b83add-eff8-4fe2-9aee-577d1644e356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643313708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.643313708
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.472953226
Short name T132
Test name
Test status
Simulation time 3174803592 ps
CPU time 55.8 seconds
Started Mar 03 02:37:07 PM PST 24
Finished Mar 03 02:38:03 PM PST 24
Peak memory 199992 kb
Host smart-011ddc2a-3eec-43c4-9c65-5851e3dd862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472953226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.472953226
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.4015543917
Short name T327
Test name
Test status
Simulation time 1962934859 ps
CPU time 2.44 seconds
Started Mar 03 02:37:01 PM PST 24
Finished Mar 03 02:37:03 PM PST 24
Peak memory 199904 kb
Host smart-90b7530a-5c8d-4446-918c-c4e29de056e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015543917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.4015543917
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.228550882
Short name T72
Test name
Test status
Simulation time 657082379299 ps
CPU time 1906.43 seconds
Started Mar 03 02:37:01 PM PST 24
Finished Mar 03 03:08:48 PM PST 24
Peak memory 228712 kb
Host smart-a9fa4469-3bf7-4b8b-8db6-a75f3f17f5b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228550882 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.228550882
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.4210959572
Short name T585
Test name
Test status
Simulation time 110087242 ps
CPU time 1.15 seconds
Started Mar 03 02:37:01 PM PST 24
Finished Mar 03 02:37:02 PM PST 24
Peak memory 198628 kb
Host smart-12674137-6449-4243-87ff-0b0ebe5a06d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210959572 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.4210959572
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3555238181
Short name T274
Test name
Test status
Simulation time 31721135178 ps
CPU time 408.6 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:43:49 PM PST 24
Peak memory 199924 kb
Host smart-82fa64ac-aea5-4f2c-839b-c6bfcdc4eeed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555238181 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_sha_vectors.3555238181
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2782694415
Short name T257
Test name
Test status
Simulation time 303730532 ps
CPU time 13.38 seconds
Started Mar 03 02:36:59 PM PST 24
Finished Mar 03 02:37:12 PM PST 24
Peak memory 199908 kb
Host smart-aed7dccc-ff1a-4f0f-8e1b-6e9db7d70659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782694415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2782694415
Directory /workspace/9.hmac_wipe_secret/latest
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