Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14778831	1			T1	21528		T2	25892		T3	33922
all_values[1]	14778831	1			T1	21528		T2	25892		T3	33922
all_values[2]	14778831	1			T1	21528		T2	25892		T3	33922

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144801

1

T2

780

T3

1019

T21

10

auto[1]

44191692

1

T1

64584

T2

76896

T3

100747

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38019815

1

T1

48699

T2

57316

T3

76825

auto[1]

6316678

1

T1

15885

T2

20360

T3

24941

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	54843	1			T2	778		T21	8		T30	182
all_values[0]	auto[0]	auto[1]	501	1			T2	2		T21	2		T30	8
all_values[0]	auto[1]	auto[0]	14675037	1			T1	21519		T2	25105		T3	33907
all_values[0]	auto[1]	auto[1]	48450	1			T1	9		T2	7		T3	15
all_values[1]	auto[0]	auto[0]	41707	1			T3	1019		T4	2		T27	4
all_values[1]	auto[0]	auto[1]	199	1			T11	3		T12	1		T15	2
all_values[1]	auto[1]	auto[0]	14736099	1			T1	21528		T2	25892		T3	32903
all_values[1]	auto[1]	auto[1]	826	1			T6	1		T18	1		T29	4
all_values[2]	auto[0]	auto[0]	33443	1			T30	115		T11	234		T12	934
all_values[2]	auto[0]	auto[1]	14108	1			T11	6		T12	5		T15	2
all_values[2]	auto[1]	auto[0]	8478686	1			T1	5652		T2	5541		T3	8996
all_values[2]	auto[1]	auto[1]	6252594	1			T1	15876		T2	20351		T3	24926