Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7037903

1

T1

3656

T2

980

T3

6076

auto[1]

2456830

1

T1

2546

T2

4544

T3

4518

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2468683

1

T1

2814

T2

4096

T3

5942

auto[1]

7026050

1

T1

3388

T2

1428

T3

4652

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6417881

1

T1

4569

T2

2963

T3

5130

auto[1]

3076852

1

T1

1633

T2

2561

T3

5464

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6438112	1			T1	6073		T2	4466		T3	10308
fifo_depth[1]	463287	1			T1	97		T2	246		T3	184
fifo_depth[2]	379681	1			T1	27		T2	249		T3	64
fifo_depth[3]	298030	1			T1	2		T2	197		T3	26
fifo_depth[4]	270929	1			T1	3		T2	115		T3	7
fifo_depth[5]	224123	1			T2	76		T3	4		T13	1
fifo_depth[6]	224400	1			T2	67		T3	1		T21	6
fifo_depth[7]	189046	1			T2	51		T21	5		T14	2
fifo_depth[8]	213099	1			T2	23		T21	8		T4	6
fifo_depth[9]	126432	1			T2	17		T21	1		T4	3
fifo_depth[10]	123464	1			T2	11		T21	2		T4	2
fifo_depth[11]	71993	1			T2	3		T21	1		T4	2
fifo_depth[12]	118032	1			T2	1		T4	7		T5	92
fifo_depth[13]	50355	1			T2	2		T4	4		T5	46
fifo_depth[14]	83991	1			T4	5		T5	20		T6	20
fifo_depth[15]	45219	1			T4	4		T5	4		T6	9
fifo_depth[16]	174540	1			T4	4		T5	3		T6	3

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3056621

1

T1

129

T2

1058

T3

286

auto[1]

6438112

1

T1

6073

T2

4466

T3

10308

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9320193

1

T1

6202

T2

5524

T3

10594

auto[1]

174540

1

T4

4

T5

3

T6

3

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

198109

1

T1

16

T2

40

T3

34

auto[0]

auto[0]

auto[0]

auto[1]

197426

1

T2

361

T3

15

T4

7

auto[0]

auto[0]

auto[1]

auto[0]

1046024

1

T1

1

T3

21

T13

847

auto[0]

auto[0]

auto[1]

auto[1]

206834

1

T1

46

T2

450

T3

34

auto[0]

auto[1]

auto[0]

auto[0]

361323

1

T2

76

T3

95

T21

21

auto[0]

auto[1]

auto[0]

auto[1]

365442

1

T3

10

T21

9

T4

7

auto[0]

auto[1]

auto[1]

auto[0]

352216

1

T1

66

T2

75

T3

49

auto[0]

auto[1]

auto[1]

auto[1]

329247

1

T2

56

T3

28

T21

19

auto[1]

auto[0]

auto[0]

auto[0]

248681

1

T1

2269

T2

226

T3

2638

auto[1]

auto[0]

auto[0]

auto[1]

261860

1

T1

527

T2

1406

T3

484

auto[1]

auto[0]

auto[1]

auto[0]

3974970

1

T1

313

T2

2

T3

229

auto[1]

auto[0]

auto[1]

auto[1]

283977

1

T1

1397

T2

478

T3

1675

auto[1]

auto[1]

auto[0]

auto[0]

423089

1

T1

1

T2

457

T3

1875

auto[1]

auto[1]

auto[0]

auto[1]

412753

1

T1

1

T2

1530

T3

791

auto[1]

auto[1]

auto[1]

auto[0]

433491

1

T1

990

T2

104

T3

1135

auto[1]

auto[1]

auto[1]

auto[1]

399291

1

T1

575

T2

263

T3

1481

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

421779

1

T1

2285

T2

266

T3

2672

auto[0]

auto[0]

auto[0]

auto[1]

433971

1

T1

527

T2

1767

T3

499

auto[0]

auto[0]

auto[1]

auto[0]

4996638

1

T1

314

T2

2

T3

250

auto[0]

auto[0]

auto[1]

auto[1]

471233

1

T1

1443

T2

928

T3

1709

auto[0]

auto[1]

auto[0]

auto[0]

764143

1

T1

1

T2

533

T3

1970

auto[0]

auto[1]

auto[0]

auto[1]

760366

1

T1

1

T2

1530

T3

801

auto[0]

auto[1]

auto[1]

auto[0]

764945

1

T1

1056

T2

179

T3

1184

auto[0]

auto[1]

auto[1]

auto[1]

707118

1

T1

575

T2

319

T3

1509

auto[1]

auto[0]

auto[0]

auto[0]

25011

1

T32

1

T38

1

T11

1

auto[1]

auto[0]

auto[0]

auto[1]

25315

1

T4

2

T5

2

T15

1

auto[1]

auto[0]

auto[1]

auto[0]

24356

1

T29

2

T31

3

T11

90

auto[1]

auto[0]

auto[1]

auto[1]

19578

1

T30

1

T11

1

T15

458

auto[1]

auto[1]

auto[0]

auto[0]

20269

1

T4

1

T5

1

T6

2

auto[1]

auto[1]

auto[0]

auto[1]

17829

1

T32

1

T38

3

T40

3

auto[1]

auto[1]

auto[1]

auto[0]

20762

1

T6

1

T11

371

T15

41

auto[1]

auto[1]

auto[1]

auto[1]

21420

1

T4

1

T30

1

T32

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	248681	1			T1	2269		T2	226		T3	2638
fifo_depth[0]	auto[0]	auto[0]	auto[1]	261860	1			T1	527		T2	1406		T3	484
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3974970	1			T1	313		T2	2		T3	229
fifo_depth[0]	auto[0]	auto[1]	auto[1]	283977	1			T1	1397		T2	478		T3	1675
fifo_depth[0]	auto[1]	auto[0]	auto[0]	423089	1			T1	1		T2	457		T3	1875
fifo_depth[0]	auto[1]	auto[0]	auto[1]	412753	1			T1	1		T2	1530		T3	791
fifo_depth[0]	auto[1]	auto[1]	auto[0]	433491	1			T1	990		T2	104		T3	1135
fifo_depth[0]	auto[1]	auto[1]	auto[1]	399291	1			T1	575		T2	263		T3	1481
fifo_depth[1]	auto[0]	auto[0]	auto[0]	18308	1			T1	16		T2	16		T3	34
fifo_depth[1]	auto[0]	auto[0]	auto[1]	19490	1			T2	113		T3	14		T5	92
fifo_depth[1]	auto[0]	auto[1]	auto[0]	238690	1			T1	1		T3	13		T13	683
fifo_depth[1]	auto[0]	auto[1]	auto[1]	20914	1			T1	34		T2	58		T3	15
fifo_depth[1]	auto[1]	auto[0]	auto[0]	42341	1			T2	28		T3	52		T21	3
fifo_depth[1]	auto[1]	auto[0]	auto[1]	42024	1			T3	10		T5	14		T6	445
fifo_depth[1]	auto[1]	auto[1]	auto[0]	42731	1			T1	46		T2	14		T3	18
fifo_depth[1]	auto[1]	auto[1]	auto[1]	38789	1			T2	17		T3	28		T21	5
fifo_depth[2]	auto[0]	auto[0]	auto[0]	16016	1			T2	13		T5	261		T28	18
fifo_depth[2]	auto[0]	auto[0]	auto[1]	17279	1			T2	107		T3	1		T5	75
fifo_depth[2]	auto[0]	auto[1]	auto[0]	180073	1			T3	7		T13	130		T14	792
fifo_depth[2]	auto[0]	auto[1]	auto[1]	18379	1			T1	11		T2	71		T3	8
fifo_depth[2]	auto[1]	auto[0]	auto[0]	38017	1			T2	30		T3	35		T21	4
fifo_depth[2]	auto[1]	auto[0]	auto[1]	38396	1			T21	1		T5	23		T6	460
fifo_depth[2]	auto[1]	auto[1]	auto[0]	37590	1			T1	16		T2	11		T3	13
fifo_depth[2]	auto[1]	auto[1]	auto[1]	33931	1			T2	17		T21	3		T5	49
fifo_depth[3]	auto[0]	auto[0]	auto[0]	12532	1			T2	7		T5	237		T28	7
fifo_depth[3]	auto[0]	auto[0]	auto[1]	13075	1			T2	91		T5	86		T28	24
fifo_depth[3]	auto[0]	auto[1]	auto[0]	133707	1			T3	1		T13	27		T14	359
fifo_depth[3]	auto[0]	auto[1]	auto[1]	14295	1			T1	1		T2	55		T3	7
fifo_depth[3]	auto[1]	auto[0]	auto[0]	31839	1			T2	15		T3	7		T21	3
fifo_depth[3]	auto[1]	auto[0]	auto[1]	32327	1			T21	2		T5	22		T6	431
fifo_depth[3]	auto[1]	auto[1]	auto[0]	31598	1			T1	1		T2	13		T3	11
fifo_depth[3]	auto[1]	auto[1]	auto[1]	28657	1			T2	16		T5	33		T6	63
fifo_depth[4]	auto[0]	auto[0]	auto[0]	14722	1			T2	2		T5	239		T28	4
fifo_depth[4]	auto[0]	auto[0]	auto[1]	14733	1			T2	38		T5	83		T28	8
fifo_depth[4]	auto[0]	auto[1]	auto[0]	99750	1			T13	6		T14	110		T5	166
fifo_depth[4]	auto[0]	auto[1]	auto[1]	15726	1			T2	61		T3	3		T5	19
fifo_depth[4]	auto[1]	auto[0]	auto[0]	31705	1			T2	3		T3	1		T5	27
fifo_depth[4]	auto[1]	auto[0]	auto[1]	33649	1			T21	1		T5	28		T6	475
fifo_depth[4]	auto[1]	auto[1]	auto[0]	32280	1			T1	3		T2	6		T3	3
fifo_depth[4]	auto[1]	auto[1]	auto[1]	28364	1			T2	5		T21	2		T5	51
fifo_depth[5]	auto[0]	auto[0]	auto[0]	11082	1			T2	2		T5	223		T28	1
fifo_depth[5]	auto[0]	auto[0]	auto[1]	11461	1			T2	9		T5	85		T28	3
fifo_depth[5]	auto[0]	auto[1]	auto[0]	79899	1			T13	1		T14	32		T5	176
fifo_depth[5]	auto[0]	auto[1]	auto[1]	12015	1			T2	52		T3	1		T5	12
fifo_depth[5]	auto[1]	auto[0]	auto[0]	27927	1			T21	1		T5	34		T6	497
fifo_depth[5]	auto[1]	auto[0]	auto[1]	28720	1			T21	2		T5	12		T6	471
fifo_depth[5]	auto[1]	auto[1]	auto[0]	27849	1			T2	12		T3	3		T21	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	25170	1			T2	1		T21	1		T5	34
fifo_depth[6]	auto[0]	auto[0]	auto[0]	12812	1			T5	230		T38	92		T96	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	12874	1			T2	3		T5	92		T28	2
fifo_depth[6]	auto[0]	auto[1]	auto[0]	71081	1			T14	9		T4	1		T5	182
fifo_depth[6]	auto[0]	auto[1]	auto[1]	14062	1			T2	55		T4	1		T5	14
fifo_depth[6]	auto[1]	auto[0]	auto[0]	28252	1			T21	2		T5	26		T6	506
fifo_depth[6]	auto[1]	auto[0]	auto[1]	30280	1			T4	1		T5	17		T6	435
fifo_depth[6]	auto[1]	auto[1]	auto[0]	28832	1			T2	9		T3	1		T21	1
fifo_depth[6]	auto[1]	auto[1]	auto[1]	26207	1			T21	3		T4	1		T5	31
fifo_depth[7]	auto[0]	auto[0]	auto[0]	10721	1			T4	1		T5	213		T32	1
fifo_depth[7]	auto[0]	auto[0]	auto[1]	10568	1			T5	80		T38	30		T11	34
fifo_depth[7]	auto[0]	auto[1]	auto[0]	56003	1			T14	2		T4	1		T5	181
fifo_depth[7]	auto[0]	auto[1]	auto[1]	11426	1			T2	46		T4	1		T5	15
fifo_depth[7]	auto[1]	auto[0]	auto[0]	25028	1			T21	1		T5	23		T6	412
fifo_depth[7]	auto[1]	auto[0]	auto[1]	26583	1			T21	1		T5	19		T6	403
fifo_depth[7]	auto[1]	auto[1]	auto[0]	24989	1			T2	5		T4	1		T5	69
fifo_depth[7]	auto[1]	auto[1]	auto[1]	23728	1			T21	3		T4	1		T5	26
fifo_depth[8]	auto[0]	auto[0]	auto[0]	16501	1			T5	175		T30	1		T38	68
fifo_depth[8]	auto[0]	auto[0]	auto[1]	15573	1			T4	1		T5	70		T38	32
fifo_depth[8]	auto[0]	auto[1]	auto[0]	48593	1			T4	2		T5	140		T29	435
fifo_depth[8]	auto[0]	auto[1]	auto[1]	17427	1			T2	20		T5	10		T38	21
fifo_depth[8]	auto[1]	auto[0]	auto[0]	29720	1			T21	4		T5	23		T6	419
fifo_depth[8]	auto[1]	auto[0]	auto[1]	29125	1			T21	1		T4	1		T5	12
fifo_depth[8]	auto[1]	auto[1]	auto[0]	29004	1			T2	3		T21	1		T5	60
fifo_depth[8]	auto[1]	auto[1]	auto[1]	27156	1			T21	2		T4	2		T5	30
fifo_depth[9]	auto[0]	auto[0]	auto[0]	8062	1			T4	1		T5	126		T32	1
fifo_depth[9]	auto[0]	auto[0]	auto[1]	8466	1			T5	45		T30	2		T38	19
fifo_depth[9]	auto[0]	auto[1]	auto[0]	30469	1			T5	110		T29	256		T31	662
fifo_depth[9]	auto[0]	auto[1]	auto[1]	9252	1			T2	15		T4	1		T5	10
fifo_depth[9]	auto[1]	auto[0]	auto[0]	18074	1			T21	1		T5	16		T6	301
fifo_depth[9]	auto[1]	auto[0]	auto[1]	18437	1			T5	8		T6	260		T18	49
fifo_depth[9]	auto[1]	auto[1]	auto[0]	16597	1			T2	2		T5	52		T6	118
fifo_depth[9]	auto[1]	auto[1]	auto[1]	17075	1			T4	1		T5	24		T6	41
fifo_depth[10]	auto[0]	auto[0]	auto[0]	10106	1			T5	77		T30	1		T38	46
fifo_depth[10]	auto[0]	auto[0]	auto[1]	10440	1			T4	1		T5	33		T30	2
fifo_depth[10]	auto[0]	auto[1]	auto[0]	24931	1			T5	63		T29	159		T30	1
fifo_depth[10]	auto[0]	auto[1]	auto[1]	11879	1			T2	11		T4	1		T5	3
fifo_depth[10]	auto[1]	auto[0]	auto[0]	16590	1			T21	1		T5	14		T6	164
fifo_depth[10]	auto[1]	auto[0]	auto[1]	17897	1			T21	1		T5	12		T6	165
fifo_depth[10]	auto[1]	auto[1]	auto[0]	16525	1			T5	33		T6	72		T18	155
fifo_depth[10]	auto[1]	auto[1]	auto[1]	15096	1			T5	17		T6	27		T18	91
fifo_depth[11]	auto[0]	auto[0]	auto[0]	6201	1			T5	55		T38	22		T11	14
fifo_depth[11]	auto[0]	auto[0]	auto[1]	6105	1			T4	1		T5	16		T38	5
fifo_depth[11]	auto[0]	auto[1]	auto[0]	15075	1			T5	42		T29	81		T31	232
fifo_depth[11]	auto[0]	auto[1]	auto[1]	6942	1			T2	3		T5	3		T30	1
fifo_depth[11]	auto[1]	auto[0]	auto[0]	9367	1			T21	1		T5	13		T6	112
fifo_depth[11]	auto[1]	auto[0]	auto[1]	10268	1			T4	1		T5	6		T6	111
fifo_depth[11]	auto[1]	auto[1]	auto[0]	9038	1			T5	12		T6	52		T18	79
fifo_depth[11]	auto[1]	auto[1]	auto[1]	8997	1			T5	9		T6	16		T18	49
fifo_depth[12]	auto[0]	auto[0]	auto[0]	13694	1			T4	2		T5	28		T30	1
fifo_depth[12]	auto[0]	auto[0]	auto[1]	12626	1			T4	1		T5	17		T38	3
fifo_depth[12]	auto[0]	auto[1]	auto[0]	17328	1			T5	25		T29	54		T30	1
fifo_depth[12]	auto[0]	auto[1]	auto[1]	13570	1			T2	1		T4	1		T5	1
fifo_depth[12]	auto[1]	auto[0]	auto[0]	16594	1			T4	3		T5	3		T6	57
fifo_depth[12]	auto[1]	auto[0]	auto[1]	15412	1			T5	2		T6	36		T18	7
fifo_depth[12]	auto[1]	auto[1]	auto[0]	14436	1			T5	10		T6	16		T18	56
fifo_depth[12]	auto[1]	auto[1]	auto[1]	14372	1			T5	6		T6	4		T18	28
fifo_depth[13]	auto[0]	auto[0]	auto[0]	5621	1			T4	1		T5	14		T30	1
fifo_depth[13]	auto[0]	auto[0]	auto[1]	5465	1			T5	5		T30	1		T38	2
fifo_depth[13]	auto[0]	auto[1]	auto[0]	8914	1			T4	1		T5	11		T29	26
fifo_depth[13]	auto[0]	auto[1]	auto[1]	6244	1			T2	2		T38	3		T11	1
fifo_depth[13]	auto[1]	auto[0]	auto[0]	6193	1			T4	1		T5	4		T6	21
fifo_depth[13]	auto[1]	auto[0]	auto[1]	6917	1			T4	1		T5	1		T6	11
fifo_depth[13]	auto[1]	auto[1]	auto[0]	5427	1			T5	6		T6	12		T18	26
fifo_depth[13]	auto[1]	auto[1]	auto[1]	5574	1			T5	5		T6	2		T18	10
fifo_depth[14]	auto[0]	auto[0]	auto[0]	10727	1			T5	3		T30	1		T38	4
fifo_depth[14]	auto[0]	auto[0]	auto[1]	9486	1			T5	4		T38	2		T15	1
fifo_depth[14]	auto[0]	auto[1]	auto[0]	10979	1			T4	1		T5	2		T29	10
fifo_depth[14]	auto[0]	auto[1]	auto[1]	9960	1			T4	1		T32	1		T11	3
fifo_depth[14]	auto[1]	auto[0]	auto[0]	12564	1			T4	1		T5	3		T6	12
fifo_depth[14]	auto[1]	auto[0]	auto[1]	11384	1			T4	2		T5	2		T6	7
fifo_depth[14]	auto[1]	auto[1]	auto[0]	9534	1			T5	4		T6	1		T18	8
fifo_depth[14]	auto[1]	auto[1]	auto[1]	9357	1			T5	2		T18	6		T38	1
fifo_depth[15]	auto[0]	auto[0]	auto[0]	5993	1			T5	2		T30	1		T38	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	4470	1			T4	1		T54	18		T41	1
fifo_depth[15]	auto[0]	auto[1]	auto[0]	6176	1			T4	2		T5	1		T29	8
fifo_depth[15]	auto[0]	auto[1]	auto[1]	5165	1			T11	1		T15	18		T54	7
fifo_depth[15]	auto[1]	auto[0]	auto[0]	6843	1			T6	5		T18	1		T11	6
fifo_depth[15]	auto[1]	auto[0]	auto[1]	6194	1			T4	1		T5	1		T6	4
fifo_depth[15]	auto[1]	auto[1]	auto[0]	5024	1			T18	3		T11	30		T15	54
fifo_depth[15]	auto[1]	auto[1]	auto[1]	5354	1			T18	2		T30	1		T38	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	25011	1			T32	1		T38	1		T11	1
fifo_depth[16]	auto[0]	auto[0]	auto[1]	25315	1			T4	2		T5	2		T15	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	24356	1			T29	2		T31	3		T11	90
fifo_depth[16]	auto[0]	auto[1]	auto[1]	19578	1			T30	1		T11	1		T15	458
fifo_depth[16]	auto[1]	auto[0]	auto[0]	20269	1			T4	1		T5	1		T6	2
fifo_depth[16]	auto[1]	auto[0]	auto[1]	17829	1			T32	1		T38	3		T40	3
fifo_depth[16]	auto[1]	auto[1]	auto[0]	20762	1			T6	1		T11	371		T15	41
fifo_depth[16]	auto[1]	auto[1]	auto[1]	21420	1			T4	1		T30	1		T32	1