Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14778831	1			T1	21528		T2	25892		T3	33922
all_pins[1]	14778831	1			T1	21528		T2	25892		T3	33922
all_pins[2]	14778831	1			T1	21528		T2	25892		T3	33922

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	38033531	1			T1	48699		T2	57318		T3	76825
values[0x1]	6302962	1			T1	15885		T2	20358		T3	24941
transitions[0x0=>0x1]	6302814	1			T1	15885		T2	20358		T3	24941
transitions[0x1=>0x0]	6302834	1			T1	15885		T2	20358		T3	24941

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14729426	1			T1	21519		T2	25885		T3	33907
all_pins[0]	values[0x1]	49405	1			T1	9		T2	7		T3	15
all_pins[0]	transitions[0x0=>0x1]	49339	1			T1	9		T2	7		T3	15
all_pins[0]	transitions[0x1=>0x0]	6252548	1			T1	15876		T2	20351		T3	24926
all_pins[1]	values[0x0]	14777868	1			T1	21528		T2	25892		T3	33922
all_pins[1]	values[0x1]	963	1			T5	1		T6	1		T18	1
all_pins[1]	transitions[0x0=>0x1]	920	1			T5	1		T6	1		T18	1
all_pins[1]	transitions[0x1=>0x0]	49362	1			T1	9		T2	7		T3	15
all_pins[2]	values[0x0]	8526237	1			T1	5652		T2	5541		T3	8996
all_pins[2]	values[0x1]	6252594	1			T1	15876		T2	20351		T3	24926
all_pins[2]	transitions[0x0=>0x1]	6252555	1			T1	15876		T2	20351		T3	24926
all_pins[2]	transitions[0x1=>0x0]	924	1			T5	1		T6	1		T18	1