Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 911 1 T11 21 T12 7 T15 10
all_values[1] 911 1 T11 21 T12 7 T15 10
all_values[2] 911 1 T11 21 T12 7 T15 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1390 1 T11 37 T12 14 T15 8
auto[1] 1343 1 T11 26 T12 7 T15 22


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 960 1 T11 18 T12 6 T15 12
auto[1] 1773 1 T11 45 T12 15 T15 18


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1561 1 T11 33 T12 11 T15 20
auto[1] 1172 1 T11 30 T12 10 T15 10


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 175 1 T11 2 T12 1 T58 3
all_values[0] auto[0] auto[0] auto[1] 95 1 T11 5 T15 1 T58 2
all_values[0] auto[0] auto[1] auto[0] 163 1 T11 1 T15 4 T58 2
all_values[0] auto[0] auto[1] auto[1] 87 1 T11 2 T12 1 T58 2
all_values[0] auto[1] auto[0] auto[1] 208 1 T11 7 T12 5 T15 1
all_values[0] auto[1] auto[1] auto[1] 183 1 T11 4 T15 4 T58 2
all_values[1] auto[0] auto[0] auto[0] 147 1 T11 6 T12 1 T58 3
all_values[1] auto[0] auto[0] auto[1] 118 1 T11 1 T15 1 T58 1
all_values[1] auto[0] auto[1] auto[0] 157 1 T11 2 T12 2 T15 6
all_values[1] auto[0] auto[1] auto[1] 106 1 T11 4 T12 2 T15 1
all_values[1] auto[1] auto[0] auto[1] 199 1 T11 5 T12 1 T15 2
all_values[1] auto[1] auto[1] auto[1] 184 1 T11 3 T12 1 T58 5
all_values[2] auto[0] auto[0] auto[0] 156 1 T11 4 T12 1 T58 5
all_values[2] auto[0] auto[0] auto[1] 91 1 T11 3 T12 2 T15 1
all_values[2] auto[0] auto[1] auto[0] 162 1 T11 3 T12 1 T15 2
all_values[2] auto[0] auto[1] auto[1] 104 1 T15 4 T58 1 T62 1
all_values[2] auto[1] auto[0] auto[1] 201 1 T11 4 T12 3 T15 2
all_values[2] auto[1] auto[1] auto[1] 197 1 T11 7 T15 1 T58 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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