| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.63 | 98.23 | 96.36 | 100.00 | 87.50 | 95.49 | 99.49 | 99.31 |
| T537 | /workspace/coverage/default/2.hmac_error.1594067940 | Mar 05 01:09:56 PM PST 24 | Mar 05 01:11:03 PM PST 24 | 1302007592 ps | ||
| T538 | /workspace/coverage/default/7.hmac_alert_test.1888209163 | Mar 05 01:09:55 PM PST 24 | Mar 05 01:09:56 PM PST 24 | 16546748 ps | ||
| T539 | /workspace/coverage/default/28.hmac_datapath_stress.1978432603 | Mar 05 01:10:37 PM PST 24 | Mar 05 01:10:59 PM PST 24 | 437308973 ps | ||
| T540 | /workspace/coverage/default/34.hmac_error.2997117830 | Mar 05 01:10:49 PM PST 24 | Mar 05 01:12:13 PM PST 24 | 7198525492 ps | ||
| T541 | /workspace/coverage/default/13.hmac_test_sha_vectors.2117552085 | Mar 05 01:10:04 PM PST 24 | Mar 05 01:18:05 PM PST 24 | 119016508373 ps | ||
| T37 | /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.2711380253 | Mar 05 01:11:48 PM PST 24 | Mar 05 01:24:46 PM PST 24 | 17049490924 ps | ||
| T542 | /workspace/coverage/default/8.hmac_test_hmac_vectors.1507724770 | Mar 05 01:09:52 PM PST 24 | Mar 05 01:09:54 PM PST 24 | 73069926 ps | ||
| T543 | /workspace/coverage/default/39.hmac_wipe_secret.1687582378 | Mar 05 01:10:57 PM PST 24 | Mar 05 01:11:35 PM PST 24 | 2836485237 ps | ||
| T544 | /workspace/coverage/default/33.hmac_back_pressure.2093680945 | Mar 05 01:10:54 PM PST 24 | Mar 05 01:11:00 PM PST 24 | 181090284 ps | ||
| T545 | /workspace/coverage/default/10.hmac_error.1178334914 | Mar 05 01:09:54 PM PST 24 | Mar 05 01:11:43 PM PST 24 | 19229077239 ps | ||
| T546 | /workspace/coverage/default/23.hmac_wipe_secret.602211137 | Mar 05 01:10:21 PM PST 24 | Mar 05 01:11:10 PM PST 24 | 2550169952 ps | ||
| T547 | /workspace/coverage/default/4.hmac_alert_test.665995066 | Mar 05 01:09:57 PM PST 24 | Mar 05 01:09:58 PM PST 24 | 14593170 ps | ||
| T548 | /workspace/coverage/default/40.hmac_error.2459329000 | Mar 05 01:10:53 PM PST 24 | Mar 05 01:11:43 PM PST 24 | 4063620154 ps | ||
| T35 | /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.2194890088 | Mar 05 01:10:13 PM PST 24 | Mar 05 01:37:21 PM PST 24 | 230931841083 ps | ||
| T127 | /workspace/coverage/default/44.hmac_stress_all.383952254 | Mar 05 01:11:16 PM PST 24 | Mar 05 01:29:06 PM PST 24 | 76449117805 ps | ||
| T123 | /workspace/coverage/default/4.hmac_stress_all.1722982339 | Mar 05 01:09:55 PM PST 24 | Mar 05 01:16:18 PM PST 24 | 8171381550 ps | ||
| T549 | /workspace/coverage/default/7.hmac_test_hmac_vectors.1317241912 | Mar 05 01:09:53 PM PST 24 | Mar 05 01:09:55 PM PST 24 | 266296217 ps | ||
| T550 | /workspace/coverage/default/25.hmac_burst_wr.3476872402 | Mar 05 01:10:20 PM PST 24 | Mar 05 01:11:07 PM PST 24 | 2483984856 ps | ||
| T551 | /workspace/coverage/default/36.hmac_datapath_stress.4125281628 | Mar 05 01:10:47 PM PST 24 | Mar 05 01:12:41 PM PST 24 | 8527156864 ps | ||
| T552 | /workspace/coverage/default/2.hmac_back_pressure.4133474011 | Mar 05 01:09:53 PM PST 24 | Mar 05 01:10:01 PM PST 24 | 240984709 ps | ||
| T553 | /workspace/coverage/default/8.hmac_wipe_secret.685040107 | Mar 05 01:09:53 PM PST 24 | Mar 05 01:10:40 PM PST 24 | 3657414106 ps | ||
| T554 | /workspace/coverage/default/11.hmac_back_pressure.2099736361 | Mar 05 01:09:53 PM PST 24 | Mar 05 01:10:13 PM PST 24 | 2232487205 ps | ||
| T555 | /workspace/coverage/default/5.hmac_stress_all.2985705592 | Mar 05 01:09:59 PM PST 24 | Mar 05 01:20:06 PM PST 24 | 106716022030 ps | ||
| T556 | /workspace/coverage/default/21.hmac_back_pressure.2169150121 | Mar 05 01:10:11 PM PST 24 | Mar 05 01:10:16 PM PST 24 | 128595764 ps | ||
| T557 | /workspace/coverage/default/19.hmac_back_pressure.3907773139 | Mar 05 01:10:16 PM PST 24 | Mar 05 01:10:54 PM PST 24 | 1155499660 ps | ||
| T558 | /workspace/coverage/default/15.hmac_stress_all.1106312335 | Mar 05 01:10:07 PM PST 24 | Mar 05 01:18:49 PM PST 24 | 32060337465 ps | ||
| T559 | /workspace/coverage/default/41.hmac_alert_test.367657688 | Mar 05 01:11:01 PM PST 24 | Mar 05 01:11:01 PM PST 24 | 58725159 ps | ||
| T560 | /workspace/coverage/default/44.hmac_wipe_secret.2230896657 | Mar 05 01:11:15 PM PST 24 | Mar 05 01:11:33 PM PST 24 | 11711537637 ps | ||
| T561 | /workspace/coverage/default/28.hmac_wipe_secret.2246349123 | Mar 05 01:10:41 PM PST 24 | Mar 05 01:11:49 PM PST 24 | 13873104970 ps | ||
| T562 | /workspace/coverage/default/36.hmac_smoke.1875652975 | Mar 05 01:10:47 PM PST 24 | Mar 05 01:10:50 PM PST 24 | 2593734575 ps | ||
| T563 | /workspace/coverage/default/24.hmac_error.1503776123 | Mar 05 01:10:29 PM PST 24 | Mar 05 01:11:14 PM PST 24 | 923918483 ps | ||
| T564 | /workspace/coverage/default/31.hmac_error.2756623507 | Mar 05 01:10:40 PM PST 24 | Mar 05 01:11:54 PM PST 24 | 13196319894 ps | ||
| T565 | /workspace/coverage/default/1.hmac_alert_test.2035205187 | Mar 05 01:09:53 PM PST 24 | Mar 05 01:09:55 PM PST 24 | 23120025 ps | ||
| T566 | /workspace/coverage/default/14.hmac_long_msg.4133049453 | Mar 05 01:10:07 PM PST 24 | Mar 05 01:10:45 PM PST 24 | 3778744336 ps | ||
| T567 | /workspace/coverage/default/19.hmac_wipe_secret.3667230699 | Mar 05 01:10:18 PM PST 24 | Mar 05 01:10:21 PM PST 24 | 42317019 ps | ||
| T568 | /workspace/coverage/default/4.hmac_burst_wr.2246564620 | Mar 05 01:09:56 PM PST 24 | Mar 05 01:10:00 PM PST 24 | 57712364 ps | ||
| T569 | /workspace/coverage/default/20.hmac_smoke.785863656 | Mar 05 01:10:14 PM PST 24 | Mar 05 01:10:16 PM PST 24 | 317272956 ps | ||
| T570 | /workspace/coverage/default/24.hmac_back_pressure.1482255632 | Mar 05 01:10:20 PM PST 24 | Mar 05 01:10:42 PM PST 24 | 544789820 ps | ||
| T571 | /workspace/coverage/default/6.hmac_long_msg.2126156009 | Mar 05 01:09:54 PM PST 24 | Mar 05 01:10:19 PM PST 24 | 2735043243 ps | ||
| T572 | /workspace/coverage/default/39.hmac_back_pressure.4011563651 | Mar 05 01:11:06 PM PST 24 | Mar 05 01:11:37 PM PST 24 | 3667110772 ps | ||
| T573 | /workspace/coverage/default/44.hmac_alert_test.673882656 | Mar 05 01:11:17 PM PST 24 | Mar 05 01:11:17 PM PST 24 | 34174965 ps | ||
| T574 | /workspace/coverage/default/48.hmac_alert_test.614988339 | Mar 05 01:11:25 PM PST 24 | Mar 05 01:11:25 PM PST 24 | 71350147 ps | ||
| T575 | /workspace/coverage/default/47.hmac_alert_test.2902747716 | Mar 05 01:11:28 PM PST 24 | Mar 05 01:11:29 PM PST 24 | 21422275 ps | ||
| T576 | /workspace/coverage/default/18.hmac_wipe_secret.3265812067 | Mar 05 01:10:11 PM PST 24 | Mar 05 01:11:21 PM PST 24 | 7566750322 ps | ||
| T577 | /workspace/coverage/default/21.hmac_test_hmac_vectors.3137441369 | Mar 05 01:10:21 PM PST 24 | Mar 05 01:10:25 PM PST 24 | 54486919 ps | ||
| T578 | /workspace/coverage/default/7.hmac_test_sha_vectors.465621609 | Mar 05 01:09:54 PM PST 24 | Mar 05 01:16:01 PM PST 24 | 14158986164 ps | ||
| T579 | /workspace/coverage/default/4.hmac_long_msg.1746574855 | Mar 05 01:09:57 PM PST 24 | Mar 05 01:11:02 PM PST 24 | 1184569350 ps | ||
| T26 | /workspace/coverage/default/2.hmac_sec_cm.823288247 | Mar 05 01:09:55 PM PST 24 | Mar 05 01:09:57 PM PST 24 | 241127618 ps | ||
| T580 | /workspace/coverage/default/15.hmac_error.3516428574 | Mar 05 01:10:17 PM PST 24 | Mar 05 01:12:28 PM PST 24 | 4021419372 ps | ||
| T581 | /workspace/coverage/default/18.hmac_smoke.469322891 | Mar 05 01:10:17 PM PST 24 | Mar 05 01:10:20 PM PST 24 | 17820011 ps | ||
| T582 | /workspace/coverage/default/23.hmac_test_hmac_vectors.200326102 | Mar 05 01:10:27 PM PST 24 | Mar 05 01:10:29 PM PST 24 | 150124261 ps | ||
| T583 | /workspace/coverage/default/37.hmac_smoke.1820466863 | Mar 05 01:10:47 PM PST 24 | Mar 05 01:10:50 PM PST 24 | 97917128 ps | ||
| T584 | /workspace/coverage/default/26.hmac_wipe_secret.1926949134 | Mar 05 01:10:34 PM PST 24 | Mar 05 01:11:15 PM PST 24 | 51645365182 ps | ||
| T585 | /workspace/coverage/default/8.hmac_test_sha_vectors.3077677107 | Mar 05 01:09:55 PM PST 24 | Mar 05 01:17:17 PM PST 24 | 102550700890 ps | ||
| T586 | /workspace/coverage/default/10.hmac_stress_all.2602321366 | Mar 05 01:09:53 PM PST 24 | Mar 05 01:10:52 PM PST 24 | 7453579468 ps | ||
| T587 | /workspace/coverage/default/43.hmac_test_sha_vectors.3102242996 | Mar 05 01:11:13 PM PST 24 | Mar 05 01:18:23 PM PST 24 | 126164413364 ps | ||
| T588 | /workspace/coverage/default/7.hmac_datapath_stress.2278248511 | Mar 05 01:09:53 PM PST 24 | Mar 05 01:10:59 PM PST 24 | 2378663787 ps | ||
| T589 | /workspace/coverage/default/18.hmac_alert_test.3131239905 | Mar 05 01:10:06 PM PST 24 | Mar 05 01:10:07 PM PST 24 | 12521116 ps | ||
| T590 | /workspace/coverage/default/49.hmac_test_hmac_vectors.3720438087 | Mar 05 01:11:27 PM PST 24 | Mar 05 01:11:29 PM PST 24 | 28580613 ps | ||
| T591 | /workspace/coverage/default/23.hmac_burst_wr.1263799288 | Mar 05 01:10:28 PM PST 24 | Mar 05 01:10:54 PM PST 24 | 7041005398 ps | ||
| T592 | /workspace/coverage/default/1.hmac_wipe_secret.3246605619 | Mar 05 01:09:53 PM PST 24 | Mar 05 01:10:35 PM PST 24 | 4024459925 ps | ||
| T593 | /workspace/coverage/default/4.hmac_datapath_stress.1022317687 | Mar 05 01:09:54 PM PST 24 | Mar 05 01:11:41 PM PST 24 | 24268525873 ps | ||
| T594 | /workspace/coverage/default/43.hmac_long_msg.321992216 | Mar 05 01:11:02 PM PST 24 | Mar 05 01:12:02 PM PST 24 | 1084381741 ps | ||
| T595 | /workspace/coverage/default/21.hmac_alert_test.3852497484 | Mar 05 01:10:24 PM PST 24 | Mar 05 01:10:26 PM PST 24 | 31699531 ps | ||
| T596 | /workspace/coverage/default/22.hmac_error.3119983669 | Mar 05 01:10:19 PM PST 24 | Mar 05 01:11:21 PM PST 24 | 13567559134 ps | ||
| T597 | /workspace/coverage/cover_reg_top/1.hmac_intr_test.1992737969 | Mar 05 01:18:04 PM PST 24 | Mar 05 01:18:05 PM PST 24 | 118325009 ps | ||
| T598 | /workspace/coverage/cover_reg_top/24.hmac_intr_test.684904633 | Mar 05 01:18:19 PM PST 24 | Mar 05 01:18:20 PM PST 24 | 46058159 ps | ||
| T48 | /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2111074047 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:23 PM PST 24 | 50336301 ps | ||
| T599 | /workspace/coverage/cover_reg_top/36.hmac_intr_test.889337753 | Mar 05 01:18:38 PM PST 24 | Mar 05 01:18:39 PM PST 24 | 15361110 ps | ||
| T44 | /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1701086322 | Mar 05 01:18:14 PM PST 24 | Mar 05 01:18:15 PM PST 24 | 486540624 ps | ||
| T600 | /workspace/coverage/cover_reg_top/22.hmac_intr_test.2700301718 | Mar 05 01:18:23 PM PST 24 | Mar 05 01:18:24 PM PST 24 | 74280157 ps | ||
| T45 | /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.760801206 | Mar 05 01:18:33 PM PST 24 | Mar 05 01:18:35 PM PST 24 | 203253792 ps | ||
| T80 | /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1353402235 | Mar 05 01:18:17 PM PST 24 | Mar 05 01:18:26 PM PST 24 | 381472350 ps | ||
| T601 | /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3770140529 | Mar 05 01:18:13 PM PST 24 | Mar 05 01:18:15 PM PST 24 | 32407009 ps | ||
| T602 | /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3313425468 | Mar 05 01:18:19 PM PST 24 | Mar 05 01:18:20 PM PST 24 | 190753041 ps | ||
| T603 | /workspace/coverage/cover_reg_top/6.hmac_intr_test.3691959796 | Mar 05 01:18:09 PM PST 24 | Mar 05 01:18:10 PM PST 24 | 37636968 ps | ||
| T604 | /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2882389446 | Mar 05 01:18:13 PM PST 24 | Mar 05 01:18:16 PM PST 24 | 39591565 ps | ||
| T605 | /workspace/coverage/cover_reg_top/25.hmac_intr_test.651120827 | Mar 05 01:18:23 PM PST 24 | Mar 05 01:18:24 PM PST 24 | 14173499 ps | ||
| T606 | /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3133600092 | Mar 05 01:18:10 PM PST 24 | Mar 05 01:18:10 PM PST 24 | 18675394 ps | ||
| T607 | /workspace/coverage/cover_reg_top/17.hmac_intr_test.1596336848 | Mar 05 01:18:18 PM PST 24 | Mar 05 01:18:19 PM PST 24 | 56345415 ps | ||
| T46 | /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.288869875 | Mar 05 01:18:03 PM PST 24 | Mar 05 01:18:05 PM PST 24 | 83168848 ps | ||
| T608 | /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3233801006 | Mar 05 01:18:31 PM PST 24 | Mar 05 01:18:34 PM PST 24 | 492330542 ps | ||
| T609 | /workspace/coverage/cover_reg_top/19.hmac_intr_test.4187391690 | Mar 05 01:18:28 PM PST 24 | Mar 05 01:18:29 PM PST 24 | 24115798 ps | ||
| T610 | /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3773716023 | Mar 05 01:18:27 PM PST 24 | Mar 05 01:18:28 PM PST 24 | 16730155 ps | ||
| T611 | /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1705805994 | Mar 05 01:18:04 PM PST 24 | Mar 05 01:18:06 PM PST 24 | 66667107 ps | ||
| T612 | /workspace/coverage/cover_reg_top/46.hmac_intr_test.715881322 | Mar 05 01:18:33 PM PST 24 | Mar 05 01:18:33 PM PST 24 | 85457376 ps | ||
| T613 | /workspace/coverage/cover_reg_top/10.hmac_intr_test.3585340846 | Mar 05 01:18:19 PM PST 24 | Mar 05 01:18:20 PM PST 24 | 16062768 ps | ||
| T614 | /workspace/coverage/cover_reg_top/38.hmac_intr_test.4258738943 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:22 PM PST 24 | 47383370 ps | ||
| T615 | /workspace/coverage/cover_reg_top/47.hmac_intr_test.617507896 | Mar 05 01:18:40 PM PST 24 | Mar 05 01:18:41 PM PST 24 | 28417406 ps | ||
| T616 | /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.784090472 | Mar 05 01:18:11 PM PST 24 | Mar 05 01:18:14 PM PST 24 | 433679530 ps | ||
| T81 | /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.127442 | Mar 05 01:18:02 PM PST 24 | Mar 05 01:18:09 PM PST 24 | 254332264 ps | ||
| T82 | /workspace/coverage/cover_reg_top/10.hmac_csr_rw.814691012 | Mar 05 01:18:44 PM PST 24 | Mar 05 01:18:44 PM PST 24 | 41349435 ps | ||
| T617 | /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3770636439 | Mar 05 01:18:18 PM PST 24 | Mar 05 01:18:20 PM PST 24 | 53852486 ps | ||
| T83 | /workspace/coverage/cover_reg_top/2.hmac_csr_rw.4079079307 | Mar 05 01:18:09 PM PST 24 | Mar 05 01:18:10 PM PST 24 | 76492056 ps | ||
| T618 | /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4001119514 | Mar 05 01:18:19 PM PST 24 | Mar 05 01:18:21 PM PST 24 | 48983194 ps | ||
| T619 | /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3465845742 | Mar 05 01:18:02 PM PST 24 | Mar 05 01:18:05 PM PST 24 | 104821598 ps | ||
| T84 | /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2553542500 | Mar 05 01:18:18 PM PST 24 | Mar 05 01:18:19 PM PST 24 | 23725088 ps | ||
| T620 | /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4233062032 | Mar 05 01:18:10 PM PST 24 | Mar 05 01:18:12 PM PST 24 | 400938543 ps | ||
| T129 | /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.583034605 | Mar 05 01:18:19 PM PST 24 | Mar 05 01:18:22 PM PST 24 | 102277623 ps | ||
| T621 | /workspace/coverage/cover_reg_top/45.hmac_intr_test.4203030469 | Mar 05 01:18:39 PM PST 24 | Mar 05 01:18:39 PM PST 24 | 75030347 ps | ||
| T85 | /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3587010929 | Mar 05 01:18:07 PM PST 24 | Mar 05 01:18:09 PM PST 24 | 377150182 ps | ||
| T622 | /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3299269074 | Mar 05 01:18:19 PM PST 24 | Mar 05 01:18:21 PM PST 24 | 21976827 ps | ||
| T135 | /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2809517244 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:23 PM PST 24 | 111204390 ps | ||
| T132 | /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1401635998 | Mar 05 01:18:10 PM PST 24 | Mar 05 01:18:12 PM PST 24 | 77356494 ps | ||
| T623 | /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2014596001 | Mar 05 01:18:47 PM PST 24 | Mar 05 01:18:49 PM PST 24 | 540380900 ps | ||
| T624 | /workspace/coverage/cover_reg_top/40.hmac_intr_test.412237462 | Mar 05 01:18:41 PM PST 24 | Mar 05 01:18:42 PM PST 24 | 47815034 ps | ||
| T86 | /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1596278570 | Mar 05 01:18:12 PM PST 24 | Mar 05 01:18:13 PM PST 24 | 49649318 ps | ||
| T137 | /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3160497437 | Mar 05 01:18:12 PM PST 24 | Mar 05 01:18:14 PM PST 24 | 427400102 ps | ||
| T625 | /workspace/coverage/cover_reg_top/21.hmac_intr_test.4097811092 | Mar 05 01:18:23 PM PST 24 | Mar 05 01:18:24 PM PST 24 | 82235226 ps | ||
| T626 | /workspace/coverage/cover_reg_top/19.hmac_csr_rw.816805717 | Mar 05 01:18:31 PM PST 24 | Mar 05 01:18:32 PM PST 24 | 17262080 ps | ||
| T627 | /workspace/coverage/cover_reg_top/3.hmac_intr_test.3507330039 | Mar 05 01:18:09 PM PST 24 | Mar 05 01:18:10 PM PST 24 | 32780341 ps | ||
| T628 | /workspace/coverage/cover_reg_top/31.hmac_intr_test.1591377741 | Mar 05 01:18:18 PM PST 24 | Mar 05 01:18:19 PM PST 24 | 16955445 ps | ||
| T629 | /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2057900674 | Mar 05 01:18:15 PM PST 24 | Mar 05 01:18:17 PM PST 24 | 185209182 ps | ||
| T630 | /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2550346008 | Mar 05 01:18:34 PM PST 24 | Mar 05 01:18:35 PM PST 24 | 204148707 ps | ||
| T631 | /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1532489254 | Mar 05 01:18:23 PM PST 24 | Mar 05 01:18:24 PM PST 24 | 16050376 ps | ||
| T632 | /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3023812233 | Mar 05 01:18:11 PM PST 24 | Mar 05 01:18:12 PM PST 24 | 210556037 ps | ||
| T633 | /workspace/coverage/cover_reg_top/18.hmac_intr_test.1582110139 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:22 PM PST 24 | 14430950 ps | ||
| T634 | /workspace/coverage/cover_reg_top/7.hmac_intr_test.3251394045 | Mar 05 01:18:10 PM PST 24 | Mar 05 01:18:10 PM PST 24 | 14503703 ps | ||
| T635 | /workspace/coverage/cover_reg_top/30.hmac_intr_test.666590479 | Mar 05 01:18:26 PM PST 24 | Mar 05 01:18:27 PM PST 24 | 18378752 ps | ||
| T87 | /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2402267052 | Mar 05 01:18:07 PM PST 24 | Mar 05 01:18:08 PM PST 24 | 68308294 ps | ||
| T636 | /workspace/coverage/cover_reg_top/32.hmac_intr_test.1394822827 | Mar 05 01:18:26 PM PST 24 | Mar 05 01:18:27 PM PST 24 | 40724530 ps | ||
| T637 | /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4216029991 | Mar 05 01:18:25 PM PST 24 | Mar 05 01:18:26 PM PST 24 | 110157310 ps | ||
| T638 | /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2085463219 | Mar 05 01:18:11 PM PST 24 | Mar 05 01:18:12 PM PST 24 | 18517964 ps | ||
| T88 | /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3977356223 | Mar 05 01:18:35 PM PST 24 | Mar 05 01:18:36 PM PST 24 | 13968164 ps | ||
| T639 | /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1285382832 | Mar 05 01:18:09 PM PST 24 | Mar 05 01:18:10 PM PST 24 | 30992834 ps | ||
| T640 | /workspace/coverage/cover_reg_top/39.hmac_intr_test.3176793651 | Mar 05 01:18:27 PM PST 24 | Mar 05 01:18:27 PM PST 24 | 19132697 ps | ||
| T89 | /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4294960968 | Mar 05 01:18:11 PM PST 24 | Mar 05 01:18:19 PM PST 24 | 189190808 ps | ||
| T641 | /workspace/coverage/cover_reg_top/37.hmac_intr_test.3049446407 | Mar 05 01:18:31 PM PST 24 | Mar 05 01:18:32 PM PST 24 | 60072706 ps | ||
| T642 | /workspace/coverage/cover_reg_top/12.hmac_intr_test.2026454621 | Mar 05 01:18:32 PM PST 24 | Mar 05 01:18:33 PM PST 24 | 49495155 ps | ||
| T643 | /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.20986597 | Mar 05 01:18:03 PM PST 24 | Mar 05 01:18:05 PM PST 24 | 142667703 ps | ||
| T644 | /workspace/coverage/cover_reg_top/20.hmac_intr_test.4071946284 | Mar 05 01:18:48 PM PST 24 | Mar 05 01:18:48 PM PST 24 | 37316718 ps | ||
| T645 | /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.395080780 | Mar 05 01:18:22 PM PST 24 | Mar 05 01:18:24 PM PST 24 | 118443839 ps | ||
| T133 | /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1650407965 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:23 PM PST 24 | 614736633 ps | ||
| T646 | /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.358510027 | Mar 05 01:18:11 PM PST 24 | Mar 05 01:18:12 PM PST 24 | 41914086 ps | ||
| T647 | /workspace/coverage/cover_reg_top/41.hmac_intr_test.4124587812 | Mar 05 01:18:26 PM PST 24 | Mar 05 01:18:27 PM PST 24 | 67558124 ps | ||
| T648 | /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3396345632 | Mar 05 01:18:17 PM PST 24 | Mar 05 01:18:20 PM PST 24 | 110596654 ps | ||
| T649 | /workspace/coverage/cover_reg_top/8.hmac_intr_test.3502454238 | Mar 05 01:18:15 PM PST 24 | Mar 05 01:18:16 PM PST 24 | 11157169 ps | ||
| T650 | /workspace/coverage/cover_reg_top/49.hmac_intr_test.1663687161 | Mar 05 01:18:29 PM PST 24 | Mar 05 01:18:30 PM PST 24 | 15064389 ps | ||
| T651 | /workspace/coverage/cover_reg_top/34.hmac_intr_test.783622518 | Mar 05 01:18:44 PM PST 24 | Mar 05 01:18:45 PM PST 24 | 14944798 ps | ||
| T652 | /workspace/coverage/cover_reg_top/19.hmac_tl_errors.4008628030 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:28 PM PST 24 | 126879302 ps | ||
| T653 | /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.165713477 | Mar 05 01:18:13 PM PST 24 | Mar 05 01:18:17 PM PST 24 | 1129896026 ps | ||
| T130 | /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.723187252 | Mar 05 01:18:18 PM PST 24 | Mar 05 01:18:21 PM PST 24 | 486195349 ps | ||
| T654 | /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1157270217 | Mar 05 01:18:17 PM PST 24 | Mar 05 01:18:21 PM PST 24 | 119443175 ps | ||
| T655 | /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2391497038 | Mar 05 01:18:19 PM PST 24 | Mar 05 01:18:22 PM PST 24 | 52511699 ps | ||
| T656 | /workspace/coverage/cover_reg_top/0.hmac_tl_errors.957549306 | Mar 05 01:18:04 PM PST 24 | Mar 05 01:18:07 PM PST 24 | 38099329 ps | ||
| T93 | /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3130879881 | Mar 05 01:17:58 PM PST 24 | Mar 05 01:17:59 PM PST 24 | 52827113 ps | ||
| T657 | /workspace/coverage/cover_reg_top/17.hmac_tl_errors.710687306 | Mar 05 01:18:43 PM PST 24 | Mar 05 01:18:47 PM PST 24 | 196651237 ps | ||
| T658 | /workspace/coverage/cover_reg_top/0.hmac_csr_rw.183909236 | Mar 05 01:17:59 PM PST 24 | Mar 05 01:18:00 PM PST 24 | 24997993 ps | ||
| T659 | /workspace/coverage/cover_reg_top/18.hmac_tl_errors.902625523 | Mar 05 01:18:46 PM PST 24 | Mar 05 01:18:47 PM PST 24 | 726946707 ps | ||
| T660 | /workspace/coverage/cover_reg_top/35.hmac_intr_test.3943134062 | Mar 05 01:18:29 PM PST 24 | Mar 05 01:18:30 PM PST 24 | 28554876 ps | ||
| T661 | /workspace/coverage/cover_reg_top/27.hmac_intr_test.764923933 | Mar 05 01:18:27 PM PST 24 | Mar 05 01:18:28 PM PST 24 | 12995962 ps | ||
| T662 | /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1074472617 | Mar 05 01:18:09 PM PST 24 | Mar 05 01:18:10 PM PST 24 | 83245841 ps | ||
| T663 | /workspace/coverage/cover_reg_top/13.hmac_tl_errors.28278995 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:24 PM PST 24 | 451576626 ps | ||
| T90 | /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1245118073 | Mar 05 01:18:16 PM PST 24 | Mar 05 01:18:20 PM PST 24 | 197781829 ps | ||
| T664 | /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.981471220 | Mar 05 01:18:19 PM PST 24 | Mar 05 01:18:20 PM PST 24 | 703527451 ps | ||
| T665 | /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3796990785 | Mar 05 01:18:22 PM PST 24 | Mar 05 01:18:23 PM PST 24 | 37169201 ps | ||
| T666 | /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.795067040 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:23 PM PST 24 | 78595214 ps | ||
| T667 | /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1454002187 | Mar 05 01:18:16 PM PST 24 | Mar 05 01:18:17 PM PST 24 | 20133986 ps | ||
| T668 | /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3550278766 | Mar 05 01:18:05 PM PST 24 | Mar 05 01:18:07 PM PST 24 | 120800302 ps | ||
| T669 | /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1434784186 | Mar 05 01:18:08 PM PST 24 | Mar 05 01:18:12 PM PST 24 | 61240681 ps | ||
| T670 | /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2631947698 | Mar 05 01:18:27 PM PST 24 | Mar 05 01:18:29 PM PST 24 | 112027413 ps | ||
| T671 | /workspace/coverage/cover_reg_top/8.hmac_tl_errors.773358113 | Mar 05 01:18:12 PM PST 24 | Mar 05 01:18:13 PM PST 24 | 79679281 ps | ||
| T672 | /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3162592594 | Mar 05 01:18:11 PM PST 24 | Mar 05 01:18:12 PM PST 24 | 18225738 ps | ||
| T673 | /workspace/coverage/cover_reg_top/15.hmac_intr_test.2154943864 | Mar 05 01:18:32 PM PST 24 | Mar 05 01:18:33 PM PST 24 | 41018601 ps | ||
| T674 | /workspace/coverage/cover_reg_top/13.hmac_intr_test.1992760210 | Mar 05 01:18:18 PM PST 24 | Mar 05 01:18:19 PM PST 24 | 49960488 ps | ||
| T675 | /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4014115610 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:29 PM PST 24 | 36369151 ps | ||
| T676 | /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2380024340 | Mar 05 01:18:17 PM PST 24 | Mar 05 01:18:19 PM PST 24 | 22852441 ps | ||
| T677 | /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3747427992 | Mar 05 01:18:10 PM PST 24 | Mar 05 01:18:19 PM PST 24 | 810546271 ps | ||
| T678 | /workspace/coverage/cover_reg_top/42.hmac_intr_test.2875656335 | Mar 05 01:18:33 PM PST 24 | Mar 05 01:18:34 PM PST 24 | 29993205 ps | ||
| T91 | /workspace/coverage/cover_reg_top/7.hmac_csr_rw.548903620 | Mar 05 01:18:11 PM PST 24 | Mar 05 01:18:12 PM PST 24 | 101936235 ps | ||
| T131 | /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4028321604 | Mar 05 01:18:42 PM PST 24 | Mar 05 01:18:45 PM PST 24 | 169217897 ps | ||
| T134 | /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3767528078 | Mar 05 01:18:29 PM PST 24 | Mar 05 01:18:31 PM PST 24 | 1029671793 ps | ||
| T679 | /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2541871733 | Mar 05 01:18:14 PM PST 24 | Mar 05 01:18:16 PM PST 24 | 358597230 ps | ||
| T680 | /workspace/coverage/cover_reg_top/43.hmac_intr_test.3837575283 | Mar 05 01:18:40 PM PST 24 | Mar 05 01:18:41 PM PST 24 | 75129052 ps | ||
| T681 | /workspace/coverage/cover_reg_top/28.hmac_intr_test.2275569449 | Mar 05 01:18:28 PM PST 24 | Mar 05 01:18:29 PM PST 24 | 30178761 ps | ||
| T682 | /workspace/coverage/cover_reg_top/16.hmac_intr_test.1429355669 | Mar 05 01:18:26 PM PST 24 | Mar 05 01:18:26 PM PST 24 | 35033669 ps | ||
| T683 | /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2940160236 | Mar 05 01:18:19 PM PST 24 | Mar 05 01:18:22 PM PST 24 | 287926162 ps | ||
| T684 | /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3577375187 | Mar 05 01:18:03 PM PST 24 | Mar 05 01:18:06 PM PST 24 | 656182759 ps | ||
| T685 | /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1917950846 | Mar 05 01:18:09 PM PST 24 | Mar 05 01:18:12 PM PST 24 | 186014071 ps | ||
| T686 | /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2689311791 | Mar 05 01:18:14 PM PST 24 | Mar 05 01:18:16 PM PST 24 | 229091625 ps | ||
| T687 | /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.874820327 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:23 PM PST 24 | 298811493 ps | ||
| T92 | /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1788603024 | Mar 05 01:18:26 PM PST 24 | Mar 05 01:18:27 PM PST 24 | 12209651 ps | ||
| T688 | /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2395860507 | Mar 05 01:18:18 PM PST 24 | Mar 05 01:18:21 PM PST 24 | 98546976 ps | ||
| T94 | /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3266801318 | Mar 05 01:18:13 PM PST 24 | Mar 05 01:18:16 PM PST 24 | 499137217 ps | ||
| T689 | /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3847911556 | Mar 05 01:18:20 PM PST 24 | Mar 05 01:18:21 PM PST 24 | 22991474 ps | ||
| T690 | /workspace/coverage/cover_reg_top/14.hmac_intr_test.552625081 | Mar 05 01:18:20 PM PST 24 | Mar 05 01:18:21 PM PST 24 | 38536586 ps | ||
| T691 | /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.570908417 | Mar 05 01:18:44 PM PST 24 | Mar 05 01:18:47 PM PST 24 | 145354704 ps | ||
| T692 | /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3182264725 | Mar 05 01:18:20 PM PST 24 | Mar 05 01:18:22 PM PST 24 | 53829746 ps | ||
| T693 | /workspace/coverage/cover_reg_top/23.hmac_intr_test.1733353558 | Mar 05 01:18:41 PM PST 24 | Mar 05 01:18:42 PM PST 24 | 68255514 ps | ||
| T136 | /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2239717205 | Mar 05 01:18:02 PM PST 24 | Mar 05 01:18:05 PM PST 24 | 2261687540 ps | ||
| T694 | /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3460524015 | Mar 05 01:18:17 PM PST 24 | Mar 05 01:18:20 PM PST 24 | 384186719 ps | ||
| T695 | /workspace/coverage/cover_reg_top/33.hmac_intr_test.1881296476 | Mar 05 01:18:23 PM PST 24 | Mar 05 01:18:24 PM PST 24 | 14299760 ps | ||
| T696 | /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3205633244 | Mar 05 01:18:28 PM PST 24 | Mar 05 01:18:29 PM PST 24 | 828912447 ps | ||
| T138 | /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3511916726 | Mar 05 01:18:18 PM PST 24 | Mar 05 01:18:20 PM PST 24 | 87084701 ps | ||
| T697 | /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.801551825 | Mar 05 01:18:15 PM PST 24 | Mar 05 01:18:16 PM PST 24 | 78555616 ps | ||
| T698 | /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.70623310 | Mar 05 01:18:07 PM PST 24 | Mar 05 01:18:09 PM PST 24 | 351927596 ps | ||
| T699 | /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.316969146 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:23 PM PST 24 | 461805948 ps | ||
| T700 | /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.397772038 | Mar 05 01:18:11 PM PST 24 | Mar 05 01:18:13 PM PST 24 | 119472088 ps | ||
| T701 | /workspace/coverage/cover_reg_top/16.hmac_tl_errors.541415261 | Mar 05 01:18:28 PM PST 24 | Mar 05 01:18:31 PM PST 24 | 325398842 ps | ||
| T702 | /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1416947604 | Mar 05 01:18:36 PM PST 24 | Mar 05 01:18:39 PM PST 24 | 81361257 ps | ||
| T703 | /workspace/coverage/cover_reg_top/9.hmac_intr_test.1402147694 | Mar 05 01:18:20 PM PST 24 | Mar 05 01:18:21 PM PST 24 | 37801622 ps | ||
| T704 | /workspace/coverage/cover_reg_top/48.hmac_intr_test.4042884239 | Mar 05 01:18:33 PM PST 24 | Mar 05 01:18:33 PM PST 24 | 18601771 ps | ||
| T705 | /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2949811914 | Mar 05 01:18:33 PM PST 24 | Mar 05 01:18:34 PM PST 24 | 38275191 ps | ||
| T706 | /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1349104620 | Mar 05 01:18:41 PM PST 24 | Mar 05 01:18:43 PM PST 24 | 280012645 ps | ||
| T707 | /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2027611955 | Mar 05 01:18:34 PM PST 24 | Mar 05 01:18:36 PM PST 24 | 155270566 ps | ||
| T47 | /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2120959439 | Mar 05 01:18:22 PM PST 24 | Mar 05 01:18:23 PM PST 24 | 134415543 ps | ||
| T708 | /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1015770355 | Mar 05 01:18:09 PM PST 24 | Mar 05 01:18:11 PM PST 24 | 143509681 ps | ||
| T709 | /workspace/coverage/cover_reg_top/26.hmac_intr_test.3932642505 | Mar 05 01:18:32 PM PST 24 | Mar 05 01:18:33 PM PST 24 | 17294986 ps | ||
| T710 | /workspace/coverage/cover_reg_top/2.hmac_tl_errors.667737684 | Mar 05 01:18:08 PM PST 24 | Mar 05 01:18:12 PM PST 24 | 157023178 ps | ||
| T711 | /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3998362270 | Mar 05 01:18:43 PM PST 24 | Mar 05 01:18:45 PM PST 24 | 187655283 ps | ||
| T712 | /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3670704261 | Mar 05 01:18:27 PM PST 24 | Mar 05 01:18:28 PM PST 24 | 15593127 ps | ||
| T713 | /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3481183075 | Mar 05 01:18:09 PM PST 24 | Mar 05 01:18:10 PM PST 24 | 29858315 ps | ||
| T714 | /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3815800398 | Mar 05 01:18:11 PM PST 24 | Mar 05 01:18:13 PM PST 24 | 36150908 ps | ||
| T715 | /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4042065486 | Mar 05 01:18:24 PM PST 24 | Mar 05 01:18:25 PM PST 24 | 33474101 ps | ||
| T716 | /workspace/coverage/cover_reg_top/4.hmac_intr_test.2044798884 | Mar 05 01:18:12 PM PST 24 | Mar 05 01:18:13 PM PST 24 | 50111806 ps | ||
| T717 | /workspace/coverage/cover_reg_top/0.hmac_intr_test.1450941045 | Mar 05 01:18:05 PM PST 24 | Mar 05 01:18:06 PM PST 24 | 15177569 ps | ||
| T718 | /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3419291632 | Mar 05 01:18:30 PM PST 24 | Mar 05 01:18:31 PM PST 24 | 109964675 ps | ||
| T719 | /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2360049835 | Mar 05 01:18:09 PM PST 24 | Mar 05 01:18:10 PM PST 24 | 36907951 ps | ||
| T720 | /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3378148476 | Mar 05 01:18:19 PM PST 24 | Mar 05 01:18:21 PM PST 24 | 254710262 ps | ||
| T721 | /workspace/coverage/cover_reg_top/29.hmac_intr_test.2099277567 | Mar 05 01:18:25 PM PST 24 | Mar 05 01:18:25 PM PST 24 | 11985334 ps | ||
| T722 | /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.845222297 | Mar 05 01:18:15 PM PST 24 | Mar 05 01:18:17 PM PST 24 | 104370440 ps | ||
| T723 | /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1949872785 | Mar 05 01:18:21 PM PST 24 | Mar 05 01:18:22 PM PST 24 | 23960102 ps | ||
| T724 | /workspace/coverage/cover_reg_top/44.hmac_intr_test.1140190607 | Mar 05 01:18:36 PM PST 24 | Mar 05 01:18:37 PM PST 24 | 113048717 ps | ||
| T725 | /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2995899326 | Mar 05 01:18:08 PM PST 24 | Mar 05 01:18:09 PM PST 24 | 119179808 ps | ||
| T726 | /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3196561771 | Mar 05 01:18:25 PM PST 24 | Mar 05 01:18:26 PM PST 24 | 136321701 ps | ||
| T727 | /workspace/coverage/cover_reg_top/5.hmac_intr_test.2552811370 | Mar 05 01:18:15 PM PST 24 | Mar 05 01:18:16 PM PST 24 | 14360782 ps | ||
| T728 | /workspace/coverage/cover_reg_top/2.hmac_intr_test.3347639303 | Mar 05 01:18:14 PM PST 24 | Mar 05 01:18:15 PM PST 24 | 13516230 ps | ||
| T95 | /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2833826174 | Mar 05 01:18:18 PM PST 24 | Mar 05 01:18:19 PM PST 24 | 13880770 ps | ||
| T729 | /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1388625308 | Mar 05 01:18:03 PM PST 24 | Mar 05 01:18:04 PM PST 24 | 30687620 ps | ||
| T730 | /workspace/coverage/cover_reg_top/11.hmac_intr_test.3580110528 | Mar 05 01:18:25 PM PST 24 | Mar 05 01:18:25 PM PST 24 | 13901397 ps |
| Test location | /workspace/coverage/default/45.hmac_wipe_secret.1259890941 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5752345476 ps |
| CPU time | 59.92 seconds |
| Started | Mar 05 01:11:16 PM PST 24 |
| Finished | Mar 05 01:12:16 PM PST 24 |
| Peak memory | 199148 kb |
| Host | smart-452787bf-9731-47a7-95ed-96c8e0424915 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259890941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1259890941 |
| Directory | /workspace/45.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.1472490215 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 96446136554 ps |
| CPU time | 605.76 seconds |
| Started | Mar 05 01:11:55 PM PST 24 |
| Finished | Mar 05 01:22:02 PM PST 24 |
| Peak memory | 238792 kb |
| Host | smart-9be47dfb-028c-49c7-9b5d-ebbb7a73ac7b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1472490215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.1472490215 |
| Directory | /workspace/149.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.hmac_burst_wr.664480527 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 5447283779 ps |
| CPU time | 41.89 seconds |
| Started | Mar 05 01:09:52 PM PST 24 |
| Finished | Mar 05 01:10:35 PM PST 24 |
| Peak memory | 199064 kb |
| Host | smart-c048f657-e4f7-463b-b477-cfd4e9025e8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664480527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.664480527 |
| Directory | /workspace/10.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/1.hmac_sec_cm.3230414809 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 278010106 ps |
| CPU time | 0.86 seconds |
| Started | Mar 05 01:09:50 PM PST 24 |
| Finished | Mar 05 01:09:53 PM PST 24 |
| Peak memory | 216356 kb |
| Host | smart-a9d39dda-e403-4607-a72b-94cd12161999 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230414809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3230414809 |
| Directory | /workspace/1.hmac_sec_cm/latest |
| Test location | /workspace/coverage/default/37.hmac_test_sha_vectors.4192806312 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 30969357832 ps |
| CPU time | 374.8 seconds |
| Started | Mar 05 01:11:16 PM PST 24 |
| Finished | Mar 05 01:17:31 PM PST 24 |
| Peak memory | 199064 kb |
| Host | smart-602730bf-86ab-4455-9180-f2caae1337bf |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192806312 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 37.hmac_test_sha_vectors.4192806312 |
| Directory | /workspace/37.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.760801206 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 203253792 ps |
| CPU time | 2.53 seconds |
| Started | Mar 05 01:18:33 PM PST 24 |
| Finished | Mar 05 01:18:35 PM PST 24 |
| Peak memory | 198312 kb |
| Host | smart-a3a8cf1f-8a4c-4fd1-ab91-3ad9b7d66bc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760801206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.760801206 |
| Directory | /workspace/18.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.1974603136 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 144463264389 ps |
| CPU time | 5833.45 seconds |
| Started | Mar 05 01:12:09 PM PST 24 |
| Finished | Mar 05 02:49:24 PM PST 24 |
| Peak memory | 273020 kb |
| Host | smart-9cfab628-17ef-4b7e-a695-b1fccab5d04d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1974603136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.1974603136 |
| Directory | /workspace/189.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.hmac_stress_all.3752032697 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 132411260843 ps |
| CPU time | 247.33 seconds |
| Started | Mar 05 01:10:15 PM PST 24 |
| Finished | Mar 05 01:14:22 PM PST 24 |
| Peak memory | 199020 kb |
| Host | smart-28c70465-1e34-4962-b230-1142e39ae700 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752032697 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3752032697 |
| Directory | /workspace/21.hmac_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.127442 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 254332264 ps |
| CPU time | 5.69 seconds |
| Started | Mar 05 01:18:02 PM PST 24 |
| Finished | Mar 05 01:18:09 PM PST 24 |
| Peak memory | 192008 kb |
| Host | smart-1ec06579-47a3-457f-8667-44439b484f00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.127442 |
| Directory | /workspace/0.hmac_csr_bit_bash/latest |
| Test location | /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.3930419545 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 34623329610 ps |
| CPU time | 1773.45 seconds |
| Started | Mar 05 01:10:59 PM PST 24 |
| Finished | Mar 05 01:40:33 PM PST 24 |
| Peak memory | 229128 kb |
| Host | smart-93d9d833-95c4-4f1f-ba64-7a6f90afcb3d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3930419545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.3930419545 |
| Directory | /workspace/41.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3511916726 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 87084701 ps |
| CPU time | 1.21 seconds |
| Started | Mar 05 01:18:18 PM PST 24 |
| Finished | Mar 05 01:18:20 PM PST 24 |
| Peak memory | 197984 kb |
| Host | smart-61d662ec-56ce-4084-a101-db87216fa5ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511916726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3511916726 |
| Directory | /workspace/10.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.hmac_alert_test.4101110496 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 16174179 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:09:50 PM PST 24 |
| Finished | Mar 05 01:09:53 PM PST 24 |
| Peak memory | 194636 kb |
| Host | smart-86687ca6-8eba-470e-99b2-29e1a63597c5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101110496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4101110496 |
| Directory | /workspace/0.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/1.hmac_datapath_stress.2022785145 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3478288703 ps |
| CPU time | 39.48 seconds |
| Started | Mar 05 01:09:50 PM PST 24 |
| Finished | Mar 05 01:10:32 PM PST 24 |
| Peak memory | 199000 kb |
| Host | smart-ad7fb89c-a5b2-4029-96a4-575caa473668 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2022785145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2022785145 |
| Directory | /workspace/1.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1650407965 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 614736633 ps |
| CPU time | 2.37 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:23 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-4f884921-fd1b-4b70-bc20-21b298778680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650407965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1650407965 |
| Directory | /workspace/6.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/default/11.hmac_stress_all.1549776202 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2432146109 ps |
| CPU time | 103.08 seconds |
| Started | Mar 05 01:10:04 PM PST 24 |
| Finished | Mar 05 01:11:48 PM PST 24 |
| Peak memory | 199084 kb |
| Host | smart-135dc904-0d1b-485a-8d79-9405b400db41 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549776202 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1549776202 |
| Directory | /workspace/11.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.4208777422 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 73090913018 ps |
| CPU time | 1752.26 seconds |
| Started | Mar 05 01:11:54 PM PST 24 |
| Finished | Mar 05 01:41:08 PM PST 24 |
| Peak memory | 240080 kb |
| Host | smart-87255447-5054-4f7d-bbca-7c7434f6b07d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4208777422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.4208777422 |
| Directory | /workspace/128.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.hmac_error.804774540 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10627915928 ps |
| CPU time | 124.19 seconds |
| Started | Mar 05 01:10:56 PM PST 24 |
| Finished | Mar 05 01:13:00 PM PST 24 |
| Peak memory | 199068 kb |
| Host | smart-3fa7f137-bb90-4705-864c-e7fe744a5c83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=804774540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.804774540 |
| Directory | /workspace/38.hmac_error/latest |
| Test location | /workspace/coverage/default/0.hmac_stress_all.2828315633 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 71863255633 ps |
| CPU time | 1788.09 seconds |
| Started | Mar 05 01:09:50 PM PST 24 |
| Finished | Mar 05 01:39:41 PM PST 24 |
| Peak memory | 240040 kb |
| Host | smart-eb4d37c9-626c-4ae3-87e4-e18bc58a45dc |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828315633 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2828315633 |
| Directory | /workspace/0.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/1.hmac_stress_all.870657493 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 314652796913 ps |
| CPU time | 921 seconds |
| Started | Mar 05 01:09:43 PM PST 24 |
| Finished | Mar 05 01:25:06 PM PST 24 |
| Peak memory | 218500 kb |
| Host | smart-8bca96bf-558d-41c5-be93-045864791991 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870657493 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.870657493 |
| Directory | /workspace/1.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.1344365835 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 55071244210 ps |
| CPU time | 253.95 seconds |
| Started | Mar 05 01:11:54 PM PST 24 |
| Finished | Mar 05 01:16:09 PM PST 24 |
| Peak memory | 215356 kb |
| Host | smart-713563fc-6ddf-4035-8ffc-a68c0743c779 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1344365835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.1344365835 |
| Directory | /workspace/113.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.hmac_stress_all.1663499505 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 26613373532 ps |
| CPU time | 1308.34 seconds |
| Started | Mar 05 01:10:12 PM PST 24 |
| Finished | Mar 05 01:32:01 PM PST 24 |
| Peak memory | 215532 kb |
| Host | smart-8103491c-c762-4e72-bf36-e23b8d7a12ff |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663499505 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1663499505 |
| Directory | /workspace/13.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/20.hmac_stress_all.179847279 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 8716371172 ps |
| CPU time | 155.23 seconds |
| Started | Mar 05 01:10:23 PM PST 24 |
| Finished | Mar 05 01:13:00 PM PST 24 |
| Peak memory | 216280 kb |
| Host | smart-a377ac83-8110-493c-9371-b3483aa77bf2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179847279 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.179847279 |
| Directory | /workspace/20.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/27.hmac_wipe_secret.2966455999 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1748496719 ps |
| CPU time | 65.59 seconds |
| Started | Mar 05 01:10:38 PM PST 24 |
| Finished | Mar 05 01:11:44 PM PST 24 |
| Peak memory | 198932 kb |
| Host | smart-bdad108b-a5be-40b7-97fe-4a6db1a4e937 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2966455999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2966455999 |
| Directory | /workspace/27.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/38.hmac_stress_all.3047278035 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4475660675 ps |
| CPU time | 199.44 seconds |
| Started | Mar 05 01:10:54 PM PST 24 |
| Finished | Mar 05 01:14:14 PM PST 24 |
| Peak memory | 240048 kb |
| Host | smart-064750d7-3dc3-44d7-9373-904c3ccc7f2b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047278035 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3047278035 |
| Directory | /workspace/38.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/9.hmac_stress_all.3471731263 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 24680008101 ps |
| CPU time | 1201.06 seconds |
| Started | Mar 05 01:09:58 PM PST 24 |
| Finished | Mar 05 01:30:00 PM PST 24 |
| Peak memory | 199096 kb |
| Host | smart-95928316-b74c-49c3-bb93-e7de0c96998a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471731263 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3471731263 |
| Directory | /workspace/9.hmac_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2120959439 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 134415543 ps |
| CPU time | 1.69 seconds |
| Started | Mar 05 01:18:22 PM PST 24 |
| Finished | Mar 05 01:18:23 PM PST 24 |
| Peak memory | 198196 kb |
| Host | smart-3764ec98-3810-402c-90b6-37d6e5736294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120959439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2120959439 |
| Directory | /workspace/15.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3577375187 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 656182759 ps |
| CPU time | 2.55 seconds |
| Started | Mar 05 01:18:03 PM PST 24 |
| Finished | Mar 05 01:18:06 PM PST 24 |
| Peak memory | 192028 kb |
| Host | smart-cfe49861-98d3-4565-80ad-c4d3d41df045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577375187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3577375187 |
| Directory | /workspace/0.hmac_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2360049835 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 36907951 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:18:09 PM PST 24 |
| Finished | Mar 05 01:18:10 PM PST 24 |
| Peak memory | 193620 kb |
| Host | smart-b7f74e7d-0fcc-4eb1-b5a8-23bbbec56816 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360049835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2360049835 |
| Directory | /workspace/0.hmac_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.20986597 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 142667703 ps |
| CPU time | 1.18 seconds |
| Started | Mar 05 01:18:03 PM PST 24 |
| Finished | Mar 05 01:18:05 PM PST 24 |
| Peak memory | 198436 kb |
| Host | smart-197c16f3-4ec2-4e3a-a3b1-55bd96a8e622 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20986597 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.20986597 |
| Directory | /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.hmac_csr_rw.183909236 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 24997993 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:17:59 PM PST 24 |
| Finished | Mar 05 01:18:00 PM PST 24 |
| Peak memory | 194448 kb |
| Host | smart-5d23be2c-e211-4627-a59b-a73c468276b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183909236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.183909236 |
| Directory | /workspace/0.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.hmac_intr_test.1450941045 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 15177569 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 01:18:05 PM PST 24 |
| Finished | Mar 05 01:18:06 PM PST 24 |
| Peak memory | 183716 kb |
| Host | smart-74839920-4709-494d-9062-2358d94f66cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450941045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1450941045 |
| Directory | /workspace/0.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3550278766 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 120800302 ps |
| CPU time | 0.87 seconds |
| Started | Mar 05 01:18:05 PM PST 24 |
| Finished | Mar 05 01:18:07 PM PST 24 |
| Peak memory | 192004 kb |
| Host | smart-5b81ac84-0937-4ec7-9ee8-e709ae97b05f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550278766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr _outstanding.3550278766 |
| Directory | /workspace/0.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.hmac_tl_errors.957549306 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 38099329 ps |
| CPU time | 2.25 seconds |
| Started | Mar 05 01:18:04 PM PST 24 |
| Finished | Mar 05 01:18:07 PM PST 24 |
| Peak memory | 198600 kb |
| Host | smart-cc9acc41-f43a-40ab-8c74-3aed4095284b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957549306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.957549306 |
| Directory | /workspace/0.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.288869875 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 83168848 ps |
| CPU time | 1.23 seconds |
| Started | Mar 05 01:18:03 PM PST 24 |
| Finished | Mar 05 01:18:05 PM PST 24 |
| Peak memory | 197796 kb |
| Host | smart-bdf8b716-a6b0-4491-a228-2f699b61032e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288869875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.288869875 |
| Directory | /workspace/0.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.845222297 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 104370440 ps |
| CPU time | 1.89 seconds |
| Started | Mar 05 01:18:15 PM PST 24 |
| Finished | Mar 05 01:18:17 PM PST 24 |
| Peak memory | 183932 kb |
| Host | smart-d880c9e9-a346-49ac-9f40-8b77742ba207 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845222297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.845222297 |
| Directory | /workspace/1.hmac_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.165713477 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1129896026 ps |
| CPU time | 3.5 seconds |
| Started | Mar 05 01:18:13 PM PST 24 |
| Finished | Mar 05 01:18:17 PM PST 24 |
| Peak memory | 191996 kb |
| Host | smart-5c42bab1-c379-407e-96e6-0ab31def0f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165713477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.165713477 |
| Directory | /workspace/1.hmac_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3130879881 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 52827113 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:17:58 PM PST 24 |
| Finished | Mar 05 01:17:59 PM PST 24 |
| Peak memory | 193556 kb |
| Host | smart-d0e5e022-1d0b-44e3-be3e-eb54db8c74c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130879881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3130879881 |
| Directory | /workspace/1.hmac_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2882389446 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 39591565 ps |
| CPU time | 2.1 seconds |
| Started | Mar 05 01:18:13 PM PST 24 |
| Finished | Mar 05 01:18:16 PM PST 24 |
| Peak memory | 198480 kb |
| Host | smart-432d11c8-8638-4276-8af0-a4b9211743b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882389446 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2882389446 |
| Directory | /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1388625308 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 30687620 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:18:03 PM PST 24 |
| Finished | Mar 05 01:18:04 PM PST 24 |
| Peak memory | 193668 kb |
| Host | smart-e0aff685-e4c5-4fd0-bcdd-ad6abf3ec9d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388625308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1388625308 |
| Directory | /workspace/1.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.hmac_intr_test.1992737969 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 118325009 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 01:18:04 PM PST 24 |
| Finished | Mar 05 01:18:05 PM PST 24 |
| Peak memory | 183724 kb |
| Host | smart-9c1700b3-68b2-4659-b929-d112b19e4798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992737969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1992737969 |
| Directory | /workspace/1.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2541871733 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 358597230 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:18:14 PM PST 24 |
| Finished | Mar 05 01:18:16 PM PST 24 |
| Peak memory | 192112 kb |
| Host | smart-43441b5b-4932-445f-a137-a4c2731d3343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541871733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr _outstanding.2541871733 |
| Directory | /workspace/1.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3465845742 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 104821598 ps |
| CPU time | 2.41 seconds |
| Started | Mar 05 01:18:02 PM PST 24 |
| Finished | Mar 05 01:18:05 PM PST 24 |
| Peak memory | 198588 kb |
| Host | smart-bf6cebcb-0aef-45bc-b993-49cd41ca467b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465845742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3465845742 |
| Directory | /workspace/1.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2239717205 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2261687540 ps |
| CPU time | 2.56 seconds |
| Started | Mar 05 01:18:02 PM PST 24 |
| Finished | Mar 05 01:18:05 PM PST 24 |
| Peak memory | 198288 kb |
| Host | smart-08e05cf1-79e7-4a80-aaec-2868ce2983dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239717205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2239717205 |
| Directory | /workspace/1.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2111074047 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 50336301 ps |
| CPU time | 1.77 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:23 PM PST 24 |
| Peak memory | 198608 kb |
| Host | smart-1c48c3a0-9b11-4b57-97b6-f84cfa0239e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111074047 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2111074047 |
| Directory | /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.hmac_csr_rw.814691012 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 41349435 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:18:44 PM PST 24 |
| Finished | Mar 05 01:18:44 PM PST 24 |
| Peak memory | 194656 kb |
| Host | smart-94bb0bad-9671-4035-a023-8f3e1def8074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814691012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.814691012 |
| Directory | /workspace/10.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.hmac_intr_test.3585340846 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 16062768 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:18:19 PM PST 24 |
| Finished | Mar 05 01:18:20 PM PST 24 |
| Peak memory | 183640 kb |
| Host | smart-423437d7-40f5-46f3-80cc-49a8bb3cb71a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585340846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3585340846 |
| Directory | /workspace/10.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.316969146 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 461805948 ps |
| CPU time | 1.51 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:23 PM PST 24 |
| Peak memory | 192152 kb |
| Host | smart-74472991-1ed2-4d5a-9c7d-5e9f50b43a91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316969146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr _outstanding.316969146 |
| Directory | /workspace/10.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2940160236 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 287926162 ps |
| CPU time | 1.69 seconds |
| Started | Mar 05 01:18:19 PM PST 24 |
| Finished | Mar 05 01:18:22 PM PST 24 |
| Peak memory | 198616 kb |
| Host | smart-59ed026f-a398-4ae0-b8e3-4a9c76aa9d2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940160236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2940160236 |
| Directory | /workspace/10.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2380024340 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 22852441 ps |
| CPU time | 1.23 seconds |
| Started | Mar 05 01:18:17 PM PST 24 |
| Finished | Mar 05 01:18:19 PM PST 24 |
| Peak memory | 198320 kb |
| Host | smart-bd7ffa16-a01c-4df5-8b77-b225e7498994 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380024340 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2380024340 |
| Directory | /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3299269074 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 21976827 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:18:19 PM PST 24 |
| Finished | Mar 05 01:18:21 PM PST 24 |
| Peak memory | 194728 kb |
| Host | smart-0d8c1fa9-2055-4190-97c5-98b5e33977a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299269074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3299269074 |
| Directory | /workspace/11.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.hmac_intr_test.3580110528 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 13901397 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 01:18:25 PM PST 24 |
| Finished | Mar 05 01:18:25 PM PST 24 |
| Peak memory | 183700 kb |
| Host | smart-69924afc-b1ec-4e21-a882-6a6b85fb98f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580110528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3580110528 |
| Directory | /workspace/11.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2949811914 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 38275191 ps |
| CPU time | 0.83 seconds |
| Started | Mar 05 01:18:33 PM PST 24 |
| Finished | Mar 05 01:18:34 PM PST 24 |
| Peak memory | 192004 kb |
| Host | smart-028109e3-9c1e-46d8-9206-633a7fdc613b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949811914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs r_outstanding.2949811914 |
| Directory | /workspace/11.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4216029991 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 110157310 ps |
| CPU time | 1.66 seconds |
| Started | Mar 05 01:18:25 PM PST 24 |
| Finished | Mar 05 01:18:26 PM PST 24 |
| Peak memory | 198640 kb |
| Host | smart-9a5e1427-9d51-4556-9711-1e4f4f4dda0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216029991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4216029991 |
| Directory | /workspace/11.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3378148476 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 254710262 ps |
| CPU time | 1.19 seconds |
| Started | Mar 05 01:18:19 PM PST 24 |
| Finished | Mar 05 01:18:21 PM PST 24 |
| Peak memory | 197828 kb |
| Host | smart-a39b1049-66bc-41a3-8e77-866cd25596ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378148476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3378148476 |
| Directory | /workspace/11.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1416947604 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 81361257 ps |
| CPU time | 2.22 seconds |
| Started | Mar 05 01:18:36 PM PST 24 |
| Finished | Mar 05 01:18:39 PM PST 24 |
| Peak memory | 198512 kb |
| Host | smart-0781bfb5-a7ef-4488-a656-8b6b0fe28cbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416947604 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1416947604 |
| Directory | /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3977356223 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 13968164 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 01:18:35 PM PST 24 |
| Finished | Mar 05 01:18:36 PM PST 24 |
| Peak memory | 194104 kb |
| Host | smart-1416a20c-7de4-4ad0-af15-9bb6a8ec085a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977356223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3977356223 |
| Directory | /workspace/12.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.hmac_intr_test.2026454621 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 49495155 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:18:32 PM PST 24 |
| Finished | Mar 05 01:18:33 PM PST 24 |
| Peak memory | 183716 kb |
| Host | smart-233a1445-4633-46ee-a91e-16e954399a87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026454621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2026454621 |
| Directory | /workspace/12.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3205633244 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 828912447 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:18:28 PM PST 24 |
| Finished | Mar 05 01:18:29 PM PST 24 |
| Peak memory | 196748 kb |
| Host | smart-7ae06fb0-5453-4676-b80c-70c297f7fb2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205633244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs r_outstanding.3205633244 |
| Directory | /workspace/12.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2550346008 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 204148707 ps |
| CPU time | 1.21 seconds |
| Started | Mar 05 01:18:34 PM PST 24 |
| Finished | Mar 05 01:18:35 PM PST 24 |
| Peak memory | 198476 kb |
| Host | smart-0a581247-6af0-4a1f-919c-ce39be0cf27b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550346008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2550346008 |
| Directory | /workspace/12.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3460524015 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 384186719 ps |
| CPU time | 1.69 seconds |
| Started | Mar 05 01:18:17 PM PST 24 |
| Finished | Mar 05 01:18:20 PM PST 24 |
| Peak memory | 197984 kb |
| Host | smart-741c285c-809c-4988-9f09-d4af377efdf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460524015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3460524015 |
| Directory | /workspace/12.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2014596001 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 540380900 ps |
| CPU time | 1.7 seconds |
| Started | Mar 05 01:18:47 PM PST 24 |
| Finished | Mar 05 01:18:49 PM PST 24 |
| Peak memory | 198604 kb |
| Host | smart-3312dcf2-e634-4948-bd16-f6bc0e2caf35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014596001 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2014596001 |
| Directory | /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3796990785 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 37169201 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:18:22 PM PST 24 |
| Finished | Mar 05 01:18:23 PM PST 24 |
| Peak memory | 194568 kb |
| Host | smart-00709786-e2c0-4343-a467-171e32461913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796990785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3796990785 |
| Directory | /workspace/13.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.hmac_intr_test.1992760210 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 49960488 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:18:18 PM PST 24 |
| Finished | Mar 05 01:18:19 PM PST 24 |
| Peak memory | 183740 kb |
| Host | smart-3789f145-b5fc-4491-b9cd-aa5628f8cd64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992760210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1992760210 |
| Directory | /workspace/13.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4042065486 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 33474101 ps |
| CPU time | 1.32 seconds |
| Started | Mar 05 01:18:24 PM PST 24 |
| Finished | Mar 05 01:18:25 PM PST 24 |
| Peak memory | 196596 kb |
| Host | smart-ca37d659-2f04-4198-ae10-7cd93728dc6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042065486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs r_outstanding.4042065486 |
| Directory | /workspace/13.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.hmac_tl_errors.28278995 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 451576626 ps |
| CPU time | 2.07 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:24 PM PST 24 |
| Peak memory | 198580 kb |
| Host | smart-cdbb8628-b730-4144-9f93-9d452841cfbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28278995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.28278995 |
| Directory | /workspace/13.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1349104620 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 280012645 ps |
| CPU time | 1.62 seconds |
| Started | Mar 05 01:18:41 PM PST 24 |
| Finished | Mar 05 01:18:43 PM PST 24 |
| Peak memory | 198076 kb |
| Host | smart-334602f7-ab8a-4412-b2da-93eb0c643cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349104620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1349104620 |
| Directory | /workspace/13.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4014115610 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 36369151 ps |
| CPU time | 2.28 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:29 PM PST 24 |
| Peak memory | 198552 kb |
| Host | smart-03b3d952-02b2-41fc-89e2-69265ad9fb69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014115610 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.4014115610 |
| Directory | /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3670704261 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 15593127 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 01:18:27 PM PST 24 |
| Finished | Mar 05 01:18:28 PM PST 24 |
| Peak memory | 193972 kb |
| Host | smart-d89bfedc-448f-4888-8ed3-25cf710aace9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670704261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3670704261 |
| Directory | /workspace/14.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.hmac_intr_test.552625081 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 38536586 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:18:20 PM PST 24 |
| Finished | Mar 05 01:18:21 PM PST 24 |
| Peak memory | 183704 kb |
| Host | smart-a9017498-f6f4-471a-9c44-0cc62b59f80b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552625081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.552625081 |
| Directory | /workspace/14.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1532489254 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 16050376 ps |
| CPU time | 0.76 seconds |
| Started | Mar 05 01:18:23 PM PST 24 |
| Finished | Mar 05 01:18:24 PM PST 24 |
| Peak memory | 194636 kb |
| Host | smart-ac08b439-7ea5-48a5-923b-e50c68fc55f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532489254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs r_outstanding.1532489254 |
| Directory | /workspace/14.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3233801006 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 492330542 ps |
| CPU time | 2.8 seconds |
| Started | Mar 05 01:18:31 PM PST 24 |
| Finished | Mar 05 01:18:34 PM PST 24 |
| Peak memory | 198576 kb |
| Host | smart-6d09f11f-8451-4dfb-94f1-b5832a57c428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233801006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3233801006 |
| Directory | /workspace/14.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2809517244 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 111204390 ps |
| CPU time | 1.88 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:23 PM PST 24 |
| Peak memory | 198244 kb |
| Host | smart-5b0677c3-4e61-4472-832c-94e3f095d6cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809517244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2809517244 |
| Directory | /workspace/14.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3196561771 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 136321701 ps |
| CPU time | 1.16 seconds |
| Started | Mar 05 01:18:25 PM PST 24 |
| Finished | Mar 05 01:18:26 PM PST 24 |
| Peak memory | 198424 kb |
| Host | smart-6fe6034c-a178-423c-8a02-572fca3c8df0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196561771 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3196561771 |
| Directory | /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2833826174 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 13880770 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:18:18 PM PST 24 |
| Finished | Mar 05 01:18:19 PM PST 24 |
| Peak memory | 194612 kb |
| Host | smart-38b243fa-05c1-4438-a287-45eee232d6fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833826174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2833826174 |
| Directory | /workspace/15.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.hmac_intr_test.2154943864 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 41018601 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:18:32 PM PST 24 |
| Finished | Mar 05 01:18:33 PM PST 24 |
| Peak memory | 183620 kb |
| Host | smart-9af8e300-6066-41a9-a202-40cb4884ae6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154943864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2154943864 |
| Directory | /workspace/15.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2631947698 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 112027413 ps |
| CPU time | 1.33 seconds |
| Started | Mar 05 01:18:27 PM PST 24 |
| Finished | Mar 05 01:18:29 PM PST 24 |
| Peak memory | 196572 kb |
| Host | smart-5d351588-31c7-4b64-8010-f07d2093f0f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631947698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs r_outstanding.2631947698 |
| Directory | /workspace/15.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2395860507 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 98546976 ps |
| CPU time | 2.74 seconds |
| Started | Mar 05 01:18:18 PM PST 24 |
| Finished | Mar 05 01:18:21 PM PST 24 |
| Peak memory | 198548 kb |
| Host | smart-5e079eee-f03e-49e5-afeb-35d8a9110a4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395860507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2395860507 |
| Directory | /workspace/15.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3998362270 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 187655283 ps |
| CPU time | 1.43 seconds |
| Started | Mar 05 01:18:43 PM PST 24 |
| Finished | Mar 05 01:18:45 PM PST 24 |
| Peak memory | 198560 kb |
| Host | smart-49ac862a-42ef-448d-af03-0870568f5a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998362270 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3998362270 |
| Directory | /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3773716023 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 16730155 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:18:27 PM PST 24 |
| Finished | Mar 05 01:18:28 PM PST 24 |
| Peak memory | 194564 kb |
| Host | smart-ef4349e0-3b1d-4a51-a7f1-0fc00c60e91d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773716023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3773716023 |
| Directory | /workspace/16.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.hmac_intr_test.1429355669 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 35033669 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:18:26 PM PST 24 |
| Finished | Mar 05 01:18:26 PM PST 24 |
| Peak memory | 183632 kb |
| Host | smart-e60973c1-fa84-453f-ba6e-2eae229642aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429355669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1429355669 |
| Directory | /workspace/16.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.981471220 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 703527451 ps |
| CPU time | 1.15 seconds |
| Started | Mar 05 01:18:19 PM PST 24 |
| Finished | Mar 05 01:18:20 PM PST 24 |
| Peak memory | 192352 kb |
| Host | smart-136354d4-d276-41ba-8436-5ffef614eb15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981471220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr _outstanding.981471220 |
| Directory | /workspace/16.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.hmac_tl_errors.541415261 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 325398842 ps |
| CPU time | 3.48 seconds |
| Started | Mar 05 01:18:28 PM PST 24 |
| Finished | Mar 05 01:18:31 PM PST 24 |
| Peak memory | 198552 kb |
| Host | smart-b2cbda3f-d28f-4a52-af57-3587b7e6ffdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541415261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.541415261 |
| Directory | /workspace/16.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3767528078 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1029671793 ps |
| CPU time | 1.75 seconds |
| Started | Mar 05 01:18:29 PM PST 24 |
| Finished | Mar 05 01:18:31 PM PST 24 |
| Peak memory | 197992 kb |
| Host | smart-74e66223-1a4d-444c-a976-bf3ef3aa56e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767528078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3767528078 |
| Directory | /workspace/16.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2027611955 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 155270566 ps |
| CPU time | 2.42 seconds |
| Started | Mar 05 01:18:34 PM PST 24 |
| Finished | Mar 05 01:18:36 PM PST 24 |
| Peak memory | 198560 kb |
| Host | smart-bcf5e600-2773-41be-aa75-b1493d0b775b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027611955 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2027611955 |
| Directory | /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1949872785 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 23960102 ps |
| CPU time | 0.73 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:22 PM PST 24 |
| Peak memory | 194304 kb |
| Host | smart-151bbecf-8490-4af8-8067-a85dfdcdc23f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949872785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1949872785 |
| Directory | /workspace/17.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.hmac_intr_test.1596336848 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 56345415 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:18:18 PM PST 24 |
| Finished | Mar 05 01:18:19 PM PST 24 |
| Peak memory | 183588 kb |
| Host | smart-e924d0a7-5270-412b-b169-29110a309b44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596336848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1596336848 |
| Directory | /workspace/17.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3770636439 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 53852486 ps |
| CPU time | 1.17 seconds |
| Started | Mar 05 01:18:18 PM PST 24 |
| Finished | Mar 05 01:18:20 PM PST 24 |
| Peak memory | 196484 kb |
| Host | smart-cbf63dea-9708-4f79-a0dc-9806190f112e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770636439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs r_outstanding.3770636439 |
| Directory | /workspace/17.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.hmac_tl_errors.710687306 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 196651237 ps |
| CPU time | 3.56 seconds |
| Started | Mar 05 01:18:43 PM PST 24 |
| Finished | Mar 05 01:18:47 PM PST 24 |
| Peak memory | 198580 kb |
| Host | smart-3be40d4f-7fc6-486d-81fc-5a20f8897597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710687306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.710687306 |
| Directory | /workspace/17.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.570908417 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 145354704 ps |
| CPU time | 2.27 seconds |
| Started | Mar 05 01:18:44 PM PST 24 |
| Finished | Mar 05 01:18:47 PM PST 24 |
| Peak memory | 198148 kb |
| Host | smart-337c73c9-c544-460e-8fc8-a527c62243cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570908417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.570908417 |
| Directory | /workspace/17.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.874820327 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 298811493 ps |
| CPU time | 1.95 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:23 PM PST 24 |
| Peak memory | 198628 kb |
| Host | smart-02c1aeb6-e952-4b6d-8b19-c29bd2af87eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874820327 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.874820327 |
| Directory | /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1788603024 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 12209651 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:18:26 PM PST 24 |
| Finished | Mar 05 01:18:27 PM PST 24 |
| Peak memory | 194264 kb |
| Host | smart-1bc00168-9fbd-4daf-b3b9-10d015f094a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788603024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1788603024 |
| Directory | /workspace/18.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.hmac_intr_test.1582110139 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 14430950 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:22 PM PST 24 |
| Peak memory | 183732 kb |
| Host | smart-13fe6784-f3b6-4fa6-b7de-b49e67d65817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582110139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1582110139 |
| Directory | /workspace/18.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.395080780 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 118443839 ps |
| CPU time | 1.32 seconds |
| Started | Mar 05 01:18:22 PM PST 24 |
| Finished | Mar 05 01:18:24 PM PST 24 |
| Peak memory | 192196 kb |
| Host | smart-19dceeeb-87c5-4bea-8820-7d7e06f27bde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395080780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr _outstanding.395080780 |
| Directory | /workspace/18.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.hmac_tl_errors.902625523 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 726946707 ps |
| CPU time | 1.47 seconds |
| Started | Mar 05 01:18:46 PM PST 24 |
| Finished | Mar 05 01:18:47 PM PST 24 |
| Peak memory | 198580 kb |
| Host | smart-f97dc653-70fe-415d-8cee-148522b7f9a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902625523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.902625523 |
| Directory | /workspace/18.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.795067040 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 78595214 ps |
| CPU time | 1.81 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:23 PM PST 24 |
| Peak memory | 198628 kb |
| Host | smart-b2a3c590-a6e6-4b92-a452-0ecd1db553a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795067040 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.795067040 |
| Directory | /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.hmac_csr_rw.816805717 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 17262080 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 01:18:31 PM PST 24 |
| Finished | Mar 05 01:18:32 PM PST 24 |
| Peak memory | 193860 kb |
| Host | smart-afa691b5-9e11-41a3-8837-01cdae03f745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816805717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.816805717 |
| Directory | /workspace/19.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.hmac_intr_test.4187391690 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 24115798 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 01:18:28 PM PST 24 |
| Finished | Mar 05 01:18:29 PM PST 24 |
| Peak memory | 183736 kb |
| Host | smart-3fac44dd-67b5-4e01-ad63-ad7607c29bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187391690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.4187391690 |
| Directory | /workspace/19.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3419291632 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 109964675 ps |
| CPU time | 1.12 seconds |
| Started | Mar 05 01:18:30 PM PST 24 |
| Finished | Mar 05 01:18:31 PM PST 24 |
| Peak memory | 196548 kb |
| Host | smart-7fe73fea-25e6-420d-9bcf-317321df57d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419291632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs r_outstanding.3419291632 |
| Directory | /workspace/19.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.hmac_tl_errors.4008628030 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 126879302 ps |
| CPU time | 1.93 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:28 PM PST 24 |
| Peak memory | 198600 kb |
| Host | smart-ccd05836-c92c-48ae-a277-44d5b6eb546a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008628030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.4008628030 |
| Directory | /workspace/19.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4028321604 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 169217897 ps |
| CPU time | 2.57 seconds |
| Started | Mar 05 01:18:42 PM PST 24 |
| Finished | Mar 05 01:18:45 PM PST 24 |
| Peak memory | 198240 kb |
| Host | smart-edc15cac-86ff-4f65-9cd7-a55353d42d90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028321604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4028321604 |
| Directory | /workspace/19.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3587010929 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 377150182 ps |
| CPU time | 1.88 seconds |
| Started | Mar 05 01:18:07 PM PST 24 |
| Finished | Mar 05 01:18:09 PM PST 24 |
| Peak memory | 192192 kb |
| Host | smart-144d6c9f-fc25-4731-b5a2-be6d9f64895e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587010929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3587010929 |
| Directory | /workspace/2.hmac_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1353402235 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 381472350 ps |
| CPU time | 8.09 seconds |
| Started | Mar 05 01:18:17 PM PST 24 |
| Finished | Mar 05 01:18:26 PM PST 24 |
| Peak memory | 191976 kb |
| Host | smart-bae4c6fe-b476-4fda-8421-519c452fdf48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353402235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1353402235 |
| Directory | /workspace/2.hmac_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2402267052 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 68308294 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:18:07 PM PST 24 |
| Finished | Mar 05 01:18:08 PM PST 24 |
| Peak memory | 193888 kb |
| Host | smart-ae7c391f-8397-4a1e-915d-9a6ce0bf36b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402267052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2402267052 |
| Directory | /workspace/2.hmac_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3481183075 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 29858315 ps |
| CPU time | 0.96 seconds |
| Started | Mar 05 01:18:09 PM PST 24 |
| Finished | Mar 05 01:18:10 PM PST 24 |
| Peak memory | 198388 kb |
| Host | smart-4f8a040b-0486-4e04-a342-c9b25060c9db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481183075 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3481183075 |
| Directory | /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.hmac_csr_rw.4079079307 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 76492056 ps |
| CPU time | 0.71 seconds |
| Started | Mar 05 01:18:09 PM PST 24 |
| Finished | Mar 05 01:18:10 PM PST 24 |
| Peak memory | 194424 kb |
| Host | smart-ab3d70f5-73bb-41de-9409-231ff7c6614a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079079307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.4079079307 |
| Directory | /workspace/2.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.hmac_intr_test.3347639303 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 13516230 ps |
| CPU time | 0.59 seconds |
| Started | Mar 05 01:18:14 PM PST 24 |
| Finished | Mar 05 01:18:15 PM PST 24 |
| Peak memory | 183656 kb |
| Host | smart-78e11266-f4ef-467a-be36-06374fc6988b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347639303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3347639303 |
| Directory | /workspace/2.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3162592594 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 18225738 ps |
| CPU time | 0.82 seconds |
| Started | Mar 05 01:18:11 PM PST 24 |
| Finished | Mar 05 01:18:12 PM PST 24 |
| Peak memory | 191992 kb |
| Host | smart-6754466d-044f-4a0e-ad0d-3b57fe693d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162592594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr _outstanding.3162592594 |
| Directory | /workspace/2.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.hmac_tl_errors.667737684 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 157023178 ps |
| CPU time | 3.44 seconds |
| Started | Mar 05 01:18:08 PM PST 24 |
| Finished | Mar 05 01:18:12 PM PST 24 |
| Peak memory | 198592 kb |
| Host | smart-1788b567-f4fc-4990-a180-82beacf7a47d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667737684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.667737684 |
| Directory | /workspace/2.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1401635998 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 77356494 ps |
| CPU time | 1.85 seconds |
| Started | Mar 05 01:18:10 PM PST 24 |
| Finished | Mar 05 01:18:12 PM PST 24 |
| Peak memory | 197996 kb |
| Host | smart-66e553c8-12a7-4ff8-b91a-0a3a9bcd0f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401635998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1401635998 |
| Directory | /workspace/2.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.hmac_intr_test.4071946284 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 37316718 ps |
| CPU time | 0.66 seconds |
| Started | Mar 05 01:18:48 PM PST 24 |
| Finished | Mar 05 01:18:48 PM PST 24 |
| Peak memory | 183732 kb |
| Host | smart-0708e4b2-6029-4206-ac1f-f72bc3ecea8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071946284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.4071946284 |
| Directory | /workspace/20.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.hmac_intr_test.4097811092 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 82235226 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:18:23 PM PST 24 |
| Finished | Mar 05 01:18:24 PM PST 24 |
| Peak memory | 183740 kb |
| Host | smart-295a4a22-8b07-4372-8efb-9f88186543d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097811092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.4097811092 |
| Directory | /workspace/21.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.hmac_intr_test.2700301718 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 74280157 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:18:23 PM PST 24 |
| Finished | Mar 05 01:18:24 PM PST 24 |
| Peak memory | 183736 kb |
| Host | smart-2a623d57-be40-4e1c-b15a-2b657b31356f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700301718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2700301718 |
| Directory | /workspace/22.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.hmac_intr_test.1733353558 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 68255514 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:18:41 PM PST 24 |
| Finished | Mar 05 01:18:42 PM PST 24 |
| Peak memory | 183676 kb |
| Host | smart-0c3735c9-ca47-4ce8-9b0b-7d2e6cabf830 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733353558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1733353558 |
| Directory | /workspace/23.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.hmac_intr_test.684904633 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 46058159 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:18:19 PM PST 24 |
| Finished | Mar 05 01:18:20 PM PST 24 |
| Peak memory | 183688 kb |
| Host | smart-756a4cda-ad47-4140-8e73-dda8918d3b87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684904633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.684904633 |
| Directory | /workspace/24.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.hmac_intr_test.651120827 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 14173499 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:18:23 PM PST 24 |
| Finished | Mar 05 01:18:24 PM PST 24 |
| Peak memory | 183720 kb |
| Host | smart-a92e84dd-24ff-4e64-a932-70d0f13c50a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651120827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.651120827 |
| Directory | /workspace/25.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.hmac_intr_test.3932642505 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 17294986 ps |
| CPU time | 0.54 seconds |
| Started | Mar 05 01:18:32 PM PST 24 |
| Finished | Mar 05 01:18:33 PM PST 24 |
| Peak memory | 183616 kb |
| Host | smart-6ef28917-3734-49dd-ad81-1153fa5d0412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932642505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3932642505 |
| Directory | /workspace/26.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.hmac_intr_test.764923933 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 12995962 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:18:27 PM PST 24 |
| Finished | Mar 05 01:18:28 PM PST 24 |
| Peak memory | 183660 kb |
| Host | smart-74bda470-155e-4f7d-aae7-942e7e44d5d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764923933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.764923933 |
| Directory | /workspace/27.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.hmac_intr_test.2275569449 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 30178761 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:18:28 PM PST 24 |
| Finished | Mar 05 01:18:29 PM PST 24 |
| Peak memory | 183620 kb |
| Host | smart-e003b041-68a1-4fe7-a18f-ad94de610869 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275569449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2275569449 |
| Directory | /workspace/28.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.hmac_intr_test.2099277567 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 11985334 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:18:25 PM PST 24 |
| Finished | Mar 05 01:18:25 PM PST 24 |
| Peak memory | 183680 kb |
| Host | smart-92314ee2-9171-4c87-9ce7-5cc67e8b6d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099277567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2099277567 |
| Directory | /workspace/29.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1245118073 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 197781829 ps |
| CPU time | 1.86 seconds |
| Started | Mar 05 01:18:16 PM PST 24 |
| Finished | Mar 05 01:18:20 PM PST 24 |
| Peak memory | 192144 kb |
| Host | smart-1f8d9353-cc24-4146-8f2d-eb7bfa38ae2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245118073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1245118073 |
| Directory | /workspace/3.hmac_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3747427992 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 810546271 ps |
| CPU time | 9.05 seconds |
| Started | Mar 05 01:18:10 PM PST 24 |
| Finished | Mar 05 01:18:19 PM PST 24 |
| Peak memory | 192132 kb |
| Host | smart-df0ee0b6-8d5f-4595-b440-875f9d583bae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747427992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3747427992 |
| Directory | /workspace/3.hmac_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1074472617 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 83245841 ps |
| CPU time | 0.74 seconds |
| Started | Mar 05 01:18:09 PM PST 24 |
| Finished | Mar 05 01:18:10 PM PST 24 |
| Peak memory | 194028 kb |
| Host | smart-2961c097-642f-4103-8149-a5e9996051b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074472617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1074472617 |
| Directory | /workspace/3.hmac_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1705805994 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 66667107 ps |
| CPU time | 1.09 seconds |
| Started | Mar 05 01:18:04 PM PST 24 |
| Finished | Mar 05 01:18:06 PM PST 24 |
| Peak memory | 198388 kb |
| Host | smart-189ce766-0084-4486-9db5-94d879e7522b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705805994 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1705805994 |
| Directory | /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1454002187 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 20133986 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:18:16 PM PST 24 |
| Finished | Mar 05 01:18:17 PM PST 24 |
| Peak memory | 194536 kb |
| Host | smart-3bdb7da8-d2e9-4fab-85dd-4bd7b127dd97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454002187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1454002187 |
| Directory | /workspace/3.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.hmac_intr_test.3507330039 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 32780341 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:18:09 PM PST 24 |
| Finished | Mar 05 01:18:10 PM PST 24 |
| Peak memory | 183720 kb |
| Host | smart-39c79c17-afcf-4e3d-81f8-82cffa9db282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507330039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3507330039 |
| Directory | /workspace/3.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1285382832 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 30992834 ps |
| CPU time | 1.28 seconds |
| Started | Mar 05 01:18:09 PM PST 24 |
| Finished | Mar 05 01:18:10 PM PST 24 |
| Peak memory | 192088 kb |
| Host | smart-b391c8fe-84d3-4890-8bf1-02f48e516041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285382832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr _outstanding.1285382832 |
| Directory | /workspace/3.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4001119514 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 48983194 ps |
| CPU time | 1.41 seconds |
| Started | Mar 05 01:18:19 PM PST 24 |
| Finished | Mar 05 01:18:21 PM PST 24 |
| Peak memory | 198600 kb |
| Host | smart-db5f8bdb-3d71-4895-bd3d-932a9c4c2dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001119514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4001119514 |
| Directory | /workspace/3.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1701086322 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 486540624 ps |
| CPU time | 1.24 seconds |
| Started | Mar 05 01:18:14 PM PST 24 |
| Finished | Mar 05 01:18:15 PM PST 24 |
| Peak memory | 197824 kb |
| Host | smart-ebf9921b-4d8a-43f7-bd5a-10c132c306a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701086322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1701086322 |
| Directory | /workspace/3.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.hmac_intr_test.666590479 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 18378752 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:18:26 PM PST 24 |
| Finished | Mar 05 01:18:27 PM PST 24 |
| Peak memory | 183660 kb |
| Host | smart-48c75696-33f4-4efe-a4ae-296705200f19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666590479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.666590479 |
| Directory | /workspace/30.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.hmac_intr_test.1591377741 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 16955445 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:18:18 PM PST 24 |
| Finished | Mar 05 01:18:19 PM PST 24 |
| Peak memory | 183668 kb |
| Host | smart-b2664f4f-ae07-47ec-bac3-9fb673862fa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591377741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1591377741 |
| Directory | /workspace/31.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.hmac_intr_test.1394822827 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 40724530 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:18:26 PM PST 24 |
| Finished | Mar 05 01:18:27 PM PST 24 |
| Peak memory | 183732 kb |
| Host | smart-13d1a22b-067a-4162-90e4-96bd72ac14b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394822827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1394822827 |
| Directory | /workspace/32.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.hmac_intr_test.1881296476 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 14299760 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 01:18:23 PM PST 24 |
| Finished | Mar 05 01:18:24 PM PST 24 |
| Peak memory | 183732 kb |
| Host | smart-a15f679e-c9ef-45e8-aa42-602e2bc135b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881296476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1881296476 |
| Directory | /workspace/33.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.hmac_intr_test.783622518 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 14944798 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:18:44 PM PST 24 |
| Finished | Mar 05 01:18:45 PM PST 24 |
| Peak memory | 183668 kb |
| Host | smart-12d856c3-2ed9-4508-ac65-93e0b6ccab62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783622518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.783622518 |
| Directory | /workspace/34.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.hmac_intr_test.3943134062 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 28554876 ps |
| CPU time | 0.58 seconds |
| Started | Mar 05 01:18:29 PM PST 24 |
| Finished | Mar 05 01:18:30 PM PST 24 |
| Peak memory | 183716 kb |
| Host | smart-c2593d1f-eaac-4300-8b8c-d6f33adc0fee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943134062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3943134062 |
| Directory | /workspace/35.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.hmac_intr_test.889337753 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 15361110 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 01:18:38 PM PST 24 |
| Finished | Mar 05 01:18:39 PM PST 24 |
| Peak memory | 183656 kb |
| Host | smart-1c34c4d3-f8e7-4e15-8be2-e9ac09fec03b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889337753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.889337753 |
| Directory | /workspace/36.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.hmac_intr_test.3049446407 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 60072706 ps |
| CPU time | 0.59 seconds |
| Started | Mar 05 01:18:31 PM PST 24 |
| Finished | Mar 05 01:18:32 PM PST 24 |
| Peak memory | 183712 kb |
| Host | smart-912af76b-31e3-4025-a299-5d94bbe6cd10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049446407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3049446407 |
| Directory | /workspace/37.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.hmac_intr_test.4258738943 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 47383370 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:18:21 PM PST 24 |
| Finished | Mar 05 01:18:22 PM PST 24 |
| Peak memory | 183748 kb |
| Host | smart-f99dedff-546c-4b6b-8464-77a54caf6de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258738943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.4258738943 |
| Directory | /workspace/38.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.hmac_intr_test.3176793651 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 19132697 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:18:27 PM PST 24 |
| Finished | Mar 05 01:18:27 PM PST 24 |
| Peak memory | 183680 kb |
| Host | smart-e5255e64-a72d-44d1-96fc-f41b60b184e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176793651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3176793651 |
| Directory | /workspace/39.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3266801318 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 499137217 ps |
| CPU time | 2.43 seconds |
| Started | Mar 05 01:18:13 PM PST 24 |
| Finished | Mar 05 01:18:16 PM PST 24 |
| Peak memory | 195688 kb |
| Host | smart-c67c59ed-55a7-4960-8180-48d04cf9c3c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266801318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3266801318 |
| Directory | /workspace/4.hmac_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4294960968 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 189190808 ps |
| CPU time | 7.87 seconds |
| Started | Mar 05 01:18:11 PM PST 24 |
| Finished | Mar 05 01:18:19 PM PST 24 |
| Peak memory | 192036 kb |
| Host | smart-79f7f53b-ba29-4583-bb6d-7338d2e21687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294960968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4294960968 |
| Directory | /workspace/4.hmac_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1596278570 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 49649318 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 01:18:12 PM PST 24 |
| Finished | Mar 05 01:18:13 PM PST 24 |
| Peak memory | 194436 kb |
| Host | smart-af0a7a1e-dd61-4593-bd26-0c6f115dd012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596278570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1596278570 |
| Directory | /workspace/4.hmac_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2995899326 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 119179808 ps |
| CPU time | 1.2 seconds |
| Started | Mar 05 01:18:08 PM PST 24 |
| Finished | Mar 05 01:18:09 PM PST 24 |
| Peak memory | 198376 kb |
| Host | smart-f3f626a5-1d36-4243-8f41-39d3aa4a55d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995899326 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2995899326 |
| Directory | /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3182264725 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 53829746 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:18:20 PM PST 24 |
| Finished | Mar 05 01:18:22 PM PST 24 |
| Peak memory | 194448 kb |
| Host | smart-ed923b41-fba9-41a1-a937-c9c255a09314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182264725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3182264725 |
| Directory | /workspace/4.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.hmac_intr_test.2044798884 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 50111806 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 01:18:12 PM PST 24 |
| Finished | Mar 05 01:18:13 PM PST 24 |
| Peak memory | 183716 kb |
| Host | smart-07984d22-5573-4f6b-aee3-679e372b1f25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044798884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2044798884 |
| Directory | /workspace/4.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3023812233 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 210556037 ps |
| CPU time | 0.83 seconds |
| Started | Mar 05 01:18:11 PM PST 24 |
| Finished | Mar 05 01:18:12 PM PST 24 |
| Peak memory | 191992 kb |
| Host | smart-7c50e530-ef93-4b95-b6af-87ec474e6fb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023812233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr _outstanding.3023812233 |
| Directory | /workspace/4.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1434784186 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 61240681 ps |
| CPU time | 3.21 seconds |
| Started | Mar 05 01:18:08 PM PST 24 |
| Finished | Mar 05 01:18:12 PM PST 24 |
| Peak memory | 198548 kb |
| Host | smart-6bd52a37-3e47-4aed-9310-156404d3cf9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434784186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1434784186 |
| Directory | /workspace/4.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1015770355 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 143509681 ps |
| CPU time | 2.39 seconds |
| Started | Mar 05 01:18:09 PM PST 24 |
| Finished | Mar 05 01:18:11 PM PST 24 |
| Peak memory | 198312 kb |
| Host | smart-f6351bc0-67b9-4222-9c0b-564d6f4df7fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015770355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1015770355 |
| Directory | /workspace/4.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.hmac_intr_test.412237462 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 47815034 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:18:41 PM PST 24 |
| Finished | Mar 05 01:18:42 PM PST 24 |
| Peak memory | 183652 kb |
| Host | smart-0dbc5459-83f5-4c1b-8022-bc57b26beed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412237462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.412237462 |
| Directory | /workspace/40.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.hmac_intr_test.4124587812 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 67558124 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 01:18:26 PM PST 24 |
| Finished | Mar 05 01:18:27 PM PST 24 |
| Peak memory | 183684 kb |
| Host | smart-aaad05f9-114c-471b-bc49-d71977465ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124587812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.4124587812 |
| Directory | /workspace/41.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.hmac_intr_test.2875656335 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 29993205 ps |
| CPU time | 0.7 seconds |
| Started | Mar 05 01:18:33 PM PST 24 |
| Finished | Mar 05 01:18:34 PM PST 24 |
| Peak memory | 183708 kb |
| Host | smart-f199cdb6-52e4-4c47-ba45-0759a8e0940f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875656335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2875656335 |
| Directory | /workspace/42.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.hmac_intr_test.3837575283 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 75129052 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:18:40 PM PST 24 |
| Finished | Mar 05 01:18:41 PM PST 24 |
| Peak memory | 183772 kb |
| Host | smart-d515ac93-3a77-40ad-a3d5-a544db63492a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837575283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3837575283 |
| Directory | /workspace/43.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.hmac_intr_test.1140190607 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 113048717 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:18:36 PM PST 24 |
| Finished | Mar 05 01:18:37 PM PST 24 |
| Peak memory | 183720 kb |
| Host | smart-f8ebf154-4068-4012-a9b7-bbf59557d6b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140190607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1140190607 |
| Directory | /workspace/44.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.hmac_intr_test.4203030469 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 75030347 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:18:39 PM PST 24 |
| Finished | Mar 05 01:18:39 PM PST 24 |
| Peak memory | 183668 kb |
| Host | smart-380f74f7-956a-4778-aa1d-0c3b9de8fb07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203030469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.4203030469 |
| Directory | /workspace/45.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.hmac_intr_test.715881322 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 85457376 ps |
| CPU time | 0.63 seconds |
| Started | Mar 05 01:18:33 PM PST 24 |
| Finished | Mar 05 01:18:33 PM PST 24 |
| Peak memory | 183716 kb |
| Host | smart-6df94ad4-e294-46d3-a089-50e336286ba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715881322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.715881322 |
| Directory | /workspace/46.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.hmac_intr_test.617507896 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 28417406 ps |
| CPU time | 0.58 seconds |
| Started | Mar 05 01:18:40 PM PST 24 |
| Finished | Mar 05 01:18:41 PM PST 24 |
| Peak memory | 183672 kb |
| Host | smart-d7cbdee7-97bc-4dce-82f5-62c53d2306e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617507896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.617507896 |
| Directory | /workspace/47.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.hmac_intr_test.4042884239 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 18601771 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:18:33 PM PST 24 |
| Finished | Mar 05 01:18:33 PM PST 24 |
| Peak memory | 183800 kb |
| Host | smart-0b76b558-3cd8-432a-a164-f1fefbdd4be8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042884239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.4042884239 |
| Directory | /workspace/48.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.hmac_intr_test.1663687161 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 15064389 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:18:29 PM PST 24 |
| Finished | Mar 05 01:18:30 PM PST 24 |
| Peak memory | 183712 kb |
| Host | smart-d1829a10-da54-467d-8791-3224946870e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663687161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1663687161 |
| Directory | /workspace/49.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.358510027 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 41914086 ps |
| CPU time | 1.2 seconds |
| Started | Mar 05 01:18:11 PM PST 24 |
| Finished | Mar 05 01:18:12 PM PST 24 |
| Peak memory | 198432 kb |
| Host | smart-4a2e8224-0182-4848-ac41-0b20abcd7468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358510027 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.358510027 |
| Directory | /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2085463219 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 18517964 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:18:11 PM PST 24 |
| Finished | Mar 05 01:18:12 PM PST 24 |
| Peak memory | 194096 kb |
| Host | smart-a8117803-4bf7-47c2-a696-40429868cfb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085463219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2085463219 |
| Directory | /workspace/5.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.hmac_intr_test.2552811370 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 14360782 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:18:15 PM PST 24 |
| Finished | Mar 05 01:18:16 PM PST 24 |
| Peak memory | 183720 kb |
| Host | smart-acc5efcc-4c39-42b0-b677-2cb04faa3d27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552811370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2552811370 |
| Directory | /workspace/5.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.397772038 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 119472088 ps |
| CPU time | 1.33 seconds |
| Started | Mar 05 01:18:11 PM PST 24 |
| Finished | Mar 05 01:18:13 PM PST 24 |
| Peak memory | 192132 kb |
| Host | smart-9baae4a8-0c27-4b66-a8b8-9f9761e8aa48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397772038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_ outstanding.397772038 |
| Directory | /workspace/5.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4233062032 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 400938543 ps |
| CPU time | 1.72 seconds |
| Started | Mar 05 01:18:10 PM PST 24 |
| Finished | Mar 05 01:18:12 PM PST 24 |
| Peak memory | 198556 kb |
| Host | smart-057dded5-fbc2-4f0a-91ca-84af696da1c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233062032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.4233062032 |
| Directory | /workspace/5.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3396345632 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 110596654 ps |
| CPU time | 1.82 seconds |
| Started | Mar 05 01:18:17 PM PST 24 |
| Finished | Mar 05 01:18:20 PM PST 24 |
| Peak memory | 198176 kb |
| Host | smart-b7bf7235-e238-4a44-b2ee-ac0d8fc691bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396345632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3396345632 |
| Directory | /workspace/5.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.784090472 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 433679530 ps |
| CPU time | 2.04 seconds |
| Started | Mar 05 01:18:11 PM PST 24 |
| Finished | Mar 05 01:18:14 PM PST 24 |
| Peak memory | 198628 kb |
| Host | smart-5b1b1871-e3e5-40f0-a96d-588c0dff3f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784090472 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.784090472 |
| Directory | /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3133600092 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 18675394 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 01:18:10 PM PST 24 |
| Finished | Mar 05 01:18:10 PM PST 24 |
| Peak memory | 194416 kb |
| Host | smart-b59564ef-3060-499e-b013-48d915f9c639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133600092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3133600092 |
| Directory | /workspace/6.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.hmac_intr_test.3691959796 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 37636968 ps |
| CPU time | 0.59 seconds |
| Started | Mar 05 01:18:09 PM PST 24 |
| Finished | Mar 05 01:18:10 PM PST 24 |
| Peak memory | 183720 kb |
| Host | smart-4e66bc73-647c-470a-a67b-4272165a890e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691959796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3691959796 |
| Directory | /workspace/6.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3847911556 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 22991474 ps |
| CPU time | 0.97 seconds |
| Started | Mar 05 01:18:20 PM PST 24 |
| Finished | Mar 05 01:18:21 PM PST 24 |
| Peak memory | 192104 kb |
| Host | smart-a303035f-4dcc-4eca-aa84-b2b92d416042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847911556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr _outstanding.3847911556 |
| Directory | /workspace/6.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1157270217 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 119443175 ps |
| CPU time | 2.69 seconds |
| Started | Mar 05 01:18:17 PM PST 24 |
| Finished | Mar 05 01:18:21 PM PST 24 |
| Peak memory | 198560 kb |
| Host | smart-a5cfcbc8-96c8-41d2-8586-b601ee9cc532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157270217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1157270217 |
| Directory | /workspace/6.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.70623310 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 351927596 ps |
| CPU time | 1.98 seconds |
| Started | Mar 05 01:18:07 PM PST 24 |
| Finished | Mar 05 01:18:09 PM PST 24 |
| Peak memory | 198508 kb |
| Host | smart-97ff8e6d-b015-4977-8ec9-20ca41875020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70623310 -assert nopostproc +UVM_TESTNAME=h mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.70623310 |
| Directory | /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.hmac_csr_rw.548903620 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 101936235 ps |
| CPU time | 0.75 seconds |
| Started | Mar 05 01:18:11 PM PST 24 |
| Finished | Mar 05 01:18:12 PM PST 24 |
| Peak memory | 194664 kb |
| Host | smart-5172f822-d599-4829-9ada-44461fea82f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548903620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.548903620 |
| Directory | /workspace/7.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.hmac_intr_test.3251394045 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 14503703 ps |
| CPU time | 0.54 seconds |
| Started | Mar 05 01:18:10 PM PST 24 |
| Finished | Mar 05 01:18:10 PM PST 24 |
| Peak memory | 183764 kb |
| Host | smart-8b883cec-813c-4a53-a4fc-e15c2ee12a95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251394045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3251394045 |
| Directory | /workspace/7.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2057900674 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 185209182 ps |
| CPU time | 0.85 seconds |
| Started | Mar 05 01:18:15 PM PST 24 |
| Finished | Mar 05 01:18:17 PM PST 24 |
| Peak memory | 191956 kb |
| Host | smart-814433ab-4e57-47c2-9455-dc847da94ebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057900674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr _outstanding.2057900674 |
| Directory | /workspace/7.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3815800398 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 36150908 ps |
| CPU time | 1.9 seconds |
| Started | Mar 05 01:18:11 PM PST 24 |
| Finished | Mar 05 01:18:13 PM PST 24 |
| Peak memory | 198560 kb |
| Host | smart-7beb4abc-7676-448c-bee7-70b20f5ca089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815800398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3815800398 |
| Directory | /workspace/7.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3160497437 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 427400102 ps |
| CPU time | 1.81 seconds |
| Started | Mar 05 01:18:12 PM PST 24 |
| Finished | Mar 05 01:18:14 PM PST 24 |
| Peak memory | 198208 kb |
| Host | smart-69c9810b-5e63-4a29-bdd0-da47fedb1d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160497437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3160497437 |
| Directory | /workspace/7.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.801551825 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 78555616 ps |
| CPU time | 1.24 seconds |
| Started | Mar 05 01:18:15 PM PST 24 |
| Finished | Mar 05 01:18:16 PM PST 24 |
| Peak memory | 198440 kb |
| Host | smart-576c8f9c-36c0-4690-9c3d-161574039fb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801551825 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.801551825 |
| Directory | /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3770140529 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 32407009 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:18:13 PM PST 24 |
| Finished | Mar 05 01:18:15 PM PST 24 |
| Peak memory | 194152 kb |
| Host | smart-001eb7f1-e7ce-4a25-912e-61104fb95650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770140529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3770140529 |
| Directory | /workspace/8.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.hmac_intr_test.3502454238 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 11157169 ps |
| CPU time | 0.58 seconds |
| Started | Mar 05 01:18:15 PM PST 24 |
| Finished | Mar 05 01:18:16 PM PST 24 |
| Peak memory | 183720 kb |
| Host | smart-f5e3d375-9070-4436-ba5f-9bb7ff8095e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502454238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3502454238 |
| Directory | /workspace/8.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3313425468 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 190753041 ps |
| CPU time | 1.1 seconds |
| Started | Mar 05 01:18:19 PM PST 24 |
| Finished | Mar 05 01:18:20 PM PST 24 |
| Peak memory | 196392 kb |
| Host | smart-8aa9ee7a-7fc5-4792-8089-63f30fba6b43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313425468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr _outstanding.3313425468 |
| Directory | /workspace/8.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.hmac_tl_errors.773358113 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 79679281 ps |
| CPU time | 1.19 seconds |
| Started | Mar 05 01:18:12 PM PST 24 |
| Finished | Mar 05 01:18:13 PM PST 24 |
| Peak memory | 198620 kb |
| Host | smart-e7f6326e-eb1d-4716-9d21-2187ffffd62b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773358113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.773358113 |
| Directory | /workspace/8.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.583034605 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 102277623 ps |
| CPU time | 1.7 seconds |
| Started | Mar 05 01:18:19 PM PST 24 |
| Finished | Mar 05 01:18:22 PM PST 24 |
| Peak memory | 198000 kb |
| Host | smart-b913c152-4ec4-4347-8786-f6053a00f1d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583034605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.583034605 |
| Directory | /workspace/8.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2391497038 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 52511699 ps |
| CPU time | 2.85 seconds |
| Started | Mar 05 01:18:19 PM PST 24 |
| Finished | Mar 05 01:18:22 PM PST 24 |
| Peak memory | 198568 kb |
| Host | smart-2dcb85ab-5b4f-4def-914e-26b74d547ce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391497038 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2391497038 |
| Directory | /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2553542500 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 23725088 ps |
| CPU time | 0.72 seconds |
| Started | Mar 05 01:18:18 PM PST 24 |
| Finished | Mar 05 01:18:19 PM PST 24 |
| Peak memory | 194628 kb |
| Host | smart-9787942f-6e8e-41ae-acbf-e19d60f13725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553542500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2553542500 |
| Directory | /workspace/9.hmac_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.hmac_intr_test.1402147694 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 37801622 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:18:20 PM PST 24 |
| Finished | Mar 05 01:18:21 PM PST 24 |
| Peak memory | 183664 kb |
| Host | smart-6d9e6be3-0a9a-4aaa-bcd3-8d32ba18e304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402147694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1402147694 |
| Directory | /workspace/9.hmac_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2689311791 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 229091625 ps |
| CPU time | 1.31 seconds |
| Started | Mar 05 01:18:14 PM PST 24 |
| Finished | Mar 05 01:18:16 PM PST 24 |
| Peak memory | 192200 kb |
| Host | smart-2b64246f-69ca-474c-b0b6-201279d21405 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689311791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr _outstanding.2689311791 |
| Directory | /workspace/9.hmac_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1917950846 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 186014071 ps |
| CPU time | 2.19 seconds |
| Started | Mar 05 01:18:09 PM PST 24 |
| Finished | Mar 05 01:18:12 PM PST 24 |
| Peak memory | 198584 kb |
| Host | smart-97c86493-9bfa-4a51-8e31-2d0323c53d2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917950846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1917950846 |
| Directory | /workspace/9.hmac_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.723187252 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 486195349 ps |
| CPU time | 1.74 seconds |
| Started | Mar 05 01:18:18 PM PST 24 |
| Finished | Mar 05 01:18:21 PM PST 24 |
| Peak memory | 198144 kb |
| Host | smart-cb57775f-dd22-411c-b661-044b16f19925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723187252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.723187252 |
| Directory | /workspace/9.hmac_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.hmac_back_pressure.3320770326 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 440639737 ps |
| CPU time | 14.81 seconds |
| Started | Mar 05 01:09:49 PM PST 24 |
| Finished | Mar 05 01:10:07 PM PST 24 |
| Peak memory | 214316 kb |
| Host | smart-03f140ef-b954-44cc-8b97-d01028e79e41 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3320770326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3320770326 |
| Directory | /workspace/0.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/0.hmac_burst_wr.3576166387 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 7473294903 ps |
| CPU time | 51.51 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:10:46 PM PST 24 |
| Peak memory | 199008 kb |
| Host | smart-068a3cdd-072a-44ba-b893-37cd9531a3d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3576166387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3576166387 |
| Directory | /workspace/0.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/0.hmac_datapath_stress.3218977561 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1976030240 ps |
| CPU time | 67.51 seconds |
| Started | Mar 05 01:09:50 PM PST 24 |
| Finished | Mar 05 01:11:00 PM PST 24 |
| Peak memory | 198944 kb |
| Host | smart-b7b6bacc-2cf7-4d7d-9eb9-73d2286d8b28 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3218977561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3218977561 |
| Directory | /workspace/0.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/0.hmac_error.1633188667 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 13240008755 ps |
| CPU time | 53.79 seconds |
| Started | Mar 05 01:09:49 PM PST 24 |
| Finished | Mar 05 01:10:46 PM PST 24 |
| Peak memory | 199012 kb |
| Host | smart-f2485a9b-3422-4be3-87fb-8488ead7e648 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633188667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1633188667 |
| Directory | /workspace/0.hmac_error/latest |
| Test location | /workspace/coverage/default/0.hmac_long_msg.48045852 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 3519339435 ps |
| CPU time | 45.26 seconds |
| Started | Mar 05 01:09:47 PM PST 24 |
| Finished | Mar 05 01:10:33 PM PST 24 |
| Peak memory | 199200 kb |
| Host | smart-099503fc-7af2-4843-8732-73591403f932 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48045852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.48045852 |
| Directory | /workspace/0.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/0.hmac_sec_cm.3320754361 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 37889333 ps |
| CPU time | 0.79 seconds |
| Started | Mar 05 01:09:51 PM PST 24 |
| Finished | Mar 05 01:09:53 PM PST 24 |
| Peak memory | 216224 kb |
| Host | smart-ea10cfe2-c1cf-425e-85c7-852d1f3e5f83 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320754361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3320754361 |
| Directory | /workspace/0.hmac_sec_cm/latest |
| Test location | /workspace/coverage/default/0.hmac_smoke.2777671682 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 506340795 ps |
| CPU time | 3.55 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:58 PM PST 24 |
| Peak memory | 198892 kb |
| Host | smart-135cb4ea-3e2e-4c3a-90fa-561a16e3d31c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777671682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2777671682 |
| Directory | /workspace/0.hmac_smoke/latest |
| Test location | /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1515590923 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 26923559375 ps |
| CPU time | 415.33 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:16:48 PM PST 24 |
| Peak memory | 223804 kb |
| Host | smart-48dd39a3-4a66-46fa-b974-1eae80f67c19 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1515590923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1515590923 |
| Directory | /workspace/0.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.hmac_test_hmac_vectors.248090825 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 53831785 ps |
| CPU time | 1.02 seconds |
| Started | Mar 05 01:09:49 PM PST 24 |
| Finished | Mar 05 01:09:53 PM PST 24 |
| Peak memory | 197652 kb |
| Host | smart-c84be875-a8e4-468d-bb7e-3a63a1db966c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248090825 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.hmac_test_hmac_vectors.248090825 |
| Directory | /workspace/0.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/0.hmac_test_sha_vectors.3501098927 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 61687199579 ps |
| CPU time | 392.61 seconds |
| Started | Mar 05 01:09:51 PM PST 24 |
| Finished | Mar 05 01:16:25 PM PST 24 |
| Peak memory | 198992 kb |
| Host | smart-edea5f05-35a7-43b8-a8b4-5a6ee3e7b9f6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501098927 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.hmac_test_sha_vectors.3501098927 |
| Directory | /workspace/0.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/0.hmac_wipe_secret.2104135679 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 707219082 ps |
| CPU time | 11.48 seconds |
| Started | Mar 05 01:09:49 PM PST 24 |
| Finished | Mar 05 01:10:03 PM PST 24 |
| Peak memory | 198932 kb |
| Host | smart-f5c62a40-3331-418a-918c-f986bd6775c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104135679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2104135679 |
| Directory | /workspace/0.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/1.hmac_alert_test.2035205187 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 23120025 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:55 PM PST 24 |
| Peak memory | 193288 kb |
| Host | smart-2a442e03-c811-415e-9980-b63f3cb7890b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035205187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2035205187 |
| Directory | /workspace/1.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/1.hmac_back_pressure.3813027122 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 614156447 ps |
| CPU time | 5.29 seconds |
| Started | Mar 05 01:09:47 PM PST 24 |
| Finished | Mar 05 01:09:53 PM PST 24 |
| Peak memory | 198920 kb |
| Host | smart-8e4bbbdd-b470-430c-9efd-c84399920f83 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3813027122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3813027122 |
| Directory | /workspace/1.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/1.hmac_burst_wr.4165245556 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1619313395 ps |
| CPU time | 25.15 seconds |
| Started | Mar 05 01:09:48 PM PST 24 |
| Finished | Mar 05 01:10:15 PM PST 24 |
| Peak memory | 198968 kb |
| Host | smart-e6290f69-b9a1-4fc6-9bd8-35fdd4a2d8ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165245556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.4165245556 |
| Directory | /workspace/1.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/1.hmac_error.2101939507 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3460700933 ps |
| CPU time | 41.04 seconds |
| Started | Mar 05 01:09:50 PM PST 24 |
| Finished | Mar 05 01:10:33 PM PST 24 |
| Peak memory | 198960 kb |
| Host | smart-45bdd7eb-52b3-410d-8ec4-0279950557f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2101939507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2101939507 |
| Directory | /workspace/1.hmac_error/latest |
| Test location | /workspace/coverage/default/1.hmac_long_msg.2830995886 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 33196352700 ps |
| CPU time | 104.79 seconds |
| Started | Mar 05 01:09:50 PM PST 24 |
| Finished | Mar 05 01:11:37 PM PST 24 |
| Peak memory | 199004 kb |
| Host | smart-0395d7a4-6b3f-4856-b5ba-e165dfda7433 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830995886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2830995886 |
| Directory | /workspace/1.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/1.hmac_smoke.3561411031 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 598926595 ps |
| CPU time | 3.71 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:09:59 PM PST 24 |
| Peak memory | 198916 kb |
| Host | smart-46b03352-ddda-46ae-a9e1-18ca633726fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561411031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3561411031 |
| Directory | /workspace/1.hmac_smoke/latest |
| Test location | /workspace/coverage/default/1.hmac_test_hmac_vectors.836661560 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 271825091 ps |
| CPU time | 1.3 seconds |
| Started | Mar 05 01:09:48 PM PST 24 |
| Finished | Mar 05 01:09:51 PM PST 24 |
| Peak memory | 197440 kb |
| Host | smart-5143db9e-2716-41f1-b959-ddff1e125ecf |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836661560 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.hmac_test_hmac_vectors.836661560 |
| Directory | /workspace/1.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/1.hmac_test_sha_vectors.443017576 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 39212787984 ps |
| CPU time | 334.28 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:15:29 PM PST 24 |
| Peak memory | 198940 kb |
| Host | smart-cca17ca0-d4e6-4350-9c81-935ee1058520 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443017576 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.hmac_test_sha_vectors.443017576 |
| Directory | /workspace/1.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/1.hmac_wipe_secret.3246605619 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 4024459925 ps |
| CPU time | 42.16 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:10:35 PM PST 24 |
| Peak memory | 199056 kb |
| Host | smart-93c966c3-6e56-4e46-9ffb-19907e4a12cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3246605619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3246605619 |
| Directory | /workspace/1.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/10.hmac_alert_test.3876026596 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 12738203 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:09:56 PM PST 24 |
| Peak memory | 193636 kb |
| Host | smart-17e92cc5-664a-4402-a768-b00c236e4e4e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876026596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3876026596 |
| Directory | /workspace/10.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/10.hmac_back_pressure.2555511561 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1470957065 ps |
| CPU time | 11.81 seconds |
| Started | Mar 05 01:09:51 PM PST 24 |
| Finished | Mar 05 01:10:04 PM PST 24 |
| Peak memory | 215352 kb |
| Host | smart-a71f678a-b607-49e7-9257-bd49c74f819f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2555511561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2555511561 |
| Directory | /workspace/10.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/10.hmac_datapath_stress.713683321 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 41462754562 ps |
| CPU time | 141.64 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:12:19 PM PST 24 |
| Peak memory | 199116 kb |
| Host | smart-cc4c01bd-bc15-4caf-814f-a64b3c245ccc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=713683321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.713683321 |
| Directory | /workspace/10.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/10.hmac_error.1178334914 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 19229077239 ps |
| CPU time | 108.33 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:11:43 PM PST 24 |
| Peak memory | 199096 kb |
| Host | smart-c4885181-e5d7-4548-8d1c-4f3dab0a570a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178334914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1178334914 |
| Directory | /workspace/10.hmac_error/latest |
| Test location | /workspace/coverage/default/10.hmac_long_msg.43035685 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3916936788 ps |
| CPU time | 66.25 seconds |
| Started | Mar 05 01:09:58 PM PST 24 |
| Finished | Mar 05 01:11:05 PM PST 24 |
| Peak memory | 199132 kb |
| Host | smart-3cf13b39-5c30-43ce-a79c-c29103026042 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43035685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.43035685 |
| Directory | /workspace/10.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/10.hmac_smoke.600387012 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 36047962 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:09:52 PM PST 24 |
| Finished | Mar 05 01:09:58 PM PST 24 |
| Peak memory | 198100 kb |
| Host | smart-ffbf17ce-e84e-4fd5-a142-1db4cfba26d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=600387012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.600387012 |
| Directory | /workspace/10.hmac_smoke/latest |
| Test location | /workspace/coverage/default/10.hmac_stress_all.2602321366 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 7453579468 ps |
| CPU time | 58.14 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:10:52 PM PST 24 |
| Peak memory | 199124 kb |
| Host | smart-287be1a0-e0e4-40dc-ab06-fcfc1d644a0a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602321366 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2602321366 |
| Directory | /workspace/10.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/10.hmac_test_hmac_vectors.2695791820 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 155700129 ps |
| CPU time | 0.9 seconds |
| Started | Mar 05 01:10:04 PM PST 24 |
| Finished | Mar 05 01:10:06 PM PST 24 |
| Peak memory | 197072 kb |
| Host | smart-62192cd1-bb55-4419-9bd6-daa6206785b9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695791820 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.hmac_test_hmac_vectors.2695791820 |
| Directory | /workspace/10.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/10.hmac_test_sha_vectors.1184403980 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 15993068486 ps |
| CPU time | 405.77 seconds |
| Started | Mar 05 01:09:52 PM PST 24 |
| Finished | Mar 05 01:16:38 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-74a6a220-076f-4858-8a81-0ffcd2f0a140 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184403980 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 10.hmac_test_sha_vectors.1184403980 |
| Directory | /workspace/10.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/10.hmac_wipe_secret.595240757 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 14356445120 ps |
| CPU time | 83.03 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:11:17 PM PST 24 |
| Peak memory | 199116 kb |
| Host | smart-d287b5c9-bb3e-40dd-b8cf-3b33184de7cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=595240757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.595240757 |
| Directory | /workspace/10.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/11.hmac_alert_test.2621225811 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 47856395 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:10:05 PM PST 24 |
| Finished | Mar 05 01:10:07 PM PST 24 |
| Peak memory | 193688 kb |
| Host | smart-239bd17e-dc61-41fb-8674-f6ce46ff6f9c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621225811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2621225811 |
| Directory | /workspace/11.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/11.hmac_back_pressure.2099736361 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2232487205 ps |
| CPU time | 18.68 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:10:13 PM PST 24 |
| Peak memory | 223604 kb |
| Host | smart-dbcb282d-3dc2-4af7-8da4-1ed120e36c44 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2099736361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2099736361 |
| Directory | /workspace/11.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/11.hmac_burst_wr.3809222191 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1841001886 ps |
| CPU time | 32.88 seconds |
| Started | Mar 05 01:09:57 PM PST 24 |
| Finished | Mar 05 01:10:31 PM PST 24 |
| Peak memory | 198916 kb |
| Host | smart-dd4276f3-7510-4661-8adc-5613eb24f1af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809222191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3809222191 |
| Directory | /workspace/11.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/11.hmac_datapath_stress.2375116440 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 6989242488 ps |
| CPU time | 89.73 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:11:25 PM PST 24 |
| Peak memory | 199084 kb |
| Host | smart-8c61f42f-8bc7-43a6-907d-46e47b37b904 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2375116440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2375116440 |
| Directory | /workspace/11.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/11.hmac_error.3151505720 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 10550985643 ps |
| CPU time | 125.1 seconds |
| Started | Mar 05 01:10:02 PM PST 24 |
| Finished | Mar 05 01:12:07 PM PST 24 |
| Peak memory | 199140 kb |
| Host | smart-385a3058-3d55-4746-9e42-5fb0455fd7e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3151505720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3151505720 |
| Directory | /workspace/11.hmac_error/latest |
| Test location | /workspace/coverage/default/11.hmac_long_msg.1272826877 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 6419002322 ps |
| CPU time | 80.7 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:11:18 PM PST 24 |
| Peak memory | 199084 kb |
| Host | smart-d62308c2-fd42-46d5-b1e3-0d99a0b67635 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272826877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1272826877 |
| Directory | /workspace/11.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/11.hmac_smoke.1419607213 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 390303584 ps |
| CPU time | 2.45 seconds |
| Started | Mar 05 01:09:58 PM PST 24 |
| Finished | Mar 05 01:10:01 PM PST 24 |
| Peak memory | 198764 kb |
| Host | smart-7cad6a09-f3b9-4ec5-8487-696ca27d4c7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419607213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1419607213 |
| Directory | /workspace/11.hmac_smoke/latest |
| Test location | /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.1269516507 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 173939312259 ps |
| CPU time | 1109.78 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:28:38 PM PST 24 |
| Peak memory | 248032 kb |
| Host | smart-e25f0cfb-3874-40e7-a990-324c2d3e4e78 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1269516507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.1269516507 |
| Directory | /workspace/11.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.hmac_test_hmac_vectors.1483731748 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 216883888 ps |
| CPU time | 1.21 seconds |
| Started | Mar 05 01:10:15 PM PST 24 |
| Finished | Mar 05 01:10:16 PM PST 24 |
| Peak memory | 197616 kb |
| Host | smart-1edab0d4-7fa4-472a-b94d-eecfde790747 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483731748 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.hmac_test_hmac_vectors.1483731748 |
| Directory | /workspace/11.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/11.hmac_test_sha_vectors.1749299722 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 41774662514 ps |
| CPU time | 479.44 seconds |
| Started | Mar 05 01:10:05 PM PST 24 |
| Finished | Mar 05 01:18:06 PM PST 24 |
| Peak memory | 199104 kb |
| Host | smart-9eddd375-b059-45bc-881d-ee2370cfdd14 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749299722 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 11.hmac_test_sha_vectors.1749299722 |
| Directory | /workspace/11.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/11.hmac_wipe_secret.4148593830 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1218856176 ps |
| CPU time | 21.72 seconds |
| Started | Mar 05 01:10:05 PM PST 24 |
| Finished | Mar 05 01:10:28 PM PST 24 |
| Peak memory | 199016 kb |
| Host | smart-121e7e9b-ba73-4df3-a37d-d999317f0b03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4148593830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.4148593830 |
| Directory | /workspace/11.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/12.hmac_alert_test.3238959643 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 68184776 ps |
| CPU time | 0.62 seconds |
| Started | Mar 05 01:10:05 PM PST 24 |
| Finished | Mar 05 01:10:07 PM PST 24 |
| Peak memory | 193688 kb |
| Host | smart-557216c0-3309-41b1-b1e8-ad6d3245be7b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238959643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3238959643 |
| Directory | /workspace/12.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/12.hmac_back_pressure.1920627690 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5632385939 ps |
| CPU time | 57.55 seconds |
| Started | Mar 05 01:10:09 PM PST 24 |
| Finished | Mar 05 01:11:07 PM PST 24 |
| Peak memory | 240048 kb |
| Host | smart-9c24f77d-a121-4422-9b53-4b1b4a06a99d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1920627690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1920627690 |
| Directory | /workspace/12.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/12.hmac_burst_wr.3307118622 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1236551495 ps |
| CPU time | 59.01 seconds |
| Started | Mar 05 01:10:09 PM PST 24 |
| Finished | Mar 05 01:11:08 PM PST 24 |
| Peak memory | 198972 kb |
| Host | smart-845c5235-7423-4000-a75c-d11b62c73d56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307118622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3307118622 |
| Directory | /workspace/12.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/12.hmac_datapath_stress.1263683860 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2398726164 ps |
| CPU time | 64.05 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:11:12 PM PST 24 |
| Peak memory | 199052 kb |
| Host | smart-cfba7231-a298-4376-a1e1-54b72594fa6d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1263683860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1263683860 |
| Directory | /workspace/12.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/12.hmac_error.1210376395 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 8227810269 ps |
| CPU time | 106.56 seconds |
| Started | Mar 05 01:09:58 PM PST 24 |
| Finished | Mar 05 01:11:45 PM PST 24 |
| Peak memory | 198976 kb |
| Host | smart-f1b770e8-718d-43e5-97a8-a6b78e201ddd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210376395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1210376395 |
| Directory | /workspace/12.hmac_error/latest |
| Test location | /workspace/coverage/default/12.hmac_long_msg.624348939 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 3504219974 ps |
| CPU time | 7.42 seconds |
| Started | Mar 05 01:10:04 PM PST 24 |
| Finished | Mar 05 01:10:13 PM PST 24 |
| Peak memory | 199080 kb |
| Host | smart-69f942ad-cedb-484a-be46-c8a1eaeb81b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624348939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.624348939 |
| Directory | /workspace/12.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/12.hmac_smoke.1802667042 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 119137402 ps |
| CPU time | 3.18 seconds |
| Started | Mar 05 01:10:03 PM PST 24 |
| Finished | Mar 05 01:10:07 PM PST 24 |
| Peak memory | 198880 kb |
| Host | smart-d9cd06ff-0724-4c53-bc5a-adc20cf2c832 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1802667042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1802667042 |
| Directory | /workspace/12.hmac_smoke/latest |
| Test location | /workspace/coverage/default/12.hmac_stress_all.2825510087 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 29295696642 ps |
| CPU time | 485 seconds |
| Started | Mar 05 01:10:09 PM PST 24 |
| Finished | Mar 05 01:18:14 PM PST 24 |
| Peak memory | 199116 kb |
| Host | smart-fe4bd084-8eb0-4864-966c-8cd8aef67cdf |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825510087 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2825510087 |
| Directory | /workspace/12.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/12.hmac_test_hmac_vectors.2017329292 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 158222864 ps |
| CPU time | 0.98 seconds |
| Started | Mar 05 01:10:14 PM PST 24 |
| Finished | Mar 05 01:10:15 PM PST 24 |
| Peak memory | 197664 kb |
| Host | smart-74fda166-e209-4a29-89ce-b2135b773e75 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017329292 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.hmac_test_hmac_vectors.2017329292 |
| Directory | /workspace/12.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/12.hmac_test_sha_vectors.921368680 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 79352827538 ps |
| CPU time | 416.95 seconds |
| Started | Mar 05 01:10:06 PM PST 24 |
| Finished | Mar 05 01:17:04 PM PST 24 |
| Peak memory | 198996 kb |
| Host | smart-6715e106-2373-49f5-8469-5ff23678abfd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921368680 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.hmac_test_sha_vectors.921368680 |
| Directory | /workspace/12.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/12.hmac_wipe_secret.3584679375 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 30243971054 ps |
| CPU time | 44.24 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:10:52 PM PST 24 |
| Peak memory | 199056 kb |
| Host | smart-15fe927f-7609-4353-96f7-82370865ecda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584679375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3584679375 |
| Directory | /workspace/12.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/13.hmac_alert_test.2602655179 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 35717702 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:10:09 PM PST 24 |
| Peak memory | 193368 kb |
| Host | smart-0de84390-05af-4e1a-a7fb-580f860e10cc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602655179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2602655179 |
| Directory | /workspace/13.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/13.hmac_back_pressure.472663318 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 530630566 ps |
| CPU time | 16.34 seconds |
| Started | Mar 05 01:10:10 PM PST 24 |
| Finished | Mar 05 01:10:27 PM PST 24 |
| Peak memory | 207088 kb |
| Host | smart-3d7a7942-7b10-4a06-859a-c9cd83692632 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=472663318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.472663318 |
| Directory | /workspace/13.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/13.hmac_burst_wr.3388833278 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 377060592 ps |
| CPU time | 16.5 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:10:25 PM PST 24 |
| Peak memory | 198928 kb |
| Host | smart-a557b942-7575-4502-8f03-b327accd0fb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388833278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3388833278 |
| Directory | /workspace/13.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/13.hmac_datapath_stress.951706565 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 392074418 ps |
| CPU time | 19.66 seconds |
| Started | Mar 05 01:10:14 PM PST 24 |
| Finished | Mar 05 01:10:34 PM PST 24 |
| Peak memory | 198932 kb |
| Host | smart-a912a2c6-5df9-4821-be36-3b2d11eb9262 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=951706565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.951706565 |
| Directory | /workspace/13.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/13.hmac_error.2880910029 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 16583694618 ps |
| CPU time | 123.02 seconds |
| Started | Mar 05 01:10:04 PM PST 24 |
| Finished | Mar 05 01:12:08 PM PST 24 |
| Peak memory | 198980 kb |
| Host | smart-bc2c299a-f53c-4e89-a1eb-15a04c3a31d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880910029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2880910029 |
| Directory | /workspace/13.hmac_error/latest |
| Test location | /workspace/coverage/default/13.hmac_long_msg.4074914126 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 8102129216 ps |
| CPU time | 113.44 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:12:01 PM PST 24 |
| Peak memory | 199020 kb |
| Host | smart-0db40493-9dd8-4ffb-a889-6b685cac21ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074914126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4074914126 |
| Directory | /workspace/13.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/13.hmac_smoke.3074526929 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 265960056 ps |
| CPU time | 3.76 seconds |
| Started | Mar 05 01:10:05 PM PST 24 |
| Finished | Mar 05 01:10:10 PM PST 24 |
| Peak memory | 198952 kb |
| Host | smart-503ccdf2-15fb-4814-8dc8-f4532019a44d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074526929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3074526929 |
| Directory | /workspace/13.hmac_smoke/latest |
| Test location | /workspace/coverage/default/13.hmac_test_hmac_vectors.1922161655 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 34347155 ps |
| CPU time | 1.16 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:10:09 PM PST 24 |
| Peak memory | 198056 kb |
| Host | smart-7a94ce57-5633-4d82-86c6-c79726bb330d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922161655 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.hmac_test_hmac_vectors.1922161655 |
| Directory | /workspace/13.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/13.hmac_test_sha_vectors.2117552085 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 119016508373 ps |
| CPU time | 479.92 seconds |
| Started | Mar 05 01:10:04 PM PST 24 |
| Finished | Mar 05 01:18:05 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-6edae634-9ec1-461b-9df7-46421a6b16d4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117552085 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 13.hmac_test_sha_vectors.2117552085 |
| Directory | /workspace/13.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/13.hmac_wipe_secret.2872156680 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 4067747989 ps |
| CPU time | 54.75 seconds |
| Started | Mar 05 01:10:04 PM PST 24 |
| Finished | Mar 05 01:11:00 PM PST 24 |
| Peak memory | 199000 kb |
| Host | smart-9149edd3-42b1-4a9f-93ae-e45401867e8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872156680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2872156680 |
| Directory | /workspace/13.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.2711380253 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 17049490924 ps |
| CPU time | 777.66 seconds |
| Started | Mar 05 01:11:48 PM PST 24 |
| Finished | Mar 05 01:24:46 PM PST 24 |
| Peak memory | 214744 kb |
| Host | smart-15ae376b-308c-456a-b501-908bdb9e4c55 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2711380253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.2711380253 |
| Directory | /workspace/131.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.hmac_alert_test.14465092 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 62291355 ps |
| CPU time | 0.58 seconds |
| Started | Mar 05 01:10:18 PM PST 24 |
| Finished | Mar 05 01:10:21 PM PST 24 |
| Peak memory | 193632 kb |
| Host | smart-3f9c0184-f410-45f4-a932-d82d8a31b60e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14465092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.14465092 |
| Directory | /workspace/14.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/14.hmac_back_pressure.2492742393 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 136655917 ps |
| CPU time | 1.45 seconds |
| Started | Mar 05 01:10:13 PM PST 24 |
| Finished | Mar 05 01:10:14 PM PST 24 |
| Peak memory | 198936 kb |
| Host | smart-a387d124-1f4a-45dd-b23a-32eacb9af885 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2492742393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2492742393 |
| Directory | /workspace/14.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/14.hmac_burst_wr.3233830145 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 716982748 ps |
| CPU time | 33.82 seconds |
| Started | Mar 05 01:10:19 PM PST 24 |
| Finished | Mar 05 01:10:56 PM PST 24 |
| Peak memory | 198912 kb |
| Host | smart-95e49422-b2e5-468a-8a15-9b0b4d401d3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233830145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3233830145 |
| Directory | /workspace/14.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/14.hmac_datapath_stress.3824133076 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 235833766 ps |
| CPU time | 12.65 seconds |
| Started | Mar 05 01:10:07 PM PST 24 |
| Finished | Mar 05 01:10:20 PM PST 24 |
| Peak memory | 198932 kb |
| Host | smart-5190ce37-4b94-4bdf-a18c-77ee75f54b47 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3824133076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3824133076 |
| Directory | /workspace/14.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/14.hmac_error.4042497744 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 20378397242 ps |
| CPU time | 116.89 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:12:05 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-81641f6f-7341-4429-9b75-42a8bd9dd503 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042497744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.4042497744 |
| Directory | /workspace/14.hmac_error/latest |
| Test location | /workspace/coverage/default/14.hmac_long_msg.4133049453 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 3778744336 ps |
| CPU time | 36.96 seconds |
| Started | Mar 05 01:10:07 PM PST 24 |
| Finished | Mar 05 01:10:45 PM PST 24 |
| Peak memory | 199032 kb |
| Host | smart-58bae25a-d009-4123-93cd-f8573069345d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133049453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.4133049453 |
| Directory | /workspace/14.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/14.hmac_smoke.1260828091 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 267089003 ps |
| CPU time | 3.68 seconds |
| Started | Mar 05 01:10:09 PM PST 24 |
| Finished | Mar 05 01:10:13 PM PST 24 |
| Peak memory | 198800 kb |
| Host | smart-b4f48153-354c-41d9-a621-e5a9ceb826e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1260828091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1260828091 |
| Directory | /workspace/14.hmac_smoke/latest |
| Test location | /workspace/coverage/default/14.hmac_stress_all.694505840 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 110116350594 ps |
| CPU time | 1143.3 seconds |
| Started | Mar 05 01:10:11 PM PST 24 |
| Finished | Mar 05 01:29:14 PM PST 24 |
| Peak memory | 215472 kb |
| Host | smart-85b82ab4-ea50-4488-aa7f-50131bbede69 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694505840 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.694505840 |
| Directory | /workspace/14.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/14.hmac_test_hmac_vectors.2139521098 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 105458401 ps |
| CPU time | 0.92 seconds |
| Started | Mar 05 01:10:24 PM PST 24 |
| Finished | Mar 05 01:10:27 PM PST 24 |
| Peak memory | 196468 kb |
| Host | smart-a763ba24-94ae-471a-a6ef-33780f6c9735 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139521098 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.hmac_test_hmac_vectors.2139521098 |
| Directory | /workspace/14.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/14.hmac_test_sha_vectors.1373899673 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 100292247946 ps |
| CPU time | 400.47 seconds |
| Started | Mar 05 01:10:01 PM PST 24 |
| Finished | Mar 05 01:16:42 PM PST 24 |
| Peak memory | 199032 kb |
| Host | smart-681995b4-3240-45c5-97b5-64a32d1ca24e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373899673 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 14.hmac_test_sha_vectors.1373899673 |
| Directory | /workspace/14.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/14.hmac_wipe_secret.585210859 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2824902535 ps |
| CPU time | 35.74 seconds |
| Started | Mar 05 01:10:17 PM PST 24 |
| Finished | Mar 05 01:10:56 PM PST 24 |
| Peak memory | 199028 kb |
| Host | smart-6d8ece71-ad2c-4a02-9ff8-16534100c117 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=585210859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.585210859 |
| Directory | /workspace/14.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/15.hmac_alert_test.1704593593 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 26125927 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:10:16 PM PST 24 |
| Finished | Mar 05 01:10:17 PM PST 24 |
| Peak memory | 193248 kb |
| Host | smart-09630708-c817-42a6-b3c2-ec24401e682a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704593593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1704593593 |
| Directory | /workspace/15.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/15.hmac_back_pressure.2585961300 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5785403756 ps |
| CPU time | 51.89 seconds |
| Started | Mar 05 01:10:06 PM PST 24 |
| Finished | Mar 05 01:10:59 PM PST 24 |
| Peak memory | 219332 kb |
| Host | smart-70fe55d5-65e4-475d-89d4-beb24df60d62 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2585961300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2585961300 |
| Directory | /workspace/15.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/15.hmac_burst_wr.2926600454 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 352590590 ps |
| CPU time | 3.76 seconds |
| Started | Mar 05 01:10:15 PM PST 24 |
| Finished | Mar 05 01:10:19 PM PST 24 |
| Peak memory | 198936 kb |
| Host | smart-6a26b205-c4e0-4cdf-8dc1-ec75a1bf7aa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926600454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2926600454 |
| Directory | /workspace/15.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/15.hmac_datapath_stress.2748165005 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 429388754 ps |
| CPU time | 22.71 seconds |
| Started | Mar 05 01:10:14 PM PST 24 |
| Finished | Mar 05 01:10:37 PM PST 24 |
| Peak memory | 198968 kb |
| Host | smart-845948f4-56b3-4910-9622-8a4eeb42dcf2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2748165005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2748165005 |
| Directory | /workspace/15.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/15.hmac_error.3516428574 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4021419372 ps |
| CPU time | 129.23 seconds |
| Started | Mar 05 01:10:17 PM PST 24 |
| Finished | Mar 05 01:12:28 PM PST 24 |
| Peak memory | 198940 kb |
| Host | smart-24e9a2bf-9a56-4fb4-a6ed-f00afc8f013c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516428574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3516428574 |
| Directory | /workspace/15.hmac_error/latest |
| Test location | /workspace/coverage/default/15.hmac_long_msg.1353848249 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2885836807 ps |
| CPU time | 18.06 seconds |
| Started | Mar 05 01:10:03 PM PST 24 |
| Finished | Mar 05 01:10:22 PM PST 24 |
| Peak memory | 199060 kb |
| Host | smart-61ecdb78-1b85-4a9f-8047-6ec9149f6244 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353848249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1353848249 |
| Directory | /workspace/15.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/15.hmac_smoke.733485355 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 728746563 ps |
| CPU time | 2.15 seconds |
| Started | Mar 05 01:10:04 PM PST 24 |
| Finished | Mar 05 01:10:07 PM PST 24 |
| Peak memory | 198900 kb |
| Host | smart-4b9dc0f1-9b5f-4ec7-9b3a-93ca1ae84f87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733485355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.733485355 |
| Directory | /workspace/15.hmac_smoke/latest |
| Test location | /workspace/coverage/default/15.hmac_stress_all.1106312335 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 32060337465 ps |
| CPU time | 521.11 seconds |
| Started | Mar 05 01:10:07 PM PST 24 |
| Finished | Mar 05 01:18:49 PM PST 24 |
| Peak memory | 199080 kb |
| Host | smart-1167a0aa-9052-47c5-87d8-508ad5658e9c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106312335 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1106312335 |
| Directory | /workspace/15.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/15.hmac_test_hmac_vectors.3874395189 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 106088708 ps |
| CPU time | 0.93 seconds |
| Started | Mar 05 01:10:14 PM PST 24 |
| Finished | Mar 05 01:10:15 PM PST 24 |
| Peak memory | 196380 kb |
| Host | smart-6d60b2a0-ac3d-4886-9df4-e063adbea450 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874395189 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.hmac_test_hmac_vectors.3874395189 |
| Directory | /workspace/15.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/15.hmac_test_sha_vectors.2934196886 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 8518956153 ps |
| CPU time | 450.89 seconds |
| Started | Mar 05 01:10:19 PM PST 24 |
| Finished | Mar 05 01:17:52 PM PST 24 |
| Peak memory | 198992 kb |
| Host | smart-b046ee53-9193-4ac5-ae91-5705d1f8d64b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934196886 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 15.hmac_test_sha_vectors.2934196886 |
| Directory | /workspace/15.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/15.hmac_wipe_secret.234661114 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4179451889 ps |
| CPU time | 71.05 seconds |
| Started | Mar 05 01:10:15 PM PST 24 |
| Finished | Mar 05 01:11:27 PM PST 24 |
| Peak memory | 199116 kb |
| Host | smart-7ac7fbfc-14bd-4677-8e28-9828d801b011 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234661114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.234661114 |
| Directory | /workspace/15.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/16.hmac_alert_test.2056479802 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 12106117 ps |
| CPU time | 0.68 seconds |
| Started | Mar 05 01:10:07 PM PST 24 |
| Finished | Mar 05 01:10:08 PM PST 24 |
| Peak memory | 193332 kb |
| Host | smart-2d0fb97d-d050-44de-a4dd-851f48940e48 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056479802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2056479802 |
| Directory | /workspace/16.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/16.hmac_back_pressure.2560580117 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3120266633 ps |
| CPU time | 23.39 seconds |
| Started | Mar 05 01:10:25 PM PST 24 |
| Finished | Mar 05 01:10:50 PM PST 24 |
| Peak memory | 214476 kb |
| Host | smart-b655a086-b803-457c-810e-4421e12e19fb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2560580117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2560580117 |
| Directory | /workspace/16.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/16.hmac_burst_wr.75285419 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 11457535063 ps |
| CPU time | 51.76 seconds |
| Started | Mar 05 01:10:10 PM PST 24 |
| Finished | Mar 05 01:11:02 PM PST 24 |
| Peak memory | 199016 kb |
| Host | smart-812c660a-1ba5-4fe7-9251-f1dc5bac7eb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75285419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.75285419 |
| Directory | /workspace/16.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/16.hmac_datapath_stress.2861781556 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1998348474 ps |
| CPU time | 55.16 seconds |
| Started | Mar 05 01:10:25 PM PST 24 |
| Finished | Mar 05 01:11:22 PM PST 24 |
| Peak memory | 198804 kb |
| Host | smart-1b986abc-f326-4ddb-9b89-7ba9e1d2ab4e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2861781556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2861781556 |
| Directory | /workspace/16.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/16.hmac_error.469948423 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 43608963152 ps |
| CPU time | 182.22 seconds |
| Started | Mar 05 01:10:09 PM PST 24 |
| Finished | Mar 05 01:13:11 PM PST 24 |
| Peak memory | 199064 kb |
| Host | smart-98e0829a-fc6d-475e-85b6-189decaef636 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=469948423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.469948423 |
| Directory | /workspace/16.hmac_error/latest |
| Test location | /workspace/coverage/default/16.hmac_long_msg.1612091138 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2227994235 ps |
| CPU time | 28.6 seconds |
| Started | Mar 05 01:10:17 PM PST 24 |
| Finished | Mar 05 01:10:49 PM PST 24 |
| Peak memory | 198880 kb |
| Host | smart-bef02abb-ef89-4b92-aabc-1555f9239610 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612091138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1612091138 |
| Directory | /workspace/16.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/16.hmac_smoke.3607948385 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 164035858 ps |
| CPU time | 1.29 seconds |
| Started | Mar 05 01:10:05 PM PST 24 |
| Finished | Mar 05 01:10:07 PM PST 24 |
| Peak memory | 198740 kb |
| Host | smart-c5b222d0-62b5-44b8-8499-77a42858944e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607948385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3607948385 |
| Directory | /workspace/16.hmac_smoke/latest |
| Test location | /workspace/coverage/default/16.hmac_stress_all.194385528 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2658356732 ps |
| CPU time | 112.49 seconds |
| Started | Mar 05 01:10:05 PM PST 24 |
| Finished | Mar 05 01:11:59 PM PST 24 |
| Peak memory | 231848 kb |
| Host | smart-d3d08397-39d2-43d3-bcc0-ef7af83f857c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194385528 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.194385528 |
| Directory | /workspace/16.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.2194890088 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 230931841083 ps |
| CPU time | 1627.93 seconds |
| Started | Mar 05 01:10:13 PM PST 24 |
| Finished | Mar 05 01:37:21 PM PST 24 |
| Peak memory | 244880 kb |
| Host | smart-86d4496b-7a0a-4c27-af1d-d834065925e0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2194890088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.2194890088 |
| Directory | /workspace/16.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.hmac_test_hmac_vectors.1632300519 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 219622155 ps |
| CPU time | 1.14 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:10:09 PM PST 24 |
| Peak memory | 197460 kb |
| Host | smart-9b157b06-0537-4c7a-81cf-f6705728fbb6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632300519 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.hmac_test_hmac_vectors.1632300519 |
| Directory | /workspace/16.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/16.hmac_test_sha_vectors.611326324 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 15528392938 ps |
| CPU time | 364.65 seconds |
| Started | Mar 05 01:10:14 PM PST 24 |
| Finished | Mar 05 01:16:19 PM PST 24 |
| Peak memory | 198940 kb |
| Host | smart-5e852e29-0e0f-4896-9f42-4e0e938d7707 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611326324 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 16.hmac_test_sha_vectors.611326324 |
| Directory | /workspace/16.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/16.hmac_wipe_secret.3546659404 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1985170900 ps |
| CPU time | 17.49 seconds |
| Started | Mar 05 01:10:13 PM PST 24 |
| Finished | Mar 05 01:10:30 PM PST 24 |
| Peak memory | 198992 kb |
| Host | smart-c52e2a87-2337-411e-81b4-c044256d21b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546659404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3546659404 |
| Directory | /workspace/16.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.2554210588 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7104980820 ps |
| CPU time | 132.68 seconds |
| Started | Mar 05 01:11:57 PM PST 24 |
| Finished | Mar 05 01:14:10 PM PST 24 |
| Peak memory | 214568 kb |
| Host | smart-3c7a3a9e-7373-448c-b3fb-df1ed6f3a1cb |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2554210588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.2554210588 |
| Directory | /workspace/165.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.hmac_alert_test.1209671698 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 42028375 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:10:12 PM PST 24 |
| Finished | Mar 05 01:10:12 PM PST 24 |
| Peak memory | 193392 kb |
| Host | smart-31a95629-b28f-4f83-a210-05fc91d0f913 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209671698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1209671698 |
| Directory | /workspace/17.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/17.hmac_back_pressure.1461241734 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 87796110 ps |
| CPU time | 3.63 seconds |
| Started | Mar 05 01:10:07 PM PST 24 |
| Finished | Mar 05 01:10:12 PM PST 24 |
| Peak memory | 215308 kb |
| Host | smart-e8424d75-2903-4dd3-9254-fb794a89a806 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1461241734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1461241734 |
| Directory | /workspace/17.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/17.hmac_burst_wr.3023282205 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4527048626 ps |
| CPU time | 43.02 seconds |
| Started | Mar 05 01:10:15 PM PST 24 |
| Finished | Mar 05 01:10:58 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-47ac75be-a1eb-48cd-bf32-fa112f69a0ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023282205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3023282205 |
| Directory | /workspace/17.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/17.hmac_datapath_stress.1007826495 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1011142858 ps |
| CPU time | 27.86 seconds |
| Started | Mar 05 01:10:09 PM PST 24 |
| Finished | Mar 05 01:10:37 PM PST 24 |
| Peak memory | 198988 kb |
| Host | smart-cd46d5c4-abb1-471b-9d76-68358ede8e6a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1007826495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1007826495 |
| Directory | /workspace/17.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/17.hmac_error.1956708719 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2450863200 ps |
| CPU time | 126.97 seconds |
| Started | Mar 05 01:10:07 PM PST 24 |
| Finished | Mar 05 01:12:15 PM PST 24 |
| Peak memory | 198984 kb |
| Host | smart-c1ede2aa-7590-4db8-9d77-035bdf5764ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1956708719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1956708719 |
| Directory | /workspace/17.hmac_error/latest |
| Test location | /workspace/coverage/default/17.hmac_long_msg.4133891632 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 523103930 ps |
| CPU time | 7.44 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:10:15 PM PST 24 |
| Peak memory | 198860 kb |
| Host | smart-5a3a91a3-f1bd-4239-8fb0-66641a26441e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133891632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4133891632 |
| Directory | /workspace/17.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/17.hmac_smoke.2395768865 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 26364423 ps |
| CPU time | 0.99 seconds |
| Started | Mar 05 01:10:03 PM PST 24 |
| Finished | Mar 05 01:10:05 PM PST 24 |
| Peak memory | 196392 kb |
| Host | smart-9c7fe50b-551e-4b7d-9e36-381f1cf42037 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2395768865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2395768865 |
| Directory | /workspace/17.hmac_smoke/latest |
| Test location | /workspace/coverage/default/17.hmac_stress_all.3635833338 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 170155035092 ps |
| CPU time | 560.33 seconds |
| Started | Mar 05 01:10:18 PM PST 24 |
| Finished | Mar 05 01:19:41 PM PST 24 |
| Peak memory | 235908 kb |
| Host | smart-5af46bdd-6dea-4f52-a80c-32904fc49ac7 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635833338 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3635833338 |
| Directory | /workspace/17.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/17.hmac_test_hmac_vectors.1536871586 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 75821786 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:10:06 PM PST 24 |
| Finished | Mar 05 01:10:08 PM PST 24 |
| Peak memory | 197988 kb |
| Host | smart-36359327-7dde-4b9d-9b0f-9a29793c651a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536871586 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.hmac_test_hmac_vectors.1536871586 |
| Directory | /workspace/17.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/17.hmac_test_sha_vectors.1480683045 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 8086372809 ps |
| CPU time | 412.27 seconds |
| Started | Mar 05 01:10:07 PM PST 24 |
| Finished | Mar 05 01:17:00 PM PST 24 |
| Peak memory | 199008 kb |
| Host | smart-aba29f14-6d9d-450d-b1d3-674426cbfad1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480683045 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 17.hmac_test_sha_vectors.1480683045 |
| Directory | /workspace/17.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/17.hmac_wipe_secret.1485209721 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1962580995 ps |
| CPU time | 66.41 seconds |
| Started | Mar 05 01:10:03 PM PST 24 |
| Finished | Mar 05 01:11:10 PM PST 24 |
| Peak memory | 198920 kb |
| Host | smart-af3b8e19-9b96-44dd-be71-44f206fe5bd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1485209721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1485209721 |
| Directory | /workspace/17.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/18.hmac_alert_test.3131239905 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 12521116 ps |
| CPU time | 0.58 seconds |
| Started | Mar 05 01:10:06 PM PST 24 |
| Finished | Mar 05 01:10:07 PM PST 24 |
| Peak memory | 193288 kb |
| Host | smart-748490a2-ac0f-47ae-8775-7ff93486ce7c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131239905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3131239905 |
| Directory | /workspace/18.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/18.hmac_back_pressure.1377882032 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1008577770 ps |
| CPU time | 32.93 seconds |
| Started | Mar 05 01:10:24 PM PST 24 |
| Finished | Mar 05 01:10:59 PM PST 24 |
| Peak memory | 198968 kb |
| Host | smart-757d086e-ac93-4e91-a475-60e72edd302b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1377882032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1377882032 |
| Directory | /workspace/18.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/18.hmac_burst_wr.876742984 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2233032697 ps |
| CPU time | 31.86 seconds |
| Started | Mar 05 01:10:06 PM PST 24 |
| Finished | Mar 05 01:10:39 PM PST 24 |
| Peak memory | 198976 kb |
| Host | smart-d6b248e3-1151-45e9-b720-d1c69e6aff9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=876742984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.876742984 |
| Directory | /workspace/18.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/18.hmac_datapath_stress.2511920879 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 428576993 ps |
| CPU time | 5.51 seconds |
| Started | Mar 05 01:10:21 PM PST 24 |
| Finished | Mar 05 01:10:29 PM PST 24 |
| Peak memory | 198960 kb |
| Host | smart-43b45aa4-4e4b-4154-a1dc-cea11b21b349 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2511920879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2511920879 |
| Directory | /workspace/18.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/18.hmac_error.4266294202 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5302222212 ps |
| CPU time | 87.51 seconds |
| Started | Mar 05 01:10:26 PM PST 24 |
| Finished | Mar 05 01:11:54 PM PST 24 |
| Peak memory | 199044 kb |
| Host | smart-7a006050-d690-4371-86bf-832d88670d00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266294202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4266294202 |
| Directory | /workspace/18.hmac_error/latest |
| Test location | /workspace/coverage/default/18.hmac_long_msg.2984860031 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 5466806066 ps |
| CPU time | 89.38 seconds |
| Started | Mar 05 01:10:07 PM PST 24 |
| Finished | Mar 05 01:11:37 PM PST 24 |
| Peak memory | 199044 kb |
| Host | smart-29ccc4aa-746c-4afe-82d5-92b9721fce28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984860031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2984860031 |
| Directory | /workspace/18.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/18.hmac_smoke.469322891 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 17820011 ps |
| CPU time | 0.77 seconds |
| Started | Mar 05 01:10:17 PM PST 24 |
| Finished | Mar 05 01:10:20 PM PST 24 |
| Peak memory | 195792 kb |
| Host | smart-ddc69f89-c012-40f1-9c4c-3514318c12b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=469322891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.469322891 |
| Directory | /workspace/18.hmac_smoke/latest |
| Test location | /workspace/coverage/default/18.hmac_stress_all.13659777 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2398613331595 ps |
| CPU time | 2061.62 seconds |
| Started | Mar 05 01:10:15 PM PST 24 |
| Finished | Mar 05 01:44:37 PM PST 24 |
| Peak memory | 207292 kb |
| Host | smart-a17c9d12-6a64-42ac-9c74-0465fef89419 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13659777 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.13659777 |
| Directory | /workspace/18.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/18.hmac_test_hmac_vectors.316263152 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 110390690 ps |
| CPU time | 1.19 seconds |
| Started | Mar 05 01:10:02 PM PST 24 |
| Finished | Mar 05 01:10:04 PM PST 24 |
| Peak memory | 197964 kb |
| Host | smart-5da36164-fd30-455a-bb46-6eba8301b8d0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316263152 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 18.hmac_test_hmac_vectors.316263152 |
| Directory | /workspace/18.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/18.hmac_test_sha_vectors.2245412194 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 33599915025 ps |
| CPU time | 436.55 seconds |
| Started | Mar 05 01:10:23 PM PST 24 |
| Finished | Mar 05 01:17:42 PM PST 24 |
| Peak memory | 199060 kb |
| Host | smart-c5bf6fe1-0e5a-4eef-9efd-45133ae900c2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245412194 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 18.hmac_test_sha_vectors.2245412194 |
| Directory | /workspace/18.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/18.hmac_wipe_secret.3265812067 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 7566750322 ps |
| CPU time | 70.34 seconds |
| Started | Mar 05 01:10:11 PM PST 24 |
| Finished | Mar 05 01:11:21 PM PST 24 |
| Peak memory | 198988 kb |
| Host | smart-b207183e-362e-483b-901d-6ca178c104f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3265812067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3265812067 |
| Directory | /workspace/18.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/19.hmac_alert_test.2768384723 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 54165579 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:10:15 PM PST 24 |
| Finished | Mar 05 01:10:16 PM PST 24 |
| Peak memory | 193392 kb |
| Host | smart-84f1c5d2-b7fc-4137-b8e9-cda4df518ce3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768384723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2768384723 |
| Directory | /workspace/19.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/19.hmac_back_pressure.3907773139 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1155499660 ps |
| CPU time | 37.19 seconds |
| Started | Mar 05 01:10:16 PM PST 24 |
| Finished | Mar 05 01:10:54 PM PST 24 |
| Peak memory | 224468 kb |
| Host | smart-e2bead9b-ef29-45f3-9b13-9557b276b431 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3907773139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3907773139 |
| Directory | /workspace/19.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/19.hmac_burst_wr.1831619529 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 8984772227 ps |
| CPU time | 17.74 seconds |
| Started | Mar 05 01:10:10 PM PST 24 |
| Finished | Mar 05 01:10:28 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-3fa0ab75-83d7-4810-a14a-e23f50d7984f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831619529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1831619529 |
| Directory | /workspace/19.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/19.hmac_datapath_stress.4133247450 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 6263140109 ps |
| CPU time | 86.04 seconds |
| Started | Mar 05 01:10:05 PM PST 24 |
| Finished | Mar 05 01:11:33 PM PST 24 |
| Peak memory | 199048 kb |
| Host | smart-f4ffed9f-4e89-46b6-b16c-9768ede41651 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4133247450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4133247450 |
| Directory | /workspace/19.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/19.hmac_error.2744714504 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4614460590 ps |
| CPU time | 114.78 seconds |
| Started | Mar 05 01:10:24 PM PST 24 |
| Finished | Mar 05 01:12:21 PM PST 24 |
| Peak memory | 198924 kb |
| Host | smart-67196240-61b6-4664-91ae-fc781a5db90a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2744714504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2744714504 |
| Directory | /workspace/19.hmac_error/latest |
| Test location | /workspace/coverage/default/19.hmac_long_msg.3807457446 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 7158217146 ps |
| CPU time | 33.31 seconds |
| Started | Mar 05 01:10:08 PM PST 24 |
| Finished | Mar 05 01:10:41 PM PST 24 |
| Peak memory | 199076 kb |
| Host | smart-a14d6e85-d5d9-4f70-9fdf-2891c6ce069d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807457446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3807457446 |
| Directory | /workspace/19.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/19.hmac_smoke.3215382715 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 115802786 ps |
| CPU time | 2.82 seconds |
| Started | Mar 05 01:10:12 PM PST 24 |
| Finished | Mar 05 01:10:15 PM PST 24 |
| Peak memory | 198924 kb |
| Host | smart-5a98f6c7-8554-4ba2-8003-590b0d836a33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3215382715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3215382715 |
| Directory | /workspace/19.hmac_smoke/latest |
| Test location | /workspace/coverage/default/19.hmac_stress_all.2428806975 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 158601930966 ps |
| CPU time | 1054.65 seconds |
| Started | Mar 05 01:10:29 PM PST 24 |
| Finished | Mar 05 01:28:04 PM PST 24 |
| Peak memory | 223612 kb |
| Host | smart-3154a980-0ada-42aa-8afe-726d1076b4e9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428806975 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2428806975 |
| Directory | /workspace/19.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/19.hmac_test_hmac_vectors.1759842711 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 71853900 ps |
| CPU time | 1.15 seconds |
| Started | Mar 05 01:10:23 PM PST 24 |
| Finished | Mar 05 01:10:26 PM PST 24 |
| Peak memory | 197400 kb |
| Host | smart-2c206819-8344-4119-84a2-05e8c2ca56f3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759842711 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.hmac_test_hmac_vectors.1759842711 |
| Directory | /workspace/19.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/19.hmac_test_sha_vectors.767354730 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 15372320950 ps |
| CPU time | 387.99 seconds |
| Started | Mar 05 01:10:24 PM PST 24 |
| Finished | Mar 05 01:16:54 PM PST 24 |
| Peak memory | 198892 kb |
| Host | smart-83bfa820-0033-4dc1-b560-bcb6973476be |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767354730 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.hmac_test_sha_vectors.767354730 |
| Directory | /workspace/19.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/19.hmac_wipe_secret.3667230699 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 42317019 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 01:10:18 PM PST 24 |
| Finished | Mar 05 01:10:21 PM PST 24 |
| Peak memory | 194344 kb |
| Host | smart-ab4d5191-8f47-40e8-9054-cdace5c4ca24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667230699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3667230699 |
| Directory | /workspace/19.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.284320166 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 384499912358 ps |
| CPU time | 2349.83 seconds |
| Started | Mar 05 01:12:11 PM PST 24 |
| Finished | Mar 05 01:51:22 PM PST 24 |
| Peak memory | 251452 kb |
| Host | smart-a77f3c5b-f735-42c4-9412-ea95d932a2a5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=284320166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.284320166 |
| Directory | /workspace/199.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.hmac_alert_test.2515293252 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 15222291 ps |
| CPU time | 0.59 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:09:59 PM PST 24 |
| Peak memory | 193224 kb |
| Host | smart-052776e1-839c-45cd-91d2-78006c5d68cf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515293252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2515293252 |
| Directory | /workspace/2.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/2.hmac_back_pressure.4133474011 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 240984709 ps |
| CPU time | 7.42 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:10:01 PM PST 24 |
| Peak memory | 198980 kb |
| Host | smart-5a88b999-7e7a-4c1b-be56-37e38367290b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4133474011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4133474011 |
| Directory | /workspace/2.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/2.hmac_burst_wr.4163376896 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1460626564 ps |
| CPU time | 6.12 seconds |
| Started | Mar 05 01:09:50 PM PST 24 |
| Finished | Mar 05 01:09:58 PM PST 24 |
| Peak memory | 198860 kb |
| Host | smart-80203698-822d-4eea-bd18-fc07decd0709 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163376896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.4163376896 |
| Directory | /workspace/2.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/2.hmac_datapath_stress.2245860503 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 6871890817 ps |
| CPU time | 95.42 seconds |
| Started | Mar 05 01:09:49 PM PST 24 |
| Finished | Mar 05 01:11:27 PM PST 24 |
| Peak memory | 199044 kb |
| Host | smart-f4f26cbd-276d-4525-84d9-57ce9252331f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2245860503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2245860503 |
| Directory | /workspace/2.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/2.hmac_error.1594067940 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1302007592 ps |
| CPU time | 65.77 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:11:03 PM PST 24 |
| Peak memory | 198988 kb |
| Host | smart-d558cc0b-644d-442a-b859-106b349d06d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594067940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1594067940 |
| Directory | /workspace/2.hmac_error/latest |
| Test location | /workspace/coverage/default/2.hmac_long_msg.3073122383 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2697050547 ps |
| CPU time | 48.92 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:10:46 PM PST 24 |
| Peak memory | 199080 kb |
| Host | smart-84ddc78f-cbee-4ea1-a6c3-c3b18c085db9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073122383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3073122383 |
| Directory | /workspace/2.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/2.hmac_sec_cm.823288247 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 241127618 ps |
| CPU time | 0.87 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:09:57 PM PST 24 |
| Peak memory | 216372 kb |
| Host | smart-1b89fc19-0444-456c-864c-c45c741d503f |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823288247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.823288247 |
| Directory | /workspace/2.hmac_sec_cm/latest |
| Test location | /workspace/coverage/default/2.hmac_smoke.1643892651 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 469451506 ps |
| CPU time | 3.09 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:57 PM PST 24 |
| Peak memory | 198816 kb |
| Host | smart-b9f21705-59cc-426f-98fd-f632bde909ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643892651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1643892651 |
| Directory | /workspace/2.hmac_smoke/latest |
| Test location | /workspace/coverage/default/2.hmac_stress_all.1054268355 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 248800140739 ps |
| CPU time | 725.44 seconds |
| Started | Mar 05 01:09:49 PM PST 24 |
| Finished | Mar 05 01:21:57 PM PST 24 |
| Peak memory | 208284 kb |
| Host | smart-256a89da-b550-49fa-8526-2cc2407aff48 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054268355 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1054268355 |
| Directory | /workspace/2.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/2.hmac_test_hmac_vectors.3398340132 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 278268929 ps |
| CPU time | 1.12 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:55 PM PST 24 |
| Peak memory | 197464 kb |
| Host | smart-9a129fc1-7b09-43f0-a41c-95a065e94b20 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398340132 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.hmac_test_hmac_vectors.3398340132 |
| Directory | /workspace/2.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/2.hmac_test_sha_vectors.2061331944 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 28585587895 ps |
| CPU time | 465.88 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:17:41 PM PST 24 |
| Peak memory | 199032 kb |
| Host | smart-c2b1e5ec-14b2-46cd-befc-c9d2f27608ab |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061331944 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.hmac_test_sha_vectors.2061331944 |
| Directory | /workspace/2.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/2.hmac_wipe_secret.1010113817 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 7940045425 ps |
| CPU time | 13.62 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:10:09 PM PST 24 |
| Peak memory | 199088 kb |
| Host | smart-d2097ade-4aea-4e99-9ad7-1cf07c0ad1fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1010113817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1010113817 |
| Directory | /workspace/2.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/20.hmac_alert_test.961613181 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 13728257 ps |
| CPU time | 0.59 seconds |
| Started | Mar 05 01:10:20 PM PST 24 |
| Finished | Mar 05 01:10:24 PM PST 24 |
| Peak memory | 193640 kb |
| Host | smart-97b94227-384e-4c34-9aa3-985451b7c12f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961613181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.961613181 |
| Directory | /workspace/20.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/20.hmac_back_pressure.2558348445 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 6597265679 ps |
| CPU time | 52.63 seconds |
| Started | Mar 05 01:10:21 PM PST 24 |
| Finished | Mar 05 01:11:17 PM PST 24 |
| Peak memory | 231128 kb |
| Host | smart-b126ccdf-5d3b-4944-87dc-c266e5849958 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2558348445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2558348445 |
| Directory | /workspace/20.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/20.hmac_burst_wr.2714519003 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3542446354 ps |
| CPU time | 28.94 seconds |
| Started | Mar 05 01:10:25 PM PST 24 |
| Finished | Mar 05 01:10:55 PM PST 24 |
| Peak memory | 198996 kb |
| Host | smart-d197384f-b6d9-49db-83db-9ecb692e2855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714519003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2714519003 |
| Directory | /workspace/20.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/20.hmac_datapath_stress.3808433243 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2501717407 ps |
| CPU time | 31.41 seconds |
| Started | Mar 05 01:10:25 PM PST 24 |
| Finished | Mar 05 01:10:58 PM PST 24 |
| Peak memory | 199048 kb |
| Host | smart-93c4c889-a87b-474b-b03c-98b835856e82 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3808433243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3808433243 |
| Directory | /workspace/20.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/20.hmac_error.3701815616 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3666232864 ps |
| CPU time | 87.08 seconds |
| Started | Mar 05 01:10:23 PM PST 24 |
| Finished | Mar 05 01:11:53 PM PST 24 |
| Peak memory | 199048 kb |
| Host | smart-e2c17439-c7de-4824-a4f4-2c28cfe784f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3701815616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3701815616 |
| Directory | /workspace/20.hmac_error/latest |
| Test location | /workspace/coverage/default/20.hmac_long_msg.128467170 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 5910575087 ps |
| CPU time | 84.26 seconds |
| Started | Mar 05 01:10:24 PM PST 24 |
| Finished | Mar 05 01:11:51 PM PST 24 |
| Peak memory | 198972 kb |
| Host | smart-4ce432fd-1f20-4056-a9ba-f8080166589b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=128467170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.128467170 |
| Directory | /workspace/20.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/20.hmac_smoke.785863656 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 317272956 ps |
| CPU time | 1.57 seconds |
| Started | Mar 05 01:10:14 PM PST 24 |
| Finished | Mar 05 01:10:16 PM PST 24 |
| Peak memory | 198888 kb |
| Host | smart-c06e042f-d4bb-4035-8caf-b326dd4faa3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785863656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.785863656 |
| Directory | /workspace/20.hmac_smoke/latest |
| Test location | /workspace/coverage/default/20.hmac_test_hmac_vectors.1573212384 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 41289311 ps |
| CPU time | 0.9 seconds |
| Started | Mar 05 01:10:10 PM PST 24 |
| Finished | Mar 05 01:10:11 PM PST 24 |
| Peak memory | 196732 kb |
| Host | smart-3d8bb06b-1c90-49c9-9ce4-66bd6c193be6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573212384 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.hmac_test_hmac_vectors.1573212384 |
| Directory | /workspace/20.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/20.hmac_test_sha_vectors.1625136719 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 39199274583 ps |
| CPU time | 417.16 seconds |
| Started | Mar 05 01:10:23 PM PST 24 |
| Finished | Mar 05 01:17:22 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-309427f5-ad88-498f-8a69-6b1f67e59dba |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625136719 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 20.hmac_test_sha_vectors.1625136719 |
| Directory | /workspace/20.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/20.hmac_wipe_secret.3170864757 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1185435216 ps |
| CPU time | 44.09 seconds |
| Started | Mar 05 01:10:25 PM PST 24 |
| Finished | Mar 05 01:11:11 PM PST 24 |
| Peak memory | 198872 kb |
| Host | smart-acde7336-3bda-4135-a64c-39cd1a1ed274 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170864757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3170864757 |
| Directory | /workspace/20.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/21.hmac_alert_test.3852497484 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 31699531 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:10:24 PM PST 24 |
| Finished | Mar 05 01:10:26 PM PST 24 |
| Peak memory | 193248 kb |
| Host | smart-e9d63bd9-d7ff-42bf-9e34-900a868665f1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852497484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3852497484 |
| Directory | /workspace/21.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/21.hmac_back_pressure.2169150121 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 128595764 ps |
| CPU time | 3.9 seconds |
| Started | Mar 05 01:10:11 PM PST 24 |
| Finished | Mar 05 01:10:16 PM PST 24 |
| Peak memory | 198940 kb |
| Host | smart-16e1084d-7269-4891-87e1-5028b9123143 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2169150121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2169150121 |
| Directory | /workspace/21.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/21.hmac_burst_wr.958060790 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 763910353 ps |
| CPU time | 11.36 seconds |
| Started | Mar 05 01:10:23 PM PST 24 |
| Finished | Mar 05 01:10:37 PM PST 24 |
| Peak memory | 198864 kb |
| Host | smart-d3dd3210-39f9-4376-a23c-9736089542fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958060790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.958060790 |
| Directory | /workspace/21.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/21.hmac_datapath_stress.307950521 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 125478630 ps |
| CPU time | 6.41 seconds |
| Started | Mar 05 01:10:22 PM PST 24 |
| Finished | Mar 05 01:10:31 PM PST 24 |
| Peak memory | 198880 kb |
| Host | smart-8faf3dff-29f0-430b-8200-eaad8d6a0407 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=307950521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.307950521 |
| Directory | /workspace/21.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/21.hmac_error.2133131379 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2240189935 ps |
| CPU time | 36.37 seconds |
| Started | Mar 05 01:10:22 PM PST 24 |
| Finished | Mar 05 01:11:01 PM PST 24 |
| Peak memory | 198924 kb |
| Host | smart-71c3ff01-5834-4173-9688-425b514072a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2133131379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2133131379 |
| Directory | /workspace/21.hmac_error/latest |
| Test location | /workspace/coverage/default/21.hmac_long_msg.933829776 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3199479659 ps |
| CPU time | 42.6 seconds |
| Started | Mar 05 01:10:25 PM PST 24 |
| Finished | Mar 05 01:11:09 PM PST 24 |
| Peak memory | 198912 kb |
| Host | smart-46af7946-5ec0-4901-bcb6-96b920500fdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933829776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.933829776 |
| Directory | /workspace/21.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/21.hmac_smoke.2574228805 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 66403992 ps |
| CPU time | 0.65 seconds |
| Started | Mar 05 01:10:18 PM PST 24 |
| Finished | Mar 05 01:10:21 PM PST 24 |
| Peak memory | 194840 kb |
| Host | smart-484dc177-f405-4255-9bb0-c12502bd100f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574228805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2574228805 |
| Directory | /workspace/21.hmac_smoke/latest |
| Test location | /workspace/coverage/default/21.hmac_test_hmac_vectors.3137441369 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 54486919 ps |
| CPU time | 0.93 seconds |
| Started | Mar 05 01:10:21 PM PST 24 |
| Finished | Mar 05 01:10:25 PM PST 24 |
| Peak memory | 196748 kb |
| Host | smart-6eae1399-69a7-4ab9-be70-d789ee4a9194 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137441369 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.hmac_test_hmac_vectors.3137441369 |
| Directory | /workspace/21.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/21.hmac_test_sha_vectors.3039875763 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 23519381242 ps |
| CPU time | 375.63 seconds |
| Started | Mar 05 01:10:25 PM PST 24 |
| Finished | Mar 05 01:16:42 PM PST 24 |
| Peak memory | 198964 kb |
| Host | smart-3b328516-81db-4df3-85e8-23537cd2a146 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039875763 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 21.hmac_test_sha_vectors.3039875763 |
| Directory | /workspace/21.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/21.hmac_wipe_secret.739846254 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1260430851 ps |
| CPU time | 38.81 seconds |
| Started | Mar 05 01:10:22 PM PST 24 |
| Finished | Mar 05 01:11:04 PM PST 24 |
| Peak memory | 198880 kb |
| Host | smart-ff9a04e1-7aac-4b7e-8ee8-b1538c6f1bc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739846254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.739846254 |
| Directory | /workspace/21.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/22.hmac_alert_test.460307873 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 14337813 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:10:13 PM PST 24 |
| Finished | Mar 05 01:10:13 PM PST 24 |
| Peak memory | 193616 kb |
| Host | smart-48e14960-f907-4a96-830f-ca0be4d33011 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460307873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.460307873 |
| Directory | /workspace/22.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/22.hmac_back_pressure.4196076365 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 765061709 ps |
| CPU time | 11.31 seconds |
| Started | Mar 05 01:10:24 PM PST 24 |
| Finished | Mar 05 01:10:37 PM PST 24 |
| Peak memory | 207096 kb |
| Host | smart-1538cf2b-6321-464f-8b2b-4bfb8cb240fd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4196076365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.4196076365 |
| Directory | /workspace/22.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/22.hmac_burst_wr.587528290 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 543225722 ps |
| CPU time | 24.95 seconds |
| Started | Mar 05 01:10:18 PM PST 24 |
| Finished | Mar 05 01:10:45 PM PST 24 |
| Peak memory | 198940 kb |
| Host | smart-6c63d3b5-3478-4e4c-8d92-eb8dc8e789d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=587528290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.587528290 |
| Directory | /workspace/22.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/22.hmac_datapath_stress.1249070021 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3627585974 ps |
| CPU time | 98.75 seconds |
| Started | Mar 05 01:10:20 PM PST 24 |
| Finished | Mar 05 01:12:00 PM PST 24 |
| Peak memory | 199012 kb |
| Host | smart-7bca0d6c-f046-4168-bec9-af56800b3108 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1249070021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1249070021 |
| Directory | /workspace/22.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/22.hmac_error.3119983669 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 13567559134 ps |
| CPU time | 60.55 seconds |
| Started | Mar 05 01:10:19 PM PST 24 |
| Finished | Mar 05 01:11:21 PM PST 24 |
| Peak memory | 199024 kb |
| Host | smart-03d5fec4-352d-4fa5-8f61-6f0e18e05d3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119983669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3119983669 |
| Directory | /workspace/22.hmac_error/latest |
| Test location | /workspace/coverage/default/22.hmac_long_msg.1509237375 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5355581040 ps |
| CPU time | 99.07 seconds |
| Started | Mar 05 01:10:24 PM PST 24 |
| Finished | Mar 05 01:12:05 PM PST 24 |
| Peak memory | 199000 kb |
| Host | smart-b885e18a-79b6-4d45-b2ae-4c3810d82210 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1509237375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1509237375 |
| Directory | /workspace/22.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/22.hmac_smoke.3911980277 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 93497528 ps |
| CPU time | 1.41 seconds |
| Started | Mar 05 01:10:25 PM PST 24 |
| Finished | Mar 05 01:10:28 PM PST 24 |
| Peak memory | 198820 kb |
| Host | smart-f6479a7c-4104-4f8b-9be9-03e1567c1148 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911980277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3911980277 |
| Directory | /workspace/22.hmac_smoke/latest |
| Test location | /workspace/coverage/default/22.hmac_stress_all.3328241292 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 44956933101 ps |
| CPU time | 573.6 seconds |
| Started | Mar 05 01:10:15 PM PST 24 |
| Finished | Mar 05 01:19:49 PM PST 24 |
| Peak memory | 199052 kb |
| Host | smart-e587549c-2ef4-4c0a-8db6-ab9aa9635c50 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328241292 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3328241292 |
| Directory | /workspace/22.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/22.hmac_test_hmac_vectors.1597902098 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 29076531 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:10:19 PM PST 24 |
| Finished | Mar 05 01:10:23 PM PST 24 |
| Peak memory | 197264 kb |
| Host | smart-3c96ed4a-f472-4821-82db-68b41e841844 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597902098 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.hmac_test_hmac_vectors.1597902098 |
| Directory | /workspace/22.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/22.hmac_test_sha_vectors.3098696653 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 29318063540 ps |
| CPU time | 482.8 seconds |
| Started | Mar 05 01:10:24 PM PST 24 |
| Finished | Mar 05 01:18:29 PM PST 24 |
| Peak memory | 198984 kb |
| Host | smart-3cd2b1a3-1fa6-4a80-97dc-7e7243c304db |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098696653 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 22.hmac_test_sha_vectors.3098696653 |
| Directory | /workspace/22.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/22.hmac_wipe_secret.1467229435 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 12751250023 ps |
| CPU time | 54.54 seconds |
| Started | Mar 05 01:10:19 PM PST 24 |
| Finished | Mar 05 01:11:17 PM PST 24 |
| Peak memory | 199028 kb |
| Host | smart-7841831c-fc6a-46ad-86c1-887e9286aea9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1467229435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1467229435 |
| Directory | /workspace/22.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/23.hmac_alert_test.1840755175 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 15811560 ps |
| CPU time | 0.58 seconds |
| Started | Mar 05 01:10:27 PM PST 24 |
| Finished | Mar 05 01:10:28 PM PST 24 |
| Peak memory | 194416 kb |
| Host | smart-f7874f11-7b1d-4312-b2b3-8cfeb37efa05 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840755175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1840755175 |
| Directory | /workspace/23.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/23.hmac_back_pressure.173000110 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1683075169 ps |
| CPU time | 16.04 seconds |
| Started | Mar 05 01:10:15 PM PST 24 |
| Finished | Mar 05 01:10:31 PM PST 24 |
| Peak memory | 211336 kb |
| Host | smart-8c7981fe-e0fc-4816-8fc3-9bbddf8e1b0c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=173000110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.173000110 |
| Directory | /workspace/23.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/23.hmac_burst_wr.1263799288 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 7041005398 ps |
| CPU time | 24.64 seconds |
| Started | Mar 05 01:10:28 PM PST 24 |
| Finished | Mar 05 01:10:54 PM PST 24 |
| Peak memory | 199012 kb |
| Host | smart-488d6b87-66d8-432b-9a5b-b5d30f82ca4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1263799288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1263799288 |
| Directory | /workspace/23.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/23.hmac_datapath_stress.1279972978 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 319849162 ps |
| CPU time | 16.77 seconds |
| Started | Mar 05 01:10:17 PM PST 24 |
| Finished | Mar 05 01:10:37 PM PST 24 |
| Peak memory | 198880 kb |
| Host | smart-61dfe6cc-7863-4885-8062-64cc0c4bc993 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1279972978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1279972978 |
| Directory | /workspace/23.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/23.hmac_error.1661355221 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 25930911883 ps |
| CPU time | 80.21 seconds |
| Started | Mar 05 01:10:20 PM PST 24 |
| Finished | Mar 05 01:11:44 PM PST 24 |
| Peak memory | 199100 kb |
| Host | smart-34b728dd-dc83-4473-ad18-0a7fafcd3b9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661355221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1661355221 |
| Directory | /workspace/23.hmac_error/latest |
| Test location | /workspace/coverage/default/23.hmac_long_msg.68984672 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5689424451 ps |
| CPU time | 69.51 seconds |
| Started | Mar 05 01:10:21 PM PST 24 |
| Finished | Mar 05 01:11:34 PM PST 24 |
| Peak memory | 199044 kb |
| Host | smart-d941afe0-2293-4061-be7f-ece86706e064 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68984672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.68984672 |
| Directory | /workspace/23.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/23.hmac_smoke.3653396791 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 140175822 ps |
| CPU time | 3.32 seconds |
| Started | Mar 05 01:10:19 PM PST 24 |
| Finished | Mar 05 01:10:24 PM PST 24 |
| Peak memory | 198916 kb |
| Host | smart-0090ebec-c6e7-49a5-87e1-1985b1f7024f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653396791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3653396791 |
| Directory | /workspace/23.hmac_smoke/latest |
| Test location | /workspace/coverage/default/23.hmac_stress_all.603617857 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 28439834171 ps |
| CPU time | 1384.73 seconds |
| Started | Mar 05 01:10:17 PM PST 24 |
| Finished | Mar 05 01:33:23 PM PST 24 |
| Peak memory | 199140 kb |
| Host | smart-1568e064-8b9e-4780-bbf2-02fae937f32d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603617857 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.603617857 |
| Directory | /workspace/23.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/23.hmac_test_hmac_vectors.200326102 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 150124261 ps |
| CPU time | 0.92 seconds |
| Started | Mar 05 01:10:27 PM PST 24 |
| Finished | Mar 05 01:10:29 PM PST 24 |
| Peak memory | 197188 kb |
| Host | smart-23cd0577-f720-426b-a291-e5e20987a922 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200326102 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 23.hmac_test_hmac_vectors.200326102 |
| Directory | /workspace/23.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/23.hmac_test_sha_vectors.298456520 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 39250497427 ps |
| CPU time | 448.24 seconds |
| Started | Mar 05 01:10:31 PM PST 24 |
| Finished | Mar 05 01:17:59 PM PST 24 |
| Peak memory | 198932 kb |
| Host | smart-77fe32e6-4d07-4686-91fe-c540f4a93886 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298456520 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 23.hmac_test_sha_vectors.298456520 |
| Directory | /workspace/23.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/23.hmac_wipe_secret.602211137 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2550169952 ps |
| CPU time | 45.93 seconds |
| Started | Mar 05 01:10:21 PM PST 24 |
| Finished | Mar 05 01:11:10 PM PST 24 |
| Peak memory | 198992 kb |
| Host | smart-d3924ca5-1299-4248-aba1-1e2d7dd80d0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=602211137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.602211137 |
| Directory | /workspace/23.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/24.hmac_alert_test.721755180 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 13166682 ps |
| CPU time | 0.59 seconds |
| Started | Mar 05 01:10:19 PM PST 24 |
| Finished | Mar 05 01:10:22 PM PST 24 |
| Peak memory | 193640 kb |
| Host | smart-11f44d62-b2c5-49da-9bfe-52b3cca7be30 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721755180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.721755180 |
| Directory | /workspace/24.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/24.hmac_back_pressure.1482255632 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 544789820 ps |
| CPU time | 19.43 seconds |
| Started | Mar 05 01:10:20 PM PST 24 |
| Finished | Mar 05 01:10:42 PM PST 24 |
| Peak memory | 231720 kb |
| Host | smart-22d5cb62-39bd-4054-a0f0-826d7a1fb6bb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1482255632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1482255632 |
| Directory | /workspace/24.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/24.hmac_burst_wr.403905726 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 5700022454 ps |
| CPU time | 31.22 seconds |
| Started | Mar 05 01:10:20 PM PST 24 |
| Finished | Mar 05 01:10:54 PM PST 24 |
| Peak memory | 199060 kb |
| Host | smart-71c943c1-de23-497e-9d10-89382a6b2a1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403905726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.403905726 |
| Directory | /workspace/24.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/24.hmac_datapath_stress.4076125006 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1568219739 ps |
| CPU time | 80.37 seconds |
| Started | Mar 05 01:10:20 PM PST 24 |
| Finished | Mar 05 01:11:42 PM PST 24 |
| Peak memory | 198928 kb |
| Host | smart-e7ec7af8-de21-49e3-afb9-d1af16e9f99e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4076125006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4076125006 |
| Directory | /workspace/24.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/24.hmac_error.1503776123 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 923918483 ps |
| CPU time | 44.51 seconds |
| Started | Mar 05 01:10:29 PM PST 24 |
| Finished | Mar 05 01:11:14 PM PST 24 |
| Peak memory | 198932 kb |
| Host | smart-11f830bc-f6ee-4dba-a092-a9fdcd3939f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503776123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1503776123 |
| Directory | /workspace/24.hmac_error/latest |
| Test location | /workspace/coverage/default/24.hmac_long_msg.1673123296 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1870603073 ps |
| CPU time | 26.47 seconds |
| Started | Mar 05 01:10:22 PM PST 24 |
| Finished | Mar 05 01:10:51 PM PST 24 |
| Peak memory | 198884 kb |
| Host | smart-3a1d4c36-4ca8-4dab-b606-f00cf90f2f8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1673123296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1673123296 |
| Directory | /workspace/24.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/24.hmac_smoke.2844392563 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1066374897 ps |
| CPU time | 4.55 seconds |
| Started | Mar 05 01:10:21 PM PST 24 |
| Finished | Mar 05 01:10:28 PM PST 24 |
| Peak memory | 198872 kb |
| Host | smart-dbd231c4-c9ce-403a-8789-070dd4b8ee7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2844392563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2844392563 |
| Directory | /workspace/24.hmac_smoke/latest |
| Test location | /workspace/coverage/default/24.hmac_stress_all.822531285 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 48772202506 ps |
| CPU time | 560.61 seconds |
| Started | Mar 05 01:10:35 PM PST 24 |
| Finished | Mar 05 01:19:56 PM PST 24 |
| Peak memory | 218692 kb |
| Host | smart-9a9613b0-6456-4f77-891f-6f2c6a7a0e81 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822531285 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.822531285 |
| Directory | /workspace/24.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/24.hmac_test_hmac_vectors.694818051 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 175968470 ps |
| CPU time | 0.94 seconds |
| Started | Mar 05 01:10:33 PM PST 24 |
| Finished | Mar 05 01:10:35 PM PST 24 |
| Peak memory | 196876 kb |
| Host | smart-432367b3-e028-4871-9b1b-1dbffa672c0f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694818051 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 24.hmac_test_hmac_vectors.694818051 |
| Directory | /workspace/24.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/24.hmac_test_sha_vectors.3353978739 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7429541976 ps |
| CPU time | 362.04 seconds |
| Started | Mar 05 01:10:39 PM PST 24 |
| Finished | Mar 05 01:16:42 PM PST 24 |
| Peak memory | 199016 kb |
| Host | smart-9a66d2e1-c903-4fd0-9d1e-dd1c7e93b97d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353978739 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 24.hmac_test_sha_vectors.3353978739 |
| Directory | /workspace/24.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/24.hmac_wipe_secret.2480527625 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5769209946 ps |
| CPU time | 18.13 seconds |
| Started | Mar 05 01:10:17 PM PST 24 |
| Finished | Mar 05 01:10:35 PM PST 24 |
| Peak memory | 198956 kb |
| Host | smart-dbb38565-1386-4c22-aac3-d9990e3be7d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480527625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2480527625 |
| Directory | /workspace/24.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/25.hmac_alert_test.1152656573 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 21004615 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:10:33 PM PST 24 |
| Finished | Mar 05 01:10:34 PM PST 24 |
| Peak memory | 193336 kb |
| Host | smart-b6bc85d4-2994-4191-be34-744b05765806 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152656573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1152656573 |
| Directory | /workspace/25.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/25.hmac_back_pressure.2033958024 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1501471473 ps |
| CPU time | 41.6 seconds |
| Started | Mar 05 01:10:27 PM PST 24 |
| Finished | Mar 05 01:11:09 PM PST 24 |
| Peak memory | 223560 kb |
| Host | smart-2249cf59-7ee8-4e76-b1a1-2e90d4e76317 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2033958024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2033958024 |
| Directory | /workspace/25.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/25.hmac_burst_wr.3476872402 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2483984856 ps |
| CPU time | 45.99 seconds |
| Started | Mar 05 01:10:20 PM PST 24 |
| Finished | Mar 05 01:11:07 PM PST 24 |
| Peak memory | 199032 kb |
| Host | smart-62f040ec-8709-4467-a998-088d70d8e3a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3476872402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3476872402 |
| Directory | /workspace/25.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/25.hmac_datapath_stress.3921098633 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3899616815 ps |
| CPU time | 53.17 seconds |
| Started | Mar 05 01:10:30 PM PST 24 |
| Finished | Mar 05 01:11:24 PM PST 24 |
| Peak memory | 198972 kb |
| Host | smart-af3e504c-d842-42d9-8da9-bb5d40327b0c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3921098633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3921098633 |
| Directory | /workspace/25.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/25.hmac_error.2005272784 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 11577764737 ps |
| CPU time | 78.86 seconds |
| Started | Mar 05 01:10:36 PM PST 24 |
| Finished | Mar 05 01:11:55 PM PST 24 |
| Peak memory | 199052 kb |
| Host | smart-2c8a434a-69e0-4b25-96e5-60c55171ba44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005272784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2005272784 |
| Directory | /workspace/25.hmac_error/latest |
| Test location | /workspace/coverage/default/25.hmac_long_msg.235330999 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 19564417735 ps |
| CPU time | 88.32 seconds |
| Started | Mar 05 01:10:37 PM PST 24 |
| Finished | Mar 05 01:12:06 PM PST 24 |
| Peak memory | 199000 kb |
| Host | smart-98bcdf60-0d9c-4b95-bd2e-74594eb7d7c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235330999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.235330999 |
| Directory | /workspace/25.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/25.hmac_smoke.3938106594 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2806283100 ps |
| CPU time | 3.22 seconds |
| Started | Mar 05 01:10:21 PM PST 24 |
| Finished | Mar 05 01:10:27 PM PST 24 |
| Peak memory | 199020 kb |
| Host | smart-da807b26-a46e-45a5-aa7b-670f02be0d67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3938106594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3938106594 |
| Directory | /workspace/25.hmac_smoke/latest |
| Test location | /workspace/coverage/default/25.hmac_stress_all.2484095652 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 340907087815 ps |
| CPU time | 1436.08 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:34:43 PM PST 24 |
| Peak memory | 214828 kb |
| Host | smart-81163945-1ad4-4c09-b1cb-0668f14cd625 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484095652 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2484095652 |
| Directory | /workspace/25.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/25.hmac_test_hmac_vectors.4153047641 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 159334382 ps |
| CPU time | 1.03 seconds |
| Started | Mar 05 01:10:36 PM PST 24 |
| Finished | Mar 05 01:10:37 PM PST 24 |
| Peak memory | 196836 kb |
| Host | smart-8bc71fe4-9240-4fed-90f6-4d61eefa7f0b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153047641 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.hmac_test_hmac_vectors.4153047641 |
| Directory | /workspace/25.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/25.hmac_test_sha_vectors.2642651284 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 86771808424 ps |
| CPU time | 483.13 seconds |
| Started | Mar 05 01:10:22 PM PST 24 |
| Finished | Mar 05 01:18:28 PM PST 24 |
| Peak memory | 199080 kb |
| Host | smart-cf55f669-4c72-476d-92cd-4a4be2df30e3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642651284 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 25.hmac_test_sha_vectors.2642651284 |
| Directory | /workspace/25.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/25.hmac_wipe_secret.1276346231 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 52095334593 ps |
| CPU time | 76.42 seconds |
| Started | Mar 05 01:10:27 PM PST 24 |
| Finished | Mar 05 01:11:43 PM PST 24 |
| Peak memory | 199056 kb |
| Host | smart-cdf72c1e-7a7e-423f-9bf0-381d20cfd1d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276346231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1276346231 |
| Directory | /workspace/25.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/26.hmac_alert_test.2876452993 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 19091948 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:10:42 PM PST 24 |
| Finished | Mar 05 01:10:43 PM PST 24 |
| Peak memory | 194416 kb |
| Host | smart-4a816e2a-1b61-4d92-a1a5-666cb9ab0184 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876452993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2876452993 |
| Directory | /workspace/26.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/26.hmac_back_pressure.55815146 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 468549568 ps |
| CPU time | 16.25 seconds |
| Started | Mar 05 01:10:31 PM PST 24 |
| Finished | Mar 05 01:10:47 PM PST 24 |
| Peak memory | 207092 kb |
| Host | smart-dd6a54a3-5c29-441a-a4f3-e3f5dcac0506 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=55815146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.55815146 |
| Directory | /workspace/26.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/26.hmac_burst_wr.3612772101 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1592293411 ps |
| CPU time | 30.84 seconds |
| Started | Mar 05 01:10:31 PM PST 24 |
| Finished | Mar 05 01:11:02 PM PST 24 |
| Peak memory | 198836 kb |
| Host | smart-9f76e863-49d5-43b7-ada7-591ed3a32ce5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3612772101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3612772101 |
| Directory | /workspace/26.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/26.hmac_datapath_stress.1106016284 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 138768069 ps |
| CPU time | 7.66 seconds |
| Started | Mar 05 01:10:39 PM PST 24 |
| Finished | Mar 05 01:10:47 PM PST 24 |
| Peak memory | 198892 kb |
| Host | smart-342597bd-3137-40d0-8150-3848d9748409 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1106016284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1106016284 |
| Directory | /workspace/26.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/26.hmac_error.913744208 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 8713172641 ps |
| CPU time | 113.94 seconds |
| Started | Mar 05 01:10:20 PM PST 24 |
| Finished | Mar 05 01:12:17 PM PST 24 |
| Peak memory | 199116 kb |
| Host | smart-e79c75cb-d58c-4953-b8c4-1230dd1bc024 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=913744208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.913744208 |
| Directory | /workspace/26.hmac_error/latest |
| Test location | /workspace/coverage/default/26.hmac_long_msg.2682455234 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 78970839621 ps |
| CPU time | 102.25 seconds |
| Started | Mar 05 01:10:37 PM PST 24 |
| Finished | Mar 05 01:12:20 PM PST 24 |
| Peak memory | 198996 kb |
| Host | smart-af65f541-c19c-4beb-9475-3cb44d270b46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682455234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2682455234 |
| Directory | /workspace/26.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/26.hmac_smoke.1854193389 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 92000760 ps |
| CPU time | 2.4 seconds |
| Started | Mar 05 01:10:42 PM PST 24 |
| Finished | Mar 05 01:10:44 PM PST 24 |
| Peak memory | 198912 kb |
| Host | smart-d7bfef8a-8909-4ff5-8882-048fcc474d93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854193389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1854193389 |
| Directory | /workspace/26.hmac_smoke/latest |
| Test location | /workspace/coverage/default/26.hmac_stress_all.3157747736 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 45063566 ps |
| CPU time | 0.92 seconds |
| Started | Mar 05 01:10:34 PM PST 24 |
| Finished | Mar 05 01:10:36 PM PST 24 |
| Peak memory | 196392 kb |
| Host | smart-7da8c23b-3a06-441e-8437-3fb0217ca915 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157747736 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3157747736 |
| Directory | /workspace/26.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/26.hmac_test_hmac_vectors.4058287789 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 32699600 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:10:34 PM PST 24 |
| Finished | Mar 05 01:10:35 PM PST 24 |
| Peak memory | 197772 kb |
| Host | smart-6ca8eaab-450d-4aee-b3a5-9d45a3aef275 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058287789 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.hmac_test_hmac_vectors.4058287789 |
| Directory | /workspace/26.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/26.hmac_test_sha_vectors.2209857573 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 44183850181 ps |
| CPU time | 499.36 seconds |
| Started | Mar 05 01:10:31 PM PST 24 |
| Finished | Mar 05 01:18:50 PM PST 24 |
| Peak memory | 198972 kb |
| Host | smart-1eb7aae4-e641-4949-98c1-5b8089702b8a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209857573 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 26.hmac_test_sha_vectors.2209857573 |
| Directory | /workspace/26.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/26.hmac_wipe_secret.1926949134 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 51645365182 ps |
| CPU time | 40.84 seconds |
| Started | Mar 05 01:10:34 PM PST 24 |
| Finished | Mar 05 01:11:15 PM PST 24 |
| Peak memory | 199008 kb |
| Host | smart-52c9200f-315a-43cc-b064-61c962b6299a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926949134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1926949134 |
| Directory | /workspace/26.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/27.hmac_alert_test.3600877152 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 12427603 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:10:35 PM PST 24 |
| Finished | Mar 05 01:10:36 PM PST 24 |
| Peak memory | 193336 kb |
| Host | smart-9a4f945c-1233-48d3-aef3-22421d4760b9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600877152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3600877152 |
| Directory | /workspace/27.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/27.hmac_back_pressure.3246520846 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 696288413 ps |
| CPU time | 20.95 seconds |
| Started | Mar 05 01:10:34 PM PST 24 |
| Finished | Mar 05 01:10:55 PM PST 24 |
| Peak memory | 198932 kb |
| Host | smart-52d7107b-a610-40af-9615-07fb7709b0d3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3246520846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3246520846 |
| Directory | /workspace/27.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/27.hmac_burst_wr.1365974696 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1356570769 ps |
| CPU time | 66.12 seconds |
| Started | Mar 05 01:10:35 PM PST 24 |
| Finished | Mar 05 01:11:41 PM PST 24 |
| Peak memory | 198912 kb |
| Host | smart-e9a9dda6-9405-409b-89bb-f528beeed8f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365974696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1365974696 |
| Directory | /workspace/27.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/27.hmac_datapath_stress.3804185198 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2871805969 ps |
| CPU time | 38.07 seconds |
| Started | Mar 05 01:10:33 PM PST 24 |
| Finished | Mar 05 01:11:11 PM PST 24 |
| Peak memory | 198992 kb |
| Host | smart-7faba6ab-b030-4ca0-a6f2-6ffde4a0b1da |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3804185198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3804185198 |
| Directory | /workspace/27.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/27.hmac_error.3461651873 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 11024147883 ps |
| CPU time | 132.93 seconds |
| Started | Mar 05 01:10:37 PM PST 24 |
| Finished | Mar 05 01:12:50 PM PST 24 |
| Peak memory | 199044 kb |
| Host | smart-d88e2533-a974-49f9-9247-aa295d16a5a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461651873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3461651873 |
| Directory | /workspace/27.hmac_error/latest |
| Test location | /workspace/coverage/default/27.hmac_long_msg.2151711931 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5443390261 ps |
| CPU time | 73.22 seconds |
| Started | Mar 05 01:10:31 PM PST 24 |
| Finished | Mar 05 01:11:44 PM PST 24 |
| Peak memory | 199064 kb |
| Host | smart-ddaf256e-ec36-4654-8434-6508d2c87567 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2151711931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2151711931 |
| Directory | /workspace/27.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/27.hmac_smoke.2504568891 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1421265163 ps |
| CPU time | 3.96 seconds |
| Started | Mar 05 01:10:34 PM PST 24 |
| Finished | Mar 05 01:10:38 PM PST 24 |
| Peak memory | 199008 kb |
| Host | smart-58c75e4e-7d48-4584-81aa-c43ab271a3c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2504568891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2504568891 |
| Directory | /workspace/27.hmac_smoke/latest |
| Test location | /workspace/coverage/default/27.hmac_stress_all.3877676978 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 162558352830 ps |
| CPU time | 1312.68 seconds |
| Started | Mar 05 01:10:24 PM PST 24 |
| Finished | Mar 05 01:32:19 PM PST 24 |
| Peak memory | 234896 kb |
| Host | smart-3d3ad4e3-bbf9-4d57-81c1-c8efe6009386 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877676978 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3877676978 |
| Directory | /workspace/27.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/27.hmac_test_hmac_vectors.3595983319 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 251003318 ps |
| CPU time | 1.11 seconds |
| Started | Mar 05 01:10:37 PM PST 24 |
| Finished | Mar 05 01:10:39 PM PST 24 |
| Peak memory | 197912 kb |
| Host | smart-9822062d-a225-4ec7-9d9f-7b427a37bc43 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595983319 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.hmac_test_hmac_vectors.3595983319 |
| Directory | /workspace/27.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/28.hmac_alert_test.4216437046 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 49324308 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:10:39 PM PST 24 |
| Finished | Mar 05 01:10:40 PM PST 24 |
| Peak memory | 193608 kb |
| Host | smart-7f3944c1-9580-42a3-9840-0bfa95b28323 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216437046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.4216437046 |
| Directory | /workspace/28.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/28.hmac_back_pressure.1249286788 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3444845247 ps |
| CPU time | 31.45 seconds |
| Started | Mar 05 01:10:42 PM PST 24 |
| Finished | Mar 05 01:11:13 PM PST 24 |
| Peak memory | 237880 kb |
| Host | smart-6d8aa0f0-83f2-4be9-904e-3c03b4283a9e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1249286788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1249286788 |
| Directory | /workspace/28.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/28.hmac_burst_wr.2291970639 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 544635163 ps |
| CPU time | 24.15 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:11:11 PM PST 24 |
| Peak memory | 198968 kb |
| Host | smart-d7db09e7-5dc9-43b8-9988-f92b82af0950 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2291970639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2291970639 |
| Directory | /workspace/28.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/28.hmac_datapath_stress.1978432603 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 437308973 ps |
| CPU time | 21.97 seconds |
| Started | Mar 05 01:10:37 PM PST 24 |
| Finished | Mar 05 01:10:59 PM PST 24 |
| Peak memory | 198892 kb |
| Host | smart-56f596e1-5240-40c2-b650-41812bcaedad |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1978432603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1978432603 |
| Directory | /workspace/28.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/28.hmac_error.2193410504 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 16459452258 ps |
| CPU time | 67.17 seconds |
| Started | Mar 05 01:10:36 PM PST 24 |
| Finished | Mar 05 01:11:43 PM PST 24 |
| Peak memory | 199072 kb |
| Host | smart-0898677e-ec22-4455-aacb-c5817ce5d100 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193410504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2193410504 |
| Directory | /workspace/28.hmac_error/latest |
| Test location | /workspace/coverage/default/28.hmac_long_msg.2335380054 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 952776872 ps |
| CPU time | 51.97 seconds |
| Started | Mar 05 01:10:42 PM PST 24 |
| Finished | Mar 05 01:11:34 PM PST 24 |
| Peak memory | 198856 kb |
| Host | smart-d3b92f5c-8a06-4087-b17e-1e190d8e9748 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335380054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2335380054 |
| Directory | /workspace/28.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/28.hmac_smoke.274913890 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 652582162 ps |
| CPU time | 4.43 seconds |
| Started | Mar 05 01:10:43 PM PST 24 |
| Finished | Mar 05 01:10:47 PM PST 24 |
| Peak memory | 198904 kb |
| Host | smart-ab48347e-7b73-47e9-8540-2b81c654f726 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274913890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.274913890 |
| Directory | /workspace/28.hmac_smoke/latest |
| Test location | /workspace/coverage/default/28.hmac_stress_all.3850742911 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 31092963787 ps |
| CPU time | 380.57 seconds |
| Started | Mar 05 01:10:37 PM PST 24 |
| Finished | Mar 05 01:16:58 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-8c1626e3-61fb-40ed-9146-e59aca25a893 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850742911 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3850742911 |
| Directory | /workspace/28.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/28.hmac_test_hmac_vectors.1004893132 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 94908266 ps |
| CPU time | 0.85 seconds |
| Started | Mar 05 01:10:35 PM PST 24 |
| Finished | Mar 05 01:10:36 PM PST 24 |
| Peak memory | 196208 kb |
| Host | smart-20d940a1-dd9c-4c6a-9a76-c87ea56ee818 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004893132 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.hmac_test_hmac_vectors.1004893132 |
| Directory | /workspace/28.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/28.hmac_wipe_secret.2246349123 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 13873104970 ps |
| CPU time | 67.3 seconds |
| Started | Mar 05 01:10:41 PM PST 24 |
| Finished | Mar 05 01:11:49 PM PST 24 |
| Peak memory | 199084 kb |
| Host | smart-0a0730a6-6764-4f92-a9e4-03ece960630e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246349123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2246349123 |
| Directory | /workspace/28.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/29.hmac_alert_test.189007619 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 42610920 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:10:32 PM PST 24 |
| Finished | Mar 05 01:10:33 PM PST 24 |
| Peak memory | 193332 kb |
| Host | smart-da1aa071-4e45-4d52-ad86-5f194609f4c3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189007619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.189007619 |
| Directory | /workspace/29.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/29.hmac_back_pressure.2131477807 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1203451070 ps |
| CPU time | 18.28 seconds |
| Started | Mar 05 01:10:34 PM PST 24 |
| Finished | Mar 05 01:10:53 PM PST 24 |
| Peak memory | 207204 kb |
| Host | smart-9455012c-461c-45e1-9f87-bb8543cef3c9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2131477807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2131477807 |
| Directory | /workspace/29.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/29.hmac_burst_wr.3609270660 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 871666317 ps |
| CPU time | 13.01 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:10:59 PM PST 24 |
| Peak memory | 198912 kb |
| Host | smart-f2205fd7-1075-4ade-b61a-b9503f3a3c5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3609270660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3609270660 |
| Directory | /workspace/29.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/29.hmac_datapath_stress.472082892 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2856689878 ps |
| CPU time | 82.74 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:12:10 PM PST 24 |
| Peak memory | 199084 kb |
| Host | smart-8e244236-65f6-4382-a54d-7985faba5310 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=472082892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.472082892 |
| Directory | /workspace/29.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/29.hmac_error.407746264 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 37999254770 ps |
| CPU time | 105.49 seconds |
| Started | Mar 05 01:10:43 PM PST 24 |
| Finished | Mar 05 01:12:29 PM PST 24 |
| Peak memory | 199020 kb |
| Host | smart-0d17089a-4c82-457f-b1e9-260131ddc1f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407746264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.407746264 |
| Directory | /workspace/29.hmac_error/latest |
| Test location | /workspace/coverage/default/29.hmac_long_msg.2788389329 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1767709174 ps |
| CPU time | 97.95 seconds |
| Started | Mar 05 01:10:33 PM PST 24 |
| Finished | Mar 05 01:12:11 PM PST 24 |
| Peak memory | 198896 kb |
| Host | smart-5725dc03-8995-428d-8b35-8540ee0fe007 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2788389329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2788389329 |
| Directory | /workspace/29.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/29.hmac_smoke.513387893 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 430478975 ps |
| CPU time | 2.79 seconds |
| Started | Mar 05 01:10:37 PM PST 24 |
| Finished | Mar 05 01:10:40 PM PST 24 |
| Peak memory | 198952 kb |
| Host | smart-95c927be-f4a4-4845-bec3-2604a3739d09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513387893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.513387893 |
| Directory | /workspace/29.hmac_smoke/latest |
| Test location | /workspace/coverage/default/29.hmac_stress_all.454132087 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 290891576748 ps |
| CPU time | 1211.99 seconds |
| Started | Mar 05 01:10:43 PM PST 24 |
| Finished | Mar 05 01:30:56 PM PST 24 |
| Peak memory | 226028 kb |
| Host | smart-ced82f3c-b8e8-4a5c-be61-fff2703f3bc4 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454132087 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.454132087 |
| Directory | /workspace/29.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/29.hmac_test_hmac_vectors.2884359541 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 351305483 ps |
| CPU time | 1.17 seconds |
| Started | Mar 05 01:10:39 PM PST 24 |
| Finished | Mar 05 01:10:41 PM PST 24 |
| Peak memory | 198924 kb |
| Host | smart-f20ffcaa-e92d-4d1b-acd7-c103d207ec6b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884359541 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.hmac_test_hmac_vectors.2884359541 |
| Directory | /workspace/29.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/29.hmac_test_sha_vectors.4221583342 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 15537659031 ps |
| CPU time | 390.93 seconds |
| Started | Mar 05 01:10:41 PM PST 24 |
| Finished | Mar 05 01:17:12 PM PST 24 |
| Peak memory | 199016 kb |
| Host | smart-e1d9cdf8-de48-44bb-8de2-4b34b1edacc9 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221583342 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 29.hmac_test_sha_vectors.4221583342 |
| Directory | /workspace/29.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/29.hmac_wipe_secret.478902472 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 9906155502 ps |
| CPU time | 68.86 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:11:56 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-414fd43a-7b37-4681-94f0-1c5f220b740c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478902472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.478902472 |
| Directory | /workspace/29.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/3.hmac_alert_test.2312530157 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 18364153 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:10:00 PM PST 24 |
| Peak memory | 194248 kb |
| Host | smart-347ae8d3-54ac-495d-b557-9bd1782054ff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312530157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2312530157 |
| Directory | /workspace/3.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/3.hmac_back_pressure.3411212846 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 3757481633 ps |
| CPU time | 37.67 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:10:32 PM PST 24 |
| Peak memory | 209240 kb |
| Host | smart-2eee07d8-f2ea-47d7-850d-4fc907c86a82 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3411212846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3411212846 |
| Directory | /workspace/3.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/3.hmac_burst_wr.2152144784 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 536805039 ps |
| CPU time | 4.61 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:58 PM PST 24 |
| Peak memory | 198928 kb |
| Host | smart-ec224380-be0a-42dd-8386-e25bc71b9e49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2152144784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2152144784 |
| Directory | /workspace/3.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/3.hmac_datapath_stress.1562839740 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 6048680115 ps |
| CPU time | 149.59 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:12:25 PM PST 24 |
| Peak memory | 199060 kb |
| Host | smart-c3c77d70-f534-44b8-9cc6-07063ef6a689 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1562839740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1562839740 |
| Directory | /workspace/3.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/3.hmac_error.4234128608 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 4488834204 ps |
| CPU time | 61.8 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:10:57 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-c884e82a-715d-42ae-be82-0b53521fded7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4234128608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.4234128608 |
| Directory | /workspace/3.hmac_error/latest |
| Test location | /workspace/coverage/default/3.hmac_long_msg.2616994771 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 6161627917 ps |
| CPU time | 83.39 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:11:17 PM PST 24 |
| Peak memory | 199052 kb |
| Host | smart-75e3ee29-0225-45fd-ac99-1c1aef785ea9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616994771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2616994771 |
| Directory | /workspace/3.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/3.hmac_sec_cm.3874152415 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 366258915 ps |
| CPU time | 1.02 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:10:00 PM PST 24 |
| Peak memory | 217492 kb |
| Host | smart-4fc57a15-56ac-434a-a04f-e9ebe18a3e88 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874152415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3874152415 |
| Directory | /workspace/3.hmac_sec_cm/latest |
| Test location | /workspace/coverage/default/3.hmac_smoke.83211423 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 153805650 ps |
| CPU time | 1.26 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:56 PM PST 24 |
| Peak memory | 198712 kb |
| Host | smart-79e1e687-3859-45de-9297-3a8f9f8a3fba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83211423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.83211423 |
| Directory | /workspace/3.hmac_smoke/latest |
| Test location | /workspace/coverage/default/3.hmac_stress_all.1528845726 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 32617962143 ps |
| CPU time | 785.54 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:23:00 PM PST 24 |
| Peak memory | 227736 kb |
| Host | smart-567e69b0-760a-4fef-8921-c50dc42f2c8d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528845726 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1528845726 |
| Directory | /workspace/3.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/3.hmac_test_hmac_vectors.1997962197 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 27016638 ps |
| CPU time | 0.92 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:55 PM PST 24 |
| Peak memory | 197384 kb |
| Host | smart-79acd8e3-9a00-4680-8ced-f9953962f34c |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997962197 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.hmac_test_hmac_vectors.1997962197 |
| Directory | /workspace/3.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/3.hmac_test_sha_vectors.3475790818 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 52121969559 ps |
| CPU time | 443.8 seconds |
| Started | Mar 05 01:09:48 PM PST 24 |
| Finished | Mar 05 01:17:16 PM PST 24 |
| Peak memory | 199016 kb |
| Host | smart-7ca61fe0-80c1-4133-8cb8-f7aa7aae4bfd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475790818 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 3.hmac_test_sha_vectors.3475790818 |
| Directory | /workspace/3.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/3.hmac_wipe_secret.536138740 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 20212370666 ps |
| CPU time | 45.45 seconds |
| Started | Mar 05 01:09:58 PM PST 24 |
| Finished | Mar 05 01:10:44 PM PST 24 |
| Peak memory | 198936 kb |
| Host | smart-d84fb707-2500-484f-945e-f1b7d9354929 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536138740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.536138740 |
| Directory | /workspace/3.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/30.hmac_alert_test.3138503992 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 16353739 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:10:40 PM PST 24 |
| Finished | Mar 05 01:10:41 PM PST 24 |
| Peak memory | 193584 kb |
| Host | smart-bd610750-9842-47e1-949e-3a9c7b2d4e40 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138503992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3138503992 |
| Directory | /workspace/30.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/30.hmac_back_pressure.2431622626 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 804515253 ps |
| CPU time | 23.35 seconds |
| Started | Mar 05 01:10:43 PM PST 24 |
| Finished | Mar 05 01:11:07 PM PST 24 |
| Peak memory | 207148 kb |
| Host | smart-73cdba94-5531-4258-9aac-2811e1fb25aa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2431622626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2431622626 |
| Directory | /workspace/30.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/30.hmac_burst_wr.57572955 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2025751874 ps |
| CPU time | 36.71 seconds |
| Started | Mar 05 01:10:35 PM PST 24 |
| Finished | Mar 05 01:11:12 PM PST 24 |
| Peak memory | 198916 kb |
| Host | smart-8ae18497-b2a0-46d8-94e9-1039011af190 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57572955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.57572955 |
| Directory | /workspace/30.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/30.hmac_datapath_stress.900224864 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 5465770392 ps |
| CPU time | 108.18 seconds |
| Started | Mar 05 01:10:43 PM PST 24 |
| Finished | Mar 05 01:12:31 PM PST 24 |
| Peak memory | 199112 kb |
| Host | smart-a06cbe72-663d-4641-adc1-4fd58d4fe9b9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=900224864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.900224864 |
| Directory | /workspace/30.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/30.hmac_error.2902670019 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 29735486834 ps |
| CPU time | 132.82 seconds |
| Started | Mar 05 01:10:32 PM PST 24 |
| Finished | Mar 05 01:12:45 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-a62e4b30-89db-4fed-95f3-11472118c894 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902670019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2902670019 |
| Directory | /workspace/30.hmac_error/latest |
| Test location | /workspace/coverage/default/30.hmac_long_msg.3999329930 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 109883875411 ps |
| CPU time | 100.21 seconds |
| Started | Mar 05 01:10:45 PM PST 24 |
| Finished | Mar 05 01:12:25 PM PST 24 |
| Peak memory | 199164 kb |
| Host | smart-365846ab-86cf-42db-9794-894d0679a493 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3999329930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3999329930 |
| Directory | /workspace/30.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/30.hmac_smoke.45853406 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 209094326 ps |
| CPU time | 2.89 seconds |
| Started | Mar 05 01:10:35 PM PST 24 |
| Finished | Mar 05 01:10:39 PM PST 24 |
| Peak memory | 198728 kb |
| Host | smart-cad198ed-4320-415f-ad4d-6be190296442 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45853406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.45853406 |
| Directory | /workspace/30.hmac_smoke/latest |
| Test location | /workspace/coverage/default/30.hmac_stress_all.126935795 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 11077486391 ps |
| CPU time | 544.9 seconds |
| Started | Mar 05 01:10:36 PM PST 24 |
| Finished | Mar 05 01:19:41 PM PST 24 |
| Peak memory | 199084 kb |
| Host | smart-2547d7e6-704d-4b10-a119-f3260cc08dc6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126935795 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.126935795 |
| Directory | /workspace/30.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/30.hmac_test_hmac_vectors.2150022425 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 179749611 ps |
| CPU time | 1.05 seconds |
| Started | Mar 05 01:10:44 PM PST 24 |
| Finished | Mar 05 01:10:45 PM PST 24 |
| Peak memory | 198256 kb |
| Host | smart-29a7da2e-329c-4e11-af7e-58a809c05f90 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150022425 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.hmac_test_hmac_vectors.2150022425 |
| Directory | /workspace/30.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/30.hmac_test_sha_vectors.1275114053 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 118672341858 ps |
| CPU time | 471.92 seconds |
| Started | Mar 05 01:10:37 PM PST 24 |
| Finished | Mar 05 01:18:29 PM PST 24 |
| Peak memory | 199044 kb |
| Host | smart-157efb3b-a12d-4dec-92ec-c20da7ba93af |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275114053 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 30.hmac_test_sha_vectors.1275114053 |
| Directory | /workspace/30.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/30.hmac_wipe_secret.2213706990 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4584602256 ps |
| CPU time | 38.97 seconds |
| Started | Mar 05 01:10:39 PM PST 24 |
| Finished | Mar 05 01:11:18 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-18400f41-eb56-45bc-b129-b9fc6c3d1b42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213706990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2213706990 |
| Directory | /workspace/30.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/31.hmac_alert_test.318651697 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 11597392 ps |
| CPU time | 0.54 seconds |
| Started | Mar 05 01:10:44 PM PST 24 |
| Finished | Mar 05 01:10:44 PM PST 24 |
| Peak memory | 193328 kb |
| Host | smart-27977c0c-317a-42a0-969e-54d43825b43e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318651697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.318651697 |
| Directory | /workspace/31.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/31.hmac_back_pressure.1364644886 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 236340235 ps |
| CPU time | 7.5 seconds |
| Started | Mar 05 01:10:30 PM PST 24 |
| Finished | Mar 05 01:10:38 PM PST 24 |
| Peak memory | 198876 kb |
| Host | smart-c4fa3357-0a87-4772-8d48-919ac5851b03 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1364644886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1364644886 |
| Directory | /workspace/31.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/31.hmac_burst_wr.3885635544 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2571717770 ps |
| CPU time | 6.68 seconds |
| Started | Mar 05 01:10:35 PM PST 24 |
| Finished | Mar 05 01:10:42 PM PST 24 |
| Peak memory | 198988 kb |
| Host | smart-c01e5e3d-815d-4cc5-bcda-1aa5ef6f8a39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885635544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3885635544 |
| Directory | /workspace/31.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/31.hmac_datapath_stress.1550479888 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1729731841 ps |
| CPU time | 92.57 seconds |
| Started | Mar 05 01:10:32 PM PST 24 |
| Finished | Mar 05 01:12:04 PM PST 24 |
| Peak memory | 198992 kb |
| Host | smart-3bf633d6-cdb0-4a35-b266-c29f7f06a321 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1550479888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1550479888 |
| Directory | /workspace/31.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/31.hmac_error.2756623507 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 13196319894 ps |
| CPU time | 73.55 seconds |
| Started | Mar 05 01:10:40 PM PST 24 |
| Finished | Mar 05 01:11:54 PM PST 24 |
| Peak memory | 199044 kb |
| Host | smart-84e151a9-63e3-44d3-ad8c-ce1aa1ea9700 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756623507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2756623507 |
| Directory | /workspace/31.hmac_error/latest |
| Test location | /workspace/coverage/default/31.hmac_long_msg.4109741994 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 31942894454 ps |
| CPU time | 54.56 seconds |
| Started | Mar 05 01:10:36 PM PST 24 |
| Finished | Mar 05 01:11:31 PM PST 24 |
| Peak memory | 199140 kb |
| Host | smart-a54f68ef-e6e6-4fb9-8b3c-e8d5de70edda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4109741994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.4109741994 |
| Directory | /workspace/31.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/31.hmac_smoke.551535737 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 226825989 ps |
| CPU time | 2.9 seconds |
| Started | Mar 05 01:10:35 PM PST 24 |
| Finished | Mar 05 01:10:38 PM PST 24 |
| Peak memory | 198896 kb |
| Host | smart-91705d9b-7532-4ce3-b0e4-10e75161cc54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551535737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.551535737 |
| Directory | /workspace/31.hmac_smoke/latest |
| Test location | /workspace/coverage/default/31.hmac_stress_all.2292911575 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1173848893677 ps |
| CPU time | 1671.1 seconds |
| Started | Mar 05 01:10:31 PM PST 24 |
| Finished | Mar 05 01:38:22 PM PST 24 |
| Peak memory | 199100 kb |
| Host | smart-f02eeeca-1b3b-4cb6-bb46-f8ec21c89326 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292911575 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2292911575 |
| Directory | /workspace/31.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/31.hmac_test_hmac_vectors.884142011 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 282454995 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:10:32 PM PST 24 |
| Finished | Mar 05 01:10:33 PM PST 24 |
| Peak memory | 197516 kb |
| Host | smart-4b34a2f9-4334-4551-8671-a7f52fa521af |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884142011 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 31.hmac_test_hmac_vectors.884142011 |
| Directory | /workspace/31.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/31.hmac_test_sha_vectors.3221412801 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 25769558219 ps |
| CPU time | 413.53 seconds |
| Started | Mar 05 01:10:35 PM PST 24 |
| Finished | Mar 05 01:17:29 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-a8f8471a-4436-46ef-9e6e-9edf077593d3 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221412801 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 31.hmac_test_sha_vectors.3221412801 |
| Directory | /workspace/31.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/31.hmac_wipe_secret.567414427 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2327194439 ps |
| CPU time | 55.01 seconds |
| Started | Mar 05 01:10:34 PM PST 24 |
| Finished | Mar 05 01:11:29 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-a5278de0-e276-4b36-ad6f-c7ad29721386 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567414427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.567414427 |
| Directory | /workspace/31.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/32.hmac_alert_test.3043131792 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 60559527 ps |
| CPU time | 0.58 seconds |
| Started | Mar 05 01:10:44 PM PST 24 |
| Finished | Mar 05 01:10:45 PM PST 24 |
| Peak memory | 194416 kb |
| Host | smart-4b44970c-1dba-4607-b98e-6e2a8e8b7e03 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043131792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3043131792 |
| Directory | /workspace/32.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/32.hmac_back_pressure.793280970 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1533747345 ps |
| CPU time | 52.63 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:11:40 PM PST 24 |
| Peak memory | 231660 kb |
| Host | smart-af144a39-b21f-4d1d-8eb9-3091626210ef |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=793280970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.793280970 |
| Directory | /workspace/32.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/32.hmac_burst_wr.16839545 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2111033141 ps |
| CPU time | 30.87 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:11:17 PM PST 24 |
| Peak memory | 199028 kb |
| Host | smart-0dc7bc70-8336-4069-bb2e-1029ccbeb955 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16839545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.16839545 |
| Directory | /workspace/32.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/32.hmac_datapath_stress.2133744433 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2806190762 ps |
| CPU time | 78.68 seconds |
| Started | Mar 05 01:10:45 PM PST 24 |
| Finished | Mar 05 01:12:04 PM PST 24 |
| Peak memory | 198964 kb |
| Host | smart-ad5d2aa1-a966-4c23-a38a-09e6380ea79f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2133744433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2133744433 |
| Directory | /workspace/32.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/32.hmac_error.1522319771 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3611758521 ps |
| CPU time | 42.14 seconds |
| Started | Mar 05 01:10:48 PM PST 24 |
| Finished | Mar 05 01:11:31 PM PST 24 |
| Peak memory | 199172 kb |
| Host | smart-caca8c81-5c52-4387-accf-bb494f4e06af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1522319771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1522319771 |
| Directory | /workspace/32.hmac_error/latest |
| Test location | /workspace/coverage/default/32.hmac_long_msg.1345431546 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1557996293 ps |
| CPU time | 84.21 seconds |
| Started | Mar 05 01:10:45 PM PST 24 |
| Finished | Mar 05 01:12:09 PM PST 24 |
| Peak memory | 198944 kb |
| Host | smart-7d367a27-6d66-4d69-8174-85ef60c0aa0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345431546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1345431546 |
| Directory | /workspace/32.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/32.hmac_smoke.3320596626 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1346703047 ps |
| CPU time | 4.34 seconds |
| Started | Mar 05 01:10:44 PM PST 24 |
| Finished | Mar 05 01:10:48 PM PST 24 |
| Peak memory | 198992 kb |
| Host | smart-ec0bfc64-070c-4651-86a0-09ad4c2bd71b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320596626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3320596626 |
| Directory | /workspace/32.hmac_smoke/latest |
| Test location | /workspace/coverage/default/32.hmac_stress_all.2948557371 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 169078217746 ps |
| CPU time | 2722.08 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:56:08 PM PST 24 |
| Peak memory | 199132 kb |
| Host | smart-7dd3bc48-439c-46f9-a435-c93b56fbc042 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948557371 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2948557371 |
| Directory | /workspace/32.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/32.hmac_test_hmac_vectors.3758715373 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 125730144 ps |
| CPU time | 1.18 seconds |
| Started | Mar 05 01:10:53 PM PST 24 |
| Finished | Mar 05 01:10:54 PM PST 24 |
| Peak memory | 197480 kb |
| Host | smart-cc9378ef-60e8-427c-a8f4-2c87d0bfc1c1 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758715373 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.hmac_test_hmac_vectors.3758715373 |
| Directory | /workspace/32.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/32.hmac_test_sha_vectors.1831966553 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 52322112436 ps |
| CPU time | 453.76 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:18:20 PM PST 24 |
| Peak memory | 198920 kb |
| Host | smart-2da6f8f5-8886-46a9-ab37-b8cdd0f85c3d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831966553 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 32.hmac_test_sha_vectors.1831966553 |
| Directory | /workspace/32.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/32.hmac_wipe_secret.718315333 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2494921350 ps |
| CPU time | 11.9 seconds |
| Started | Mar 05 01:10:42 PM PST 24 |
| Finished | Mar 05 01:10:54 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-0e3d91da-788d-4e02-b8a8-cc80dc92c237 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718315333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.718315333 |
| Directory | /workspace/32.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/33.hmac_alert_test.4166378784 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 28715200 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:10:44 PM PST 24 |
| Finished | Mar 05 01:10:44 PM PST 24 |
| Peak memory | 193392 kb |
| Host | smart-de13b8e0-c012-409b-86cc-939911065a47 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166378784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4166378784 |
| Directory | /workspace/33.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/33.hmac_back_pressure.2093680945 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 181090284 ps |
| CPU time | 5.71 seconds |
| Started | Mar 05 01:10:54 PM PST 24 |
| Finished | Mar 05 01:11:00 PM PST 24 |
| Peak memory | 198804 kb |
| Host | smart-eadd16ac-16cc-4495-a552-20c277529140 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2093680945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2093680945 |
| Directory | /workspace/33.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/33.hmac_burst_wr.540439255 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 8930194991 ps |
| CPU time | 34.43 seconds |
| Started | Mar 05 01:10:51 PM PST 24 |
| Finished | Mar 05 01:11:26 PM PST 24 |
| Peak memory | 199120 kb |
| Host | smart-9c45cfd9-7552-409a-b30c-cb9a86b25cba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540439255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.540439255 |
| Directory | /workspace/33.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/33.hmac_datapath_stress.4266083379 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 3457740969 ps |
| CPU time | 23.71 seconds |
| Started | Mar 05 01:10:51 PM PST 24 |
| Finished | Mar 05 01:11:15 PM PST 24 |
| Peak memory | 199100 kb |
| Host | smart-af1ee25e-69b9-45dc-a446-48c4cc432efd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4266083379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4266083379 |
| Directory | /workspace/33.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/33.hmac_error.1316860185 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3568337075 ps |
| CPU time | 174.46 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:13:41 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-1131d950-02ad-4348-9686-2f8bdb65d6e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316860185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1316860185 |
| Directory | /workspace/33.hmac_error/latest |
| Test location | /workspace/coverage/default/33.hmac_long_msg.1235176151 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 39049267610 ps |
| CPU time | 120.48 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:12:47 PM PST 24 |
| Peak memory | 199164 kb |
| Host | smart-3778bf42-a923-4d8a-9032-c38b04ccdd3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235176151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1235176151 |
| Directory | /workspace/33.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/33.hmac_smoke.3750220228 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 82323584 ps |
| CPU time | 1.08 seconds |
| Started | Mar 05 01:10:50 PM PST 24 |
| Finished | Mar 05 01:10:51 PM PST 24 |
| Peak memory | 198260 kb |
| Host | smart-cfbb0f49-9ee4-4f0b-b5dc-706c8042b63e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3750220228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3750220228 |
| Directory | /workspace/33.hmac_smoke/latest |
| Test location | /workspace/coverage/default/33.hmac_stress_all.2230034484 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 92951219388 ps |
| CPU time | 633.38 seconds |
| Started | Mar 05 01:10:48 PM PST 24 |
| Finished | Mar 05 01:21:22 PM PST 24 |
| Peak memory | 199000 kb |
| Host | smart-3beab5c2-9bbf-4d58-a76b-4d08bc1596d5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230034484 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2230034484 |
| Directory | /workspace/33.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.3237091112 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 105243494600 ps |
| CPU time | 2099.59 seconds |
| Started | Mar 05 01:10:48 PM PST 24 |
| Finished | Mar 05 01:45:48 PM PST 24 |
| Peak memory | 247464 kb |
| Host | smart-a1f0a5ec-9f95-48c3-8c39-80fc280e8e74 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3237091112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.3237091112 |
| Directory | /workspace/33.hmac_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.hmac_test_hmac_vectors.1291682018 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 576981849 ps |
| CPU time | 1.22 seconds |
| Started | Mar 05 01:10:53 PM PST 24 |
| Finished | Mar 05 01:10:54 PM PST 24 |
| Peak memory | 197760 kb |
| Host | smart-64998475-5270-4ba6-ad57-617070d07a74 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291682018 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.hmac_test_hmac_vectors.1291682018 |
| Directory | /workspace/33.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/33.hmac_test_sha_vectors.2647510443 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 34528209214 ps |
| CPU time | 420.16 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:17:46 PM PST 24 |
| Peak memory | 199016 kb |
| Host | smart-eea0e2c4-e7bf-40ef-a1ce-cab1dcc89e91 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647510443 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 33.hmac_test_sha_vectors.2647510443 |
| Directory | /workspace/33.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/33.hmac_wipe_secret.4065295350 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 11622011379 ps |
| CPU time | 50.41 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:11:37 PM PST 24 |
| Peak memory | 199004 kb |
| Host | smart-d3d6281d-c9ac-46ae-b30d-194645974827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065295350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4065295350 |
| Directory | /workspace/33.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/34.hmac_alert_test.2877667439 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 12282948 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:10:49 PM PST 24 |
| Finished | Mar 05 01:10:50 PM PST 24 |
| Peak memory | 193336 kb |
| Host | smart-9b7e5d30-e223-41cb-aff6-688f8d96eb08 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877667439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2877667439 |
| Directory | /workspace/34.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/34.hmac_back_pressure.1965545001 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4485987781 ps |
| CPU time | 30.77 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:11:17 PM PST 24 |
| Peak memory | 215408 kb |
| Host | smart-fb809f05-0c75-475b-8c8f-9a40a67ac62a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1965545001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1965545001 |
| Directory | /workspace/34.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/34.hmac_burst_wr.3489500357 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3369010144 ps |
| CPU time | 46.56 seconds |
| Started | Mar 05 01:10:51 PM PST 24 |
| Finished | Mar 05 01:11:37 PM PST 24 |
| Peak memory | 199000 kb |
| Host | smart-38ed4e4d-3fe0-429b-a12e-a982665c2e65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489500357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3489500357 |
| Directory | /workspace/34.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/34.hmac_datapath_stress.1870678996 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 492981871 ps |
| CPU time | 7.1 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:10:55 PM PST 24 |
| Peak memory | 198888 kb |
| Host | smart-537a8956-c8f9-4697-b3ff-43557f849425 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1870678996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1870678996 |
| Directory | /workspace/34.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/34.hmac_error.2997117830 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 7198525492 ps |
| CPU time | 84.57 seconds |
| Started | Mar 05 01:10:49 PM PST 24 |
| Finished | Mar 05 01:12:13 PM PST 24 |
| Peak memory | 199008 kb |
| Host | smart-74f442bb-9ae2-473b-aea8-a54cae3922cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997117830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2997117830 |
| Directory | /workspace/34.hmac_error/latest |
| Test location | /workspace/coverage/default/34.hmac_long_msg.2349469312 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3418113347 ps |
| CPU time | 44.8 seconds |
| Started | Mar 05 01:10:48 PM PST 24 |
| Finished | Mar 05 01:11:33 PM PST 24 |
| Peak memory | 199056 kb |
| Host | smart-ea8af877-0d9f-4467-8593-0f3f3ed28046 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349469312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2349469312 |
| Directory | /workspace/34.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/34.hmac_smoke.583789815 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 86310096 ps |
| CPU time | 1.31 seconds |
| Started | Mar 05 01:10:52 PM PST 24 |
| Finished | Mar 05 01:10:53 PM PST 24 |
| Peak memory | 198396 kb |
| Host | smart-e346e6dc-8adf-4440-b53a-d0ca4434c627 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583789815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.583789815 |
| Directory | /workspace/34.hmac_smoke/latest |
| Test location | /workspace/coverage/default/34.hmac_stress_all.4140578560 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 177216981209 ps |
| CPU time | 2069.16 seconds |
| Started | Mar 05 01:10:51 PM PST 24 |
| Finished | Mar 05 01:45:20 PM PST 24 |
| Peak memory | 247412 kb |
| Host | smart-5fe63c1f-e5f5-4809-b250-fec60c60d458 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140578560 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.4140578560 |
| Directory | /workspace/34.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/34.hmac_test_hmac_vectors.3401411653 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 31961223 ps |
| CPU time | 1.14 seconds |
| Started | Mar 05 01:10:45 PM PST 24 |
| Finished | Mar 05 01:10:47 PM PST 24 |
| Peak memory | 197480 kb |
| Host | smart-3611fa42-08dc-437b-975d-582b7f9c5909 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401411653 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.hmac_test_hmac_vectors.3401411653 |
| Directory | /workspace/34.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/34.hmac_test_sha_vectors.3843836054 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 8454656769 ps |
| CPU time | 414.73 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:17:41 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-44554dd6-08e1-49f0-a25c-19e6a9ac02a8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843836054 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 34.hmac_test_sha_vectors.3843836054 |
| Directory | /workspace/34.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/34.hmac_wipe_secret.3792684439 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 10531237109 ps |
| CPU time | 52.23 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:11:40 PM PST 24 |
| Peak memory | 199112 kb |
| Host | smart-d642455a-e831-45ab-bacd-f04ae50764d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792684439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3792684439 |
| Directory | /workspace/34.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/35.hmac_alert_test.619018755 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 93565459 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:10:48 PM PST 24 |
| Peak memory | 193368 kb |
| Host | smart-5517303e-ea70-4ce7-a47e-88fd5b81cc0c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619018755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.619018755 |
| Directory | /workspace/35.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/35.hmac_back_pressure.4149022487 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 467380224 ps |
| CPU time | 4.81 seconds |
| Started | Mar 05 01:11:00 PM PST 24 |
| Finished | Mar 05 01:11:05 PM PST 24 |
| Peak memory | 207076 kb |
| Host | smart-9d9508ce-bed8-40ce-8e5e-71cf3068b205 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4149022487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.4149022487 |
| Directory | /workspace/35.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/35.hmac_burst_wr.3719413722 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 4050041298 ps |
| CPU time | 66.15 seconds |
| Started | Mar 05 01:10:48 PM PST 24 |
| Finished | Mar 05 01:11:55 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-f312edcc-0c84-46b0-93bd-183e24cb81b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719413722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3719413722 |
| Directory | /workspace/35.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/35.hmac_datapath_stress.952917722 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 60644056 ps |
| CPU time | 2.42 seconds |
| Started | Mar 05 01:10:48 PM PST 24 |
| Finished | Mar 05 01:10:51 PM PST 24 |
| Peak memory | 198868 kb |
| Host | smart-5849b42b-e521-492e-a945-2144719315f6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=952917722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.952917722 |
| Directory | /workspace/35.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/35.hmac_error.3285737734 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2032537679 ps |
| CPU time | 23.41 seconds |
| Started | Mar 05 01:10:44 PM PST 24 |
| Finished | Mar 05 01:11:08 PM PST 24 |
| Peak memory | 198884 kb |
| Host | smart-9b3148d4-9650-4287-bf1c-c5eeb4d9f7ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285737734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3285737734 |
| Directory | /workspace/35.hmac_error/latest |
| Test location | /workspace/coverage/default/35.hmac_long_msg.340465486 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 19286267231 ps |
| CPU time | 94.12 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:12:20 PM PST 24 |
| Peak memory | 199120 kb |
| Host | smart-3cba037f-cb9c-4b51-9cc7-2cdc52e28a25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340465486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.340465486 |
| Directory | /workspace/35.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/35.hmac_smoke.552095057 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 523384081 ps |
| CPU time | 2.96 seconds |
| Started | Mar 05 01:10:51 PM PST 24 |
| Finished | Mar 05 01:10:54 PM PST 24 |
| Peak memory | 198920 kb |
| Host | smart-8e0a210e-80c5-4670-bdf9-0cadc155ad2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552095057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.552095057 |
| Directory | /workspace/35.hmac_smoke/latest |
| Test location | /workspace/coverage/default/35.hmac_stress_all.2202673893 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 172811599286 ps |
| CPU time | 2906.1 seconds |
| Started | Mar 05 01:10:49 PM PST 24 |
| Finished | Mar 05 01:59:15 PM PST 24 |
| Peak memory | 226672 kb |
| Host | smart-b659defa-6caa-464b-a6a0-de74c261d6cb |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202673893 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2202673893 |
| Directory | /workspace/35.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/35.hmac_test_hmac_vectors.3027004192 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 33945339 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:10:48 PM PST 24 |
| Finished | Mar 05 01:10:49 PM PST 24 |
| Peak memory | 197228 kb |
| Host | smart-aff24388-8f65-4416-aaf2-8db3c10c18c6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027004192 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.hmac_test_hmac_vectors.3027004192 |
| Directory | /workspace/35.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/35.hmac_test_sha_vectors.1620404327 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 31344879631 ps |
| CPU time | 433.36 seconds |
| Started | Mar 05 01:10:46 PM PST 24 |
| Finished | Mar 05 01:18:00 PM PST 24 |
| Peak memory | 199008 kb |
| Host | smart-ad33c30f-d81d-4d96-ba92-5dfa7ebabaea |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620404327 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 35.hmac_test_sha_vectors.1620404327 |
| Directory | /workspace/35.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/35.hmac_wipe_secret.1403491372 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 30648223152 ps |
| CPU time | 62.74 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:11:50 PM PST 24 |
| Peak memory | 199116 kb |
| Host | smart-7b644343-3fd4-4824-9dc7-0bea0f03cda5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403491372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1403491372 |
| Directory | /workspace/35.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/36.hmac_alert_test.777142132 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 33346675 ps |
| CPU time | 0.59 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:10:48 PM PST 24 |
| Peak memory | 192124 kb |
| Host | smart-936dfe72-097d-4f3d-8538-ebef51723f0b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777142132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.777142132 |
| Directory | /workspace/36.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/36.hmac_back_pressure.3303421362 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1046531129 ps |
| CPU time | 37.69 seconds |
| Started | Mar 05 01:10:43 PM PST 24 |
| Finished | Mar 05 01:11:21 PM PST 24 |
| Peak memory | 231412 kb |
| Host | smart-c4a1c75e-fd35-4dfa-9302-53ac3ab7ac15 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3303421362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3303421362 |
| Directory | /workspace/36.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/36.hmac_burst_wr.3789512660 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3498628872 ps |
| CPU time | 42.06 seconds |
| Started | Mar 05 01:10:48 PM PST 24 |
| Finished | Mar 05 01:11:30 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-4c8c4090-7878-4ecd-bd19-476898710a28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3789512660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3789512660 |
| Directory | /workspace/36.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/36.hmac_datapath_stress.4125281628 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 8527156864 ps |
| CPU time | 113.07 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:12:41 PM PST 24 |
| Peak memory | 199072 kb |
| Host | smart-20202916-23fb-4d14-a50c-a6bfa8a00387 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4125281628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.4125281628 |
| Directory | /workspace/36.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/36.hmac_error.1584441663 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 14045522414 ps |
| CPU time | 171.77 seconds |
| Started | Mar 05 01:10:49 PM PST 24 |
| Finished | Mar 05 01:13:41 PM PST 24 |
| Peak memory | 199076 kb |
| Host | smart-36e4702e-b650-4f03-9582-0188f4745eea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584441663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1584441663 |
| Directory | /workspace/36.hmac_error/latest |
| Test location | /workspace/coverage/default/36.hmac_long_msg.2042844046 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1272188472 ps |
| CPU time | 12.6 seconds |
| Started | Mar 05 01:10:55 PM PST 24 |
| Finished | Mar 05 01:11:08 PM PST 24 |
| Peak memory | 198904 kb |
| Host | smart-e20a80cf-beda-4c37-a088-c772b897b7dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042844046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2042844046 |
| Directory | /workspace/36.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/36.hmac_smoke.1875652975 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2593734575 ps |
| CPU time | 2.54 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:10:50 PM PST 24 |
| Peak memory | 198960 kb |
| Host | smart-9443c8dd-b510-45de-ac92-4fb5efbe8b46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1875652975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1875652975 |
| Directory | /workspace/36.hmac_smoke/latest |
| Test location | /workspace/coverage/default/36.hmac_stress_all.1568148740 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 72918024932 ps |
| CPU time | 955.35 seconds |
| Started | Mar 05 01:10:44 PM PST 24 |
| Finished | Mar 05 01:26:39 PM PST 24 |
| Peak memory | 215300 kb |
| Host | smart-c277608d-6219-4a9f-ac83-86459123960e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568148740 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1568148740 |
| Directory | /workspace/36.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/36.hmac_test_hmac_vectors.482870007 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 136774385 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:10:58 PM PST 24 |
| Finished | Mar 05 01:10:59 PM PST 24 |
| Peak memory | 198076 kb |
| Host | smart-a5058023-1b7a-49bd-be6f-c6be2b6040fa |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482870007 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 36.hmac_test_hmac_vectors.482870007 |
| Directory | /workspace/36.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/36.hmac_test_sha_vectors.2495859611 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 108643642219 ps |
| CPU time | 444.16 seconds |
| Started | Mar 05 01:10:52 PM PST 24 |
| Finished | Mar 05 01:18:17 PM PST 24 |
| Peak memory | 199048 kb |
| Host | smart-164d6433-ee16-441d-82f7-33a1493fb90d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495859611 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 36.hmac_test_sha_vectors.2495859611 |
| Directory | /workspace/36.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/36.hmac_wipe_secret.3963935645 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3053930857 ps |
| CPU time | 35.93 seconds |
| Started | Mar 05 01:10:44 PM PST 24 |
| Finished | Mar 05 01:11:21 PM PST 24 |
| Peak memory | 199112 kb |
| Host | smart-08ad3410-8b79-47b1-8150-d7c29305ad62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963935645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3963935645 |
| Directory | /workspace/36.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/37.hmac_alert_test.1731884431 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 25903405 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 01:10:50 PM PST 24 |
| Finished | Mar 05 01:10:51 PM PST 24 |
| Peak memory | 193616 kb |
| Host | smart-e3090b9d-c6f2-4cc5-acf0-1122e7c7ab08 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731884431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1731884431 |
| Directory | /workspace/37.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/37.hmac_back_pressure.422140716 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1008550626 ps |
| CPU time | 35.74 seconds |
| Started | Mar 05 01:10:54 PM PST 24 |
| Finished | Mar 05 01:11:30 PM PST 24 |
| Peak memory | 221580 kb |
| Host | smart-ac91d3ad-03c0-426e-940b-4fa5e059266c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=422140716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.422140716 |
| Directory | /workspace/37.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/37.hmac_burst_wr.2412315098 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1435771061 ps |
| CPU time | 18.72 seconds |
| Started | Mar 05 01:10:50 PM PST 24 |
| Finished | Mar 05 01:11:08 PM PST 24 |
| Peak memory | 198824 kb |
| Host | smart-a6682b43-4364-43c9-a470-4a04c189ccee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412315098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2412315098 |
| Directory | /workspace/37.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/37.hmac_datapath_stress.1949141632 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 23550344 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:10:45 PM PST 24 |
| Finished | Mar 05 01:10:46 PM PST 24 |
| Peak memory | 194340 kb |
| Host | smart-cad1c9ad-da2a-45d4-bb56-d02cfff86fa1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1949141632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1949141632 |
| Directory | /workspace/37.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/37.hmac_error.1795026814 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 7302235381 ps |
| CPU time | 123.23 seconds |
| Started | Mar 05 01:10:50 PM PST 24 |
| Finished | Mar 05 01:12:53 PM PST 24 |
| Peak memory | 199092 kb |
| Host | smart-e9ee6f8a-aa2b-4641-8137-3644461c0797 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795026814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1795026814 |
| Directory | /workspace/37.hmac_error/latest |
| Test location | /workspace/coverage/default/37.hmac_long_msg.508226806 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 8299481105 ps |
| CPU time | 85.4 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:12:13 PM PST 24 |
| Peak memory | 197864 kb |
| Host | smart-918c1b36-077d-4051-8919-c7f0bd7d9e8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508226806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.508226806 |
| Directory | /workspace/37.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/37.hmac_smoke.1820466863 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 97917128 ps |
| CPU time | 2.53 seconds |
| Started | Mar 05 01:10:47 PM PST 24 |
| Finished | Mar 05 01:10:50 PM PST 24 |
| Peak memory | 198768 kb |
| Host | smart-4fba111b-a4fa-4b27-91b6-4972a20455e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820466863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1820466863 |
| Directory | /workspace/37.hmac_smoke/latest |
| Test location | /workspace/coverage/default/37.hmac_stress_all.222672262 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 114404766425 ps |
| CPU time | 1323.79 seconds |
| Started | Mar 05 01:10:54 PM PST 24 |
| Finished | Mar 05 01:32:58 PM PST 24 |
| Peak memory | 207284 kb |
| Host | smart-19cbaecc-0c92-4cec-bbf6-b066b6937a5e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222672262 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.222672262 |
| Directory | /workspace/37.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/37.hmac_test_hmac_vectors.116301879 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 33582808 ps |
| CPU time | 1.05 seconds |
| Started | Mar 05 01:10:58 PM PST 24 |
| Finished | Mar 05 01:10:59 PM PST 24 |
| Peak memory | 197496 kb |
| Host | smart-5757a0c1-0f7b-41d1-83be-e1fcd45299ca |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116301879 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 37.hmac_test_hmac_vectors.116301879 |
| Directory | /workspace/37.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/37.hmac_wipe_secret.372244238 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 7080042017 ps |
| CPU time | 35.25 seconds |
| Started | Mar 05 01:10:51 PM PST 24 |
| Finished | Mar 05 01:11:26 PM PST 24 |
| Peak memory | 199084 kb |
| Host | smart-0f399cdb-241f-4b6f-99c3-49c0b285c020 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372244238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.372244238 |
| Directory | /workspace/37.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/38.hmac_alert_test.3106407227 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 22592874 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:10:51 PM PST 24 |
| Finished | Mar 05 01:10:52 PM PST 24 |
| Peak memory | 193368 kb |
| Host | smart-a4ebeb19-4295-4e84-94ed-24904399ca85 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106407227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3106407227 |
| Directory | /workspace/38.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/38.hmac_back_pressure.1938915873 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1023308099 ps |
| CPU time | 17 seconds |
| Started | Mar 05 01:10:52 PM PST 24 |
| Finished | Mar 05 01:11:09 PM PST 24 |
| Peak memory | 207100 kb |
| Host | smart-6e64ac5c-516e-437d-84c5-2dbcb0f1b863 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1938915873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1938915873 |
| Directory | /workspace/38.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/38.hmac_burst_wr.3660001136 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1725218236 ps |
| CPU time | 19.19 seconds |
| Started | Mar 05 01:11:02 PM PST 24 |
| Finished | Mar 05 01:11:21 PM PST 24 |
| Peak memory | 198968 kb |
| Host | smart-58a58287-5af8-4269-8f07-a2ae051eda71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660001136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3660001136 |
| Directory | /workspace/38.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/38.hmac_datapath_stress.2017861889 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 784393803 ps |
| CPU time | 21.18 seconds |
| Started | Mar 05 01:10:55 PM PST 24 |
| Finished | Mar 05 01:11:16 PM PST 24 |
| Peak memory | 198888 kb |
| Host | smart-98471c83-0a50-4d6c-aa31-991dd4cd8275 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2017861889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2017861889 |
| Directory | /workspace/38.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/38.hmac_long_msg.816166359 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3764515079 ps |
| CPU time | 47.49 seconds |
| Started | Mar 05 01:10:53 PM PST 24 |
| Finished | Mar 05 01:11:40 PM PST 24 |
| Peak memory | 199056 kb |
| Host | smart-7201bbad-1f8f-492a-8f8c-aa110ebd08a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816166359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.816166359 |
| Directory | /workspace/38.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/38.hmac_smoke.2170150064 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 898267175 ps |
| CPU time | 3.65 seconds |
| Started | Mar 05 01:12:54 PM PST 24 |
| Finished | Mar 05 01:12:59 PM PST 24 |
| Peak memory | 198764 kb |
| Host | smart-563894bf-5ce6-406e-b5f7-0380c46d80ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2170150064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2170150064 |
| Directory | /workspace/38.hmac_smoke/latest |
| Test location | /workspace/coverage/default/38.hmac_test_hmac_vectors.515839694 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 266985190 ps |
| CPU time | 0.91 seconds |
| Started | Mar 05 01:12:55 PM PST 24 |
| Finished | Mar 05 01:12:56 PM PST 24 |
| Peak memory | 196752 kb |
| Host | smart-e97689fe-b596-42da-9e6b-7b61be049083 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515839694 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 38.hmac_test_hmac_vectors.515839694 |
| Directory | /workspace/38.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/38.hmac_test_sha_vectors.1286621694 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 26678263750 ps |
| CPU time | 449.19 seconds |
| Started | Mar 05 01:10:55 PM PST 24 |
| Finished | Mar 05 01:18:24 PM PST 24 |
| Peak memory | 199032 kb |
| Host | smart-e8330e59-03ca-48da-9fc6-cbc74e10feac |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286621694 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 38.hmac_test_sha_vectors.1286621694 |
| Directory | /workspace/38.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/38.hmac_wipe_secret.2254220821 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 14254987541 ps |
| CPU time | 44.61 seconds |
| Started | Mar 05 01:10:55 PM PST 24 |
| Finished | Mar 05 01:11:40 PM PST 24 |
| Peak memory | 199024 kb |
| Host | smart-64732766-f1a4-4fdf-a1f6-77f346f12fe7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254220821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2254220821 |
| Directory | /workspace/38.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/39.hmac_alert_test.3198100061 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 12664586 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:11:22 PM PST 24 |
| Finished | Mar 05 01:11:22 PM PST 24 |
| Peak memory | 193528 kb |
| Host | smart-8b7e7957-bee6-4504-8bb2-58bbf7d54c3e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198100061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3198100061 |
| Directory | /workspace/39.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/39.hmac_back_pressure.4011563651 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3667110772 ps |
| CPU time | 30.97 seconds |
| Started | Mar 05 01:11:06 PM PST 24 |
| Finished | Mar 05 01:11:37 PM PST 24 |
| Peak memory | 225312 kb |
| Host | smart-2965587b-2214-496d-9d6d-165a35f87680 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4011563651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.4011563651 |
| Directory | /workspace/39.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/39.hmac_burst_wr.2904545767 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 4152764598 ps |
| CPU time | 26.78 seconds |
| Started | Mar 05 01:10:58 PM PST 24 |
| Finished | Mar 05 01:11:25 PM PST 24 |
| Peak memory | 199048 kb |
| Host | smart-f27319a1-3de9-4690-9646-076dfd5b57b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2904545767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2904545767 |
| Directory | /workspace/39.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/39.hmac_datapath_stress.1268199112 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3116270588 ps |
| CPU time | 37.24 seconds |
| Started | Mar 05 01:11:06 PM PST 24 |
| Finished | Mar 05 01:11:44 PM PST 24 |
| Peak memory | 198952 kb |
| Host | smart-aed7a967-9c17-4bef-964f-cff66deaf9d2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1268199112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1268199112 |
| Directory | /workspace/39.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/39.hmac_error.1671960513 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 10347559627 ps |
| CPU time | 119.04 seconds |
| Started | Mar 05 01:10:51 PM PST 24 |
| Finished | Mar 05 01:12:51 PM PST 24 |
| Peak memory | 199100 kb |
| Host | smart-62d99dd2-7a4d-4376-a996-9c3702c67b0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671960513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1671960513 |
| Directory | /workspace/39.hmac_error/latest |
| Test location | /workspace/coverage/default/39.hmac_long_msg.4047652794 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1862816799 ps |
| CPU time | 20.93 seconds |
| Started | Mar 05 01:10:58 PM PST 24 |
| Finished | Mar 05 01:11:19 PM PST 24 |
| Peak memory | 198880 kb |
| Host | smart-ca09df34-9239-4a1d-82c2-1fbfbf471894 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047652794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.4047652794 |
| Directory | /workspace/39.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/39.hmac_smoke.129814103 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 235496345 ps |
| CPU time | 2.82 seconds |
| Started | Mar 05 01:11:02 PM PST 24 |
| Finished | Mar 05 01:11:05 PM PST 24 |
| Peak memory | 198932 kb |
| Host | smart-b8b9638d-3b05-4849-86cf-249f59a01511 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=129814103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.129814103 |
| Directory | /workspace/39.hmac_smoke/latest |
| Test location | /workspace/coverage/default/39.hmac_stress_all.4052408711 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2398132326 ps |
| CPU time | 36.26 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:13:15 PM PST 24 |
| Peak memory | 196760 kb |
| Host | smart-2a9fa5fe-1e7f-4383-951e-bc1c9fc5cb8e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052408711 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4052408711 |
| Directory | /workspace/39.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/39.hmac_test_hmac_vectors.631243916 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 87427477 ps |
| CPU time | 0.91 seconds |
| Started | Mar 05 01:12:55 PM PST 24 |
| Finished | Mar 05 01:12:56 PM PST 24 |
| Peak memory | 196576 kb |
| Host | smart-cdf26cdb-125e-444d-aea4-6e53b6a6838e |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631243916 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 39.hmac_test_hmac_vectors.631243916 |
| Directory | /workspace/39.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/39.hmac_test_sha_vectors.1319891760 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 53184692029 ps |
| CPU time | 397.16 seconds |
| Started | Mar 05 01:12:55 PM PST 24 |
| Finished | Mar 05 01:19:33 PM PST 24 |
| Peak memory | 198852 kb |
| Host | smart-b4a4e5a8-b376-4c2b-b2c5-9aa06f508178 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319891760 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 39.hmac_test_sha_vectors.1319891760 |
| Directory | /workspace/39.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/39.hmac_wipe_secret.1687582378 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2836485237 ps |
| CPU time | 37.87 seconds |
| Started | Mar 05 01:10:57 PM PST 24 |
| Finished | Mar 05 01:11:35 PM PST 24 |
| Peak memory | 198996 kb |
| Host | smart-2f8bf546-d158-45c4-adf3-614a6d50f3eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1687582378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1687582378 |
| Directory | /workspace/39.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/4.hmac_alert_test.665995066 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 14593170 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:09:57 PM PST 24 |
| Finished | Mar 05 01:09:58 PM PST 24 |
| Peak memory | 193616 kb |
| Host | smart-24a295e2-3bff-41e4-914d-a5cab29157ed |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665995066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.665995066 |
| Directory | /workspace/4.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/4.hmac_back_pressure.1146847751 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 279873194 ps |
| CPU time | 7.98 seconds |
| Started | Mar 05 01:09:49 PM PST 24 |
| Finished | Mar 05 01:10:00 PM PST 24 |
| Peak memory | 214396 kb |
| Host | smart-58f5bb64-3c47-4a9b-a7ca-543980e5cd9d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1146847751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1146847751 |
| Directory | /workspace/4.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/4.hmac_burst_wr.2246564620 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 57712364 ps |
| CPU time | 2.77 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:10:00 PM PST 24 |
| Peak memory | 198920 kb |
| Host | smart-ab0b9523-e428-4de8-a7a7-3762b05ac4c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246564620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2246564620 |
| Directory | /workspace/4.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/4.hmac_datapath_stress.1022317687 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 24268525873 ps |
| CPU time | 106.38 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:11:41 PM PST 24 |
| Peak memory | 198988 kb |
| Host | smart-f06b5690-9ca6-43df-9a2c-84f73b381893 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1022317687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1022317687 |
| Directory | /workspace/4.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/4.hmac_error.4064905807 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 6285344734 ps |
| CPU time | 73.33 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:11:08 PM PST 24 |
| Peak memory | 199056 kb |
| Host | smart-a30ee8f4-253c-49ad-9b20-c213b8120a79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4064905807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.4064905807 |
| Directory | /workspace/4.hmac_error/latest |
| Test location | /workspace/coverage/default/4.hmac_long_msg.1746574855 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1184569350 ps |
| CPU time | 64.35 seconds |
| Started | Mar 05 01:09:57 PM PST 24 |
| Finished | Mar 05 01:11:02 PM PST 24 |
| Peak memory | 198948 kb |
| Host | smart-d59cc06b-f6c1-4c80-a6d8-031ab628e4d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746574855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1746574855 |
| Directory | /workspace/4.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/4.hmac_sec_cm.3031317224 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 236336359 ps |
| CPU time | 0.9 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:09:57 PM PST 24 |
| Peak memory | 216292 kb |
| Host | smart-39f57773-27e8-4ab4-a8f7-ec9edc0f755d |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031317224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3031317224 |
| Directory | /workspace/4.hmac_sec_cm/latest |
| Test location | /workspace/coverage/default/4.hmac_smoke.1583717734 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 293244177 ps |
| CPU time | 3.49 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:10:02 PM PST 24 |
| Peak memory | 198820 kb |
| Host | smart-95ce0b18-5429-4e2d-952e-ce89bcf8a389 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1583717734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1583717734 |
| Directory | /workspace/4.hmac_smoke/latest |
| Test location | /workspace/coverage/default/4.hmac_stress_all.1722982339 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 8171381550 ps |
| CPU time | 382.16 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:16:18 PM PST 24 |
| Peak memory | 232516 kb |
| Host | smart-cd9190d6-a280-4063-b1fe-58aec80c8c98 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722982339 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1722982339 |
| Directory | /workspace/4.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/4.hmac_test_hmac_vectors.2696171061 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 103997096 ps |
| CPU time | 0.88 seconds |
| Started | Mar 05 01:09:57 PM PST 24 |
| Finished | Mar 05 01:09:58 PM PST 24 |
| Peak memory | 196284 kb |
| Host | smart-f1e1d028-8e33-45aa-9a68-6be7813eaa78 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696171061 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.hmac_test_hmac_vectors.2696171061 |
| Directory | /workspace/4.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/4.hmac_test_sha_vectors.379818891 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 146764173425 ps |
| CPU time | 477.6 seconds |
| Started | Mar 05 01:09:58 PM PST 24 |
| Finished | Mar 05 01:17:56 PM PST 24 |
| Peak memory | 199064 kb |
| Host | smart-777a528f-4811-4361-8f29-93332aa911a5 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379818891 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.hmac_test_sha_vectors.379818891 |
| Directory | /workspace/4.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/4.hmac_wipe_secret.3693215416 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2213347374 ps |
| CPU time | 37.51 seconds |
| Started | Mar 05 01:09:51 PM PST 24 |
| Finished | Mar 05 01:10:30 PM PST 24 |
| Peak memory | 198996 kb |
| Host | smart-b0613480-c700-46a3-963d-7791f5983b8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693215416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3693215416 |
| Directory | /workspace/4.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/40.hmac_alert_test.2768572646 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 54622326 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 01:11:06 PM PST 24 |
| Finished | Mar 05 01:11:06 PM PST 24 |
| Peak memory | 194336 kb |
| Host | smart-09f7b367-a1f3-4359-88ec-cb6b7411e7fc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768572646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2768572646 |
| Directory | /workspace/40.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/40.hmac_back_pressure.3172099863 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2818406505 ps |
| CPU time | 46.03 seconds |
| Started | Mar 05 01:10:58 PM PST 24 |
| Finished | Mar 05 01:11:44 PM PST 24 |
| Peak memory | 231764 kb |
| Host | smart-20102718-84e8-42dc-94c9-900f4c9c09db |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3172099863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3172099863 |
| Directory | /workspace/40.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/40.hmac_burst_wr.2157770213 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1973224718 ps |
| CPU time | 37.33 seconds |
| Started | Mar 05 01:10:55 PM PST 24 |
| Finished | Mar 05 01:11:32 PM PST 24 |
| Peak memory | 198936 kb |
| Host | smart-e85b64bb-53d3-4545-9bb8-0c2e0f074b1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157770213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2157770213 |
| Directory | /workspace/40.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/40.hmac_datapath_stress.3667516534 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 11545853327 ps |
| CPU time | 107.4 seconds |
| Started | Mar 05 01:10:50 PM PST 24 |
| Finished | Mar 05 01:12:37 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-d27f2ec7-b011-4aba-8643-4c4ebf5ac7f6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3667516534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3667516534 |
| Directory | /workspace/40.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/40.hmac_error.2459329000 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4063620154 ps |
| CPU time | 49.96 seconds |
| Started | Mar 05 01:10:53 PM PST 24 |
| Finished | Mar 05 01:11:43 PM PST 24 |
| Peak memory | 199120 kb |
| Host | smart-c3a98216-2e06-4ec2-ab34-258a6c136574 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2459329000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2459329000 |
| Directory | /workspace/40.hmac_error/latest |
| Test location | /workspace/coverage/default/40.hmac_long_msg.438715583 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 181043158 ps |
| CPU time | 3.06 seconds |
| Started | Mar 05 01:11:02 PM PST 24 |
| Finished | Mar 05 01:11:05 PM PST 24 |
| Peak memory | 198932 kb |
| Host | smart-c68dc149-82e9-4807-8d86-1d729dbff3fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438715583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.438715583 |
| Directory | /workspace/40.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/40.hmac_smoke.2764099870 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 504020607 ps |
| CPU time | 3.04 seconds |
| Started | Mar 05 01:11:02 PM PST 24 |
| Finished | Mar 05 01:11:05 PM PST 24 |
| Peak memory | 198912 kb |
| Host | smart-afaa2258-c7ba-49dd-b585-3509d96856f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2764099870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2764099870 |
| Directory | /workspace/40.hmac_smoke/latest |
| Test location | /workspace/coverage/default/40.hmac_stress_all.1173620798 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 299714914658 ps |
| CPU time | 207.3 seconds |
| Started | Mar 05 01:11:06 PM PST 24 |
| Finished | Mar 05 01:14:34 PM PST 24 |
| Peak memory | 215408 kb |
| Host | smart-48cffac0-84eb-4099-9b3e-273b9b53124a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173620798 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1173620798 |
| Directory | /workspace/40.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/40.hmac_test_hmac_vectors.64025810 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 144383801 ps |
| CPU time | 1.23 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:12:40 PM PST 24 |
| Peak memory | 196128 kb |
| Host | smart-53e1bc0b-7b16-46ea-8082-125dcb8cff2f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64025810 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 40.hmac_test_hmac_vectors.64025810 |
| Directory | /workspace/40.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/40.hmac_test_sha_vectors.2644260001 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 43004378817 ps |
| CPU time | 454.51 seconds |
| Started | Mar 05 01:10:52 PM PST 24 |
| Finished | Mar 05 01:18:27 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-2427d3d6-1015-4447-92b5-365631782c13 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644260001 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 40.hmac_test_sha_vectors.2644260001 |
| Directory | /workspace/40.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/40.hmac_wipe_secret.1548996072 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 17022816517 ps |
| CPU time | 21.61 seconds |
| Started | Mar 05 01:10:55 PM PST 24 |
| Finished | Mar 05 01:11:17 PM PST 24 |
| Peak memory | 199076 kb |
| Host | smart-88d6b7d8-4959-4fad-a523-46f9f4f1f9ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548996072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1548996072 |
| Directory | /workspace/40.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/41.hmac_alert_test.367657688 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 58725159 ps |
| CPU time | 0.67 seconds |
| Started | Mar 05 01:11:01 PM PST 24 |
| Finished | Mar 05 01:11:01 PM PST 24 |
| Peak memory | 193392 kb |
| Host | smart-87b8fa09-35f3-42c6-9780-6fe817839e96 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367657688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.367657688 |
| Directory | /workspace/41.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/41.hmac_back_pressure.586951524 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1210028128 ps |
| CPU time | 39.29 seconds |
| Started | Mar 05 01:11:06 PM PST 24 |
| Finished | Mar 05 01:11:46 PM PST 24 |
| Peak memory | 209056 kb |
| Host | smart-0a380f07-85c8-4455-9080-f79346468280 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=586951524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.586951524 |
| Directory | /workspace/41.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/41.hmac_burst_wr.2331224584 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1439281631 ps |
| CPU time | 7.39 seconds |
| Started | Mar 05 01:10:58 PM PST 24 |
| Finished | Mar 05 01:11:05 PM PST 24 |
| Peak memory | 198840 kb |
| Host | smart-48afa8ad-e958-4f75-a721-57408042870f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2331224584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2331224584 |
| Directory | /workspace/41.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/41.hmac_datapath_stress.1046821207 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 4699257519 ps |
| CPU time | 118.31 seconds |
| Started | Mar 05 01:12:54 PM PST 24 |
| Finished | Mar 05 01:14:53 PM PST 24 |
| Peak memory | 198848 kb |
| Host | smart-f4352be8-c9c2-4f79-ab06-1c4540566a78 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1046821207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1046821207 |
| Directory | /workspace/41.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/41.hmac_error.620036386 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 16457784518 ps |
| CPU time | 186.53 seconds |
| Started | Mar 05 01:11:01 PM PST 24 |
| Finished | Mar 05 01:14:08 PM PST 24 |
| Peak memory | 199020 kb |
| Host | smart-203dbd88-200d-41d7-bdc6-fd7fa340dc00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620036386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.620036386 |
| Directory | /workspace/41.hmac_error/latest |
| Test location | /workspace/coverage/default/41.hmac_long_msg.680861611 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 313087110 ps |
| CPU time | 15.07 seconds |
| Started | Mar 05 01:12:39 PM PST 24 |
| Finished | Mar 05 01:12:54 PM PST 24 |
| Peak memory | 196836 kb |
| Host | smart-d1963ba5-0191-43ce-b7cf-809488c840f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680861611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.680861611 |
| Directory | /workspace/41.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/41.hmac_smoke.744773581 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 505420439 ps |
| CPU time | 2.97 seconds |
| Started | Mar 05 01:12:55 PM PST 24 |
| Finished | Mar 05 01:12:58 PM PST 24 |
| Peak memory | 198696 kb |
| Host | smart-42b3b389-c7cc-4427-90d6-7ae522a28228 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744773581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.744773581 |
| Directory | /workspace/41.hmac_smoke/latest |
| Test location | /workspace/coverage/default/41.hmac_stress_all.2606794268 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 151923934695 ps |
| CPU time | 465.9 seconds |
| Started | Mar 05 01:11:00 PM PST 24 |
| Finished | Mar 05 01:18:46 PM PST 24 |
| Peak memory | 231672 kb |
| Host | smart-f8443e52-bbf8-454e-8c07-57b1d2721b53 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606794268 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2606794268 |
| Directory | /workspace/41.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/41.hmac_test_hmac_vectors.1002202145 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 31366161 ps |
| CPU time | 1.12 seconds |
| Started | Mar 05 01:11:00 PM PST 24 |
| Finished | Mar 05 01:11:01 PM PST 24 |
| Peak memory | 198876 kb |
| Host | smart-f7ea6f4f-402a-4392-a289-0937dc52deda |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002202145 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.hmac_test_hmac_vectors.1002202145 |
| Directory | /workspace/41.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/41.hmac_test_sha_vectors.3788152574 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 180675522586 ps |
| CPU time | 505.83 seconds |
| Started | Mar 05 01:11:00 PM PST 24 |
| Finished | Mar 05 01:19:26 PM PST 24 |
| Peak memory | 199020 kb |
| Host | smart-2f68094e-4a35-424e-9539-28043e0f9374 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788152574 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 41.hmac_test_sha_vectors.3788152574 |
| Directory | /workspace/41.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/41.hmac_wipe_secret.1015292131 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3243922563 ps |
| CPU time | 57.72 seconds |
| Started | Mar 05 01:11:00 PM PST 24 |
| Finished | Mar 05 01:11:58 PM PST 24 |
| Peak memory | 198996 kb |
| Host | smart-408edfe7-628f-4e32-b8b2-04ac7238d019 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1015292131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1015292131 |
| Directory | /workspace/41.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/42.hmac_alert_test.1587515025 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 34365863 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:11:04 PM PST 24 |
| Finished | Mar 05 01:11:04 PM PST 24 |
| Peak memory | 193336 kb |
| Host | smart-83de9a2f-859c-4103-9053-330c542dd735 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587515025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1587515025 |
| Directory | /workspace/42.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/42.hmac_back_pressure.882477836 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 5617780826 ps |
| CPU time | 44.65 seconds |
| Started | Mar 05 01:11:01 PM PST 24 |
| Finished | Mar 05 01:11:46 PM PST 24 |
| Peak memory | 207188 kb |
| Host | smart-c077b2c7-b073-414c-82d3-9ccc2d8732a0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=882477836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.882477836 |
| Directory | /workspace/42.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/42.hmac_burst_wr.1272200293 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 518263180 ps |
| CPU time | 19.56 seconds |
| Started | Mar 05 01:11:00 PM PST 24 |
| Finished | Mar 05 01:11:20 PM PST 24 |
| Peak memory | 198844 kb |
| Host | smart-961d6693-04ce-452f-9ead-9424ed836356 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272200293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1272200293 |
| Directory | /workspace/42.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/42.hmac_datapath_stress.3805223884 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5665843180 ps |
| CPU time | 73.03 seconds |
| Started | Mar 05 01:11:02 PM PST 24 |
| Finished | Mar 05 01:12:15 PM PST 24 |
| Peak memory | 198968 kb |
| Host | smart-20efeaf9-41c8-4e8a-9529-a8cd1bb11838 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3805223884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3805223884 |
| Directory | /workspace/42.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/42.hmac_error.689070837 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 11062450856 ps |
| CPU time | 132.35 seconds |
| Started | Mar 05 01:11:01 PM PST 24 |
| Finished | Mar 05 01:13:13 PM PST 24 |
| Peak memory | 199128 kb |
| Host | smart-73081473-79be-48cb-b0ab-1f819eb297c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689070837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.689070837 |
| Directory | /workspace/42.hmac_error/latest |
| Test location | /workspace/coverage/default/42.hmac_long_msg.2440828221 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 5232430754 ps |
| CPU time | 34.8 seconds |
| Started | Mar 05 01:11:01 PM PST 24 |
| Finished | Mar 05 01:11:36 PM PST 24 |
| Peak memory | 198968 kb |
| Host | smart-6b0956d9-0338-4619-8b5e-c89752380214 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440828221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2440828221 |
| Directory | /workspace/42.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/42.hmac_smoke.84372452 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 197985920 ps |
| CPU time | 2.69 seconds |
| Started | Mar 05 01:11:00 PM PST 24 |
| Finished | Mar 05 01:11:03 PM PST 24 |
| Peak memory | 198960 kb |
| Host | smart-8bea0c5c-8770-4ad6-95aa-4b7a2958ab34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84372452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.84372452 |
| Directory | /workspace/42.hmac_smoke/latest |
| Test location | /workspace/coverage/default/42.hmac_stress_all.169085898 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 33656591838 ps |
| CPU time | 595.71 seconds |
| Started | Mar 05 01:10:59 PM PST 24 |
| Finished | Mar 05 01:20:55 PM PST 24 |
| Peak memory | 207320 kb |
| Host | smart-fb71e753-0048-4e2d-95ef-08449f192678 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169085898 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.169085898 |
| Directory | /workspace/42.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/42.hmac_test_hmac_vectors.2930358958 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 99169157 ps |
| CPU time | 1.18 seconds |
| Started | Mar 05 01:11:02 PM PST 24 |
| Finished | Mar 05 01:11:04 PM PST 24 |
| Peak memory | 197992 kb |
| Host | smart-c438bcfb-3b4d-4be7-b32c-a2a345f07615 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930358958 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 42.hmac_test_hmac_vectors.2930358958 |
| Directory | /workspace/42.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/42.hmac_test_sha_vectors.3487974363 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 125505711493 ps |
| CPU time | 425.4 seconds |
| Started | Mar 05 01:11:02 PM PST 24 |
| Finished | Mar 05 01:18:08 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-c50baa6b-2f3e-498e-a754-c44eabcf6348 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487974363 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 42.hmac_test_sha_vectors.3487974363 |
| Directory | /workspace/42.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/42.hmac_wipe_secret.3384751798 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 364227878 ps |
| CPU time | 19.08 seconds |
| Started | Mar 05 01:11:02 PM PST 24 |
| Finished | Mar 05 01:11:21 PM PST 24 |
| Peak memory | 198900 kb |
| Host | smart-2f669ca6-8087-4681-8e76-b076d1c3a605 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3384751798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3384751798 |
| Directory | /workspace/42.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/43.hmac_alert_test.3248179992 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13271291 ps |
| CPU time | 0.59 seconds |
| Started | Mar 05 01:11:15 PM PST 24 |
| Finished | Mar 05 01:11:17 PM PST 24 |
| Peak memory | 193548 kb |
| Host | smart-f0db4b8f-480b-4048-aa05-4f5d8b5e9306 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248179992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3248179992 |
| Directory | /workspace/43.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/43.hmac_back_pressure.1084618437 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 27197920046 ps |
| CPU time | 45.19 seconds |
| Started | Mar 05 01:11:02 PM PST 24 |
| Finished | Mar 05 01:11:48 PM PST 24 |
| Peak memory | 207308 kb |
| Host | smart-7eb8a27e-51fa-4c6c-811a-2b7a03bd86fb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1084618437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1084618437 |
| Directory | /workspace/43.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/43.hmac_burst_wr.283752110 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 6854171271 ps |
| CPU time | 35.37 seconds |
| Started | Mar 05 01:11:01 PM PST 24 |
| Finished | Mar 05 01:11:37 PM PST 24 |
| Peak memory | 199052 kb |
| Host | smart-6bd89639-a6f7-4a23-980e-9e897bd24d99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283752110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.283752110 |
| Directory | /workspace/43.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/43.hmac_datapath_stress.2004148831 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 607668592 ps |
| CPU time | 9.23 seconds |
| Started | Mar 05 01:11:01 PM PST 24 |
| Finished | Mar 05 01:11:10 PM PST 24 |
| Peak memory | 198896 kb |
| Host | smart-b0969f9f-b29f-488f-9c6f-6a6cafe306c4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2004148831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2004148831 |
| Directory | /workspace/43.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/43.hmac_error.94062937 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 22047481109 ps |
| CPU time | 179.15 seconds |
| Started | Mar 05 01:11:20 PM PST 24 |
| Finished | Mar 05 01:14:20 PM PST 24 |
| Peak memory | 199108 kb |
| Host | smart-9cd32e4e-04fe-4b05-813a-4c31976dca6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94062937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.94062937 |
| Directory | /workspace/43.hmac_error/latest |
| Test location | /workspace/coverage/default/43.hmac_long_msg.321992216 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 1084381741 ps |
| CPU time | 60.4 seconds |
| Started | Mar 05 01:11:02 PM PST 24 |
| Finished | Mar 05 01:12:02 PM PST 24 |
| Peak memory | 198948 kb |
| Host | smart-d4b4f199-2d4b-41c3-a7c4-f19ea18adf20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=321992216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.321992216 |
| Directory | /workspace/43.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/43.hmac_smoke.3334426962 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 268134785 ps |
| CPU time | 1.38 seconds |
| Started | Mar 05 01:11:01 PM PST 24 |
| Finished | Mar 05 01:11:03 PM PST 24 |
| Peak memory | 197820 kb |
| Host | smart-6d293c04-540d-4648-a0fd-419b44da7697 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3334426962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3334426962 |
| Directory | /workspace/43.hmac_smoke/latest |
| Test location | /workspace/coverage/default/43.hmac_stress_all.2834518256 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 36028835816 ps |
| CPU time | 612.66 seconds |
| Started | Mar 05 01:11:18 PM PST 24 |
| Finished | Mar 05 01:21:31 PM PST 24 |
| Peak memory | 231656 kb |
| Host | smart-ce90f77c-7cc3-4be4-b1d0-af3b07ec672f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834518256 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2834518256 |
| Directory | /workspace/43.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/43.hmac_test_hmac_vectors.3455026637 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 63811624 ps |
| CPU time | 0.99 seconds |
| Started | Mar 05 01:11:14 PM PST 24 |
| Finished | Mar 05 01:11:15 PM PST 24 |
| Peak memory | 197360 kb |
| Host | smart-d5e3b3e6-abcf-4a57-81ce-9e1a39f940b0 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455026637 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.hmac_test_hmac_vectors.3455026637 |
| Directory | /workspace/43.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/43.hmac_test_sha_vectors.3102242996 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 126164413364 ps |
| CPU time | 430.09 seconds |
| Started | Mar 05 01:11:13 PM PST 24 |
| Finished | Mar 05 01:18:23 PM PST 24 |
| Peak memory | 198940 kb |
| Host | smart-0c77738d-89b2-4efc-8edf-c84355477b20 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102242996 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 43.hmac_test_sha_vectors.3102242996 |
| Directory | /workspace/43.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/43.hmac_wipe_secret.1988431901 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 35217525168 ps |
| CPU time | 77.62 seconds |
| Started | Mar 05 01:11:15 PM PST 24 |
| Finished | Mar 05 01:12:32 PM PST 24 |
| Peak memory | 199056 kb |
| Host | smart-fe859fd4-e100-4ccc-bd64-0831c78559e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988431901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1988431901 |
| Directory | /workspace/43.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/44.hmac_alert_test.673882656 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 34174965 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:11:17 PM PST 24 |
| Finished | Mar 05 01:11:17 PM PST 24 |
| Peak memory | 193364 kb |
| Host | smart-7d409d98-4bca-4ddc-8434-69a8cf87a3d7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673882656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.673882656 |
| Directory | /workspace/44.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/44.hmac_back_pressure.2165109108 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 5726138359 ps |
| CPU time | 44.58 seconds |
| Started | Mar 05 01:11:15 PM PST 24 |
| Finished | Mar 05 01:12:01 PM PST 24 |
| Peak memory | 215504 kb |
| Host | smart-9eda46b9-a3b7-4fe2-ad81-d7352eb86e0e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2165109108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2165109108 |
| Directory | /workspace/44.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/44.hmac_burst_wr.2291089825 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 366328763 ps |
| CPU time | 5.36 seconds |
| Started | Mar 05 01:11:15 PM PST 24 |
| Finished | Mar 05 01:11:20 PM PST 24 |
| Peak memory | 198992 kb |
| Host | smart-4e1ed193-d907-4420-9668-451bb9de82c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2291089825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2291089825 |
| Directory | /workspace/44.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/44.hmac_datapath_stress.3775520182 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1136018279 ps |
| CPU time | 59.5 seconds |
| Started | Mar 05 01:11:14 PM PST 24 |
| Finished | Mar 05 01:12:13 PM PST 24 |
| Peak memory | 198936 kb |
| Host | smart-2abcec35-d5ea-4670-9852-01bc1fda6d80 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3775520182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3775520182 |
| Directory | /workspace/44.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/44.hmac_error.291393704 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 487017215 ps |
| CPU time | 6.86 seconds |
| Started | Mar 05 01:11:14 PM PST 24 |
| Finished | Mar 05 01:11:21 PM PST 24 |
| Peak memory | 198940 kb |
| Host | smart-1cdfc9bd-31cf-40c7-81cc-8e1550da4c58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=291393704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.291393704 |
| Directory | /workspace/44.hmac_error/latest |
| Test location | /workspace/coverage/default/44.hmac_long_msg.3194270400 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 4757067031 ps |
| CPU time | 70.96 seconds |
| Started | Mar 05 01:11:14 PM PST 24 |
| Finished | Mar 05 01:12:25 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-3c8ab7bf-87ad-49ce-9095-8275cfe6c415 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194270400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3194270400 |
| Directory | /workspace/44.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/44.hmac_smoke.385947443 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 116651708 ps |
| CPU time | 2.81 seconds |
| Started | Mar 05 01:11:16 PM PST 24 |
| Finished | Mar 05 01:11:19 PM PST 24 |
| Peak memory | 198964 kb |
| Host | smart-012e32c1-282b-4cad-8dbb-be2a545d6919 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385947443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.385947443 |
| Directory | /workspace/44.hmac_smoke/latest |
| Test location | /workspace/coverage/default/44.hmac_stress_all.383952254 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 76449117805 ps |
| CPU time | 1069.64 seconds |
| Started | Mar 05 01:11:16 PM PST 24 |
| Finished | Mar 05 01:29:06 PM PST 24 |
| Peak memory | 223088 kb |
| Host | smart-f968a048-f610-4167-a3d8-28f3b3e69c5a |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383952254 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.383952254 |
| Directory | /workspace/44.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/44.hmac_test_hmac_vectors.975671533 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 65701593 ps |
| CPU time | 1.05 seconds |
| Started | Mar 05 01:11:15 PM PST 24 |
| Finished | Mar 05 01:11:16 PM PST 24 |
| Peak memory | 197568 kb |
| Host | smart-a3cb4762-0ede-41f6-b045-3b2ffec4cb74 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975671533 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 44.hmac_test_hmac_vectors.975671533 |
| Directory | /workspace/44.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/44.hmac_test_sha_vectors.134619606 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 56534615311 ps |
| CPU time | 463.53 seconds |
| Started | Mar 05 01:11:13 PM PST 24 |
| Finished | Mar 05 01:18:56 PM PST 24 |
| Peak memory | 198912 kb |
| Host | smart-13ab168c-c08d-4f6e-82b9-ff12c85bc437 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134619606 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 44.hmac_test_sha_vectors.134619606 |
| Directory | /workspace/44.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/44.hmac_wipe_secret.2230896657 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 11711537637 ps |
| CPU time | 18.42 seconds |
| Started | Mar 05 01:11:15 PM PST 24 |
| Finished | Mar 05 01:11:33 PM PST 24 |
| Peak memory | 199116 kb |
| Host | smart-1b335c16-6efd-42d1-a51a-9f3dd98cdf51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2230896657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2230896657 |
| Directory | /workspace/44.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/45.hmac_alert_test.2422224781 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 15167358 ps |
| CPU time | 0.6 seconds |
| Started | Mar 05 01:11:14 PM PST 24 |
| Finished | Mar 05 01:11:15 PM PST 24 |
| Peak memory | 194464 kb |
| Host | smart-e5729641-c8b7-4c29-ab77-659e2d5558d3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422224781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2422224781 |
| Directory | /workspace/45.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/45.hmac_back_pressure.3997286050 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1687586396 ps |
| CPU time | 67.43 seconds |
| Started | Mar 05 01:11:18 PM PST 24 |
| Finished | Mar 05 01:12:26 PM PST 24 |
| Peak memory | 231080 kb |
| Host | smart-f7cbe97e-c7d2-4b21-99b3-fe5af435e5ed |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3997286050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3997286050 |
| Directory | /workspace/45.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/45.hmac_burst_wr.1487265792 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 12871113102 ps |
| CPU time | 36.23 seconds |
| Started | Mar 05 01:11:13 PM PST 24 |
| Finished | Mar 05 01:11:49 PM PST 24 |
| Peak memory | 198992 kb |
| Host | smart-ab5ffc2a-87eb-4bcd-87fd-cb92686d2a47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487265792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1487265792 |
| Directory | /workspace/45.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/45.hmac_datapath_stress.3796522039 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2775215927 ps |
| CPU time | 42.64 seconds |
| Started | Mar 05 01:11:14 PM PST 24 |
| Finished | Mar 05 01:11:57 PM PST 24 |
| Peak memory | 199012 kb |
| Host | smart-7a106cb7-3593-478f-a881-83639d940a7b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3796522039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3796522039 |
| Directory | /workspace/45.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/45.hmac_error.2595909600 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1855984836 ps |
| CPU time | 93.63 seconds |
| Started | Mar 05 01:11:14 PM PST 24 |
| Finished | Mar 05 01:12:48 PM PST 24 |
| Peak memory | 198888 kb |
| Host | smart-20e09284-258b-4a34-846b-52268cb3bea8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2595909600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2595909600 |
| Directory | /workspace/45.hmac_error/latest |
| Test location | /workspace/coverage/default/45.hmac_long_msg.769446865 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 945842186 ps |
| CPU time | 24.92 seconds |
| Started | Mar 05 01:11:15 PM PST 24 |
| Finished | Mar 05 01:11:40 PM PST 24 |
| Peak memory | 198888 kb |
| Host | smart-83f6c4af-adcf-45d6-b1b4-32da00214634 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=769446865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.769446865 |
| Directory | /workspace/45.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/45.hmac_smoke.420983335 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2591174504 ps |
| CPU time | 2.18 seconds |
| Started | Mar 05 01:11:15 PM PST 24 |
| Finished | Mar 05 01:11:17 PM PST 24 |
| Peak memory | 199040 kb |
| Host | smart-25f96213-9cbd-48fb-a10c-c651eda54836 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420983335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.420983335 |
| Directory | /workspace/45.hmac_smoke/latest |
| Test location | /workspace/coverage/default/45.hmac_stress_all.1967476985 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 74773922388 ps |
| CPU time | 965.98 seconds |
| Started | Mar 05 01:11:15 PM PST 24 |
| Finished | Mar 05 01:27:21 PM PST 24 |
| Peak memory | 199120 kb |
| Host | smart-a72c9ff5-a3f7-4e90-b5f6-5f91985c4e98 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967476985 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1967476985 |
| Directory | /workspace/45.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/45.hmac_test_hmac_vectors.1021522937 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 47803281 ps |
| CPU time | 0.9 seconds |
| Started | Mar 05 01:11:14 PM PST 24 |
| Finished | Mar 05 01:11:15 PM PST 24 |
| Peak memory | 196348 kb |
| Host | smart-213fce9d-24b6-4d80-8691-21f1963961de |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021522937 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.hmac_test_hmac_vectors.1021522937 |
| Directory | /workspace/45.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/45.hmac_test_sha_vectors.2947616238 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 33505937624 ps |
| CPU time | 440.46 seconds |
| Started | Mar 05 01:11:14 PM PST 24 |
| Finished | Mar 05 01:18:34 PM PST 24 |
| Peak memory | 198984 kb |
| Host | smart-862b5dee-a0a6-4c48-8442-1a818ccccce8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947616238 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 45.hmac_test_sha_vectors.2947616238 |
| Directory | /workspace/45.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/46.hmac_alert_test.257928838 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 12747328 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:11:26 PM PST 24 |
| Finished | Mar 05 01:11:28 PM PST 24 |
| Peak memory | 193388 kb |
| Host | smart-7f91b26b-f6eb-4276-8547-ff00ffa6dae7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257928838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.257928838 |
| Directory | /workspace/46.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/46.hmac_back_pressure.250956402 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 834690431 ps |
| CPU time | 24.15 seconds |
| Started | Mar 05 01:11:12 PM PST 24 |
| Finished | Mar 05 01:11:37 PM PST 24 |
| Peak memory | 207156 kb |
| Host | smart-a056f044-8a6e-4480-8413-22f4c28ba8ab |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=250956402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.250956402 |
| Directory | /workspace/46.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/46.hmac_burst_wr.1951177934 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 8544838912 ps |
| CPU time | 74.19 seconds |
| Started | Mar 05 01:11:17 PM PST 24 |
| Finished | Mar 05 01:12:31 PM PST 24 |
| Peak memory | 199088 kb |
| Host | smart-75a99baa-903b-4a10-87ae-c7b80cfc758e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1951177934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1951177934 |
| Directory | /workspace/46.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/46.hmac_datapath_stress.854134706 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 924856612 ps |
| CPU time | 26.61 seconds |
| Started | Mar 05 01:11:12 PM PST 24 |
| Finished | Mar 05 01:11:39 PM PST 24 |
| Peak memory | 198904 kb |
| Host | smart-7905b467-87d1-48d5-90c1-2c303fa2de16 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=854134706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.854134706 |
| Directory | /workspace/46.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/46.hmac_error.1222667128 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4377740748 ps |
| CPU time | 52.68 seconds |
| Started | Mar 05 01:11:26 PM PST 24 |
| Finished | Mar 05 01:12:19 PM PST 24 |
| Peak memory | 198984 kb |
| Host | smart-8ed8052e-f798-4e79-b372-f0875a1c3018 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222667128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1222667128 |
| Directory | /workspace/46.hmac_error/latest |
| Test location | /workspace/coverage/default/46.hmac_long_msg.1903965803 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 3586493198 ps |
| CPU time | 33.42 seconds |
| Started | Mar 05 01:11:13 PM PST 24 |
| Finished | Mar 05 01:11:46 PM PST 24 |
| Peak memory | 199000 kb |
| Host | smart-3bfffa42-4ed0-4167-b6a4-b19003cd8056 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1903965803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1903965803 |
| Directory | /workspace/46.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/46.hmac_smoke.3857367099 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 179482765 ps |
| CPU time | 2.64 seconds |
| Started | Mar 05 01:11:17 PM PST 24 |
| Finished | Mar 05 01:11:19 PM PST 24 |
| Peak memory | 198856 kb |
| Host | smart-7176b70b-219d-40d7-81ac-31a569a82dda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857367099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3857367099 |
| Directory | /workspace/46.hmac_smoke/latest |
| Test location | /workspace/coverage/default/46.hmac_stress_all.2912117815 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 71791732510 ps |
| CPU time | 516.58 seconds |
| Started | Mar 05 01:11:26 PM PST 24 |
| Finished | Mar 05 01:20:05 PM PST 24 |
| Peak memory | 198952 kb |
| Host | smart-6de9843a-b18a-4f6a-8a47-67514e231af6 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912117815 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2912117815 |
| Directory | /workspace/46.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/46.hmac_test_hmac_vectors.1867095774 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 208624895 ps |
| CPU time | 1.23 seconds |
| Started | Mar 05 01:11:25 PM PST 24 |
| Finished | Mar 05 01:11:26 PM PST 24 |
| Peak memory | 197944 kb |
| Host | smart-28508a7b-5e70-4777-ae2b-393b9049a0eb |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867095774 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.hmac_test_hmac_vectors.1867095774 |
| Directory | /workspace/46.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/46.hmac_test_sha_vectors.2093343273 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 60887688991 ps |
| CPU time | 466.09 seconds |
| Started | Mar 05 01:11:24 PM PST 24 |
| Finished | Mar 05 01:19:10 PM PST 24 |
| Peak memory | 199036 kb |
| Host | smart-002bca68-fd1e-4392-b61a-620e140ccc38 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093343273 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 46.hmac_test_sha_vectors.2093343273 |
| Directory | /workspace/46.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/46.hmac_wipe_secret.1641002355 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2833858946 ps |
| CPU time | 41.26 seconds |
| Started | Mar 05 01:11:26 PM PST 24 |
| Finished | Mar 05 01:12:08 PM PST 24 |
| Peak memory | 199080 kb |
| Host | smart-69e7ddea-3bed-4885-8f70-a6728d0fd808 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641002355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1641002355 |
| Directory | /workspace/46.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/47.hmac_alert_test.2902747716 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 21422275 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:11:28 PM PST 24 |
| Finished | Mar 05 01:11:29 PM PST 24 |
| Peak memory | 193368 kb |
| Host | smart-573ff4a4-d2e6-47ad-b4ad-13e506064943 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902747716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2902747716 |
| Directory | /workspace/47.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/47.hmac_back_pressure.3720410675 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1420517057 ps |
| CPU time | 47.18 seconds |
| Started | Mar 05 01:11:28 PM PST 24 |
| Finished | Mar 05 01:12:16 PM PST 24 |
| Peak memory | 221472 kb |
| Host | smart-1a82b349-0d0e-4350-b314-af24dd46f971 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3720410675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3720410675 |
| Directory | /workspace/47.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/47.hmac_burst_wr.3766700663 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 83788392 ps |
| CPU time | 1.14 seconds |
| Started | Mar 05 01:11:31 PM PST 24 |
| Finished | Mar 05 01:11:33 PM PST 24 |
| Peak memory | 198864 kb |
| Host | smart-85f0592c-deaa-4f69-a82f-8c0ab43a7779 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766700663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3766700663 |
| Directory | /workspace/47.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/47.hmac_datapath_stress.2656905535 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 9375745856 ps |
| CPU time | 73.95 seconds |
| Started | Mar 05 01:11:27 PM PST 24 |
| Finished | Mar 05 01:12:42 PM PST 24 |
| Peak memory | 198996 kb |
| Host | smart-0f94e71a-f5af-4d32-a8ec-6f08eac1b543 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2656905535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2656905535 |
| Directory | /workspace/47.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/47.hmac_error.2205488665 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 5346216926 ps |
| CPU time | 15.51 seconds |
| Started | Mar 05 01:11:24 PM PST 24 |
| Finished | Mar 05 01:11:39 PM PST 24 |
| Peak memory | 199068 kb |
| Host | smart-4c5f57fe-a19e-4760-8483-eab9562f716b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205488665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2205488665 |
| Directory | /workspace/47.hmac_error/latest |
| Test location | /workspace/coverage/default/47.hmac_long_msg.333567235 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1204238482 ps |
| CPU time | 10.21 seconds |
| Started | Mar 05 01:11:28 PM PST 24 |
| Finished | Mar 05 01:11:40 PM PST 24 |
| Peak memory | 198896 kb |
| Host | smart-8b051ed3-1a11-4e29-9aa8-974ab143019a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=333567235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.333567235 |
| Directory | /workspace/47.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/47.hmac_smoke.517451161 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 422734466 ps |
| CPU time | 2.89 seconds |
| Started | Mar 05 01:11:28 PM PST 24 |
| Finished | Mar 05 01:11:32 PM PST 24 |
| Peak memory | 199000 kb |
| Host | smart-e0a1934f-7390-447d-b434-27aa91e0e168 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517451161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.517451161 |
| Directory | /workspace/47.hmac_smoke/latest |
| Test location | /workspace/coverage/default/47.hmac_stress_all.830426591 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1307633846 ps |
| CPU time | 52.95 seconds |
| Started | Mar 05 01:11:26 PM PST 24 |
| Finished | Mar 05 01:12:21 PM PST 24 |
| Peak memory | 231548 kb |
| Host | smart-de41efb9-6243-4d18-8ef2-1dab4f64eff8 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830426591 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.830426591 |
| Directory | /workspace/47.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/47.hmac_test_hmac_vectors.2811698734 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 44779932 ps |
| CPU time | 0.98 seconds |
| Started | Mar 05 01:11:25 PM PST 24 |
| Finished | Mar 05 01:11:27 PM PST 24 |
| Peak memory | 196852 kb |
| Host | smart-14a3ba9b-fda6-45c3-9e48-133cd51bbede |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811698734 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.hmac_test_hmac_vectors.2811698734 |
| Directory | /workspace/47.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/47.hmac_test_sha_vectors.223419583 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 15853327078 ps |
| CPU time | 392.12 seconds |
| Started | Mar 05 01:11:28 PM PST 24 |
| Finished | Mar 05 01:18:01 PM PST 24 |
| Peak memory | 198976 kb |
| Host | smart-71afcd60-2eed-4851-ba09-eb12694d5bfa |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223419583 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 47.hmac_test_sha_vectors.223419583 |
| Directory | /workspace/47.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/47.hmac_wipe_secret.1124707147 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 235757824 ps |
| CPU time | 10.39 seconds |
| Started | Mar 05 01:11:28 PM PST 24 |
| Finished | Mar 05 01:11:39 PM PST 24 |
| Peak memory | 198556 kb |
| Host | smart-5d64c907-3611-4e10-a04e-70262e8927cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124707147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1124707147 |
| Directory | /workspace/47.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/48.hmac_alert_test.614988339 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 71350147 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:11:25 PM PST 24 |
| Finished | Mar 05 01:11:25 PM PST 24 |
| Peak memory | 193280 kb |
| Host | smart-4350676b-308a-4c01-8f21-1a6395173fad |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614988339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.614988339 |
| Directory | /workspace/48.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/48.hmac_back_pressure.2068991278 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 220050857 ps |
| CPU time | 1.99 seconds |
| Started | Mar 05 01:11:24 PM PST 24 |
| Finished | Mar 05 01:11:27 PM PST 24 |
| Peak memory | 198900 kb |
| Host | smart-6f8e495e-e435-4dcf-833b-e6392329d81a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2068991278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2068991278 |
| Directory | /workspace/48.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/48.hmac_burst_wr.2153618845 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4417121886 ps |
| CPU time | 40.67 seconds |
| Started | Mar 05 01:11:31 PM PST 24 |
| Finished | Mar 05 01:12:12 PM PST 24 |
| Peak memory | 199104 kb |
| Host | smart-3affa5f0-6cb0-4e22-a77e-105fc8bed043 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153618845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2153618845 |
| Directory | /workspace/48.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/48.hmac_datapath_stress.424807449 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 587638188 ps |
| CPU time | 31.38 seconds |
| Started | Mar 05 01:11:24 PM PST 24 |
| Finished | Mar 05 01:11:56 PM PST 24 |
| Peak memory | 198936 kb |
| Host | smart-544c9d78-4f00-4865-8b82-35a63b689561 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=424807449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.424807449 |
| Directory | /workspace/48.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/48.hmac_error.399778081 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 7671491141 ps |
| CPU time | 109.89 seconds |
| Started | Mar 05 01:11:28 PM PST 24 |
| Finished | Mar 05 01:13:19 PM PST 24 |
| Peak memory | 198632 kb |
| Host | smart-31ed0800-7d04-40db-9fdb-571135d6ff92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399778081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.399778081 |
| Directory | /workspace/48.hmac_error/latest |
| Test location | /workspace/coverage/default/48.hmac_long_msg.3655394124 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 19434752145 ps |
| CPU time | 39.14 seconds |
| Started | Mar 05 01:11:28 PM PST 24 |
| Finished | Mar 05 01:12:08 PM PST 24 |
| Peak memory | 199004 kb |
| Host | smart-f46a12e2-6da7-4854-8698-ff69496fac4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655394124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3655394124 |
| Directory | /workspace/48.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/48.hmac_smoke.2525557056 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 15678335 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:11:25 PM PST 24 |
| Finished | Mar 05 01:11:27 PM PST 24 |
| Peak memory | 194708 kb |
| Host | smart-2f032b35-6a2b-4b94-8e5e-fb1be8910ca0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525557056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2525557056 |
| Directory | /workspace/48.hmac_smoke/latest |
| Test location | /workspace/coverage/default/48.hmac_stress_all.1388217064 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 34935145892 ps |
| CPU time | 417.51 seconds |
| Started | Mar 05 01:11:25 PM PST 24 |
| Finished | Mar 05 01:18:24 PM PST 24 |
| Peak memory | 199064 kb |
| Host | smart-9c11f958-f987-48ea-990e-81126e988c23 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388217064 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1388217064 |
| Directory | /workspace/48.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/48.hmac_test_hmac_vectors.412591604 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 90331387 ps |
| CPU time | 0.93 seconds |
| Started | Mar 05 01:11:32 PM PST 24 |
| Finished | Mar 05 01:11:34 PM PST 24 |
| Peak memory | 195800 kb |
| Host | smart-bb43743f-a534-4986-8cac-ebf5e6d8fac2 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412591604 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 48.hmac_test_hmac_vectors.412591604 |
| Directory | /workspace/48.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/48.hmac_test_sha_vectors.258925693 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 29799433564 ps |
| CPU time | 377.93 seconds |
| Started | Mar 05 01:11:26 PM PST 24 |
| Finished | Mar 05 01:17:45 PM PST 24 |
| Peak memory | 198980 kb |
| Host | smart-3c4f7821-06d5-4986-acc9-4dbdf3562fbf |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258925693 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 48.hmac_test_sha_vectors.258925693 |
| Directory | /workspace/48.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/48.hmac_wipe_secret.1351079273 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 5014181545 ps |
| CPU time | 79.9 seconds |
| Started | Mar 05 01:11:26 PM PST 24 |
| Finished | Mar 05 01:12:47 PM PST 24 |
| Peak memory | 199048 kb |
| Host | smart-1c8dcc21-eeb2-4253-83eb-9f7ca893bd08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1351079273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1351079273 |
| Directory | /workspace/48.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/49.hmac_alert_test.688863545 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 15033184 ps |
| CPU time | 0.61 seconds |
| Started | Mar 05 01:11:25 PM PST 24 |
| Finished | Mar 05 01:11:26 PM PST 24 |
| Peak memory | 193532 kb |
| Host | smart-c2f929c3-f6f9-4e84-b814-c0dd04176d09 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688863545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.688863545 |
| Directory | /workspace/49.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/49.hmac_back_pressure.3294675893 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 966573974 ps |
| CPU time | 14.61 seconds |
| Started | Mar 05 01:11:26 PM PST 24 |
| Finished | Mar 05 01:11:42 PM PST 24 |
| Peak memory | 198864 kb |
| Host | smart-bcd9871a-810d-43ca-869f-282de91b9941 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3294675893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3294675893 |
| Directory | /workspace/49.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/49.hmac_burst_wr.3200174486 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 207016781 ps |
| CPU time | 3.15 seconds |
| Started | Mar 05 01:11:28 PM PST 24 |
| Finished | Mar 05 01:11:32 PM PST 24 |
| Peak memory | 198904 kb |
| Host | smart-cf6d57bc-48f2-4c02-9f1f-ad80ccc37ed4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200174486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3200174486 |
| Directory | /workspace/49.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/49.hmac_datapath_stress.69322754 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7331254170 ps |
| CPU time | 97.06 seconds |
| Started | Mar 05 01:11:25 PM PST 24 |
| Finished | Mar 05 01:13:03 PM PST 24 |
| Peak memory | 199016 kb |
| Host | smart-9e76bdd2-5b51-40a5-bad5-af73d1b4e9bc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=69322754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.69322754 |
| Directory | /workspace/49.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/49.hmac_error.2429907332 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2853242617 ps |
| CPU time | 47.57 seconds |
| Started | Mar 05 01:11:26 PM PST 24 |
| Finished | Mar 05 01:12:15 PM PST 24 |
| Peak memory | 199000 kb |
| Host | smart-5b19aafc-08e9-43f2-975f-f0ec65c2e298 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429907332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2429907332 |
| Directory | /workspace/49.hmac_error/latest |
| Test location | /workspace/coverage/default/49.hmac_long_msg.622461016 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3520797804 ps |
| CPU time | 65.67 seconds |
| Started | Mar 05 01:11:32 PM PST 24 |
| Finished | Mar 05 01:12:39 PM PST 24 |
| Peak memory | 198584 kb |
| Host | smart-b85c1894-0683-4df1-a716-f7b9cf2918fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622461016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.622461016 |
| Directory | /workspace/49.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/49.hmac_smoke.4283858350 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 263988599 ps |
| CPU time | 3.3 seconds |
| Started | Mar 05 01:11:25 PM PST 24 |
| Finished | Mar 05 01:11:28 PM PST 24 |
| Peak memory | 198912 kb |
| Host | smart-fefa79d9-fa34-4de2-9cbb-522a185a41f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283858350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.4283858350 |
| Directory | /workspace/49.hmac_smoke/latest |
| Test location | /workspace/coverage/default/49.hmac_stress_all.380487723 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 71895136992 ps |
| CPU time | 1279.82 seconds |
| Started | Mar 05 01:11:25 PM PST 24 |
| Finished | Mar 05 01:32:45 PM PST 24 |
| Peak memory | 231808 kb |
| Host | smart-40232332-4690-4dcf-8135-c521a5d81cdc |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380487723 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.380487723 |
| Directory | /workspace/49.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/49.hmac_test_hmac_vectors.3720438087 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 28580613 ps |
| CPU time | 0.92 seconds |
| Started | Mar 05 01:11:27 PM PST 24 |
| Finished | Mar 05 01:11:29 PM PST 24 |
| Peak memory | 196552 kb |
| Host | smart-b9623630-ff6c-4724-92ca-bf4640206f7f |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720438087 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.hmac_test_hmac_vectors.3720438087 |
| Directory | /workspace/49.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/49.hmac_test_sha_vectors.3967247784 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 118742314822 ps |
| CPU time | 480.5 seconds |
| Started | Mar 05 01:11:31 PM PST 24 |
| Finished | Mar 05 01:19:32 PM PST 24 |
| Peak memory | 199100 kb |
| Host | smart-cd10494c-96a3-4a4a-a635-96daf4f65d87 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967247784 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 49.hmac_test_sha_vectors.3967247784 |
| Directory | /workspace/49.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/49.hmac_wipe_secret.4098000611 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1430018632 ps |
| CPU time | 64.59 seconds |
| Started | Mar 05 01:11:25 PM PST 24 |
| Finished | Mar 05 01:12:30 PM PST 24 |
| Peak memory | 198944 kb |
| Host | smart-d63594ad-7450-45f3-96f7-cefd09d28c8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098000611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4098000611 |
| Directory | /workspace/49.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/5.hmac_alert_test.1911731556 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 10854476 ps |
| CPU time | 0.57 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:54 PM PST 24 |
| Peak memory | 193640 kb |
| Host | smart-794ceaf6-c017-4d17-bbee-23f7141009d9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911731556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1911731556 |
| Directory | /workspace/5.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/5.hmac_back_pressure.2456238913 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1379287976 ps |
| CPU time | 50.82 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:10:48 PM PST 24 |
| Peak memory | 230716 kb |
| Host | smart-e13b17a6-e3e3-4db8-92db-2dcfb6653da6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2456238913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2456238913 |
| Directory | /workspace/5.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/5.hmac_burst_wr.4174472295 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4689994831 ps |
| CPU time | 22.03 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:10:21 PM PST 24 |
| Peak memory | 199052 kb |
| Host | smart-9f119925-eb0b-457d-a46d-6c728dba41a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174472295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.4174472295 |
| Directory | /workspace/5.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/5.hmac_datapath_stress.1624591739 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1194534911 ps |
| CPU time | 55.69 seconds |
| Started | Mar 05 01:09:58 PM PST 24 |
| Finished | Mar 05 01:10:54 PM PST 24 |
| Peak memory | 199016 kb |
| Host | smart-d5b8095a-4f0c-435e-a859-c8fdffd4aba5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1624591739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1624591739 |
| Directory | /workspace/5.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/5.hmac_error.2696635135 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 57441769847 ps |
| CPU time | 166.41 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:12:46 PM PST 24 |
| Peak memory | 198808 kb |
| Host | smart-49a240cf-8a17-412d-8553-c886e0dc8192 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2696635135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2696635135 |
| Directory | /workspace/5.hmac_error/latest |
| Test location | /workspace/coverage/default/5.hmac_long_msg.197618894 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 13930747335 ps |
| CPU time | 79.07 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:11:14 PM PST 24 |
| Peak memory | 199072 kb |
| Host | smart-da5f43e2-2023-49e0-96ee-01c2582b0932 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=197618894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.197618894 |
| Directory | /workspace/5.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/5.hmac_smoke.1432634772 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 337026283 ps |
| CPU time | 2.21 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:09:59 PM PST 24 |
| Peak memory | 198972 kb |
| Host | smart-9b6b6030-44b5-4131-bf2b-0fe9d915ea9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432634772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1432634772 |
| Directory | /workspace/5.hmac_smoke/latest |
| Test location | /workspace/coverage/default/5.hmac_stress_all.2985705592 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 106716022030 ps |
| CPU time | 607.49 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:20:06 PM PST 24 |
| Peak memory | 221784 kb |
| Host | smart-604dc7e9-55c0-4a16-9757-f577a2340267 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985705592 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2985705592 |
| Directory | /workspace/5.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/5.hmac_test_hmac_vectors.1820620435 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 50678752 ps |
| CPU time | 1.06 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:09:56 PM PST 24 |
| Peak memory | 196692 kb |
| Host | smart-2e60d986-8345-4e75-9bc1-21c25951dc9d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820620435 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.hmac_test_hmac_vectors.1820620435 |
| Directory | /workspace/5.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/5.hmac_test_sha_vectors.3716568694 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 41693450877 ps |
| CPU time | 458.71 seconds |
| Started | Mar 05 01:09:51 PM PST 24 |
| Finished | Mar 05 01:17:31 PM PST 24 |
| Peak memory | 199084 kb |
| Host | smart-00f6196b-8786-45c0-ace5-2c4b5e528535 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716568694 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 5.hmac_test_sha_vectors.3716568694 |
| Directory | /workspace/5.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/5.hmac_wipe_secret.4272171492 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2587406872 ps |
| CPU time | 45.26 seconds |
| Started | Mar 05 01:09:57 PM PST 24 |
| Finished | Mar 05 01:10:43 PM PST 24 |
| Peak memory | 199056 kb |
| Host | smart-3fb1b9f9-fe3d-4e00-a1f3-9f43a4566c92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272171492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4272171492 |
| Directory | /workspace/5.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/6.hmac_alert_test.2477018721 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 17784870 ps |
| CPU time | 0.55 seconds |
| Started | Mar 05 01:09:52 PM PST 24 |
| Finished | Mar 05 01:09:53 PM PST 24 |
| Peak memory | 193624 kb |
| Host | smart-b01213fb-0c3b-463d-8572-5cf677ebfe98 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477018721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2477018721 |
| Directory | /workspace/6.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/6.hmac_back_pressure.2603248490 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 373409205 ps |
| CPU time | 12.01 seconds |
| Started | Mar 05 01:09:52 PM PST 24 |
| Finished | Mar 05 01:10:05 PM PST 24 |
| Peak memory | 198924 kb |
| Host | smart-6ffa1a71-a7ee-4092-8ee6-b83e0c104469 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2603248490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2603248490 |
| Directory | /workspace/6.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/6.hmac_burst_wr.4278878220 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 701734778 ps |
| CPU time | 32.83 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:10:30 PM PST 24 |
| Peak memory | 198892 kb |
| Host | smart-273d0bfb-58fa-43cc-b3e7-cbb7eafd224f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278878220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4278878220 |
| Directory | /workspace/6.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/6.hmac_datapath_stress.386402397 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 4803285685 ps |
| CPU time | 127.99 seconds |
| Started | Mar 05 01:09:49 PM PST 24 |
| Finished | Mar 05 01:12:00 PM PST 24 |
| Peak memory | 198984 kb |
| Host | smart-9836a3fa-7459-49cd-a6bd-a3a224a23376 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=386402397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.386402397 |
| Directory | /workspace/6.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/6.hmac_error.3953115738 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 10385982336 ps |
| CPU time | 39.37 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:10:35 PM PST 24 |
| Peak memory | 199048 kb |
| Host | smart-ed48a6a6-04da-47fd-9e2b-08633e1108c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953115738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3953115738 |
| Directory | /workspace/6.hmac_error/latest |
| Test location | /workspace/coverage/default/6.hmac_long_msg.2126156009 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2735043243 ps |
| CPU time | 24.2 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:10:19 PM PST 24 |
| Peak memory | 198924 kb |
| Host | smart-f785c081-5710-486b-9662-00737000f8ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126156009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2126156009 |
| Directory | /workspace/6.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/6.hmac_smoke.3329538891 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 339113325 ps |
| CPU time | 4.24 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:57 PM PST 24 |
| Peak memory | 198940 kb |
| Host | smart-80b5ae4e-45a0-48f3-afa9-c2f921c6d8f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329538891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3329538891 |
| Directory | /workspace/6.hmac_smoke/latest |
| Test location | /workspace/coverage/default/6.hmac_stress_all.2648377712 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 271188933942 ps |
| CPU time | 979.79 seconds |
| Started | Mar 05 01:09:52 PM PST 24 |
| Finished | Mar 05 01:26:12 PM PST 24 |
| Peak memory | 207344 kb |
| Host | smart-b21edd68-e955-43f7-a717-dfe020928716 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648377712 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2648377712 |
| Directory | /workspace/6.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/6.hmac_test_hmac_vectors.1177259333 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 196551372 ps |
| CPU time | 1.11 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:55 PM PST 24 |
| Peak memory | 197912 kb |
| Host | smart-943a5d89-4ef9-4a79-8a6d-938baebb4233 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177259333 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.hmac_test_hmac_vectors.1177259333 |
| Directory | /workspace/6.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/6.hmac_test_sha_vectors.2063926736 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 12491122356 ps |
| CPU time | 405.73 seconds |
| Started | Mar 05 01:09:51 PM PST 24 |
| Finished | Mar 05 01:16:38 PM PST 24 |
| Peak memory | 198972 kb |
| Host | smart-3c31ca4b-6410-4bad-a820-7a351e92dccc |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063926736 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 6.hmac_test_sha_vectors.2063926736 |
| Directory | /workspace/6.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/6.hmac_wipe_secret.190498080 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2708469957 ps |
| CPU time | 52.83 seconds |
| Started | Mar 05 01:09:52 PM PST 24 |
| Finished | Mar 05 01:10:45 PM PST 24 |
| Peak memory | 199064 kb |
| Host | smart-688e8974-85fc-474c-ad33-d8bbb8614ee8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=190498080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.190498080 |
| Directory | /workspace/6.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/7.hmac_alert_test.1888209163 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 16546748 ps |
| CPU time | 0.59 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:09:56 PM PST 24 |
| Peak memory | 193284 kb |
| Host | smart-53e8e123-c63a-444f-b4a6-cafd880f8eb8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888209163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1888209163 |
| Directory | /workspace/7.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/7.hmac_back_pressure.2056836761 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 6671550613 ps |
| CPU time | 27.1 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:10:21 PM PST 24 |
| Peak memory | 207280 kb |
| Host | smart-ba237190-1c84-42de-9fc0-15379526f620 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2056836761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2056836761 |
| Directory | /workspace/7.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/7.hmac_burst_wr.12368068 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3349247929 ps |
| CPU time | 17.97 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:10:15 PM PST 24 |
| Peak memory | 199056 kb |
| Host | smart-f851a06a-9e24-4eac-9fef-fc2cdd1c8273 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12368068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.12368068 |
| Directory | /workspace/7.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/7.hmac_datapath_stress.2278248511 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2378663787 ps |
| CPU time | 65.93 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:10:59 PM PST 24 |
| Peak memory | 199052 kb |
| Host | smart-ed1465a8-63fe-42fc-8b0d-cc7f7da6cf13 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2278248511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2278248511 |
| Directory | /workspace/7.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/7.hmac_error.2323075495 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 11232462815 ps |
| CPU time | 185.5 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:12:59 PM PST 24 |
| Peak memory | 199056 kb |
| Host | smart-d7035704-936a-4edc-bf01-02e9c6a2ecdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323075495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2323075495 |
| Directory | /workspace/7.hmac_error/latest |
| Test location | /workspace/coverage/default/7.hmac_long_msg.3172934744 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 496394815 ps |
| CPU time | 6.55 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:10:01 PM PST 24 |
| Peak memory | 198952 kb |
| Host | smart-3433b2aa-e8c1-44d8-9ee3-8bbf9fb31fc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172934744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3172934744 |
| Directory | /workspace/7.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/7.hmac_smoke.1737388319 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 49833082 ps |
| CPU time | 1.32 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:56 PM PST 24 |
| Peak memory | 198888 kb |
| Host | smart-5915fd3c-c6b2-44ff-b8d2-95d0033527e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1737388319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1737388319 |
| Directory | /workspace/7.hmac_smoke/latest |
| Test location | /workspace/coverage/default/7.hmac_stress_all.2852928134 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 349024976316 ps |
| CPU time | 1410.6 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:33:26 PM PST 24 |
| Peak memory | 199092 kb |
| Host | smart-c0d749d1-4e8e-4b67-a49c-e50988c68405 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852928134 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2852928134 |
| Directory | /workspace/7.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/7.hmac_test_hmac_vectors.1317241912 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 266296217 ps |
| CPU time | 1.07 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:09:55 PM PST 24 |
| Peak memory | 197740 kb |
| Host | smart-9553b7d7-d2ec-496d-9af9-48f25d06d523 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317241912 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.hmac_test_hmac_vectors.1317241912 |
| Directory | /workspace/7.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/7.hmac_test_sha_vectors.465621609 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 14158986164 ps |
| CPU time | 361.19 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:16:01 PM PST 24 |
| Peak memory | 198992 kb |
| Host | smart-5c199a5b-6e49-4e1a-8337-799ae36430fc |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465621609 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.hmac_test_sha_vectors.465621609 |
| Directory | /workspace/7.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/7.hmac_wipe_secret.2946732131 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1172836695 ps |
| CPU time | 22.14 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:10:17 PM PST 24 |
| Peak memory | 198824 kb |
| Host | smart-2d54cf1b-ad19-4aa7-93af-9afdbefa2dcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2946732131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2946732131 |
| Directory | /workspace/7.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/8.hmac_alert_test.3299093541 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 39655100 ps |
| CPU time | 0.64 seconds |
| Started | Mar 05 01:09:57 PM PST 24 |
| Finished | Mar 05 01:09:58 PM PST 24 |
| Peak memory | 194660 kb |
| Host | smart-b8af1e5f-4302-42be-8681-f3c06ac527a5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299093541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3299093541 |
| Directory | /workspace/8.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/8.hmac_back_pressure.3808535861 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 933271532 ps |
| CPU time | 14.17 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:10:09 PM PST 24 |
| Peak memory | 207100 kb |
| Host | smart-75fb87a7-d274-4d38-9db2-a1310b3c4723 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3808535861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3808535861 |
| Directory | /workspace/8.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/8.hmac_burst_wr.1594604238 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3789630363 ps |
| CPU time | 52.35 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:10:47 PM PST 24 |
| Peak memory | 198980 kb |
| Host | smart-0ad89109-a838-41e0-b1dc-61f8b4d8e1aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594604238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1594604238 |
| Directory | /workspace/8.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/8.hmac_datapath_stress.1732312249 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1527958832 ps |
| CPU time | 45.15 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:10:41 PM PST 24 |
| Peak memory | 198844 kb |
| Host | smart-4abf5c14-3a2d-47d7-a80f-69dafaa06c64 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1732312249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1732312249 |
| Directory | /workspace/8.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/8.hmac_error.1309084941 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 21783159287 ps |
| CPU time | 120.44 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:11:59 PM PST 24 |
| Peak memory | 199072 kb |
| Host | smart-2c8f8363-8a65-4a6a-b163-7febe5964057 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1309084941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1309084941 |
| Directory | /workspace/8.hmac_error/latest |
| Test location | /workspace/coverage/default/8.hmac_long_msg.2498211935 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 76332242656 ps |
| CPU time | 101.58 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:11:37 PM PST 24 |
| Peak memory | 199000 kb |
| Host | smart-6aef5156-8691-4331-96d5-4796f3db7897 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498211935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2498211935 |
| Directory | /workspace/8.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/8.hmac_smoke.1321805018 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 55428389 ps |
| CPU time | 1.61 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:10:01 PM PST 24 |
| Peak memory | 198692 kb |
| Host | smart-d1393b2d-5803-4c0b-bc50-69b03560f362 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321805018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1321805018 |
| Directory | /workspace/8.hmac_smoke/latest |
| Test location | /workspace/coverage/default/8.hmac_stress_all.1016738061 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 56946561951 ps |
| CPU time | 1061.38 seconds |
| Started | Mar 05 01:09:54 PM PST 24 |
| Finished | Mar 05 01:27:36 PM PST 24 |
| Peak memory | 207180 kb |
| Host | smart-027dd58a-2669-4223-8591-263a4288de6b |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016738061 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1016738061 |
| Directory | /workspace/8.hmac_stress_all/latest |
| Test location | /workspace/coverage/default/8.hmac_test_hmac_vectors.1507724770 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 73069926 ps |
| CPU time | 1.25 seconds |
| Started | Mar 05 01:09:52 PM PST 24 |
| Finished | Mar 05 01:09:54 PM PST 24 |
| Peak memory | 198296 kb |
| Host | smart-8d53f84c-d3e4-4930-a268-951ea4414812 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507724770 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.hmac_test_hmac_vectors.1507724770 |
| Directory | /workspace/8.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/8.hmac_test_sha_vectors.3077677107 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 102550700890 ps |
| CPU time | 441.86 seconds |
| Started | Mar 05 01:09:55 PM PST 24 |
| Finished | Mar 05 01:17:17 PM PST 24 |
| Peak memory | 198928 kb |
| Host | smart-a78d912a-c557-4e13-b4cb-383400b7309d |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077677107 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 8.hmac_test_sha_vectors.3077677107 |
| Directory | /workspace/8.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/8.hmac_wipe_secret.685040107 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3657414106 ps |
| CPU time | 46.65 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:10:40 PM PST 24 |
| Peak memory | 198984 kb |
| Host | smart-8299c939-3aa1-4658-a066-aecd2eec778b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=685040107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.685040107 |
| Directory | /workspace/8.hmac_wipe_secret/latest |
| Test location | /workspace/coverage/default/9.hmac_alert_test.2342954306 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 20003271 ps |
| CPU time | 0.56 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:10:00 PM PST 24 |
| Peak memory | 193124 kb |
| Host | smart-266ef2fc-554d-4117-835c-ca770113eb7b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342954306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2342954306 |
| Directory | /workspace/9.hmac_alert_test/latest |
| Test location | /workspace/coverage/default/9.hmac_back_pressure.367204991 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2126741945 ps |
| CPU time | 20.39 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:10:17 PM PST 24 |
| Peak memory | 231708 kb |
| Host | smart-b6d0d5de-2156-43af-8b4f-0e770f225608 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=367204991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.367204991 |
| Directory | /workspace/9.hmac_back_pressure/latest |
| Test location | /workspace/coverage/default/9.hmac_burst_wr.1514320751 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 9020013518 ps |
| CPU time | 58.94 seconds |
| Started | Mar 05 01:10:01 PM PST 24 |
| Finished | Mar 05 01:11:00 PM PST 24 |
| Peak memory | 198944 kb |
| Host | smart-63d2afa5-ff8a-4838-971f-e5cae5a64b84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1514320751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1514320751 |
| Directory | /workspace/9.hmac_burst_wr/latest |
| Test location | /workspace/coverage/default/9.hmac_datapath_stress.649511179 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2000441472 ps |
| CPU time | 25.66 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:10:23 PM PST 24 |
| Peak memory | 198928 kb |
| Host | smart-080f8642-f2f1-43ad-8cab-c2e5a09c028e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=649511179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.649511179 |
| Directory | /workspace/9.hmac_datapath_stress/latest |
| Test location | /workspace/coverage/default/9.hmac_error.2203062080 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2695260334 ps |
| CPU time | 31.67 seconds |
| Started | Mar 05 01:09:59 PM PST 24 |
| Finished | Mar 05 01:10:31 PM PST 24 |
| Peak memory | 198936 kb |
| Host | smart-0e34fb3d-b2a4-4d2f-8bad-22a3d9974b9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2203062080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2203062080 |
| Directory | /workspace/9.hmac_error/latest |
| Test location | /workspace/coverage/default/9.hmac_long_msg.444288630 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 722083582 ps |
| CPU time | 11.01 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:10:07 PM PST 24 |
| Peak memory | 198912 kb |
| Host | smart-4c59cacd-b00b-4bee-9a31-86a3bd9fff03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444288630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.444288630 |
| Directory | /workspace/9.hmac_long_msg/latest |
| Test location | /workspace/coverage/default/9.hmac_smoke.739666223 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 858732113 ps |
| CPU time | 3.62 seconds |
| Started | Mar 05 01:09:56 PM PST 24 |
| Finished | Mar 05 01:10:01 PM PST 24 |
| Peak memory | 198360 kb |
| Host | smart-9ca7baee-2bcd-434e-ac70-19750860a002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739666223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.739666223 |
| Directory | /workspace/9.hmac_smoke/latest |
| Test location | /workspace/coverage/default/9.hmac_test_hmac_vectors.3204080403 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 41214036 ps |
| CPU time | 0.98 seconds |
| Started | Mar 05 01:10:00 PM PST 24 |
| Finished | Mar 05 01:10:02 PM PST 24 |
| Peak memory | 196680 kb |
| Host | smart-4e2f8563-0369-4692-acc2-2a38334ae363 |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204080403 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.hmac_test_hmac_vectors.3204080403 |
| Directory | /workspace/9.hmac_test_hmac_vectors/latest |
| Test location | /workspace/coverage/default/9.hmac_test_sha_vectors.1961575697 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 183233158301 ps |
| CPU time | 456.14 seconds |
| Started | Mar 05 01:09:53 PM PST 24 |
| Finished | Mar 05 01:17:29 PM PST 24 |
| Peak memory | 199116 kb |
| Host | smart-5984ad8f-c628-4579-8890-2f156896cabd |
| User | root |
| Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961575697 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.hmac_test_sha_vectors.1961575697 |
| Directory | /workspace/9.hmac_test_sha_vectors/latest |
| Test location | /workspace/coverage/default/9.hmac_wipe_secret.2281718388 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 675747342 ps |
| CPU time | 22.46 seconds |
| Started | Mar 05 01:10:05 PM PST 24 |
| Finished | Mar 05 01:10:28 PM PST 24 |
| Peak memory | 198808 kb |
| Host | smart-1789dbbc-0cd5-4b3f-9c9d-e58100545d79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281718388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2281718388 |
| Directory | /workspace/9.hmac_wipe_secret/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |