Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 13837660 1 T1 163847 T2 8654 T3 16669
all_values[1] 13837660 1 T1 163847 T2 8654 T3 16669
all_values[2] 13837660 1 T1 163847 T2 8654 T3 16669



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 97327 1 T1 784 T3 75 T4 9
auto[1] 41415653 1 T1 490757 T2 25962 T3 49932



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 39048054 1 T1 473317 T2 25927 T3 49946
auto[1] 2464926 1 T1 18224 T2 35 T3 61



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 12 0 12 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 28528 1 T3 23 T4 3 T26 138
all_values[0] auto[0] auto[1] 485 1 T3 2 T4 1 T26 2
all_values[0] auto[1] auto[0] 13761165 1 T1 163336 T2 8619 T3 16585
all_values[0] auto[1] auto[1] 47482 1 T1 511 T2 35 T3 59
all_values[1] auto[0] auto[0] 26405 1 T1 1 T3 25 T4 1
all_values[1] auto[0] auto[1] 185 1 T29 1 T6 1 T13 1
all_values[1] auto[1] auto[0] 13810490 1 T1 163846 T2 8654 T3 16644
all_values[1] auto[1] auto[1] 580 1 T4 1 T26 1 T29 1
all_values[2] auto[0] auto[0] 33448 1 T1 783 T3 25 T4 1
all_values[2] auto[0] auto[1] 8276 1 T4 3 T29 6 T6 5
all_values[2] auto[1] auto[0] 11388018 1 T1 145351 T2 8654 T3 16644
all_values[2] auto[1] auto[1] 2407918 1 T1 17713 T17 9200 T18 10363

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%