Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6647421

1

T1

93723

T2

4805

T3

5650

auto[1]

2667810

1

T1

24861

T2

3797

T3

10891

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2659460

1

T1

21623

T2

4978

T3

10822

auto[1]

6655771

1

T1

96961

T2

3624

T3

5719

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5982754

1

T1

93621

T2

4507

T3

7926

auto[1]

3332477

1

T1

24963

T2

4095

T3

8615

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5910724	1			T1	56582		T2	7998		T3	14347
fifo_depth[1]	434451	1			T1	6631		T2	382		T3	946
fifo_depth[2]	358578	1			T1	6655		T2	156		T3	729
fifo_depth[3]	291148	1			T1	6005		T2	51		T3	336
fifo_depth[4]	253005	1			T1	5400		T2	13		T3	131
fifo_depth[5]	224064	1			T1	4516		T2	2		T3	30
fifo_depth[6]	214757	1			T1	4439		T3	14		T4	6
fifo_depth[7]	188086	1			T1	3613		T3	5		T4	8
fifo_depth[8]	175309	1			T1	3083		T3	3		T4	8
fifo_depth[9]	119010	1			T1	2005		T4	10		T19	159
fifo_depth[10]	93760	1			T1	1817		T4	7		T19	153
fifo_depth[11]	59259	1			T1	909		T4	4		T19	189
fifo_depth[12]	63139	1			T1	1420		T4	3		T19	253
fifo_depth[13]	33241	1			T1	598		T4	2		T19	270
fifo_depth[14]	43626	1			T1	1404		T19	273		T31	1
fifo_depth[15]	29935	1			T1	810		T19	306		T32	226
fifo_depth[16]	115602	1			T1	1880		T19	416		T32	720

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3546048

1

T1

63083

T2

604

T3

2194

auto[1]

5769183

1

T1

55501

T2

7998

T3

14347

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9173690

1

T1

117503

T2

8602

T3

16541

auto[1]

141541

1

T1

1081

T4

7

T19

2355

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

256956

1

T1

3982

T2

29

T3

156

auto[0]

auto[0]

auto[0]

auto[1]

262183

1

T1

1506

T2

127

T3

566

auto[0]

auto[0]

auto[1]

auto[0]

1006000

1

T1

31826

T2

118

T3

169

auto[0]

auto[0]

auto[1]

auto[1]

252632

1

T1

5289

T2

28

T3

153

auto[0]

auto[1]

auto[0]

auto[0]

406972

1

T1

4539

T2

130

T3

338

auto[0]

auto[1]

auto[0]

auto[1]

471467

1

T1

7637

T2

66

T3

397

auto[0]

auto[1]

auto[1]

auto[0]

450995

1

T1

3739

T2

68

T3

87

auto[0]

auto[1]

auto[1]

auto[1]

438843

1

T1

4565

T2

38

T3

328

auto[1]

auto[0]

auto[0]

auto[0]

239307

1

T1

1006

T2

383

T3

1045

auto[1]

auto[0]

auto[0]

auto[1]

235759

1

T1

383

T2

1715

T3

3636

auto[1]

auto[0]

auto[1]

auto[0]

3486502

1

T1

47709

T2

1652

T3

1138

auto[1]

auto[0]

auto[1]

auto[1]

243415

1

T1

1920

T2

455

T3

1063

auto[1]

auto[1]

auto[0]

auto[0]

403738

1

T1

367

T2

1603

T3

2102

auto[1]

auto[1]

auto[0]

auto[1]

383078

1

T1

2203

T2

925

T3

2582

auto[1]

auto[1]

auto[1]

auto[0]

396951

1

T1

555

T2

822

T3

615

auto[1]

auto[1]

auto[1]

auto[1]

380433

1

T1

1358

T2

443

T3

2166

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

481135

1

T1

4806

T2

412

T3

1201

auto[0]

auto[0]

auto[0]

auto[1]

480474

1

T1

1857

T2

1842

T3

4202

auto[0]

auto[0]

auto[1]

auto[0]

4470147

1

T1

79489

T2

1770

T3

1307

auto[0]

auto[0]

auto[1]

auto[1]

481715

1

T1

7128

T2

483

T3

1216

auto[0]

auto[1]

auto[0]

auto[0]

793229

1

T1

4535

T2

1733

T3

2440

auto[0]

auto[1]

auto[0]

auto[1]

832307

1

T1

9753

T2

991

T3

2979

auto[0]

auto[1]

auto[1]

auto[0]

831896

1

T1

4235

T2

890

T3

702

auto[0]

auto[1]

auto[1]

auto[1]

802787

1

T1

5700

T2

481

T3

2494

auto[1]

auto[0]

auto[0]

auto[0]

15128

1

T1

182

T19

1579

T32

9

auto[1]

auto[0]

auto[0]

auto[1]

17468

1

T1

32

T4

1

T32

345

auto[1]

auto[0]

auto[1]

auto[0]

22355

1

T1

46

T4

1

T19

120

auto[1]

auto[0]

auto[1]

auto[1]

14332

1

T1

81

T4

1

T19

36

auto[1]

auto[1]

auto[0]

auto[0]

17481

1

T1

371

T19

61

T32

71

auto[1]

auto[1]

auto[0]

auto[1]

22238

1

T1

87

T4

1

T19

17

auto[1]

auto[1]

auto[1]

auto[0]

16050

1

T1

59

T4

1

T19

532

auto[1]

auto[1]

auto[1]

auto[1]

16489

1

T1

223

T4

2

T19

10

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	254435	1			T1	1188		T2	383		T3	1045
fifo_depth[0]	auto[0]	auto[0]	auto[1]	253227	1			T1	415		T2	1715		T3	3636
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3508857	1			T1	47755		T2	1652		T3	1138
fifo_depth[0]	auto[0]	auto[1]	auto[1]	257747	1			T1	2001		T2	455		T3	1063
fifo_depth[0]	auto[1]	auto[0]	auto[0]	421219	1			T1	738		T2	1603		T3	2102
fifo_depth[0]	auto[1]	auto[0]	auto[1]	405316	1			T1	2290		T2	925		T3	2582
fifo_depth[0]	auto[1]	auto[1]	auto[0]	413001	1			T1	614		T2	822		T3	615
fifo_depth[0]	auto[1]	auto[1]	auto[1]	396922	1			T1	1581		T2	443		T3	2166
fifo_depth[1]	auto[0]	auto[0]	auto[0]	19841	1			T1	186		T2	17		T3	66
fifo_depth[1]	auto[0]	auto[0]	auto[1]	19155	1			T1	74		T2	83		T3	245
fifo_depth[1]	auto[0]	auto[1]	auto[0]	209248	1			T1	5126		T2	79		T3	71
fifo_depth[1]	auto[0]	auto[1]	auto[1]	19163	1			T1	277		T2	18		T3	64
fifo_depth[1]	auto[1]	auto[0]	auto[0]	41098	1			T1	98		T2	80		T3	135
fifo_depth[1]	auto[1]	auto[0]	auto[1]	43177	1			T1	497		T2	46		T3	157
fifo_depth[1]	auto[1]	auto[1]	auto[0]	41072	1			T1	135		T2	39		T3	50
fifo_depth[1]	auto[1]	auto[1]	auto[1]	41697	1			T1	238		T2	20		T3	158
fifo_depth[2]	auto[0]	auto[0]	auto[0]	17075	1			T1	188		T2	9		T3	47
fifo_depth[2]	auto[0]	auto[0]	auto[1]	16052	1			T1	72		T2	32		T3	184
fifo_depth[2]	auto[0]	auto[1]	auto[0]	159721	1			T1	5130		T2	26		T3	57
fifo_depth[2]	auto[0]	auto[1]	auto[1]	16818	1			T1	278		T2	6		T3	53
fifo_depth[2]	auto[1]	auto[0]	auto[0]	35890	1			T1	141		T2	37		T3	117
fifo_depth[2]	auto[1]	auto[0]	auto[1]	39075	1			T1	476		T2	14		T3	137
fifo_depth[2]	auto[1]	auto[1]	auto[0]	37094	1			T1	131		T2	21		T3	24
fifo_depth[2]	auto[1]	auto[1]	auto[1]	36853	1			T1	239		T2	11		T3	110
fifo_depth[3]	auto[0]	auto[0]	auto[0]	14243	1			T1	200		T2	2		T3	30
fifo_depth[3]	auto[0]	auto[0]	auto[1]	13087	1			T1	75		T2	11		T3	86
fifo_depth[3]	auto[0]	auto[1]	auto[0]	120167	1			T1	4513		T2	11		T3	26
fifo_depth[3]	auto[0]	auto[1]	auto[1]	13369	1			T1	281		T2	3		T3	23
fifo_depth[3]	auto[1]	auto[0]	auto[0]	31158	1			T1	105		T2	8		T3	52
fifo_depth[3]	auto[1]	auto[0]	auto[1]	34467	1			T1	471		T2	5		T3	71
fifo_depth[3]	auto[1]	auto[1]	auto[0]	32130	1			T1	132		T2	6		T3	9
fifo_depth[3]	auto[1]	auto[1]	auto[1]	32527	1			T1	228		T2	5		T3	39
fifo_depth[4]	auto[0]	auto[0]	auto[0]	14147	1			T1	272		T2	1		T3	9
fifo_depth[4]	auto[0]	auto[0]	auto[1]	12501	1			T1	63		T3	37		T32	1
fifo_depth[4]	auto[0]	auto[1]	auto[0]	88714	1			T1	3648		T2	2		T3	11
fifo_depth[4]	auto[0]	auto[1]	auto[1]	12677	1			T1	260		T2	1		T3	10
fifo_depth[4]	auto[1]	auto[0]	auto[0]	29699	1			T1	382		T2	5		T3	22
fifo_depth[4]	auto[1]	auto[0]	auto[1]	33459	1			T1	470		T2	1		T3	24
fifo_depth[4]	auto[1]	auto[1]	auto[0]	30518	1			T1	121		T2	1		T3	4
fifo_depth[4]	auto[1]	auto[1]	auto[1]	31290	1			T1	184		T2	2		T3	14
fifo_depth[5]	auto[0]	auto[0]	auto[0]	12270	1			T1	197		T3	2		T19	1
fifo_depth[5]	auto[0]	auto[0]	auto[1]	10970	1			T1	76		T2	1		T3	8
fifo_depth[5]	auto[0]	auto[1]	auto[0]	73639	1			T1	3056		T3	2		T32	19
fifo_depth[5]	auto[0]	auto[1]	auto[1]	11258	1			T1	289		T19	4		T28	53
fifo_depth[5]	auto[1]	auto[0]	auto[0]	27321	1			T1	101		T3	10		T4	4
fifo_depth[5]	auto[1]	auto[0]	auto[1]	31216	1			T1	455		T3	5		T4	1
fifo_depth[5]	auto[1]	auto[1]	auto[0]	28161	1			T1	122		T2	1		T4	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	29229	1			T1	220		T3	3		T4	1
fifo_depth[6]	auto[0]	auto[0]	auto[0]	12606	1			T1	253		T3	2		T19	3
fifo_depth[6]	auto[0]	auto[0]	auto[1]	11235	1			T1	61		T3	3		T32	2
fifo_depth[6]	auto[0]	auto[1]	auto[0]	64220	1			T1	2728		T3	2		T32	41
fifo_depth[6]	auto[0]	auto[1]	auto[1]	11544	1			T1	258		T3	2		T19	4
fifo_depth[6]	auto[1]	auto[0]	auto[0]	26996	1			T1	374		T3	2		T31	5
fifo_depth[6]	auto[1]	auto[0]	auto[1]	31396	1			T1	442		T3	1		T4	2
fifo_depth[6]	auto[1]	auto[1]	auto[0]	27903	1			T1	125		T4	2		T31	2
fifo_depth[6]	auto[1]	auto[1]	auto[1]	28857	1			T1	198		T3	2		T4	2
fifo_depth[7]	auto[0]	auto[0]	auto[0]	11150	1			T1	185		T19	1		T32	12
fifo_depth[7]	auto[0]	auto[0]	auto[1]	10278	1			T1	80		T3	2		T32	1
fifo_depth[7]	auto[0]	auto[1]	auto[0]	50859	1			T1	2223		T32	17		T18	766
fifo_depth[7]	auto[0]	auto[1]	auto[1]	10420	1			T1	283		T19	2		T28	55
fifo_depth[7]	auto[1]	auto[0]	auto[0]	24662	1			T1	120		T4	1		T31	4
fifo_depth[7]	auto[1]	auto[0]	auto[1]	28213	1			T1	423		T3	2		T4	1
fifo_depth[7]	auto[1]	auto[1]	auto[0]	25707	1			T1	123		T4	4		T19	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	26797	1			T1	176		T3	1		T4	2
fifo_depth[8]	auto[0]	auto[0]	auto[0]	11896	1			T1	248		T19	4		T32	109
fifo_depth[8]	auto[0]	auto[0]	auto[1]	11043	1			T1	79		T3	1		T32	3
fifo_depth[8]	auto[0]	auto[1]	auto[0]	39736	1			T1	1605		T19	1		T32	75
fifo_depth[8]	auto[0]	auto[1]	auto[1]	10389	1			T1	202		T3	1		T26	1
fifo_depth[8]	auto[1]	auto[0]	auto[0]	23480	1			T1	342		T4	2		T31	6
fifo_depth[8]	auto[1]	auto[0]	auto[1]	27376	1			T1	336		T19	125		T32	1
fifo_depth[8]	auto[1]	auto[1]	auto[0]	25861	1			T1	101		T4	3		T19	1
fifo_depth[8]	auto[1]	auto[1]	auto[1]	25528	1			T1	170		T3	1		T4	3
fifo_depth[9]	auto[0]	auto[0]	auto[0]	7539	1			T1	114		T32	11		T28	77
fifo_depth[9]	auto[0]	auto[0]	auto[1]	7176	1			T1	67		T32	2		T6	251
fifo_depth[9]	auto[0]	auto[1]	auto[0]	26248	1			T1	1066		T19	1		T32	16
fifo_depth[9]	auto[0]	auto[1]	auto[1]	7460	1			T1	157		T28	33		T129	13
fifo_depth[9]	auto[1]	auto[0]	auto[0]	16620	1			T1	103		T4	3		T31	6
fifo_depth[9]	auto[1]	auto[0]	auto[1]	19087	1			T1	299		T4	1		T19	157
fifo_depth[9]	auto[1]	auto[1]	auto[0]	17186	1			T1	73		T4	3		T31	1
fifo_depth[9]	auto[1]	auto[1]	auto[1]	17694	1			T1	126		T4	3		T19	1
fifo_depth[10]	auto[0]	auto[0]	auto[0]	7224	1			T1	189		T19	5		T32	98
fifo_depth[10]	auto[0]	auto[0]	auto[1]	6198	1			T1	79		T32	2		T6	174
fifo_depth[10]	auto[0]	auto[1]	auto[0]	18214	1			T1	726		T19	3		T32	74
fifo_depth[10]	auto[0]	auto[1]	auto[1]	6536	1			T1	103		T19	14		T28	29
fifo_depth[10]	auto[1]	auto[0]	auto[0]	13140	1			T1	308		T4	1		T19	9
fifo_depth[10]	auto[1]	auto[0]	auto[1]	14958	1			T1	258		T4	1		T19	121
fifo_depth[10]	auto[1]	auto[1]	auto[0]	13970	1			T1	51		T4	4		T32	36
fifo_depth[10]	auto[1]	auto[1]	auto[1]	13520	1			T1	103		T4	1		T19	1
fifo_depth[11]	auto[0]	auto[0]	auto[0]	4285	1			T1	59		T19	1		T32	8
fifo_depth[11]	auto[0]	auto[0]	auto[1]	4623	1			T1	62		T32	1		T6	91
fifo_depth[11]	auto[0]	auto[1]	auto[0]	10893	1			T1	384		T19	4		T32	13
fifo_depth[11]	auto[0]	auto[1]	auto[1]	4323	1			T1	51		T19	14		T28	10
fifo_depth[11]	auto[1]	auto[0]	auto[0]	8073	1			T1	80		T19	10		T32	47
fifo_depth[11]	auto[1]	auto[0]	auto[1]	9389	1			T1	177		T4	1		T19	158
fifo_depth[11]	auto[1]	auto[1]	auto[0]	8768	1			T1	35		T4	2		T32	40
fifo_depth[11]	auto[1]	auto[1]	auto[1]	8905	1			T1	61		T4	1		T19	2
fifo_depth[12]	auto[0]	auto[0]	auto[0]	5616	1			T1	119		T19	6		T32	111
fifo_depth[12]	auto[0]	auto[0]	auto[1]	6333	1			T1	55		T32	4		T130	1
fifo_depth[12]	auto[0]	auto[1]	auto[0]	8177	1			T1	276		T19	1		T32	75
fifo_depth[12]	auto[0]	auto[1]	auto[1]	5783	1			T1	61		T19	81		T28	6
fifo_depth[12]	auto[1]	auto[0]	auto[0]	7473	1			T1	314		T4	1		T19	42
fifo_depth[12]	auto[1]	auto[0]	auto[1]	10033	1			T1	498		T19	120		T32	50
fifo_depth[12]	auto[1]	auto[1]	auto[0]	10938	1			T1	52		T4	1		T19	1
fifo_depth[12]	auto[1]	auto[1]	auto[1]	8786	1			T1	45		T4	1		T19	2
fifo_depth[13]	auto[0]	auto[0]	auto[0]	3142	1			T1	30		T32	7		T28	5
fifo_depth[13]	auto[0]	auto[0]	auto[1]	3690	1			T1	48		T32	1		T5	1
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4579	1			T1	178		T32	13		T18	24
fifo_depth[13]	auto[0]	auto[1]	auto[1]	3200	1			T1	48		T19	84		T26	1
fifo_depth[13]	auto[1]	auto[0]	auto[0]	4027	1			T1	75		T19	59		T31	1
fifo_depth[13]	auto[1]	auto[0]	auto[1]	4816	1			T1	147		T19	126		T32	40
fifo_depth[13]	auto[1]	auto[1]	auto[0]	5107	1			T1	54		T32	39		T91	6
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4680	1			T1	18		T4	2		T19	1
fifo_depth[14]	auto[0]	auto[0]	auto[0]	4959	1			T1	88		T19	7		T32	110
fifo_depth[14]	auto[0]	auto[0]	auto[1]	4733	1			T1	45		T32	16		T6	9
fifo_depth[14]	auto[0]	auto[1]	auto[0]	4603	1			T1	110		T19	2		T32	60
fifo_depth[14]	auto[0]	auto[1]	auto[1]	5100	1			T1	164		T19	79		T28	2
fifo_depth[14]	auto[1]	auto[0]	auto[0]	4834	1			T1	302		T19	66		T31	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	6442	1			T1	419		T19	117		T32	80
fifo_depth[14]	auto[1]	auto[1]	auto[0]	7897	1			T1	242		T19	1		T32	4
fifo_depth[14]	auto[1]	auto[1]	auto[1]	5058	1			T1	34		T19	1		T32	2
fifo_depth[15]	auto[0]	auto[0]	auto[0]	3356	1			T1	19		T19	2		T32	10
fifo_depth[15]	auto[0]	auto[0]	auto[1]	4041	1			T1	44		T32	6		T84	1
fifo_depth[15]	auto[0]	auto[1]	auto[0]	3217	1			T1	89		T19	3		T32	11
fifo_depth[15]	auto[0]	auto[1]	auto[1]	3446	1			T1	198		T19	79		T5	14
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3108	1			T1	57		T19	92		T32	82
fifo_depth[15]	auto[1]	auto[0]	auto[1]	4057	1			T1	125		T19	129		T32	76
fifo_depth[15]	auto[1]	auto[1]	auto[0]	4877	1			T1	242		T32	39		T91	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	3833	1			T1	36		T19	1		T32	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	13767	1			T1	69		T19	53		T32	76
fifo_depth[16]	auto[0]	auto[0]	auto[1]	13147	1			T1	208		T32	48		T130	22
fifo_depth[16]	auto[0]	auto[1]	auto[0]	16466	1			T1	85		T19	3		T32	384
fifo_depth[16]	auto[0]	auto[1]	auto[1]	12067	1			T1	131		T19	46		T130	2
fifo_depth[16]	auto[1]	auto[0]	auto[0]	12512	1			T1	280		T19	191		T32	45
fifo_depth[16]	auto[1]	auto[0]	auto[1]	12598	1			T1	381		T19	120		T32	61
fifo_depth[16]	auto[1]	auto[1]	auto[0]	17439	1			T1	207		T19	3		T32	5
fifo_depth[16]	auto[1]	auto[1]	auto[1]	17606	1			T1	519		T32	101		T26	171