Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13837660	1			T1	163847		T2	8654		T3	16669
all_pins[1]	13837660	1			T1	163847		T2	8654		T3	16669
all_pins[2]	13837660	1			T1	163847		T2	8654		T3	16669

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	39055721	1			T1	473309		T2	25926		T3	49946
values[0x1]	2457259	1			T1	18232		T2	36		T3	61
transitions[0x0=>0x1]	2457122	1			T1	18232		T2	36		T3	61
transitions[0x1=>0x0]	2457139	1			T1	18232		T2	36		T3	61

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13788931	1			T1	163329		T2	8618		T3	16608
all_pins[0]	values[0x1]	48729	1			T1	518		T2	36		T3	61
all_pins[0]	transitions[0x0=>0x1]	48674	1			T1	518		T2	36		T3	61
all_pins[0]	transitions[0x1=>0x0]	2407880	1			T1	17713		T17	9200		T18	10363
all_pins[1]	values[0x0]	13837048	1			T1	163846		T2	8654		T3	16669
all_pins[1]	values[0x1]	612	1			T1	1		T4	1		T26	1
all_pins[1]	transitions[0x0=>0x1]	578	1			T1	1		T4	1		T26	1
all_pins[1]	transitions[0x1=>0x0]	48695	1			T1	518		T2	36		T3	61
all_pins[2]	values[0x0]	11429742	1			T1	146134		T2	8654		T3	16669
all_pins[2]	values[0x1]	2407918	1			T1	17713		T17	9200		T18	10363
all_pins[2]	transitions[0x0=>0x1]	2407870	1			T1	17713		T17	9200		T18	10363
all_pins[2]	transitions[0x1=>0x0]	564	1			T1	1		T4	1		T26	1