Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	883	1			T4	4		T29	7		T6	11
all_values[1]	883	1			T4	4		T29	7		T6	11
all_values[2]	883	1			T4	4		T29	7		T6	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1358

1

T4

7

T29

12

T6

16

auto[1]

1291

1

T4

5

T29

9

T6

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

931

1

T4

4

T29

4

T6

11

auto[1]

1718

1

T4

8

T29

17

T6

22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1525

1

T4

6

T29

11

T6

17

auto[1]

1124

1

T4

6

T29

10

T6

16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

173

1

T4

1

T6

3

T13

1

all_values[0]

auto[0]

auto[0]

auto[1]

101

1

T29

1

T6

1

T13

3

all_values[0]

auto[0]

auto[1]

auto[0]

168

1

T29

1

T6

2

T13

4

all_values[0]

auto[0]

auto[1]

auto[1]

82

1

T29

1

T6

1

T30

2

all_values[0]

auto[1]

auto[0]

auto[1]

185

1

T4

2

T29

1

T6

2

all_values[0]

auto[1]

auto[1]

auto[1]

174

1

T4

1

T29

3

T6

2

all_values[1]

auto[0]

auto[0]

auto[0]

133

1

T4

1

T29

2

T6

3

all_values[1]

auto[0]

auto[0]

auto[1]

109

1

T29

1

T30

3

T49

1

all_values[1]

auto[0]

auto[1]

auto[0]

144

1

T4

1

T29

1

T6

1

all_values[1]

auto[0]

auto[1]

auto[1]

120

1

T4

1

T29

1

T6

2

all_values[1]

auto[1]

auto[0]

auto[1]

188

1

T29

1

T6

1

T13

2

all_values[1]

auto[1]

auto[1]

auto[1]

189

1

T4

1

T29

1

T6

4

all_values[2]

auto[0]

auto[0]

auto[0]

174

1

T13

4

T30

2

T49

2

all_values[2]

auto[0]

auto[0]

auto[1]

98

1

T4

1

T29

3

T6

1

all_values[2]

auto[0]

auto[1]

auto[0]

139

1

T4

1

T6

2

T13

1

all_values[2]

auto[0]

auto[1]

auto[1]

84

1

T6

1

T13

1

T30

1

all_values[2]

auto[1]

auto[0]

auto[1]

197

1

T4

2

T29

3

T6

5

all_values[2]

auto[1]

auto[1]

auto[1]

191

1

T29

1

T6

2

T13

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal