Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.39 92.80 85.92 100.00 76.32 88.15 99.49 69.08


Total test records in report: 736
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T547 /workspace/coverage/default/43.hmac_error.559213828 Mar 07 01:05:18 PM PST 24 Mar 07 01:06:13 PM PST 24 7067748271 ps
T548 /workspace/coverage/default/20.hmac_back_pressure.3278534694 Mar 07 01:03:54 PM PST 24 Mar 07 01:03:58 PM PST 24 296219485 ps
T78 /workspace/coverage/default/38.hmac_stress_all.3739731363 Mar 07 01:04:51 PM PST 24 Mar 07 01:10:25 PM PST 24 85268260187 ps
T549 /workspace/coverage/default/12.hmac_wipe_secret.2400937686 Mar 07 01:03:18 PM PST 24 Mar 07 01:03:21 PM PST 24 168299683 ps
T550 /workspace/coverage/default/37.hmac_burst_wr.4281399559 Mar 07 01:04:48 PM PST 24 Mar 07 01:04:58 PM PST 24 2390744628 ps
T551 /workspace/coverage/default/47.hmac_stress_all.2764068753 Mar 07 01:05:21 PM PST 24 Mar 07 01:16:28 PM PST 24 189530467664 ps
T552 /workspace/coverage/default/39.hmac_burst_wr.15344817 Mar 07 01:04:49 PM PST 24 Mar 07 01:04:53 PM PST 24 709714577 ps
T553 /workspace/coverage/default/17.hmac_test_sha_vectors.2409684644 Mar 07 01:03:29 PM PST 24 Mar 07 01:10:36 PM PST 24 7816704859 ps
T554 /workspace/coverage/default/26.hmac_wipe_secret.2678486487 Mar 07 01:04:07 PM PST 24 Mar 07 01:04:48 PM PST 24 8799062897 ps
T555 /workspace/coverage/default/46.hmac_datapath_stress.3522837298 Mar 07 01:05:21 PM PST 24 Mar 07 01:06:43 PM PST 24 1472466382 ps
T556 /workspace/coverage/default/44.hmac_datapath_stress.3412797699 Mar 07 01:05:11 PM PST 24 Mar 07 01:06:24 PM PST 24 1287146209 ps
T557 /workspace/coverage/default/24.hmac_test_sha_vectors.1061239219 Mar 07 01:03:54 PM PST 24 Mar 07 01:12:19 PM PST 24 40247060039 ps
T558 /workspace/coverage/default/49.hmac_burst_wr.3967305466 Mar 07 01:05:31 PM PST 24 Mar 07 01:05:49 PM PST 24 5350671602 ps
T559 /workspace/coverage/default/44.hmac_test_hmac_vectors.641801108 Mar 07 01:05:12 PM PST 24 Mar 07 01:05:14 PM PST 24 29125853 ps
T560 /workspace/coverage/default/48.hmac_burst_wr.2438327536 Mar 07 01:05:25 PM PST 24 Mar 07 01:06:18 PM PST 24 5526498396 ps
T561 /workspace/coverage/default/39.hmac_test_hmac_vectors.1976309193 Mar 07 01:04:49 PM PST 24 Mar 07 01:04:51 PM PST 24 28727538 ps
T562 /workspace/coverage/default/22.hmac_test_sha_vectors.2772425999 Mar 07 01:03:44 PM PST 24 Mar 07 01:10:48 PM PST 24 156002562632 ps
T563 /workspace/coverage/default/37.hmac_error.3742556940 Mar 07 01:04:48 PM PST 24 Mar 07 01:04:59 PM PST 24 213668608 ps
T564 /workspace/coverage/default/6.hmac_wipe_secret.3896683908 Mar 07 01:02:29 PM PST 24 Mar 07 01:03:52 PM PST 24 5558047199 ps
T565 /workspace/coverage/default/16.hmac_test_hmac_vectors.3522806274 Mar 07 01:03:30 PM PST 24 Mar 07 01:03:31 PM PST 24 239950332 ps
T37 /workspace/coverage/default/2.hmac_sec_cm.414241480 Mar 07 01:02:08 PM PST 24 Mar 07 01:02:09 PM PST 24 526973011 ps
T566 /workspace/coverage/default/31.hmac_wipe_secret.1019820665 Mar 07 01:04:19 PM PST 24 Mar 07 01:05:35 PM PST 24 5892904495 ps
T567 /workspace/coverage/default/32.hmac_error.3256556086 Mar 07 01:04:35 PM PST 24 Mar 07 01:06:48 PM PST 24 15066632150 ps
T568 /workspace/coverage/default/42.hmac_test_sha_vectors.3503083421 Mar 07 01:05:03 PM PST 24 Mar 07 01:13:39 PM PST 24 160056932574 ps
T79 /workspace/coverage/default/33.hmac_stress_all.3616126638 Mar 07 01:04:29 PM PST 24 Mar 07 01:18:22 PM PST 24 246688800394 ps
T569 /workspace/coverage/default/7.hmac_stress_all.845691683 Mar 07 01:02:42 PM PST 24 Mar 07 01:21:22 PM PST 24 39657805326 ps
T570 /workspace/coverage/default/47.hmac_test_hmac_vectors.4191522368 Mar 07 01:05:23 PM PST 24 Mar 07 01:05:26 PM PST 24 262084916 ps
T571 /workspace/coverage/default/36.hmac_stress_all.1666378530 Mar 07 01:04:47 PM PST 24 Mar 07 01:06:11 PM PST 24 8416392073 ps
T572 /workspace/coverage/default/14.hmac_long_msg.744295443 Mar 07 01:03:24 PM PST 24 Mar 07 01:04:53 PM PST 24 18072868278 ps
T573 /workspace/coverage/default/36.hmac_back_pressure.449906236 Mar 07 01:04:49 PM PST 24 Mar 07 01:04:57 PM PST 24 216643170 ps
T574 /workspace/coverage/default/27.hmac_burst_wr.1808611427 Mar 07 01:04:09 PM PST 24 Mar 07 01:04:28 PM PST 24 1416336931 ps
T575 /workspace/coverage/default/33.hmac_back_pressure.3558784334 Mar 07 01:04:35 PM PST 24 Mar 07 01:05:29 PM PST 24 2432095478 ps
T576 /workspace/coverage/default/7.hmac_long_msg.2523960271 Mar 07 01:02:36 PM PST 24 Mar 07 01:02:44 PM PST 24 392361589 ps
T92 /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.223369210 Mar 07 01:04:47 PM PST 24 Mar 07 01:37:51 PM PST 24 53126112074 ps
T93 /workspace/coverage/default/48.hmac_test_hmac_vectors.11667242 Mar 07 01:05:23 PM PST 24 Mar 07 01:05:25 PM PST 24 59733821 ps
T94 /workspace/coverage/default/37.hmac_test_hmac_vectors.3444605461 Mar 07 01:04:50 PM PST 24 Mar 07 01:04:52 PM PST 24 29591989 ps
T95 /workspace/coverage/default/26.hmac_long_msg.4245327321 Mar 07 01:04:08 PM PST 24 Mar 07 01:04:36 PM PST 24 5645911762 ps
T96 /workspace/coverage/default/49.hmac_error.44102014 Mar 07 01:05:32 PM PST 24 Mar 07 01:07:43 PM PST 24 7107899222 ps
T97 /workspace/coverage/default/28.hmac_wipe_secret.2126095743 Mar 07 01:04:08 PM PST 24 Mar 07 01:04:12 PM PST 24 564516805 ps
T98 /workspace/coverage/default/16.hmac_back_pressure.3541434630 Mar 07 01:03:31 PM PST 24 Mar 07 01:04:33 PM PST 24 6244119353 ps
T99 /workspace/coverage/default/17.hmac_long_msg.3985102230 Mar 07 01:03:37 PM PST 24 Mar 07 01:03:50 PM PST 24 953226023 ps
T100 /workspace/coverage/default/9.hmac_stress_all.896746373 Mar 07 01:02:54 PM PST 24 Mar 07 01:20:44 PM PST 24 229232577725 ps
T101 /workspace/coverage/default/12.hmac_alert_test.978181851 Mar 07 01:03:17 PM PST 24 Mar 07 01:03:18 PM PST 24 106449886 ps
T577 /workspace/coverage/default/47.hmac_error.2854176724 Mar 07 01:05:22 PM PST 24 Mar 07 01:08:07 PM PST 24 18697089055 ps
T578 /workspace/coverage/default/23.hmac_long_msg.4075986227 Mar 07 01:03:43 PM PST 24 Mar 07 01:05:05 PM PST 24 5461045635 ps
T579 /workspace/coverage/default/29.hmac_error.3002067706 Mar 07 01:04:18 PM PST 24 Mar 07 01:05:53 PM PST 24 44696839282 ps
T580 /workspace/coverage/default/37.hmac_wipe_secret.2551025873 Mar 07 01:04:48 PM PST 24 Mar 07 01:05:49 PM PST 24 5692607213 ps
T581 /workspace/coverage/default/25.hmac_error.191033080 Mar 07 01:03:55 PM PST 24 Mar 07 01:04:18 PM PST 24 419765195 ps
T582 /workspace/coverage/default/7.hmac_datapath_stress.3370359493 Mar 07 01:02:35 PM PST 24 Mar 07 01:03:45 PM PST 24 5562832273 ps
T583 /workspace/coverage/default/43.hmac_test_sha_vectors.2959783334 Mar 07 01:05:14 PM PST 24 Mar 07 01:12:14 PM PST 24 14886428089 ps
T584 /workspace/coverage/default/45.hmac_long_msg.801085902 Mar 07 01:05:11 PM PST 24 Mar 07 01:06:17 PM PST 24 3054756554 ps
T585 /workspace/coverage/default/16.hmac_test_sha_vectors.619275839 Mar 07 01:03:30 PM PST 24 Mar 07 01:10:59 PM PST 24 18516858717 ps
T586 /workspace/coverage/default/24.hmac_stress_all.2549141077 Mar 07 01:03:54 PM PST 24 Mar 07 01:11:15 PM PST 24 23884941331 ps
T587 /workspace/coverage/default/13.hmac_error.1393930474 Mar 07 01:03:17 PM PST 24 Mar 07 01:04:25 PM PST 24 1245130464 ps
T588 /workspace/coverage/default/3.hmac_wipe_secret.506715819 Mar 07 01:02:10 PM PST 24 Mar 07 01:03:10 PM PST 24 8889280674 ps
T589 /workspace/coverage/default/24.hmac_burst_wr.1183966335 Mar 07 01:03:54 PM PST 24 Mar 07 01:04:31 PM PST 24 702027072 ps
T590 /workspace/coverage/default/17.hmac_back_pressure.688753706 Mar 07 01:03:35 PM PST 24 Mar 07 01:04:25 PM PST 24 10785540945 ps
T591 /workspace/coverage/default/11.hmac_smoke.2704248561 Mar 07 01:02:53 PM PST 24 Mar 07 01:03:00 PM PST 24 1541148095 ps
T592 /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.1937013391 Mar 07 01:05:49 PM PST 24 Mar 07 01:14:05 PM PST 24 102781854395 ps
T593 /workspace/coverage/default/31.hmac_burst_wr.3691397458 Mar 07 01:04:17 PM PST 24 Mar 07 01:04:44 PM PST 24 2705492548 ps
T594 /workspace/coverage/default/49.hmac_long_msg.2284563492 Mar 07 01:05:31 PM PST 24 Mar 07 01:05:59 PM PST 24 2082209410 ps
T595 /workspace/coverage/default/43.hmac_test_hmac_vectors.1622363772 Mar 07 01:05:10 PM PST 24 Mar 07 01:05:11 PM PST 24 227668722 ps
T596 /workspace/coverage/default/26.hmac_stress_all.2968911846 Mar 07 01:04:08 PM PST 24 Mar 07 01:14:10 PM PST 24 47082692570 ps
T597 /workspace/coverage/default/10.hmac_test_hmac_vectors.2502361234 Mar 07 01:02:54 PM PST 24 Mar 07 01:02:55 PM PST 24 507110876 ps
T598 /workspace/coverage/default/26.hmac_error.1894776103 Mar 07 01:04:07 PM PST 24 Mar 07 01:05:24 PM PST 24 4789915702 ps
T599 /workspace/coverage/default/0.hmac_burst_wr.1258279164 Mar 07 01:02:17 PM PST 24 Mar 07 01:03:31 PM PST 24 3062453901 ps
T600 /workspace/coverage/default/5.hmac_datapath_stress.2230773736 Mar 07 01:02:29 PM PST 24 Mar 07 01:04:42 PM PST 24 6543163382 ps
T601 /workspace/coverage/default/5.hmac_error.2321572406 Mar 07 01:02:24 PM PST 24 Mar 07 01:05:15 PM PST 24 9957906163 ps
T602 /workspace/coverage/default/10.hmac_alert_test.3603181254 Mar 07 01:02:52 PM PST 24 Mar 07 01:02:53 PM PST 24 13181660 ps
T603 /workspace/coverage/default/34.hmac_error.3189966375 Mar 07 01:04:28 PM PST 24 Mar 07 01:05:41 PM PST 24 3312852163 ps
T604 /workspace/coverage/default/14.hmac_datapath_stress.348752868 Mar 07 01:03:17 PM PST 24 Mar 07 01:03:46 PM PST 24 3685640222 ps
T63 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1553527216 Mar 07 12:53:57 PM PST 24 Mar 07 12:54:01 PM PST 24 65390884 ps
T59 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3741116058 Mar 07 12:54:14 PM PST 24 Mar 07 12:54:16 PM PST 24 158156110 ps
T605 /workspace/coverage/cover_reg_top/3.hmac_intr_test.302564234 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:03 PM PST 24 62806942 ps
T64 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4293174973 Mar 07 12:54:03 PM PST 24 Mar 07 12:54:05 PM PST 24 120014469 ps
T606 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1564661658 Mar 07 12:54:10 PM PST 24 Mar 07 12:54:12 PM PST 24 266998602 ps
T80 /workspace/coverage/cover_reg_top/44.hmac_intr_test.906465175 Mar 07 12:53:56 PM PST 24 Mar 07 12:53:57 PM PST 24 61896788 ps
T607 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3296516533 Mar 07 12:53:49 PM PST 24 Mar 07 12:53:49 PM PST 24 16781640 ps
T608 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4226576413 Mar 07 12:53:50 PM PST 24 Mar 07 12:53:51 PM PST 24 81812317 ps
T609 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3547907454 Mar 07 12:53:49 PM PST 24 Mar 07 12:53:50 PM PST 24 56607348 ps
T610 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1311818217 Mar 07 12:53:43 PM PST 24 Mar 07 12:53:44 PM PST 24 15386932 ps
T611 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.662701484 Mar 07 12:53:52 PM PST 24 Mar 07 12:53:55 PM PST 24 40810647 ps
T612 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3045688824 Mar 07 12:53:45 PM PST 24 Mar 07 12:53:47 PM PST 24 302102316 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3652825568 Mar 07 12:53:48 PM PST 24 Mar 07 01:04:06 PM PST 24 181859085029 ps
T81 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2517008034 Mar 07 12:53:49 PM PST 24 Mar 07 12:53:50 PM PST 24 27719468 ps
T614 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3531230594 Mar 07 12:53:39 PM PST 24 Mar 07 12:53:40 PM PST 24 175942829 ps
T615 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2310692010 Mar 07 12:53:53 PM PST 24 Mar 07 12:53:59 PM PST 24 16203425 ps
T616 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.675027292 Mar 07 12:53:58 PM PST 24 Mar 07 12:54:02 PM PST 24 51946980 ps
T617 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2474208952 Mar 07 12:53:43 PM PST 24 Mar 07 12:53:46 PM PST 24 318482885 ps
T618 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2786736700 Mar 07 12:53:49 PM PST 24 Mar 07 12:53:51 PM PST 24 34050396 ps
T102 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3616769227 Mar 07 12:53:45 PM PST 24 Mar 07 12:53:46 PM PST 24 85858468 ps
T619 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1414217423 Mar 07 12:53:46 PM PST 24 Mar 07 12:53:50 PM PST 24 189128228 ps
T620 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3947909328 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:04 PM PST 24 29621851 ps
T621 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3992368924 Mar 07 12:53:51 PM PST 24 Mar 07 12:53:54 PM PST 24 116576687 ps
T622 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.272454707 Mar 07 12:53:31 PM PST 24 Mar 07 12:53:33 PM PST 24 77698792 ps
T623 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2743754938 Mar 07 12:53:53 PM PST 24 Mar 07 12:53:55 PM PST 24 74660569 ps
T624 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.831415563 Mar 07 12:53:47 PM PST 24 Mar 07 12:53:50 PM PST 24 420492154 ps
T625 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.199219850 Mar 07 12:53:59 PM PST 24 Mar 07 12:54:01 PM PST 24 296248104 ps
T60 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.284284985 Mar 07 12:53:55 PM PST 24 Mar 07 12:54:03 PM PST 24 53600673 ps
T626 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.414430702 Mar 07 12:53:56 PM PST 24 Mar 07 12:53:57 PM PST 24 29115726 ps
T61 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3779098502 Mar 07 12:53:51 PM PST 24 Mar 07 12:53:55 PM PST 24 223432963 ps
T627 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1464118114 Mar 07 12:53:57 PM PST 24 Mar 07 12:53:58 PM PST 24 11078582 ps
T628 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3914141750 Mar 07 12:54:17 PM PST 24 Mar 07 12:54:18 PM PST 24 53867932 ps
T629 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2339458015 Mar 07 12:53:42 PM PST 24 Mar 07 12:53:48 PM PST 24 723149908 ps
T630 /workspace/coverage/cover_reg_top/22.hmac_intr_test.362764655 Mar 07 12:54:16 PM PST 24 Mar 07 12:54:17 PM PST 24 15784178 ps
T631 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3969103773 Mar 07 12:53:28 PM PST 24 Mar 07 12:53:32 PM PST 24 188833497 ps
T632 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.956170035 Mar 07 12:53:58 PM PST 24 Mar 07 12:54:01 PM PST 24 533746283 ps
T633 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2881626581 Mar 07 12:53:41 PM PST 24 Mar 07 12:53:43 PM PST 24 16723564 ps
T634 /workspace/coverage/cover_reg_top/0.hmac_intr_test.800521504 Mar 07 12:53:42 PM PST 24 Mar 07 12:53:48 PM PST 24 16501507 ps
T635 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.981477505 Mar 07 12:53:55 PM PST 24 Mar 07 12:54:02 PM PST 24 451108730 ps
T103 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2624009133 Mar 07 12:53:40 PM PST 24 Mar 07 12:53:48 PM PST 24 618265548 ps
T636 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1686264848 Mar 07 12:53:49 PM PST 24 Mar 07 12:53:51 PM PST 24 17637173 ps
T122 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3637305312 Mar 07 12:53:47 PM PST 24 Mar 07 12:53:50 PM PST 24 296601981 ps
T637 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2309615690 Mar 07 12:54:16 PM PST 24 Mar 07 12:54:17 PM PST 24 51692970 ps
T638 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1547563200 Mar 07 12:53:41 PM PST 24 Mar 07 12:53:42 PM PST 24 18499313 ps
T639 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1674939444 Mar 07 12:53:48 PM PST 24 Mar 07 12:53:49 PM PST 24 25445825 ps
T640 /workspace/coverage/cover_reg_top/16.hmac_intr_test.699587749 Mar 07 12:54:09 PM PST 24 Mar 07 12:54:10 PM PST 24 27794952 ps
T641 /workspace/coverage/cover_reg_top/40.hmac_intr_test.4152672058 Mar 07 12:54:10 PM PST 24 Mar 07 12:54:10 PM PST 24 43038452 ps
T104 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.263125323 Mar 07 12:54:00 PM PST 24 Mar 07 12:54:03 PM PST 24 120279178 ps
T642 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.388860459 Mar 07 12:53:47 PM PST 24 Mar 07 12:53:48 PM PST 24 83296214 ps
T643 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2552854324 Mar 07 12:53:48 PM PST 24 Mar 07 12:53:50 PM PST 24 79943895 ps
T644 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3133140154 Mar 07 12:53:49 PM PST 24 Mar 07 12:53:51 PM PST 24 62149530 ps
T645 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1895250654 Mar 07 12:53:57 PM PST 24 Mar 07 12:53:58 PM PST 24 17632127 ps
T646 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1191553445 Mar 07 12:53:50 PM PST 24 Mar 07 12:53:54 PM PST 24 70996074 ps
T647 /workspace/coverage/cover_reg_top/28.hmac_intr_test.508554912 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:04 PM PST 24 16565732 ps
T123 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2169773178 Mar 07 12:54:03 PM PST 24 Mar 07 12:54:07 PM PST 24 125485114 ps
T105 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1667659171 Mar 07 12:53:44 PM PST 24 Mar 07 12:53:45 PM PST 24 20240005 ps
T111 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1564885730 Mar 07 12:53:47 PM PST 24 Mar 07 12:53:57 PM PST 24 1224284184 ps
T648 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1827734178 Mar 07 12:53:41 PM PST 24 Mar 07 12:53:42 PM PST 24 12546069 ps
T649 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2215416889 Mar 07 12:53:46 PM PST 24 Mar 07 12:53:48 PM PST 24 51274475 ps
T126 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3202695120 Mar 07 12:53:43 PM PST 24 Mar 07 12:53:47 PM PST 24 1013564166 ps
T650 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1743298728 Mar 07 12:53:42 PM PST 24 Mar 07 12:53:43 PM PST 24 39575876 ps
T106 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1408436508 Mar 07 12:53:52 PM PST 24 Mar 07 12:53:53 PM PST 24 102543465 ps
T107 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2726002604 Mar 07 12:53:58 PM PST 24 Mar 07 12:54:02 PM PST 24 167147207 ps
T651 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2509787658 Mar 07 12:53:53 PM PST 24 Mar 07 12:53:55 PM PST 24 88843089 ps
T119 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.774254284 Mar 07 12:53:54 PM PST 24 Mar 07 12:53:58 PM PST 24 1672563334 ps
T652 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.694359041 Mar 07 12:53:47 PM PST 24 Mar 07 12:53:51 PM PST 24 360464786 ps
T653 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3139318992 Mar 07 12:54:13 PM PST 24 Mar 07 12:54:14 PM PST 24 15020290 ps
T654 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2810751162 Mar 07 12:53:51 PM PST 24 Mar 07 12:53:52 PM PST 24 43576881 ps
T655 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2454419584 Mar 07 12:54:01 PM PST 24 Mar 07 12:54:03 PM PST 24 17312342 ps
T656 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.664632609 Mar 07 12:53:41 PM PST 24 Mar 07 12:53:43 PM PST 24 74639850 ps
T108 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2286490701 Mar 07 12:53:41 PM PST 24 Mar 07 12:53:42 PM PST 24 153323246 ps
T657 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1241740103 Mar 07 12:53:58 PM PST 24 Mar 07 12:53:59 PM PST 24 15483753 ps
T658 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.266230504 Mar 07 12:53:49 PM PST 24 Mar 07 12:53:51 PM PST 24 236359746 ps
T659 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4125104548 Mar 07 12:53:40 PM PST 24 Mar 07 12:53:41 PM PST 24 115145509 ps
T109 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.792459777 Mar 07 12:53:46 PM PST 24 Mar 07 12:53:47 PM PST 24 84491356 ps
T660 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1747201496 Mar 07 12:53:59 PM PST 24 Mar 07 12:54:01 PM PST 24 118064801 ps
T125 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.86499968 Mar 07 12:53:40 PM PST 24 Mar 07 12:53:43 PM PST 24 100928715 ps
T661 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3603176998 Mar 07 12:53:46 PM PST 24 Mar 07 12:53:47 PM PST 24 172724347 ps
T110 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1694336206 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:13 PM PST 24 115639353 ps
T662 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2071024262 Mar 07 12:53:51 PM PST 24 Mar 07 12:53:52 PM PST 24 26496599 ps
T663 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2437040444 Mar 07 12:53:59 PM PST 24 Mar 07 12:54:01 PM PST 24 30337502 ps
T128 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2863779584 Mar 07 12:53:54 PM PST 24 Mar 07 12:53:57 PM PST 24 717975137 ps
T664 /workspace/coverage/cover_reg_top/26.hmac_intr_test.509383637 Mar 07 12:54:15 PM PST 24 Mar 07 12:54:16 PM PST 24 137691673 ps
T127 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1500349866 Mar 07 12:53:54 PM PST 24 Mar 07 12:53:56 PM PST 24 173353668 ps
T112 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3885350299 Mar 07 12:53:53 PM PST 24 Mar 07 12:53:54 PM PST 24 19375620 ps
T665 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3144669755 Mar 07 12:53:42 PM PST 24 Mar 07 12:53:44 PM PST 24 368175340 ps
T666 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.507833081 Mar 07 12:54:04 PM PST 24 Mar 07 12:54:06 PM PST 24 51716698 ps
T667 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2564283566 Mar 07 12:53:57 PM PST 24 Mar 07 12:53:59 PM PST 24 22431222 ps
T668 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2227858877 Mar 07 12:53:57 PM PST 24 Mar 07 12:53:58 PM PST 24 48342555 ps
T669 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2596149454 Mar 07 12:53:49 PM PST 24 Mar 07 12:53:53 PM PST 24 502701004 ps
T670 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2803360783 Mar 07 12:53:58 PM PST 24 Mar 07 12:54:01 PM PST 24 432277408 ps
T671 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4195366693 Mar 07 12:54:07 PM PST 24 Mar 07 12:54:09 PM PST 24 273693589 ps
T672 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3167425107 Mar 07 12:53:50 PM PST 24 Mar 07 12:53:54 PM PST 24 1932250010 ps
T673 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1024439439 Mar 07 12:54:08 PM PST 24 Mar 07 12:54:09 PM PST 24 22984981 ps
T674 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3364410142 Mar 07 12:53:55 PM PST 24 Mar 07 01:11:18 PM PST 24 66448261778 ps
T120 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.448107139 Mar 07 12:53:51 PM PST 24 Mar 07 12:53:55 PM PST 24 463204151 ps
T675 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2746657783 Mar 07 12:54:09 PM PST 24 Mar 07 12:54:10 PM PST 24 138971549 ps
T676 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1768826828 Mar 07 12:53:53 PM PST 24 Mar 07 12:53:54 PM PST 24 13508425 ps
T677 /workspace/coverage/cover_reg_top/23.hmac_intr_test.172279722 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:13 PM PST 24 52640355 ps
T115 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2011673182 Mar 07 12:53:57 PM PST 24 Mar 07 12:53:58 PM PST 24 26255417 ps
T124 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.574901397 Mar 07 12:53:53 PM PST 24 Mar 07 12:54:02 PM PST 24 163626390 ps
T678 /workspace/coverage/cover_reg_top/32.hmac_intr_test.438102817 Mar 07 12:53:53 PM PST 24 Mar 07 12:53:53 PM PST 24 13481315 ps
T679 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3374290187 Mar 07 12:54:01 PM PST 24 Mar 07 12:54:06 PM PST 24 157662683 ps
T680 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1466907698 Mar 07 12:53:47 PM PST 24 Mar 07 12:53:50 PM PST 24 819963620 ps
T681 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4007104744 Mar 07 12:53:50 PM PST 24 Mar 07 12:53:52 PM PST 24 22779855 ps
T682 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1198553215 Mar 07 12:54:09 PM PST 24 Mar 07 12:54:12 PM PST 24 86071081 ps
T683 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3669695565 Mar 07 12:54:19 PM PST 24 Mar 07 12:54:20 PM PST 24 15261886 ps
T684 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3072944881 Mar 07 12:53:56 PM PST 24 Mar 07 12:54:02 PM PST 24 27110749 ps
T685 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1276036769 Mar 07 12:53:55 PM PST 24 Mar 07 12:53:56 PM PST 24 52800258 ps
T686 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3114084352 Mar 07 12:53:52 PM PST 24 Mar 07 12:53:53 PM PST 24 16363085 ps
T687 /workspace/coverage/cover_reg_top/4.hmac_intr_test.4204006951 Mar 07 12:53:45 PM PST 24 Mar 07 12:53:45 PM PST 24 13670484 ps
T688 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2017682199 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:13 PM PST 24 17044583 ps
T689 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1780210106 Mar 07 12:54:08 PM PST 24 Mar 07 12:54:09 PM PST 24 53232518 ps
T690 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2418717853 Mar 07 12:53:59 PM PST 24 Mar 07 12:54:00 PM PST 24 12763964 ps
T691 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.285360516 Mar 07 12:53:46 PM PST 24 Mar 07 12:53:48 PM PST 24 69093813 ps
T692 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2807309595 Mar 07 12:53:50 PM PST 24 Mar 07 12:53:52 PM PST 24 53048076 ps
T693 /workspace/coverage/cover_reg_top/47.hmac_intr_test.326036982 Mar 07 12:54:23 PM PST 24 Mar 07 12:54:24 PM PST 24 38195246 ps
T694 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.642437661 Mar 07 12:53:43 PM PST 24 Mar 07 12:53:45 PM PST 24 32832183 ps
T695 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2296227268 Mar 07 12:54:15 PM PST 24 Mar 07 12:54:17 PM PST 24 32324855 ps
T696 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1060910660 Mar 07 12:53:48 PM PST 24 Mar 07 12:53:54 PM PST 24 717939627 ps
T697 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4262055107 Mar 07 12:53:46 PM PST 24 Mar 07 12:53:49 PM PST 24 91290267 ps
T698 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.476887643 Mar 07 12:53:52 PM PST 24 Mar 07 12:53:54 PM PST 24 27930911 ps
T113 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2698547471 Mar 07 12:53:53 PM PST 24 Mar 07 12:53:55 PM PST 24 84373667 ps
T699 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3322060180 Mar 07 12:53:53 PM PST 24 Mar 07 12:56:59 PM PST 24 46283039062 ps
T114 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2389711927 Mar 07 12:53:50 PM PST 24 Mar 07 12:54:00 PM PST 24 863715367 ps
T700 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1126705536 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:13 PM PST 24 13968233 ps
T701 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2925760312 Mar 07 12:53:46 PM PST 24 Mar 07 12:53:53 PM PST 24 71348203 ps
T121 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.652205412 Mar 07 12:53:50 PM PST 24 Mar 07 12:53:54 PM PST 24 275653397 ps
T702 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3464425586 Mar 07 12:53:56 PM PST 24 Mar 07 12:53:59 PM PST 24 83020932 ps
T703 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3177523288 Mar 07 12:54:05 PM PST 24 Mar 07 12:54:06 PM PST 24 50178023 ps
T116 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2751728816 Mar 07 12:54:01 PM PST 24 Mar 07 12:54:03 PM PST 24 20409747 ps
T704 /workspace/coverage/cover_reg_top/31.hmac_intr_test.43757449 Mar 07 12:54:03 PM PST 24 Mar 07 12:54:04 PM PST 24 17525159 ps
T705 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.122713753 Mar 07 12:53:47 PM PST 24 Mar 07 12:53:57 PM PST 24 481556941 ps
T706 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2511153923 Mar 07 12:54:04 PM PST 24 Mar 07 12:54:07 PM PST 24 52829317 ps
T707 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.20331923 Mar 07 12:53:47 PM PST 24 Mar 07 12:53:49 PM PST 24 95291528 ps
T708 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.782372187 Mar 07 12:53:59 PM PST 24 Mar 07 12:54:02 PM PST 24 435779823 ps
T117 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3555690867 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:08 PM PST 24 409651389 ps
T709 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1356619062 Mar 07 12:53:49 PM PST 24 Mar 07 12:53:52 PM PST 24 523795939 ps
T710 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3536185485 Mar 07 12:53:57 PM PST 24 Mar 07 12:53:58 PM PST 24 46777123 ps
T711 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3270129107 Mar 07 12:53:53 PM PST 24 Mar 07 12:53:54 PM PST 24 85987444 ps
T712 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3459944238 Mar 07 12:53:56 PM PST 24 Mar 07 12:53:58 PM PST 24 52944665 ps
T713 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3454046713 Mar 07 12:53:59 PM PST 24 Mar 07 12:54:00 PM PST 24 17739334 ps
T714 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2708652898 Mar 07 12:54:39 PM PST 24 Mar 07 12:54:40 PM PST 24 12987792 ps
T715 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3411180923 Mar 07 12:53:48 PM PST 24 Mar 07 12:53:50 PM PST 24 104304815 ps
T716 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1414970635 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:13 PM PST 24 40510166 ps
T717 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.235695273 Mar 07 12:54:05 PM PST 24 Mar 07 12:54:06 PM PST 24 21342343 ps
T718 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1238888044 Mar 07 12:54:08 PM PST 24 Mar 07 12:54:10 PM PST 24 80507504 ps
T719 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1719249015 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:04 PM PST 24 27139222 ps
T720 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.743210252 Mar 07 12:53:32 PM PST 24 Mar 07 12:53:35 PM PST 24 318001585 ps
T721 /workspace/coverage/cover_reg_top/29.hmac_intr_test.782015893 Mar 07 12:53:49 PM PST 24 Mar 07 12:53:50 PM PST 24 32579612 ps
T722 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3656066029 Mar 07 12:53:48 PM PST 24 Mar 07 12:53:52 PM PST 24 888632945 ps
T723 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2050501843 Mar 07 12:53:58 PM PST 24 Mar 07 12:54:00 PM PST 24 268292965 ps
T724 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.915665533 Mar 07 12:53:40 PM PST 24 Mar 07 12:53:41 PM PST 24 128486283 ps
T725 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3483119911 Mar 07 12:54:07 PM PST 24 Mar 07 12:54:08 PM PST 24 94209695 ps
T726 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3933355326 Mar 07 12:53:55 PM PST 24 Mar 07 12:53:56 PM PST 24 34769511 ps
T727 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3904056792 Mar 07 12:53:43 PM PST 24 Mar 07 12:53:44 PM PST 24 67406787 ps
T728 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1316814357 Mar 07 12:53:55 PM PST 24 Mar 07 12:53:56 PM PST 24 14361807 ps
T729 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2384428313 Mar 07 12:53:55 PM PST 24 Mar 07 12:53:56 PM PST 24 143302724 ps
T730 /workspace/coverage/cover_reg_top/38.hmac_intr_test.218035677 Mar 07 12:53:46 PM PST 24 Mar 07 12:53:47 PM PST 24 35602076 ps
T731 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2113978971 Mar 07 12:54:12 PM PST 24 Mar 07 12:54:13 PM PST 24 20982503 ps
T732 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.825568457 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:08 PM PST 24 14680553 ps
T733 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3382199834 Mar 07 12:53:40 PM PST 24 Mar 07 12:53:42 PM PST 24 34259343 ps
T734 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3732754006 Mar 07 12:53:59 PM PST 24 Mar 07 12:54:01 PM PST 24 109103199 ps
T735 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1336335667 Mar 07 12:54:02 PM PST 24 Mar 07 12:54:06 PM PST 24 676782983 ps
T736 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2388208005 Mar 07 12:53:42 PM PST 24 Mar 07 12:53:43 PM PST 24 72534232 ps

Test location /workspace/coverage/default/3.hmac_burst_wr.3532493678
Short name T19
Test name
Test status
Simulation time 2272371140 ps
CPU time 26.68 seconds
Started Mar 07 01:02:08 PM PST 24
Finished Mar 07 01:02:35 PM PST 24
Peak memory 199952 kb
Host smart-e926efab-cefd-474b-80e8-1249cdbae2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532493678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3532493678
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.371284574
Short name T6
Test name
Test status
Simulation time 19668240484 ps
CPU time 1115.96 seconds
Started Mar 07 01:06:07 PM PST 24
Finished Mar 07 01:24:44 PM PST 24
Peak memory 243004 kb
Host smart-9b564f01-5ce3-410b-96e2-2d2cdda24e58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371284574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.371284574
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.3116626842
Short name T10
Test name
Test status
Simulation time 393612638496 ps
CPU time 4682.47 seconds
Started Mar 07 01:04:09 PM PST 24
Finished Mar 07 02:22:13 PM PST 24
Peak memory 265456 kb
Host smart-9742637f-e609-4ccc-920e-c7915b165a47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116626842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.3116626842
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.382485074
Short name T33
Test name
Test status
Simulation time 100426900 ps
CPU time 0.96 seconds
Started Mar 07 01:02:09 PM PST 24
Finished Mar 07 01:02:10 PM PST 24
Peak memory 219396 kb
Host smart-da992919-501e-475d-aba2-0fc7cd936b88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382485074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.382485074
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/29.hmac_stress_all.4238036063
Short name T13
Test name
Test status
Simulation time 312397193133 ps
CPU time 1330.04 seconds
Started Mar 07 01:04:25 PM PST 24
Finished Mar 07 01:26:35 PM PST 24
Peak memory 208228 kb
Host smart-806846ca-b18b-4fbc-99cb-b2c3fb436df3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238036063 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.4238036063
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all.355421440
Short name T1
Test name
Test status
Simulation time 18499997713 ps
CPU time 1065.6 seconds
Started Mar 07 01:02:09 PM PST 24
Finished Mar 07 01:19:54 PM PST 24
Peak memory 200004 kb
Host smart-65abc9d0-c9fd-4781-8a4b-200a26a00f1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355421440 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.355421440
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3741116058
Short name T59
Test name
Test status
Simulation time 158156110 ps
CPU time 1.84 seconds
Started Mar 07 12:54:14 PM PST 24
Finished Mar 07 12:54:16 PM PST 24
Peak memory 199108 kb
Host smart-46ce98e3-0d02-4b5e-80ab-64dd974cae0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741116058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3741116058
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2624009133
Short name T103
Test name
Test status
Simulation time 618265548 ps
CPU time 7.9 seconds
Started Mar 07 12:53:40 PM PST 24
Finished Mar 07 12:53:48 PM PST 24
Peak memory 198240 kb
Host smart-c74cc203-81a7-4d68-87c6-2faf63435439
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624009133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2624009133
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3779098502
Short name T61
Test name
Test status
Simulation time 223432963 ps
CPU time 4.13 seconds
Started Mar 07 12:53:51 PM PST 24
Finished Mar 07 12:53:55 PM PST 24
Peak memory 199044 kb
Host smart-dcc66d6c-a025-4dc8-8b82-92383e1238c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779098502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3779098502
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2169028058
Short name T23
Test name
Test status
Simulation time 35636858 ps
CPU time 0.54 seconds
Started Mar 07 01:02:13 PM PST 24
Finished Mar 07 01:02:14 PM PST 24
Peak memory 194300 kb
Host smart-2ca0a153-7af5-4cab-8cf1-410014d90998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169028058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2169028058
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_stress_all.500003946
Short name T49
Test name
Test status
Simulation time 210707575278 ps
CPU time 1916.5 seconds
Started Mar 07 01:03:34 PM PST 24
Finished Mar 07 01:35:33 PM PST 24
Peak memory 216192 kb
Host smart-8797e528-9d2f-4f96-b4dd-51073ccc03b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500003946 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.500003946
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.652205412
Short name T121
Test name
Test status
Simulation time 275653397 ps
CPU time 4.52 seconds
Started Mar 07 12:53:50 PM PST 24
Finished Mar 07 12:53:54 PM PST 24
Peak memory 199028 kb
Host smart-e63167e9-38f2-4a8e-a751-209795caa811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652205412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.652205412
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2517008034
Short name T81
Test name
Test status
Simulation time 27719468 ps
CPU time 0.57 seconds
Started Mar 07 12:53:49 PM PST 24
Finished Mar 07 12:53:50 PM PST 24
Peak memory 193588 kb
Host smart-833b9eaf-9f3d-44a6-b214-99687da60e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517008034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2517008034
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3412985679
Short name T26
Test name
Test status
Simulation time 520513324 ps
CPU time 6.21 seconds
Started Mar 07 01:02:19 PM PST 24
Finished Mar 07 01:02:25 PM PST 24
Peak memory 199792 kb
Host smart-e7cd2cde-a556-4223-a282-765291c191e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412985679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3412985679
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.2726815868
Short name T52
Test name
Test status
Simulation time 248095319772 ps
CPU time 1797.01 seconds
Started Mar 07 01:06:04 PM PST 24
Finished Mar 07 01:36:02 PM PST 24
Peak memory 224684 kb
Host smart-4d113379-2f88-4778-b131-f52117dbeec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726815868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.2726815868
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.122713753
Short name T705
Test name
Test status
Simulation time 481556941 ps
CPU time 9.93 seconds
Started Mar 07 12:53:47 PM PST 24
Finished Mar 07 12:53:57 PM PST 24
Peak memory 197688 kb
Host smart-30edc041-bedd-4c05-83e7-2dabc1875ee0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122713753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.122713753
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2286490701
Short name T108
Test name
Test status
Simulation time 153323246 ps
CPU time 0.78 seconds
Started Mar 07 12:53:41 PM PST 24
Finished Mar 07 12:53:42 PM PST 24
Peak memory 196068 kb
Host smart-bda7f5a9-701d-49ed-8e24-b86923aa7582
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286490701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2286490701
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.642437661
Short name T694
Test name
Test status
Simulation time 32832183 ps
CPU time 1.09 seconds
Started Mar 07 12:53:43 PM PST 24
Finished Mar 07 12:53:45 PM PST 24
Peak memory 199012 kb
Host smart-f2bd5b3b-fa9b-42b3-ad39-5c48704a0867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642437661 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.642437661
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2388208005
Short name T736
Test name
Test status
Simulation time 72534232 ps
CPU time 0.73 seconds
Started Mar 07 12:53:42 PM PST 24
Finished Mar 07 12:53:43 PM PST 24
Peak memory 196308 kb
Host smart-50e29c69-e076-4772-99f1-333391e17a0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388208005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2388208005
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.800521504
Short name T634
Test name
Test status
Simulation time 16501507 ps
CPU time 0.58 seconds
Started Mar 07 12:53:42 PM PST 24
Finished Mar 07 12:53:48 PM PST 24
Peak memory 193564 kb
Host smart-57960576-1305-42b0-828e-4cd7917b5d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800521504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.800521504
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3382199834
Short name T733
Test name
Test status
Simulation time 34259343 ps
CPU time 1.56 seconds
Started Mar 07 12:53:40 PM PST 24
Finished Mar 07 12:53:42 PM PST 24
Peak memory 198676 kb
Host smart-d145f664-bb2d-4b6d-a243-ba5084a22397
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382199834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3382199834
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.272454707
Short name T622
Test name
Test status
Simulation time 77698792 ps
CPU time 1.17 seconds
Started Mar 07 12:53:31 PM PST 24
Finished Mar 07 12:53:33 PM PST 24
Peak memory 199000 kb
Host smart-f16c3951-2616-4ca9-9cc3-13ef71dc46f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272454707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.272454707
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.743210252
Short name T720
Test name
Test status
Simulation time 318001585 ps
CPU time 1.91 seconds
Started Mar 07 12:53:32 PM PST 24
Finished Mar 07 12:53:35 PM PST 24
Peak memory 199048 kb
Host smart-70b3403f-fabe-4b6d-b63d-5bd9c5dcd0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743210252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.743210252
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1356619062
Short name T709
Test name
Test status
Simulation time 523795939 ps
CPU time 3.12 seconds
Started Mar 07 12:53:49 PM PST 24
Finished Mar 07 12:53:52 PM PST 24
Peak memory 197612 kb
Host smart-1ec5e64e-8b61-4190-a5bb-294837e55f3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356619062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1356619062
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2339458015
Short name T629
Test name
Test status
Simulation time 723149908 ps
CPU time 5.57 seconds
Started Mar 07 12:53:42 PM PST 24
Finished Mar 07 12:53:48 PM PST 24
Peak memory 197492 kb
Host smart-128bab95-535b-4654-8aca-7b8857f3dd0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339458015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2339458015
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2881626581
Short name T633
Test name
Test status
Simulation time 16723564 ps
CPU time 0.75 seconds
Started Mar 07 12:53:41 PM PST 24
Finished Mar 07 12:53:43 PM PST 24
Peak memory 196656 kb
Host smart-53ebff42-27d4-4636-9b7b-654554228123
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881626581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2881626581
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3652825568
Short name T613
Test name
Test status
Simulation time 181859085029 ps
CPU time 617.65 seconds
Started Mar 07 12:53:48 PM PST 24
Finished Mar 07 01:04:06 PM PST 24
Peak memory 215576 kb
Host smart-7bbbbad3-2087-4f0e-a52a-61a594b47c4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652825568 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3652825568
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4125104548
Short name T659
Test name
Test status
Simulation time 115145509 ps
CPU time 0.71 seconds
Started Mar 07 12:53:40 PM PST 24
Finished Mar 07 12:53:41 PM PST 24
Peak memory 196344 kb
Host smart-2e414c79-0886-4b7b-96ec-c4675e0f681f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125104548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4125104548
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1827734178
Short name T648
Test name
Test status
Simulation time 12546069 ps
CPU time 0.58 seconds
Started Mar 07 12:53:41 PM PST 24
Finished Mar 07 12:53:42 PM PST 24
Peak memory 193588 kb
Host smart-d30f77b9-b92a-4c28-b829-c603a4476bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827734178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1827734178
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1024439439
Short name T673
Test name
Test status
Simulation time 22984981 ps
CPU time 1.08 seconds
Started Mar 07 12:54:08 PM PST 24
Finished Mar 07 12:54:09 PM PST 24
Peak memory 198632 kb
Host smart-9ec47c7c-278d-4df9-86d7-42a77e8e506b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024439439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1024439439
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3969103773
Short name T631
Test name
Test status
Simulation time 188833497 ps
CPU time 4.12 seconds
Started Mar 07 12:53:28 PM PST 24
Finished Mar 07 12:53:32 PM PST 24
Peak memory 199124 kb
Host smart-d4f51731-6e95-4532-8dc2-c1aab3625eab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969103773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3969103773
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.664632609
Short name T656
Test name
Test status
Simulation time 74639850 ps
CPU time 1.75 seconds
Started Mar 07 12:53:41 PM PST 24
Finished Mar 07 12:53:43 PM PST 24
Peak memory 199044 kb
Host smart-8ff9a5e6-4af0-4230-94eb-05a4978b37a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664632609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.664632609
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2925760312
Short name T701
Test name
Test status
Simulation time 71348203 ps
CPU time 1.75 seconds
Started Mar 07 12:53:46 PM PST 24
Finished Mar 07 12:53:53 PM PST 24
Peak memory 199132 kb
Host smart-6c51e9eb-11b9-475b-bd11-c79231039944
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925760312 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2925760312
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1667659171
Short name T105
Test name
Test status
Simulation time 20240005 ps
CPU time 0.92 seconds
Started Mar 07 12:53:44 PM PST 24
Finished Mar 07 12:53:45 PM PST 24
Peak memory 197808 kb
Host smart-c99eee60-5318-49c7-89c9-a03efe364fb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667659171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1667659171
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1311818217
Short name T610
Test name
Test status
Simulation time 15386932 ps
CPU time 0.64 seconds
Started Mar 07 12:53:43 PM PST 24
Finished Mar 07 12:53:44 PM PST 24
Peak memory 193652 kb
Host smart-e52389c8-330f-4dd4-b0ba-0f49377d8b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311818217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1311818217
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2552854324
Short name T643
Test name
Test status
Simulation time 79943895 ps
CPU time 1.63 seconds
Started Mar 07 12:53:48 PM PST 24
Finished Mar 07 12:53:50 PM PST 24
Peak memory 198276 kb
Host smart-a2c447bc-d411-474c-9414-f189bb0c667c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552854324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2552854324
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2807309595
Short name T692
Test name
Test status
Simulation time 53048076 ps
CPU time 1.44 seconds
Started Mar 07 12:53:50 PM PST 24
Finished Mar 07 12:53:52 PM PST 24
Peak memory 199080 kb
Host smart-0d7b528e-2105-4da1-b59e-ab4e8eb91fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807309595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2807309595
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.574901397
Short name T124
Test name
Test status
Simulation time 163626390 ps
CPU time 3.85 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:54:02 PM PST 24
Peak memory 199064 kb
Host smart-0d0d2186-3089-4e71-bb19-8ec43b89b68a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574901397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.574901397
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.675027292
Short name T616
Test name
Test status
Simulation time 51946980 ps
CPU time 3.14 seconds
Started Mar 07 12:53:58 PM PST 24
Finished Mar 07 12:54:02 PM PST 24
Peak memory 207368 kb
Host smart-f9b72a9c-9d1f-457d-83c7-b9b0e36195fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675027292 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.675027292
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2751728816
Short name T116
Test name
Test status
Simulation time 20409747 ps
CPU time 0.89 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:54:03 PM PST 24
Peak memory 198112 kb
Host smart-ba99a36c-e4f3-4b5a-992b-21db829d6365
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751728816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2751728816
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1276036769
Short name T685
Test name
Test status
Simulation time 52800258 ps
CPU time 0.6 seconds
Started Mar 07 12:53:55 PM PST 24
Finished Mar 07 12:53:56 PM PST 24
Peak memory 193688 kb
Host smart-1e7d52b4-1e56-4779-9d59-8832209c2378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276036769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1276036769
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.266230504
Short name T658
Test name
Test status
Simulation time 236359746 ps
CPU time 2.11 seconds
Started Mar 07 12:53:49 PM PST 24
Finished Mar 07 12:53:51 PM PST 24
Peak memory 198732 kb
Host smart-8f0b8a2c-5ae3-453a-9fa2-c15ffa05d46b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266230504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.266230504
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3656066029
Short name T722
Test name
Test status
Simulation time 888632945 ps
CPU time 3.22 seconds
Started Mar 07 12:53:48 PM PST 24
Finished Mar 07 12:53:52 PM PST 24
Peak memory 199140 kb
Host smart-731d1f83-546e-4bf7-96da-4a015e5b83d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656066029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3656066029
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.662701484
Short name T611
Test name
Test status
Simulation time 40810647 ps
CPU time 2.78 seconds
Started Mar 07 12:53:52 PM PST 24
Finished Mar 07 12:53:55 PM PST 24
Peak memory 199160 kb
Host smart-92d8e2d0-16f2-47f7-8bd7-ae5e81f8f779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662701484 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.662701484
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.825568457
Short name T732
Test name
Test status
Simulation time 14680553 ps
CPU time 0.7 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:08 PM PST 24
Peak memory 196468 kb
Host smart-df4b198e-f79a-4631-9e76-e98248b02f64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825568457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.825568457
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2384428313
Short name T729
Test name
Test status
Simulation time 143302724 ps
CPU time 0.58 seconds
Started Mar 07 12:53:55 PM PST 24
Finished Mar 07 12:53:56 PM PST 24
Peak memory 193572 kb
Host smart-3b687bc5-fa2b-439f-8e06-729143882385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384428313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2384428313
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.199219850
Short name T625
Test name
Test status
Simulation time 296248104 ps
CPU time 1.64 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:54:01 PM PST 24
Peak memory 198004 kb
Host smart-aa47670a-5f92-4919-be4a-a23b8e921c5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199219850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.199219850
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1191553445
Short name T646
Test name
Test status
Simulation time 70996074 ps
CPU time 3.99 seconds
Started Mar 07 12:53:50 PM PST 24
Finished Mar 07 12:53:54 PM PST 24
Peak memory 199132 kb
Host smart-8046c761-c9ff-4cc6-a6cd-b0b2a4ae7770
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191553445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1191553445
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.86499968
Short name T125
Test name
Test status
Simulation time 100928715 ps
CPU time 2.89 seconds
Started Mar 07 12:53:40 PM PST 24
Finished Mar 07 12:53:43 PM PST 24
Peak memory 199052 kb
Host smart-97dceb1c-3182-46c1-ad49-f6d7c326aa1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86499968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.86499968
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1743298728
Short name T650
Test name
Test status
Simulation time 39575876 ps
CPU time 1.21 seconds
Started Mar 07 12:53:42 PM PST 24
Finished Mar 07 12:53:43 PM PST 24
Peak memory 198976 kb
Host smart-293f45b7-5ea8-45aa-b7b9-1806f32f96b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743298728 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1743298728
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1408436508
Short name T106
Test name
Test status
Simulation time 102543465 ps
CPU time 0.67 seconds
Started Mar 07 12:53:52 PM PST 24
Finished Mar 07 12:53:53 PM PST 24
Peak memory 196556 kb
Host smart-99985eb0-aa25-492a-823c-66909d08b9a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408436508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1408436508
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4226576413
Short name T608
Test name
Test status
Simulation time 81812317 ps
CPU time 1.06 seconds
Started Mar 07 12:53:50 PM PST 24
Finished Mar 07 12:53:51 PM PST 24
Peak memory 198628 kb
Host smart-79c37bf8-387e-4081-b5df-8532e7b80b77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226576413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.4226576413
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3167425107
Short name T672
Test name
Test status
Simulation time 1932250010 ps
CPU time 3.8 seconds
Started Mar 07 12:53:50 PM PST 24
Finished Mar 07 12:53:54 PM PST 24
Peak memory 199236 kb
Host smart-58edddb0-8556-4451-b5f6-8dba25ab2a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167425107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3167425107
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.476887643
Short name T698
Test name
Test status
Simulation time 27930911 ps
CPU time 1.6 seconds
Started Mar 07 12:53:52 PM PST 24
Finished Mar 07 12:53:54 PM PST 24
Peak memory 199208 kb
Host smart-591685c4-8398-4613-bdc8-d7970338d567
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476887643 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.476887643
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.263125323
Short name T104
Test name
Test status
Simulation time 120279178 ps
CPU time 0.96 seconds
Started Mar 07 12:54:00 PM PST 24
Finished Mar 07 12:54:03 PM PST 24
Peak memory 198976 kb
Host smart-b2c2d81f-e857-4886-a3ae-3acb4c066d14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263125323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.263125323
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2310692010
Short name T615
Test name
Test status
Simulation time 16203425 ps
CPU time 0.57 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:53:59 PM PST 24
Peak memory 193564 kb
Host smart-d9647b5d-348a-43bc-a12a-a295893837e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310692010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2310692010
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3732754006
Short name T734
Test name
Test status
Simulation time 109103199 ps
CPU time 1.85 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:54:01 PM PST 24
Peak memory 198784 kb
Host smart-e386b081-29fa-47b0-afb2-f28560bc9e25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732754006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3732754006
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.831415563
Short name T624
Test name
Test status
Simulation time 420492154 ps
CPU time 2.21 seconds
Started Mar 07 12:53:47 PM PST 24
Finished Mar 07 12:53:50 PM PST 24
Peak memory 199096 kb
Host smart-23be74bf-d25d-4e3b-bf4c-29783f229f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831415563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.831415563
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1198553215
Short name T682
Test name
Test status
Simulation time 86071081 ps
CPU time 2.82 seconds
Started Mar 07 12:54:09 PM PST 24
Finished Mar 07 12:54:12 PM PST 24
Peak memory 199020 kb
Host smart-c74a07d8-2f68-4c55-a81d-ae79cfb70020
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198553215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1198553215
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1564661658
Short name T606
Test name
Test status
Simulation time 266998602 ps
CPU time 2.5 seconds
Started Mar 07 12:54:10 PM PST 24
Finished Mar 07 12:54:12 PM PST 24
Peak memory 199100 kb
Host smart-4cedc4f5-f14b-4483-a01d-fb845b790335
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564661658 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1564661658
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3914141750
Short name T628
Test name
Test status
Simulation time 53867932 ps
CPU time 0.73 seconds
Started Mar 07 12:54:17 PM PST 24
Finished Mar 07 12:54:18 PM PST 24
Peak memory 196544 kb
Host smart-024fa148-aedf-417f-ae73-1376790f6b7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914141750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3914141750
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2418717853
Short name T690
Test name
Test status
Simulation time 12763964 ps
CPU time 0.58 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:54:00 PM PST 24
Peak memory 193560 kb
Host smart-61e996bc-e6b1-42b7-a96c-4ec7c5569c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418717853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2418717853
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4293174973
Short name T64
Test name
Test status
Simulation time 120014469 ps
CPU time 1.63 seconds
Started Mar 07 12:54:03 PM PST 24
Finished Mar 07 12:54:05 PM PST 24
Peak memory 199040 kb
Host smart-afd17c03-a41c-4b4e-a3fe-239fb069e682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293174973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.4293174973
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.285360516
Short name T691
Test name
Test status
Simulation time 69093813 ps
CPU time 1.44 seconds
Started Mar 07 12:53:46 PM PST 24
Finished Mar 07 12:53:48 PM PST 24
Peak memory 199120 kb
Host smart-8f5954ed-c23e-4bf0-97a7-28e95b5c4790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285360516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.285360516
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.284284985
Short name T60
Test name
Test status
Simulation time 53600673 ps
CPU time 1.76 seconds
Started Mar 07 12:53:55 PM PST 24
Finished Mar 07 12:54:03 PM PST 24
Peak memory 199076 kb
Host smart-7948c08b-58f8-4897-8800-2670a6e24cd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284284985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.284284985
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3364410142
Short name T674
Test name
Test status
Simulation time 66448261778 ps
CPU time 1042.24 seconds
Started Mar 07 12:53:55 PM PST 24
Finished Mar 07 01:11:18 PM PST 24
Peak memory 211244 kb
Host smart-b9f434bb-a39f-4030-9e35-e0bf17e5f424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364410142 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3364410142
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1719249015
Short name T719
Test name
Test status
Simulation time 27139222 ps
CPU time 0.89 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:04 PM PST 24
Peak memory 198124 kb
Host smart-17671013-0fd8-4d50-bbf7-025d306fc08b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719249015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1719249015
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.699587749
Short name T640
Test name
Test status
Simulation time 27794952 ps
CPU time 0.59 seconds
Started Mar 07 12:54:09 PM PST 24
Finished Mar 07 12:54:10 PM PST 24
Peak memory 193656 kb
Host smart-aaf434f2-0bf0-45d5-b719-fdf21042fb06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699587749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.699587749
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2296227268
Short name T695
Test name
Test status
Simulation time 32324855 ps
CPU time 1.51 seconds
Started Mar 07 12:54:15 PM PST 24
Finished Mar 07 12:54:17 PM PST 24
Peak memory 198352 kb
Host smart-8370037c-a70f-4b4a-9168-aa1e766b7240
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296227268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2296227268
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2596149454
Short name T669
Test name
Test status
Simulation time 502701004 ps
CPU time 3.12 seconds
Started Mar 07 12:53:49 PM PST 24
Finished Mar 07 12:53:53 PM PST 24
Peak memory 199176 kb
Host smart-3934115c-ea6b-45e0-8167-fc9c36a0a5d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596149454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2596149454
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3202695120
Short name T126
Test name
Test status
Simulation time 1013564166 ps
CPU time 3.01 seconds
Started Mar 07 12:53:43 PM PST 24
Finished Mar 07 12:53:47 PM PST 24
Peak memory 199040 kb
Host smart-24a3c5bb-d799-49a7-a669-528bc0bb9264
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202695120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3202695120
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3459944238
Short name T712
Test name
Test status
Simulation time 52944665 ps
CPU time 1.75 seconds
Started Mar 07 12:53:56 PM PST 24
Finished Mar 07 12:53:58 PM PST 24
Peak memory 199124 kb
Host smart-f29a885b-6fa2-4b22-899d-9f5f6f70ef90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459944238 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3459944238
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.414430702
Short name T626
Test name
Test status
Simulation time 29115726 ps
CPU time 0.66 seconds
Started Mar 07 12:53:56 PM PST 24
Finished Mar 07 12:53:57 PM PST 24
Peak memory 196136 kb
Host smart-a1589705-05ef-45d4-ac6d-e292caa423a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414430702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.414430702
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2746657783
Short name T675
Test name
Test status
Simulation time 138971549 ps
CPU time 0.57 seconds
Started Mar 07 12:54:09 PM PST 24
Finished Mar 07 12:54:10 PM PST 24
Peak memory 193588 kb
Host smart-58ccdbba-d2ac-43b9-8a9b-1ba46da3b526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746657783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2746657783
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4195366693
Short name T671
Test name
Test status
Simulation time 273693589 ps
CPU time 2.12 seconds
Started Mar 07 12:54:07 PM PST 24
Finished Mar 07 12:54:09 PM PST 24
Peak memory 198764 kb
Host smart-b64d55ee-346f-4c08-be45-9ea62d189b64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195366693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4195366693
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3464425586
Short name T702
Test name
Test status
Simulation time 83020932 ps
CPU time 2.37 seconds
Started Mar 07 12:53:56 PM PST 24
Finished Mar 07 12:53:59 PM PST 24
Peak memory 199112 kb
Host smart-e29d1ad2-8c96-44ed-8bf3-aee994049828
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464425586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3464425586
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1500349866
Short name T127
Test name
Test status
Simulation time 173353668 ps
CPU time 1.71 seconds
Started Mar 07 12:53:54 PM PST 24
Finished Mar 07 12:53:56 PM PST 24
Peak memory 199076 kb
Host smart-84e6f16b-37c7-4d0a-96c6-c0e806675c80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500349866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1500349866
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2803360783
Short name T670
Test name
Test status
Simulation time 432277408 ps
CPU time 2.37 seconds
Started Mar 07 12:53:58 PM PST 24
Finished Mar 07 12:54:01 PM PST 24
Peak memory 199104 kb
Host smart-c4a180ff-f55c-4496-9c77-43b8663361e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803360783 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2803360783
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3270129107
Short name T711
Test name
Test status
Simulation time 85987444 ps
CPU time 0.81 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:53:54 PM PST 24
Peak memory 198080 kb
Host smart-4f267b96-2443-4f44-b91f-f5305cb81dbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270129107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3270129107
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1464118114
Short name T627
Test name
Test status
Simulation time 11078582 ps
CPU time 0.54 seconds
Started Mar 07 12:53:57 PM PST 24
Finished Mar 07 12:53:58 PM PST 24
Peak memory 193572 kb
Host smart-e537b738-5732-4121-9af2-275915c39ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464118114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1464118114
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3536185485
Short name T710
Test name
Test status
Simulation time 46777123 ps
CPU time 1.11 seconds
Started Mar 07 12:53:57 PM PST 24
Finished Mar 07 12:53:58 PM PST 24
Peak memory 196784 kb
Host smart-d6045d46-f288-46b6-80b9-d778d28cd3b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536185485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3536185485
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2509787658
Short name T651
Test name
Test status
Simulation time 88843089 ps
CPU time 2.3 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:53:55 PM PST 24
Peak memory 199048 kb
Host smart-fef46dad-5e78-4554-8ad8-21da89171c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509787658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2509787658
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.448107139
Short name T120
Test name
Test status
Simulation time 463204151 ps
CPU time 3.93 seconds
Started Mar 07 12:53:51 PM PST 24
Finished Mar 07 12:53:55 PM PST 24
Peak memory 199044 kb
Host smart-eb0bfa1b-3e8a-4e3b-92a5-26266a509be5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448107139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.448107139
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1238888044
Short name T718
Test name
Test status
Simulation time 80507504 ps
CPU time 2.11 seconds
Started Mar 07 12:54:08 PM PST 24
Finished Mar 07 12:54:10 PM PST 24
Peak memory 199184 kb
Host smart-78ca360c-8ff9-4bb8-ab43-ec965a668fea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238888044 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1238888044
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1694336206
Short name T110
Test name
Test status
Simulation time 115639353 ps
CPU time 0.88 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 198000 kb
Host smart-6983eaaa-f7b8-485b-97cd-701e41061989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694336206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1694336206
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1414970635
Short name T716
Test name
Test status
Simulation time 40510166 ps
CPU time 0.65 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 193644 kb
Host smart-a5125e5f-5d86-4519-bb62-ba4faf6c3e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414970635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1414970635
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2786736700
Short name T618
Test name
Test status
Simulation time 34050396 ps
CPU time 1.58 seconds
Started Mar 07 12:53:49 PM PST 24
Finished Mar 07 12:53:51 PM PST 24
Peak memory 197756 kb
Host smart-5638f602-2c5b-4310-a83a-d62b5852bec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786736700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2786736700
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1414217423
Short name T619
Test name
Test status
Simulation time 189128228 ps
CPU time 3.45 seconds
Started Mar 07 12:53:46 PM PST 24
Finished Mar 07 12:53:50 PM PST 24
Peak memory 199076 kb
Host smart-299a2b8b-0dd6-4147-92c7-1fc40a85be03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414217423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1414217423
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2169773178
Short name T123
Test name
Test status
Simulation time 125485114 ps
CPU time 3.81 seconds
Started Mar 07 12:54:03 PM PST 24
Finished Mar 07 12:54:07 PM PST 24
Peak memory 199044 kb
Host smart-e4f35c9c-c889-45fb-97cc-d116569ec8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169773178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2169773178
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2726002604
Short name T107
Test name
Test status
Simulation time 167147207 ps
CPU time 3.11 seconds
Started Mar 07 12:53:58 PM PST 24
Finished Mar 07 12:54:02 PM PST 24
Peak memory 197332 kb
Host smart-701478c7-0ae9-4697-b11f-3fea39dc2ca6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726002604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2726002604
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1060910660
Short name T696
Test name
Test status
Simulation time 717939627 ps
CPU time 5.56 seconds
Started Mar 07 12:53:48 PM PST 24
Finished Mar 07 12:53:54 PM PST 24
Peak memory 197628 kb
Host smart-1ebaccb0-a96d-496f-925d-98d9833debea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060910660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1060910660
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2698547471
Short name T113
Test name
Test status
Simulation time 84373667 ps
CPU time 0.95 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:53:55 PM PST 24
Peak memory 198624 kb
Host smart-73a97257-4223-48e1-9a96-03eccff42c12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698547471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2698547471
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.20331923
Short name T707
Test name
Test status
Simulation time 95291528 ps
CPU time 1.68 seconds
Started Mar 07 12:53:47 PM PST 24
Finished Mar 07 12:53:49 PM PST 24
Peak memory 199084 kb
Host smart-6ed461de-1fc9-4c74-8c92-45675e2afbdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20331923 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.20331923
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.792459777
Short name T109
Test name
Test status
Simulation time 84491356 ps
CPU time 0.8 seconds
Started Mar 07 12:53:46 PM PST 24
Finished Mar 07 12:53:47 PM PST 24
Peak memory 197672 kb
Host smart-980f5952-5887-40c0-a1d3-f5563b08a383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792459777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.792459777
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3296516533
Short name T607
Test name
Test status
Simulation time 16781640 ps
CPU time 0.59 seconds
Started Mar 07 12:53:49 PM PST 24
Finished Mar 07 12:53:49 PM PST 24
Peak memory 193572 kb
Host smart-9e29c039-254f-4838-8442-3a819f954d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296516533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3296516533
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.388860459
Short name T642
Test name
Test status
Simulation time 83296214 ps
CPU time 1.15 seconds
Started Mar 07 12:53:47 PM PST 24
Finished Mar 07 12:53:48 PM PST 24
Peak memory 198480 kb
Host smart-9540f1d6-acfc-4077-a09d-8c9f7d2023e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388860459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.388860459
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2474208952
Short name T617
Test name
Test status
Simulation time 318482885 ps
CPU time 2.93 seconds
Started Mar 07 12:53:43 PM PST 24
Finished Mar 07 12:53:46 PM PST 24
Peak memory 199200 kb
Host smart-08f943d0-71e1-461d-9822-af6e5742f3b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474208952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2474208952
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2863779584
Short name T128
Test name
Test status
Simulation time 717975137 ps
CPU time 3.16 seconds
Started Mar 07 12:53:54 PM PST 24
Finished Mar 07 12:53:57 PM PST 24
Peak memory 199024 kb
Host smart-0fb43383-1734-40a6-85d8-c32c1de3c60f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863779584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2863779584
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3933355326
Short name T726
Test name
Test status
Simulation time 34769511 ps
CPU time 0.54 seconds
Started Mar 07 12:53:55 PM PST 24
Finished Mar 07 12:53:56 PM PST 24
Peak memory 193464 kb
Host smart-6901b6de-b350-405d-9546-93d7e0c41e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933355326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3933355326
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1126705536
Short name T700
Test name
Test status
Simulation time 13968233 ps
CPU time 0.57 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 193568 kb
Host smart-e5e6a09a-4af5-4e15-af0c-ff88b2ca34d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126705536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1126705536
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.362764655
Short name T630
Test name
Test status
Simulation time 15784178 ps
CPU time 0.62 seconds
Started Mar 07 12:54:16 PM PST 24
Finished Mar 07 12:54:17 PM PST 24
Peak memory 193540 kb
Host smart-43150e03-1c53-40c5-9129-e4bc5551d30a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362764655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.362764655
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.172279722
Short name T677
Test name
Test status
Simulation time 52640355 ps
CPU time 0.57 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 193568 kb
Host smart-b2371fa6-bf1d-43db-a084-400078cd25af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172279722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.172279722
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3072944881
Short name T684
Test name
Test status
Simulation time 27110749 ps
CPU time 0.55 seconds
Started Mar 07 12:53:56 PM PST 24
Finished Mar 07 12:54:02 PM PST 24
Peak memory 193464 kb
Host smart-4e5d3ecd-6d89-453e-9648-c945c1332041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072944881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3072944881
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1780210106
Short name T689
Test name
Test status
Simulation time 53232518 ps
CPU time 0.59 seconds
Started Mar 07 12:54:08 PM PST 24
Finished Mar 07 12:54:09 PM PST 24
Peak memory 193588 kb
Host smart-994a80cc-6275-4876-9eef-667ef11ed95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780210106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1780210106
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.509383637
Short name T664
Test name
Test status
Simulation time 137691673 ps
CPU time 0.58 seconds
Started Mar 07 12:54:15 PM PST 24
Finished Mar 07 12:54:16 PM PST 24
Peak memory 193592 kb
Host smart-c51782ae-2705-4903-b6f7-181f01dce6fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509383637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.509383637
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1895250654
Short name T645
Test name
Test status
Simulation time 17632127 ps
CPU time 0.57 seconds
Started Mar 07 12:53:57 PM PST 24
Finished Mar 07 12:53:58 PM PST 24
Peak memory 193636 kb
Host smart-0670ebf2-e98f-4bbb-9e58-f0cd592e4bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895250654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1895250654
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.508554912
Short name T647
Test name
Test status
Simulation time 16565732 ps
CPU time 0.58 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:04 PM PST 24
Peak memory 193568 kb
Host smart-a54b173d-9576-47a2-9d0b-66c222548f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508554912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.508554912
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.782015893
Short name T721
Test name
Test status
Simulation time 32579612 ps
CPU time 0.63 seconds
Started Mar 07 12:53:49 PM PST 24
Finished Mar 07 12:53:50 PM PST 24
Peak memory 192764 kb
Host smart-2e9f4e19-6bbd-4bf6-b56a-e251ad979eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782015893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.782015893
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.981477505
Short name T635
Test name
Test status
Simulation time 451108730 ps
CPU time 6.57 seconds
Started Mar 07 12:53:55 PM PST 24
Finished Mar 07 12:54:02 PM PST 24
Peak memory 198220 kb
Host smart-11bcb797-832d-4fa3-adf5-8edf1ee9ed53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981477505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.981477505
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1564885730
Short name T111
Test name
Test status
Simulation time 1224284184 ps
CPU time 9.65 seconds
Started Mar 07 12:53:47 PM PST 24
Finished Mar 07 12:53:57 PM PST 24
Peak memory 197340 kb
Host smart-0781d2f2-8539-4abe-9e1c-92c8e489c3ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564885730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1564885730
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2011673182
Short name T115
Test name
Test status
Simulation time 26255417 ps
CPU time 0.88 seconds
Started Mar 07 12:53:57 PM PST 24
Finished Mar 07 12:53:58 PM PST 24
Peak memory 197820 kb
Host smart-c9f48ccf-c437-4a1d-ba19-310063a7a54a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011673182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2011673182
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3133140154
Short name T644
Test name
Test status
Simulation time 62149530 ps
CPU time 1.64 seconds
Started Mar 07 12:53:49 PM PST 24
Finished Mar 07 12:53:51 PM PST 24
Peak memory 199104 kb
Host smart-c2914dd9-07cd-44ef-bfb9-b79a8513cd08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133140154 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3133140154
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3114084352
Short name T686
Test name
Test status
Simulation time 16363085 ps
CPU time 0.82 seconds
Started Mar 07 12:53:52 PM PST 24
Finished Mar 07 12:53:53 PM PST 24
Peak memory 197984 kb
Host smart-0002c876-4cf2-4afa-9d10-73d1ae06e58e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114084352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3114084352
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.302564234
Short name T605
Test name
Test status
Simulation time 62806942 ps
CPU time 0.59 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:03 PM PST 24
Peak memory 193652 kb
Host smart-c3ae3279-97c7-48ce-b5a9-e61689eb7307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302564234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.302564234
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.915665533
Short name T724
Test name
Test status
Simulation time 128486283 ps
CPU time 1.17 seconds
Started Mar 07 12:53:40 PM PST 24
Finished Mar 07 12:53:41 PM PST 24
Peak memory 197536 kb
Host smart-ba0a2cbb-c444-4e08-9a8f-1cc0c2a9fa7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915665533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.915665533
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3374290187
Short name T679
Test name
Test status
Simulation time 157662683 ps
CPU time 3.6 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:54:06 PM PST 24
Peak memory 199096 kb
Host smart-7dfc836b-597c-44f1-ad9a-aff1623a767b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374290187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3374290187
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3139318992
Short name T653
Test name
Test status
Simulation time 15020290 ps
CPU time 0.58 seconds
Started Mar 07 12:54:13 PM PST 24
Finished Mar 07 12:54:14 PM PST 24
Peak memory 193644 kb
Host smart-9c280f81-6684-462a-ac06-f1784fab0d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139318992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3139318992
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.43757449
Short name T704
Test name
Test status
Simulation time 17525159 ps
CPU time 0.62 seconds
Started Mar 07 12:54:03 PM PST 24
Finished Mar 07 12:54:04 PM PST 24
Peak memory 193540 kb
Host smart-e0dd6168-f329-4c3f-961f-f356c17be907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43757449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.43757449
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.438102817
Short name T678
Test name
Test status
Simulation time 13481315 ps
CPU time 0.55 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:53:53 PM PST 24
Peak memory 193560 kb
Host smart-9e92dcc3-8193-4daf-bb9f-489a3adbe686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438102817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.438102817
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2071024262
Short name T662
Test name
Test status
Simulation time 26496599 ps
CPU time 0.6 seconds
Started Mar 07 12:53:51 PM PST 24
Finished Mar 07 12:53:52 PM PST 24
Peak memory 193540 kb
Host smart-43da377d-6252-4279-8d61-829a8524d822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071024262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2071024262
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3483119911
Short name T725
Test name
Test status
Simulation time 94209695 ps
CPU time 0.59 seconds
Started Mar 07 12:54:07 PM PST 24
Finished Mar 07 12:54:08 PM PST 24
Peak memory 193484 kb
Host smart-b3c52858-4162-41b0-bbfa-bd947c6b70d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483119911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3483119911
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2810751162
Short name T654
Test name
Test status
Simulation time 43576881 ps
CPU time 0.6 seconds
Started Mar 07 12:53:51 PM PST 24
Finished Mar 07 12:53:52 PM PST 24
Peak memory 193556 kb
Host smart-93410556-0768-4116-a553-ffa6ffc52c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810751162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2810751162
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1674939444
Short name T639
Test name
Test status
Simulation time 25445825 ps
CPU time 0.56 seconds
Started Mar 07 12:53:48 PM PST 24
Finished Mar 07 12:53:49 PM PST 24
Peak memory 193540 kb
Host smart-7d700044-b321-420d-9e4d-5f917fec4aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674939444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1674939444
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2227858877
Short name T668
Test name
Test status
Simulation time 48342555 ps
CPU time 0.56 seconds
Started Mar 07 12:53:57 PM PST 24
Finished Mar 07 12:53:58 PM PST 24
Peak memory 193536 kb
Host smart-fcd27685-bca2-480f-a410-2d0120b44ad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227858877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2227858877
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.218035677
Short name T730
Test name
Test status
Simulation time 35602076 ps
CPU time 0.59 seconds
Started Mar 07 12:53:46 PM PST 24
Finished Mar 07 12:53:47 PM PST 24
Peak memory 193476 kb
Host smart-ed939508-3403-4b11-a306-a2b0b1e631db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218035677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.218035677
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2309615690
Short name T637
Test name
Test status
Simulation time 51692970 ps
CPU time 0.61 seconds
Started Mar 07 12:54:16 PM PST 24
Finished Mar 07 12:54:17 PM PST 24
Peak memory 193512 kb
Host smart-41b7be62-2e7f-4b45-b1e0-617b250ac6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309615690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2309615690
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3555690867
Short name T117
Test name
Test status
Simulation time 409651389 ps
CPU time 5.4 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:08 PM PST 24
Peak memory 197816 kb
Host smart-4fac2335-4a29-4281-a246-059adc7716b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555690867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3555690867
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2389711927
Short name T114
Test name
Test status
Simulation time 863715367 ps
CPU time 9.35 seconds
Started Mar 07 12:53:50 PM PST 24
Finished Mar 07 12:54:00 PM PST 24
Peak memory 197392 kb
Host smart-ddf65dfb-13ce-464f-9a21-f77a1529815b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389711927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2389711927
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3616769227
Short name T102
Test name
Test status
Simulation time 85858468 ps
CPU time 1.03 seconds
Started Mar 07 12:53:45 PM PST 24
Finished Mar 07 12:53:46 PM PST 24
Peak memory 198920 kb
Host smart-70e43775-1a83-4f85-8daa-97206880f506
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616769227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3616769227
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4262055107
Short name T697
Test name
Test status
Simulation time 91290267 ps
CPU time 3.01 seconds
Started Mar 07 12:53:46 PM PST 24
Finished Mar 07 12:53:49 PM PST 24
Peak memory 199192 kb
Host smart-162edb50-b48d-48db-959a-262ad0ee6df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262055107 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4262055107
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4007104744
Short name T681
Test name
Test status
Simulation time 22779855 ps
CPU time 0.83 seconds
Started Mar 07 12:53:50 PM PST 24
Finished Mar 07 12:53:52 PM PST 24
Peak memory 197984 kb
Host smart-e5eb5a94-8a60-492e-a015-ccfd4d1fa1f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007104744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.4007104744
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.4204006951
Short name T687
Test name
Test status
Simulation time 13670484 ps
CPU time 0.62 seconds
Started Mar 07 12:53:45 PM PST 24
Finished Mar 07 12:53:45 PM PST 24
Peak memory 193640 kb
Host smart-982cb5c7-2eb8-41fd-92d1-9ad654ae123b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204006951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.4204006951
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3411180923
Short name T715
Test name
Test status
Simulation time 104304815 ps
CPU time 1.84 seconds
Started Mar 07 12:53:48 PM PST 24
Finished Mar 07 12:53:50 PM PST 24
Peak memory 199020 kb
Host smart-8e929f57-92b7-44b7-b88e-a1aa39499f31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411180923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3411180923
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2511153923
Short name T706
Test name
Test status
Simulation time 52829317 ps
CPU time 2.98 seconds
Started Mar 07 12:54:04 PM PST 24
Finished Mar 07 12:54:07 PM PST 24
Peak memory 199112 kb
Host smart-bb4c86b4-deb0-4acc-9772-6cc5eb46bf07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511153923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2511153923
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1466907698
Short name T680
Test name
Test status
Simulation time 819963620 ps
CPU time 2.93 seconds
Started Mar 07 12:53:47 PM PST 24
Finished Mar 07 12:53:50 PM PST 24
Peak memory 199060 kb
Host smart-84e2f9f1-f670-45ba-9244-d9e2f2d3a3bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466907698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1466907698
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.4152672058
Short name T641
Test name
Test status
Simulation time 43038452 ps
CPU time 0.57 seconds
Started Mar 07 12:54:10 PM PST 24
Finished Mar 07 12:54:10 PM PST 24
Peak memory 193536 kb
Host smart-90588385-17a7-4cd6-9903-e68650fde8e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152672058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4152672058
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1768826828
Short name T676
Test name
Test status
Simulation time 13508425 ps
CPU time 0.57 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:53:54 PM PST 24
Peak memory 193532 kb
Host smart-ff7009d1-bcf5-433f-870c-958034118bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768826828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1768826828
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2708652898
Short name T714
Test name
Test status
Simulation time 12987792 ps
CPU time 0.61 seconds
Started Mar 07 12:54:39 PM PST 24
Finished Mar 07 12:54:40 PM PST 24
Peak memory 193584 kb
Host smart-2d3830a5-e2c7-487c-9e08-90656999a781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708652898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2708652898
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3947909328
Short name T620
Test name
Test status
Simulation time 29621851 ps
CPU time 0.55 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:04 PM PST 24
Peak memory 193516 kb
Host smart-d23b45af-6c83-464b-bd69-476834cc792d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947909328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3947909328
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.906465175
Short name T80
Test name
Test status
Simulation time 61896788 ps
CPU time 0.6 seconds
Started Mar 07 12:53:56 PM PST 24
Finished Mar 07 12:53:57 PM PST 24
Peak memory 193588 kb
Host smart-23de1901-974d-4938-8348-94fa7701e19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906465175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.906465175
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3177523288
Short name T703
Test name
Test status
Simulation time 50178023 ps
CPU time 0.57 seconds
Started Mar 07 12:54:05 PM PST 24
Finished Mar 07 12:54:06 PM PST 24
Peak memory 193580 kb
Host smart-e0498f80-0749-4538-aa89-87266844b1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177523288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3177523288
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2113978971
Short name T731
Test name
Test status
Simulation time 20982503 ps
CPU time 0.58 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 193564 kb
Host smart-80c3dee4-03ed-4a1b-b0af-27ba37172dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113978971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2113978971
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.326036982
Short name T693
Test name
Test status
Simulation time 38195246 ps
CPU time 0.59 seconds
Started Mar 07 12:54:23 PM PST 24
Finished Mar 07 12:54:24 PM PST 24
Peak memory 193584 kb
Host smart-49a469e0-1751-41ec-9fd4-202bf41da9be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326036982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.326036982
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2017682199
Short name T688
Test name
Test status
Simulation time 17044583 ps
CPU time 0.64 seconds
Started Mar 07 12:54:12 PM PST 24
Finished Mar 07 12:54:13 PM PST 24
Peak memory 193644 kb
Host smart-a266c9d0-6bae-4e0d-8547-84f8cebf6422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017682199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2017682199
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3454046713
Short name T713
Test name
Test status
Simulation time 17739334 ps
CPU time 0.56 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:54:00 PM PST 24
Peak memory 193532 kb
Host smart-1fc44c8e-1874-40bf-ad86-b177fedd7567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454046713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3454046713
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2050501843
Short name T723
Test name
Test status
Simulation time 268292965 ps
CPU time 1.27 seconds
Started Mar 07 12:53:58 PM PST 24
Finished Mar 07 12:54:00 PM PST 24
Peak memory 199100 kb
Host smart-27e520c8-2afb-4a8c-9414-ed789e340b59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050501843 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2050501843
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1241740103
Short name T657
Test name
Test status
Simulation time 15483753 ps
CPU time 0.8 seconds
Started Mar 07 12:53:58 PM PST 24
Finished Mar 07 12:53:59 PM PST 24
Peak memory 197484 kb
Host smart-86f751c5-94cc-4993-9eec-2b791e1160dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241740103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1241740103
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3669695565
Short name T683
Test name
Test status
Simulation time 15261886 ps
CPU time 0.57 seconds
Started Mar 07 12:54:19 PM PST 24
Finished Mar 07 12:54:20 PM PST 24
Peak memory 193508 kb
Host smart-35537023-33ac-41d4-9bd4-9c7e4355ae64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669695565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3669695565
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3144669755
Short name T665
Test name
Test status
Simulation time 368175340 ps
CPU time 1.19 seconds
Started Mar 07 12:53:42 PM PST 24
Finished Mar 07 12:53:44 PM PST 24
Peak memory 196804 kb
Host smart-e6e0df92-aaac-4f2b-8af1-8b0147964fcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144669755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3144669755
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.694359041
Short name T652
Test name
Test status
Simulation time 360464786 ps
CPU time 3.63 seconds
Started Mar 07 12:53:47 PM PST 24
Finished Mar 07 12:53:51 PM PST 24
Peak memory 199076 kb
Host smart-693ee000-6f6b-47e3-aa02-c431f78f7641
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694359041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.694359041
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.774254284
Short name T119
Test name
Test status
Simulation time 1672563334 ps
CPU time 4.57 seconds
Started Mar 07 12:53:54 PM PST 24
Finished Mar 07 12:53:58 PM PST 24
Peak memory 198956 kb
Host smart-4b2a765f-0378-4e16-ad30-1d3903f465fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774254284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.774254284
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.235695273
Short name T717
Test name
Test status
Simulation time 21342343 ps
CPU time 1.22 seconds
Started Mar 07 12:54:05 PM PST 24
Finished Mar 07 12:54:06 PM PST 24
Peak memory 198996 kb
Host smart-0a271a40-6cf5-4287-a869-60c0406d1a66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235695273 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.235695273
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1547563200
Short name T638
Test name
Test status
Simulation time 18499313 ps
CPU time 0.72 seconds
Started Mar 07 12:53:41 PM PST 24
Finished Mar 07 12:53:42 PM PST 24
Peak memory 196556 kb
Host smart-44b9ca39-cdc9-4c51-b81c-2db111cc78f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547563200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1547563200
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3904056792
Short name T727
Test name
Test status
Simulation time 67406787 ps
CPU time 0.63 seconds
Started Mar 07 12:53:43 PM PST 24
Finished Mar 07 12:53:44 PM PST 24
Peak memory 193512 kb
Host smart-bcbe6aa7-e54c-49fc-8a6d-e146d383acd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904056792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3904056792
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3531230594
Short name T614
Test name
Test status
Simulation time 175942829 ps
CPU time 1.06 seconds
Started Mar 07 12:53:39 PM PST 24
Finished Mar 07 12:53:40 PM PST 24
Peak memory 197636 kb
Host smart-4a4cd0f7-4979-4392-9250-e418ca1d43a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531230594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3531230594
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3992368924
Short name T621
Test name
Test status
Simulation time 116576687 ps
CPU time 3.27 seconds
Started Mar 07 12:53:51 PM PST 24
Finished Mar 07 12:53:54 PM PST 24
Peak memory 199068 kb
Host smart-ed86e002-48c7-4af2-b005-da68a365cd0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992368924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3992368924
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3637305312
Short name T122
Test name
Test status
Simulation time 296601981 ps
CPU time 3.1 seconds
Started Mar 07 12:53:47 PM PST 24
Finished Mar 07 12:53:50 PM PST 24
Peak memory 198988 kb
Host smart-01a41a7e-e622-42a9-a827-38c32b2a6f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637305312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3637305312
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1553527216
Short name T63
Test name
Test status
Simulation time 65390884 ps
CPU time 3.74 seconds
Started Mar 07 12:53:57 PM PST 24
Finished Mar 07 12:54:01 PM PST 24
Peak memory 199068 kb
Host smart-3b3b8352-1f39-4f74-a851-2fde6abcffee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553527216 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1553527216
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2437040444
Short name T663
Test name
Test status
Simulation time 30337502 ps
CPU time 0.81 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:54:01 PM PST 24
Peak memory 197360 kb
Host smart-01761d88-5951-499e-aac8-6cce03bd4d4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437040444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2437040444
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1316814357
Short name T728
Test name
Test status
Simulation time 14361807 ps
CPU time 0.61 seconds
Started Mar 07 12:53:55 PM PST 24
Finished Mar 07 12:53:56 PM PST 24
Peak memory 193600 kb
Host smart-4cddec3e-2220-40c3-9752-7759cd4924a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316814357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1316814357
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.782372187
Short name T708
Test name
Test status
Simulation time 435779823 ps
CPU time 2.22 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:54:02 PM PST 24
Peak memory 198356 kb
Host smart-b5994d39-250e-47a4-9ad9-ad859d6f2b5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782372187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.782372187
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2215416889
Short name T649
Test name
Test status
Simulation time 51274475 ps
CPU time 1.52 seconds
Started Mar 07 12:53:46 PM PST 24
Finished Mar 07 12:53:48 PM PST 24
Peak memory 199120 kb
Host smart-a0907e21-99a0-4eee-bc5f-f2f9126d73e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215416889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2215416889
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3603176998
Short name T661
Test name
Test status
Simulation time 172724347 ps
CPU time 1.7 seconds
Started Mar 07 12:53:46 PM PST 24
Finished Mar 07 12:53:47 PM PST 24
Peak memory 199152 kb
Host smart-e0a00728-5ad0-4c0c-bbcc-70a84602e452
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603176998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3603176998
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2564283566
Short name T667
Test name
Test status
Simulation time 22431222 ps
CPU time 1.34 seconds
Started Mar 07 12:53:57 PM PST 24
Finished Mar 07 12:53:59 PM PST 24
Peak memory 199160 kb
Host smart-b9dc761b-0eb2-422f-9993-c8e6da2eeaf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564283566 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2564283566
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3885350299
Short name T112
Test name
Test status
Simulation time 19375620 ps
CPU time 0.88 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:53:54 PM PST 24
Peak memory 198940 kb
Host smart-efe94fb3-ab2d-488c-b201-095b41a579b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885350299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3885350299
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3547907454
Short name T609
Test name
Test status
Simulation time 56607348 ps
CPU time 0.58 seconds
Started Mar 07 12:53:49 PM PST 24
Finished Mar 07 12:53:50 PM PST 24
Peak memory 193592 kb
Host smart-d38f08d6-083b-404e-a975-a262a45eb3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547907454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3547907454
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.956170035
Short name T632
Test name
Test status
Simulation time 533746283 ps
CPU time 2.26 seconds
Started Mar 07 12:53:58 PM PST 24
Finished Mar 07 12:54:01 PM PST 24
Peak memory 198480 kb
Host smart-b320d66f-5186-4d88-b77c-1a5c00f80b91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956170035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.956170035
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2743754938
Short name T623
Test name
Test status
Simulation time 74660569 ps
CPU time 1.67 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:53:55 PM PST 24
Peak memory 199036 kb
Host smart-2b44ac4f-68c6-41c7-9bff-a2ffef036cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743754938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2743754938
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1747201496
Short name T660
Test name
Test status
Simulation time 118064801 ps
CPU time 1.92 seconds
Started Mar 07 12:53:59 PM PST 24
Finished Mar 07 12:54:01 PM PST 24
Peak memory 199032 kb
Host smart-a6068078-ea0d-44db-9d63-e7b04747783c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747201496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1747201496
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3322060180
Short name T699
Test name
Test status
Simulation time 46283039062 ps
CPU time 185.59 seconds
Started Mar 07 12:53:53 PM PST 24
Finished Mar 07 12:56:59 PM PST 24
Peak memory 199568 kb
Host smart-e87b9916-c2c1-46d0-ae9b-5d20d6cf3f88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322060180 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3322060180
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1686264848
Short name T636
Test name
Test status
Simulation time 17637173 ps
CPU time 0.8 seconds
Started Mar 07 12:53:49 PM PST 24
Finished Mar 07 12:53:51 PM PST 24
Peak memory 197736 kb
Host smart-a29dd374-3297-4608-8baf-03e7bd4b14f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686264848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1686264848
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2454419584
Short name T655
Test name
Test status
Simulation time 17312342 ps
CPU time 0.63 seconds
Started Mar 07 12:54:01 PM PST 24
Finished Mar 07 12:54:03 PM PST 24
Peak memory 193656 kb
Host smart-fabf8c73-f66d-4bc5-8fb3-6aeec6093a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454419584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2454419584
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.507833081
Short name T666
Test name
Test status
Simulation time 51716698 ps
CPU time 1.05 seconds
Started Mar 07 12:54:04 PM PST 24
Finished Mar 07 12:54:06 PM PST 24
Peak memory 197672 kb
Host smart-3318ac7e-7b1f-41ad-afe9-c53849e717cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507833081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.507833081
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3045688824
Short name T612
Test name
Test status
Simulation time 302102316 ps
CPU time 1.94 seconds
Started Mar 07 12:53:45 PM PST 24
Finished Mar 07 12:53:47 PM PST 24
Peak memory 199216 kb
Host smart-dd5de390-61e2-4b9c-bb4d-0893b86b19b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045688824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3045688824
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1336335667
Short name T735
Test name
Test status
Simulation time 676782983 ps
CPU time 3.77 seconds
Started Mar 07 12:54:02 PM PST 24
Finished Mar 07 12:54:06 PM PST 24
Peak memory 199060 kb
Host smart-a62a9dc1-c1e0-4db5-a964-a9238eb41ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336335667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1336335667
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3145320752
Short name T541
Test name
Test status
Simulation time 121892459 ps
CPU time 0.53 seconds
Started Mar 07 01:02:16 PM PST 24
Finished Mar 07 01:02:17 PM PST 24
Peak memory 195300 kb
Host smart-2a290497-fcb9-4b4d-9c69-4011319fbe2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145320752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3145320752
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2070305229
Short name T406
Test name
Test status
Simulation time 1281751079 ps
CPU time 44.25 seconds
Started Mar 07 01:02:13 PM PST 24
Finished Mar 07 01:02:57 PM PST 24
Peak memory 215916 kb
Host smart-83ca31e0-2fcb-4087-9e6d-23123d081857
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070305229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2070305229
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1258279164
Short name T599
Test name
Test status
Simulation time 3062453901 ps
CPU time 73.49 seconds
Started Mar 07 01:02:17 PM PST 24
Finished Mar 07 01:03:31 PM PST 24
Peak memory 199932 kb
Host smart-9141c948-fc27-488b-a459-beef1570b418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258279164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1258279164
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1734456268
Short name T398
Test name
Test status
Simulation time 1326646937 ps
CPU time 17.53 seconds
Started Mar 07 01:02:10 PM PST 24
Finished Mar 07 01:02:28 PM PST 24
Peak memory 199828 kb
Host smart-8096c0a2-628c-4db6-85b4-90e587b908da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734456268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1734456268
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2037816133
Short name T279
Test name
Test status
Simulation time 11531677484 ps
CPU time 144.64 seconds
Started Mar 07 01:02:21 PM PST 24
Finished Mar 07 01:04:45 PM PST 24
Peak memory 200028 kb
Host smart-6a27d65f-4149-44d6-b71a-d7eeea923394
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037816133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2037816133
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1802881445
Short name T221
Test name
Test status
Simulation time 700309717 ps
CPU time 5.92 seconds
Started Mar 07 01:02:12 PM PST 24
Finished Mar 07 01:02:18 PM PST 24
Peak memory 199860 kb
Host smart-2244aed5-7f4d-40a3-8772-0cacfee8f1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802881445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1802881445
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.461272105
Short name T483
Test name
Test status
Simulation time 27018294 ps
CPU time 1.09 seconds
Started Mar 07 01:02:10 PM PST 24
Finished Mar 07 01:02:12 PM PST 24
Peak memory 199844 kb
Host smart-787645c4-66d0-41ec-9890-2ad41058c34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461272105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.461272105
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1776828387
Short name T30
Test name
Test status
Simulation time 166366468165 ps
CPU time 2185.86 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:38:37 PM PST 24
Peak memory 200016 kb
Host smart-ad1a520f-a7fd-4465-83a8-e95386243bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776828387 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1776828387
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.636498051
Short name T204
Test name
Test status
Simulation time 62869640 ps
CPU time 1.16 seconds
Started Mar 07 01:02:06 PM PST 24
Finished Mar 07 01:02:08 PM PST 24
Peak memory 199352 kb
Host smart-7c71b7cb-ac5c-4a50-b92a-50023fca5b17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636498051 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.636498051
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1477869141
Short name T69
Test name
Test status
Simulation time 38523959449 ps
CPU time 447.24 seconds
Started Mar 07 01:02:16 PM PST 24
Finished Mar 07 01:09:43 PM PST 24
Peak memory 200004 kb
Host smart-d6c9dd9b-2def-4ad3-b130-85f6da08f762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477869141 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.1477869141
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2082759209
Short name T511
Test name
Test status
Simulation time 6155158163 ps
CPU time 70.5 seconds
Started Mar 07 01:02:15 PM PST 24
Finished Mar 07 01:03:25 PM PST 24
Peak memory 199988 kb
Host smart-dcb7edf2-fba2-4df0-bb72-bc4bfdefefa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082759209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2082759209
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2792427864
Short name T55
Test name
Test status
Simulation time 1828353642 ps
CPU time 69.12 seconds
Started Mar 07 01:02:08 PM PST 24
Finished Mar 07 01:03:18 PM PST 24
Peak memory 228844 kb
Host smart-2ca1820c-8c32-4618-b6bc-35b960605575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792427864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2792427864
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1958978004
Short name T148
Test name
Test status
Simulation time 923167265 ps
CPU time 11.37 seconds
Started Mar 07 01:02:24 PM PST 24
Finished Mar 07 01:02:36 PM PST 24
Peak memory 199688 kb
Host smart-a96f0d3e-33b8-42e4-be2b-84cc1a932b64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958978004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1958978004
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.350278641
Short name T473
Test name
Test status
Simulation time 4976627243 ps
CPU time 102.76 seconds
Started Mar 07 01:02:09 PM PST 24
Finished Mar 07 01:03:51 PM PST 24
Peak memory 199964 kb
Host smart-8cced91c-e9fe-4cbe-a302-ef8dfa935aa7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350278641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.350278641
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.214854955
Short name T248
Test name
Test status
Simulation time 507755893 ps
CPU time 29.9 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:02:41 PM PST 24
Peak memory 199912 kb
Host smart-b8beec3e-9729-4754-9a07-02c0b3052710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214854955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.214854955
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1246278093
Short name T34
Test name
Test status
Simulation time 114757846 ps
CPU time 0.88 seconds
Started Mar 07 01:02:12 PM PST 24
Finished Mar 07 01:02:13 PM PST 24
Peak memory 218416 kb
Host smart-70a4d089-48aa-4412-b389-9ee60bc59123
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246278093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1246278093
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.116624016
Short name T250
Test name
Test status
Simulation time 721447380 ps
CPU time 2.5 seconds
Started Mar 07 01:02:16 PM PST 24
Finished Mar 07 01:02:19 PM PST 24
Peak memory 199872 kb
Host smart-6c583830-3a12-435f-902b-8da5644d189f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116624016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.116624016
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3348026823
Short name T459
Test name
Test status
Simulation time 188901508 ps
CPU time 0.94 seconds
Started Mar 07 01:02:08 PM PST 24
Finished Mar 07 01:02:09 PM PST 24
Peak memory 198048 kb
Host smart-3554ca37-2ba2-4b35-9c5b-8706e483484c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348026823 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.3348026823
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2476532854
Short name T444
Test name
Test status
Simulation time 8522848688 ps
CPU time 486.52 seconds
Started Mar 07 01:02:14 PM PST 24
Finished Mar 07 01:10:21 PM PST 24
Peak memory 199996 kb
Host smart-7df7d4ee-4408-4f5e-b844-e3ac5ec85afa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476532854 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2476532854
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3488123336
Short name T362
Test name
Test status
Simulation time 719641760 ps
CPU time 13.17 seconds
Started Mar 07 01:02:16 PM PST 24
Finished Mar 07 01:02:30 PM PST 24
Peak memory 199892 kb
Host smart-fc667aae-e5be-4d5b-b698-90cd8eaa0fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488123336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3488123336
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3603181254
Short name T602
Test name
Test status
Simulation time 13181660 ps
CPU time 0.6 seconds
Started Mar 07 01:02:52 PM PST 24
Finished Mar 07 01:02:53 PM PST 24
Peak memory 195268 kb
Host smart-b0353a42-211e-426e-9b53-2848063856fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603181254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3603181254
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.908955462
Short name T446
Test name
Test status
Simulation time 217336817 ps
CPU time 7.33 seconds
Started Mar 07 01:02:53 PM PST 24
Finished Mar 07 01:03:00 PM PST 24
Peak memory 199880 kb
Host smart-ccb1137c-b6dd-4886-9756-e1ae7c5768b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908955462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.908955462
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4279819290
Short name T500
Test name
Test status
Simulation time 1142553903 ps
CPU time 54.31 seconds
Started Mar 07 01:02:53 PM PST 24
Finished Mar 07 01:03:47 PM PST 24
Peak memory 199864 kb
Host smart-d09e801b-fda8-430d-a442-30715fa5116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279819290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4279819290
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.617139497
Short name T529
Test name
Test status
Simulation time 2865464228 ps
CPU time 172.96 seconds
Started Mar 07 01:02:56 PM PST 24
Finished Mar 07 01:05:49 PM PST 24
Peak memory 199904 kb
Host smart-7585ab2c-ee70-4ea8-a821-c1abccf733dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617139497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.617139497
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3159714567
Short name T384
Test name
Test status
Simulation time 27539919444 ps
CPU time 181.87 seconds
Started Mar 07 01:02:52 PM PST 24
Finished Mar 07 01:05:54 PM PST 24
Peak memory 199976 kb
Host smart-6cb9d89c-e86f-4cbe-86df-2ecd18172194
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159714567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3159714567
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.392722420
Short name T247
Test name
Test status
Simulation time 7774926768 ps
CPU time 101.41 seconds
Started Mar 07 01:02:55 PM PST 24
Finished Mar 07 01:04:36 PM PST 24
Peak memory 199824 kb
Host smart-2c216b30-e7b4-4246-827d-25c7eb4250ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392722420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.392722420
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2148778856
Short name T132
Test name
Test status
Simulation time 485353575 ps
CPU time 5.61 seconds
Started Mar 07 01:02:52 PM PST 24
Finished Mar 07 01:02:59 PM PST 24
Peak memory 199880 kb
Host smart-8e61f1a3-4d41-46e5-bf43-09532895f1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148778856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2148778856
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.610057182
Short name T151
Test name
Test status
Simulation time 2009556659 ps
CPU time 104.28 seconds
Started Mar 07 01:02:53 PM PST 24
Finished Mar 07 01:04:37 PM PST 24
Peak memory 199900 kb
Host smart-4b0075f5-a333-4ff4-a26c-dc16fc928482
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610057182 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.610057182
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2502361234
Short name T597
Test name
Test status
Simulation time 507110876 ps
CPU time 1.14 seconds
Started Mar 07 01:02:54 PM PST 24
Finished Mar 07 01:02:55 PM PST 24
Peak memory 199892 kb
Host smart-c91a7251-2adc-411f-a243-08f61331b171
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502361234 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2502361234
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.2040719719
Short name T415
Test name
Test status
Simulation time 8517602873 ps
CPU time 445.26 seconds
Started Mar 07 01:02:55 PM PST 24
Finished Mar 07 01:10:20 PM PST 24
Peak memory 200008 kb
Host smart-7ae0e0be-5f63-4c92-88e5-4ff42cd3b451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040719719 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.2040719719
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2199700422
Short name T134
Test name
Test status
Simulation time 5806451599 ps
CPU time 38.95 seconds
Started Mar 07 01:02:52 PM PST 24
Finished Mar 07 01:03:31 PM PST 24
Peak memory 199976 kb
Host smart-08625a0d-8374-458e-b984-55530ecd65d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199700422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2199700422
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.1937013391
Short name T592
Test name
Test status
Simulation time 102781854395 ps
CPU time 495.27 seconds
Started Mar 07 01:05:49 PM PST 24
Finished Mar 07 01:14:05 PM PST 24
Peak memory 210720 kb
Host smart-bf5a324a-7db0-48c9-859d-195c0933f35d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937013391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.1937013391
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.799049296
Short name T375
Test name
Test status
Simulation time 45256642 ps
CPU time 0.57 seconds
Started Mar 07 01:02:54 PM PST 24
Finished Mar 07 01:02:55 PM PST 24
Peak memory 195348 kb
Host smart-9cfef6f6-b5b1-4ba5-8048-f8a7106c74de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799049296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.799049296
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1489951422
Short name T512
Test name
Test status
Simulation time 739541984 ps
CPU time 31.39 seconds
Started Mar 07 01:02:54 PM PST 24
Finished Mar 07 01:03:25 PM PST 24
Peak memory 223328 kb
Host smart-5a6ecfcd-ebfb-40a0-a7cc-44edf1312bc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489951422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1489951422
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3217876936
Short name T294
Test name
Test status
Simulation time 328597481 ps
CPU time 4.21 seconds
Started Mar 07 01:02:53 PM PST 24
Finished Mar 07 01:02:58 PM PST 24
Peak memory 199988 kb
Host smart-a5e4f826-a5ba-4e2d-a750-1b95d0d12418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217876936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3217876936
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3022257999
Short name T424
Test name
Test status
Simulation time 6031859726 ps
CPU time 67.49 seconds
Started Mar 07 01:02:54 PM PST 24
Finished Mar 07 01:04:01 PM PST 24
Peak memory 199964 kb
Host smart-f67d59f1-4bb4-4e0b-b497-4f998ccdd992
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022257999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3022257999
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2536942308
Short name T344
Test name
Test status
Simulation time 5670050987 ps
CPU time 100.96 seconds
Started Mar 07 01:02:54 PM PST 24
Finished Mar 07 01:04:35 PM PST 24
Peak memory 199992 kb
Host smart-9dc4c9c9-80f7-40a3-86a3-503211b70ded
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536942308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2536942308
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.524087901
Short name T450
Test name
Test status
Simulation time 1021430334 ps
CPU time 58.9 seconds
Started Mar 07 01:02:53 PM PST 24
Finished Mar 07 01:03:52 PM PST 24
Peak memory 199868 kb
Host smart-dbb0586c-4af7-422e-a546-ddb47c71a334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524087901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.524087901
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2704248561
Short name T591
Test name
Test status
Simulation time 1541148095 ps
CPU time 6.06 seconds
Started Mar 07 01:02:53 PM PST 24
Finished Mar 07 01:03:00 PM PST 24
Peak memory 199892 kb
Host smart-1e26d903-45fc-4d77-953b-203a03f52bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704248561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2704248561
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2799993360
Short name T188
Test name
Test status
Simulation time 399266129279 ps
CPU time 1786.49 seconds
Started Mar 07 01:02:56 PM PST 24
Finished Mar 07 01:32:43 PM PST 24
Peak memory 228644 kb
Host smart-378cc64e-8ccd-4f1a-896a-5dc3b6a9f2a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799993360 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2799993360
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.919193360
Short name T7
Test name
Test status
Simulation time 45637438463 ps
CPU time 889.98 seconds
Started Mar 07 01:02:52 PM PST 24
Finished Mar 07 01:17:42 PM PST 24
Peak memory 208212 kb
Host smart-24733f29-b530-46dd-9438-2b308688259d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919193360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.919193360
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1600410851
Short name T439
Test name
Test status
Simulation time 213255271 ps
CPU time 0.9 seconds
Started Mar 07 01:02:53 PM PST 24
Finished Mar 07 01:02:54 PM PST 24
Peak memory 198116 kb
Host smart-01cc9af5-a89c-4d86-9f03-87edd64b15fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600410851 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1600410851
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2343012931
Short name T356
Test name
Test status
Simulation time 15506197642 ps
CPU time 445.01 seconds
Started Mar 07 01:02:54 PM PST 24
Finished Mar 07 01:10:19 PM PST 24
Peak memory 199844 kb
Host smart-129554f0-be02-49b7-bca3-80220c905346
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343012931 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.2343012931
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3118993335
Short name T513
Test name
Test status
Simulation time 3219960292 ps
CPU time 27.1 seconds
Started Mar 07 01:02:53 PM PST 24
Finished Mar 07 01:03:20 PM PST 24
Peak memory 199888 kb
Host smart-0dec62e2-27f9-4516-8a48-0c48137be3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118993335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3118993335
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.978181851
Short name T101
Test name
Test status
Simulation time 106449886 ps
CPU time 0.59 seconds
Started Mar 07 01:03:17 PM PST 24
Finished Mar 07 01:03:18 PM PST 24
Peak memory 195280 kb
Host smart-9484184a-5a48-41cc-b971-71be2bb78d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978181851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.978181851
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1459811584
Short name T469
Test name
Test status
Simulation time 82472709 ps
CPU time 3.1 seconds
Started Mar 07 01:03:19 PM PST 24
Finished Mar 07 01:03:22 PM PST 24
Peak memory 199888 kb
Host smart-a45c4495-d169-40fd-acab-6729453ec69c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459811584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1459811584
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3678355901
Short name T198
Test name
Test status
Simulation time 3922946924 ps
CPU time 38.49 seconds
Started Mar 07 01:03:19 PM PST 24
Finished Mar 07 01:03:58 PM PST 24
Peak memory 199928 kb
Host smart-41580f3e-51fa-43ec-9ba5-11f07d26e9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678355901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3678355901
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.624188808
Short name T400
Test name
Test status
Simulation time 5207560774 ps
CPU time 64.99 seconds
Started Mar 07 01:03:20 PM PST 24
Finished Mar 07 01:04:25 PM PST 24
Peak memory 199956 kb
Host smart-e4863894-bd76-4336-a71c-a6a5a606dddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=624188808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.624188808
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2729662236
Short name T430
Test name
Test status
Simulation time 7367803591 ps
CPU time 92.23 seconds
Started Mar 07 01:03:26 PM PST 24
Finished Mar 07 01:04:59 PM PST 24
Peak memory 199988 kb
Host smart-202cc86f-0593-41bc-a6ff-b4b32e52aaa2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729662236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2729662236
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1750754777
Short name T295
Test name
Test status
Simulation time 4990887630 ps
CPU time 43.33 seconds
Started Mar 07 01:03:22 PM PST 24
Finished Mar 07 01:04:06 PM PST 24
Peak memory 199996 kb
Host smart-3b241919-1b6a-4155-899b-695ab9b9c34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750754777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1750754777
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.36117145
Short name T318
Test name
Test status
Simulation time 219820800 ps
CPU time 6.48 seconds
Started Mar 07 01:02:53 PM PST 24
Finished Mar 07 01:03:00 PM PST 24
Peak memory 199780 kb
Host smart-78919f6f-31db-4634-9a55-34be17fe6a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36117145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.36117145
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2283594221
Short name T154
Test name
Test status
Simulation time 17796741953 ps
CPU time 508.98 seconds
Started Mar 07 01:03:19 PM PST 24
Finished Mar 07 01:11:48 PM PST 24
Peak memory 200024 kb
Host smart-71ff054f-1395-4f0d-99e8-dbc0221af189
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283594221 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2283594221
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.851235442
Short name T457
Test name
Test status
Simulation time 143749262 ps
CPU time 1.24 seconds
Started Mar 07 01:03:20 PM PST 24
Finished Mar 07 01:03:22 PM PST 24
Peak memory 199312 kb
Host smart-4ab85eb2-7e45-4287-8062-883924507cc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851235442 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.851235442
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1653186914
Short name T498
Test name
Test status
Simulation time 34211458301 ps
CPU time 471.99 seconds
Started Mar 07 01:03:18 PM PST 24
Finished Mar 07 01:11:10 PM PST 24
Peak memory 200004 kb
Host smart-13393c22-6625-4386-8c76-65784c5d36c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653186914 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.1653186914
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2400937686
Short name T549
Test name
Test status
Simulation time 168299683 ps
CPU time 3.74 seconds
Started Mar 07 01:03:18 PM PST 24
Finished Mar 07 01:03:21 PM PST 24
Peak memory 199864 kb
Host smart-09989b2b-7d27-40fc-9e56-6f1c0592c333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400937686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2400937686
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.3645859088
Short name T11
Test name
Test status
Simulation time 20181935516 ps
CPU time 949.25 seconds
Started Mar 07 01:05:52 PM PST 24
Finished Mar 07 01:21:42 PM PST 24
Peak memory 245156 kb
Host smart-2f27096a-5a09-40e2-ad84-4af34cf314eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645859088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.3645859088
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.146135507
Short name T244
Test name
Test status
Simulation time 26471718 ps
CPU time 0.57 seconds
Started Mar 07 01:03:22 PM PST 24
Finished Mar 07 01:03:23 PM PST 24
Peak memory 194320 kb
Host smart-d9824f44-3f2d-4dc9-93b0-99fb9b123a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146135507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.146135507
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2898384226
Short name T300
Test name
Test status
Simulation time 679533427 ps
CPU time 23.81 seconds
Started Mar 07 01:03:21 PM PST 24
Finished Mar 07 01:03:45 PM PST 24
Peak memory 225692 kb
Host smart-21a992c8-1e27-4519-87f0-84cea042bee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2898384226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2898384226
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2005471306
Short name T240
Test name
Test status
Simulation time 4629428903 ps
CPU time 64.88 seconds
Started Mar 07 01:03:21 PM PST 24
Finished Mar 07 01:04:26 PM PST 24
Peak memory 200024 kb
Host smart-6e2d1ca4-b419-4d23-ae96-b38fc7701a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005471306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2005471306
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2405846045
Short name T299
Test name
Test status
Simulation time 9048545692 ps
CPU time 147.71 seconds
Started Mar 07 01:03:24 PM PST 24
Finished Mar 07 01:05:52 PM PST 24
Peak memory 199972 kb
Host smart-465a06c9-e3d3-4695-86fd-c38b925c5824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405846045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2405846045
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1393930474
Short name T587
Test name
Test status
Simulation time 1245130464 ps
CPU time 67.25 seconds
Started Mar 07 01:03:17 PM PST 24
Finished Mar 07 01:04:25 PM PST 24
Peak memory 199900 kb
Host smart-20eaa163-fb4a-4c70-a926-4d6afce197b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393930474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1393930474
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2398905808
Short name T470
Test name
Test status
Simulation time 988970107 ps
CPU time 20.88 seconds
Started Mar 07 01:03:26 PM PST 24
Finished Mar 07 01:03:47 PM PST 24
Peak memory 199920 kb
Host smart-93f96b18-62c5-4ce0-8a49-2f751f96434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398905808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2398905808
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.4059884734
Short name T429
Test name
Test status
Simulation time 203961969 ps
CPU time 2.79 seconds
Started Mar 07 01:03:21 PM PST 24
Finished Mar 07 01:03:24 PM PST 24
Peak memory 199960 kb
Host smart-63e4485d-2ea2-41e2-99b2-3e92b5e15ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059884734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.4059884734
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3898416078
Short name T305
Test name
Test status
Simulation time 73147356691 ps
CPU time 346.77 seconds
Started Mar 07 01:03:21 PM PST 24
Finished Mar 07 01:09:08 PM PST 24
Peak memory 216384 kb
Host smart-dcde03e3-09f9-4aab-a3e6-07030b0e4ac0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898416078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3898416078
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3043628820
Short name T205
Test name
Test status
Simulation time 40560404 ps
CPU time 1.02 seconds
Started Mar 07 01:03:24 PM PST 24
Finished Mar 07 01:03:25 PM PST 24
Peak memory 197500 kb
Host smart-1b4b253b-bf88-44bc-b86e-dde7ee14acdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043628820 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3043628820
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1679489734
Short name T348
Test name
Test status
Simulation time 15138717751 ps
CPU time 421.38 seconds
Started Mar 07 01:03:22 PM PST 24
Finished Mar 07 01:10:23 PM PST 24
Peak memory 199948 kb
Host smart-e4b5e318-3081-4060-8590-f37c9c73275c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679489734 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.1679489734
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.529581578
Short name T453
Test name
Test status
Simulation time 3410132553 ps
CPU time 64.58 seconds
Started Mar 07 01:03:22 PM PST 24
Finished Mar 07 01:04:27 PM PST 24
Peak memory 199916 kb
Host smart-ff6560ae-450e-4083-a218-105127b6a133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529581578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.529581578
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.626519666
Short name T67
Test name
Test status
Simulation time 63765443953 ps
CPU time 3336.69 seconds
Started Mar 07 01:05:54 PM PST 24
Finished Mar 07 02:01:31 PM PST 24
Peak memory 249260 kb
Host smart-eaee1cb8-f4c9-4624-bbd4-789548165f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626519666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.626519666
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1780166258
Short name T397
Test name
Test status
Simulation time 41458548 ps
CPU time 0.57 seconds
Started Mar 07 01:03:17 PM PST 24
Finished Mar 07 01:03:17 PM PST 24
Peak memory 194292 kb
Host smart-7e0dba30-5d39-4fc2-b5d9-404f95b5cbad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780166258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1780166258
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1182900676
Short name T56
Test name
Test status
Simulation time 30761305625 ps
CPU time 58.76 seconds
Started Mar 07 01:03:22 PM PST 24
Finished Mar 07 01:04:21 PM PST 24
Peak memory 224912 kb
Host smart-b462b7b7-849f-4321-96ca-c5e71e8fc7d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182900676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1182900676
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.208293241
Short name T411
Test name
Test status
Simulation time 10059839099 ps
CPU time 23.19 seconds
Started Mar 07 01:03:18 PM PST 24
Finished Mar 07 01:03:41 PM PST 24
Peak memory 199992 kb
Host smart-aa320f45-2cda-45cd-960f-e822ffc06aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208293241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.208293241
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.348752868
Short name T604
Test name
Test status
Simulation time 3685640222 ps
CPU time 29.33 seconds
Started Mar 07 01:03:17 PM PST 24
Finished Mar 07 01:03:46 PM PST 24
Peak memory 199904 kb
Host smart-3615518e-191f-4e25-9d96-5a01c9b71b18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=348752868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.348752868
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.4005108347
Short name T243
Test name
Test status
Simulation time 47508573411 ps
CPU time 89.31 seconds
Started Mar 07 01:03:17 PM PST 24
Finished Mar 07 01:04:46 PM PST 24
Peak memory 200028 kb
Host smart-8b44e859-603b-4379-a341-d88b30937b49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005108347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.4005108347
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.744295443
Short name T572
Test name
Test status
Simulation time 18072868278 ps
CPU time 89.02 seconds
Started Mar 07 01:03:24 PM PST 24
Finished Mar 07 01:04:53 PM PST 24
Peak memory 199548 kb
Host smart-6cc8db41-33b7-46ef-aeb3-57bbbd124934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744295443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.744295443
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1649330046
Short name T302
Test name
Test status
Simulation time 670327719 ps
CPU time 2.35 seconds
Started Mar 07 01:03:21 PM PST 24
Finished Mar 07 01:03:24 PM PST 24
Peak memory 199876 kb
Host smart-67e3f861-e89b-4b61-9140-c88289418c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649330046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1649330046
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.394799400
Short name T353
Test name
Test status
Simulation time 130224767463 ps
CPU time 458.26 seconds
Started Mar 07 01:03:22 PM PST 24
Finished Mar 07 01:11:01 PM PST 24
Peak memory 248496 kb
Host smart-7dca65bf-714e-4fd5-83b6-2feea7a3ecb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394799400 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.394799400
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2684925899
Short name T199
Test name
Test status
Simulation time 27032089 ps
CPU time 0.9 seconds
Started Mar 07 01:03:21 PM PST 24
Finished Mar 07 01:03:22 PM PST 24
Peak memory 197552 kb
Host smart-499f8e95-e5b5-41f4-beb1-273889eac71d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684925899 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2684925899
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1264027222
Short name T157
Test name
Test status
Simulation time 286623535616 ps
CPU time 516.84 seconds
Started Mar 07 01:03:17 PM PST 24
Finished Mar 07 01:11:54 PM PST 24
Peak memory 200008 kb
Host smart-63b53569-bff5-4052-bc2c-0230353c5adc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264027222 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1264027222
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2180103570
Short name T392
Test name
Test status
Simulation time 21135795654 ps
CPU time 67.58 seconds
Started Mar 07 01:03:28 PM PST 24
Finished Mar 07 01:04:35 PM PST 24
Peak memory 199992 kb
Host smart-86fd8e64-9286-4b2f-b3ca-8890c0e5fde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180103570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2180103570
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.454530096
Short name T5
Test name
Test status
Simulation time 107271963347 ps
CPU time 252.63 seconds
Started Mar 07 01:06:07 PM PST 24
Finished Mar 07 01:10:19 PM PST 24
Peak memory 215572 kb
Host smart-f32c16b0-f053-4b35-8dec-e724133219f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454530096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.454530096
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2069584054
Short name T382
Test name
Test status
Simulation time 23075841 ps
CPU time 0.56 seconds
Started Mar 07 01:03:30 PM PST 24
Finished Mar 07 01:03:31 PM PST 24
Peak memory 195352 kb
Host smart-a3771a2c-6933-4f91-87ab-2265573ca5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069584054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2069584054
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.288620475
Short name T53
Test name
Test status
Simulation time 1390477810 ps
CPU time 63.5 seconds
Started Mar 07 01:03:21 PM PST 24
Finished Mar 07 01:04:24 PM PST 24
Peak memory 232612 kb
Host smart-88790d46-ce2f-42e1-ac4f-121fef95d3f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288620475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.288620475
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.203627181
Short name T213
Test name
Test status
Simulation time 2725213298 ps
CPU time 40.49 seconds
Started Mar 07 01:03:17 PM PST 24
Finished Mar 07 01:03:58 PM PST 24
Peak memory 199856 kb
Host smart-5405e06a-7409-4890-a736-a387cd24e915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203627181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.203627181
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2251183646
Short name T464
Test name
Test status
Simulation time 1734136656 ps
CPU time 99.44 seconds
Started Mar 07 01:03:01 PM PST 24
Finished Mar 07 01:04:42 PM PST 24
Peak memory 199904 kb
Host smart-38cbb59c-07eb-4b04-9b87-73ff6957c5e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251183646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2251183646
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.270022716
Short name T159
Test name
Test status
Simulation time 1863104281 ps
CPU time 103.22 seconds
Started Mar 07 01:03:29 PM PST 24
Finished Mar 07 01:05:12 PM PST 24
Peak memory 199780 kb
Host smart-549d6d62-26db-4c4c-8b85-4bbdaaf22e75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270022716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.270022716
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1218042678
Short name T3
Test name
Test status
Simulation time 6359502538 ps
CPU time 120 seconds
Started Mar 07 01:03:21 PM PST 24
Finished Mar 07 01:05:22 PM PST 24
Peak memory 199860 kb
Host smart-d2cf4326-b40a-4cc9-80f6-b5758aa11536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218042678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1218042678
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1061537614
Short name T442
Test name
Test status
Simulation time 189878401 ps
CPU time 5.41 seconds
Started Mar 07 01:03:22 PM PST 24
Finished Mar 07 01:03:27 PM PST 24
Peak memory 199884 kb
Host smart-dd51bfc5-df7c-49b0-92c2-a35430f3ba31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061537614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1061537614
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3068390447
Short name T293
Test name
Test status
Simulation time 2150889690 ps
CPU time 40.17 seconds
Started Mar 07 01:03:22 PM PST 24
Finished Mar 07 01:04:03 PM PST 24
Peak memory 199992 kb
Host smart-45135a6b-b0d7-46f6-8699-df78d6b4b86b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068390447 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3068390447
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.418016432
Short name T543
Test name
Test status
Simulation time 764995082 ps
CPU time 1.25 seconds
Started Mar 07 01:03:17 PM PST 24
Finished Mar 07 01:03:18 PM PST 24
Peak memory 199628 kb
Host smart-db89aa68-5013-4450-9297-f974d4338394
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418016432 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.418016432
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2449887487
Short name T229
Test name
Test status
Simulation time 105182347882 ps
CPU time 445.9 seconds
Started Mar 07 01:03:26 PM PST 24
Finished Mar 07 01:10:52 PM PST 24
Peak memory 200024 kb
Host smart-9f03199e-b1b0-42d8-a827-daea3233b226
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449887487 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.2449887487
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3770229500
Short name T27
Test name
Test status
Simulation time 17341334590 ps
CPU time 78.08 seconds
Started Mar 07 01:03:26 PM PST 24
Finished Mar 07 01:04:44 PM PST 24
Peak memory 200088 kb
Host smart-ea9bf0c9-5408-4432-b15d-6691c71739f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770229500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3770229500
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2670894766
Short name T325
Test name
Test status
Simulation time 18921978 ps
CPU time 0.58 seconds
Started Mar 07 01:03:35 PM PST 24
Finished Mar 07 01:03:37 PM PST 24
Peak memory 194296 kb
Host smart-f61b0c52-dbc8-413a-8e39-5b8d28bd272b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670894766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2670894766
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3541434630
Short name T98
Test name
Test status
Simulation time 6244119353 ps
CPU time 62.07 seconds
Started Mar 07 01:03:31 PM PST 24
Finished Mar 07 01:04:33 PM PST 24
Peak memory 247052 kb
Host smart-e3d52797-86b2-4e46-b485-f5808e4470d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3541434630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3541434630
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2029127015
Short name T524
Test name
Test status
Simulation time 794669609 ps
CPU time 12.62 seconds
Started Mar 07 01:03:37 PM PST 24
Finished Mar 07 01:03:50 PM PST 24
Peak memory 199824 kb
Host smart-27cc97a7-974e-4f48-a066-9ad709f1c92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029127015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2029127015
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1619587224
Short name T245
Test name
Test status
Simulation time 3758174955 ps
CPU time 106.45 seconds
Started Mar 07 01:03:32 PM PST 24
Finished Mar 07 01:05:20 PM PST 24
Peak memory 199912 kb
Host smart-f9f6fd3e-f17d-4282-ad6a-b888f7dc9bc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619587224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1619587224
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1691948200
Short name T14
Test name
Test status
Simulation time 10073036862 ps
CPU time 86.16 seconds
Started Mar 07 01:03:32 PM PST 24
Finished Mar 07 01:05:00 PM PST 24
Peak memory 200080 kb
Host smart-dddf50a6-8ecf-498b-9ce9-8147fe5e5c66
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691948200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1691948200
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2985038235
Short name T131
Test name
Test status
Simulation time 17036913 ps
CPU time 0.73 seconds
Started Mar 07 01:03:32 PM PST 24
Finished Mar 07 01:03:34 PM PST 24
Peak memory 197488 kb
Host smart-9d747789-f4de-4d62-9e30-620224ca2608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985038235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2985038235
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1822615830
Short name T241
Test name
Test status
Simulation time 134420721 ps
CPU time 2.34 seconds
Started Mar 07 01:03:34 PM PST 24
Finished Mar 07 01:03:39 PM PST 24
Peak memory 199628 kb
Host smart-19973711-d88a-41ec-933e-14abb6a011cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822615830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1822615830
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.599817468
Short name T201
Test name
Test status
Simulation time 118158864 ps
CPU time 1.25 seconds
Started Mar 07 01:03:32 PM PST 24
Finished Mar 07 01:03:35 PM PST 24
Peak memory 199132 kb
Host smart-836de7ee-0993-46b0-890e-6dd4e03fb016
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599817468 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.599817468
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3522806274
Short name T565
Test name
Test status
Simulation time 239950332 ps
CPU time 0.99 seconds
Started Mar 07 01:03:30 PM PST 24
Finished Mar 07 01:03:31 PM PST 24
Peak memory 198376 kb
Host smart-8c935c32-2329-416b-ada7-f719843ca18d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522806274 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3522806274
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.619275839
Short name T585
Test name
Test status
Simulation time 18516858717 ps
CPU time 448.82 seconds
Started Mar 07 01:03:30 PM PST 24
Finished Mar 07 01:10:59 PM PST 24
Peak memory 200008 kb
Host smart-d643866f-9de2-41e3-a185-ad8f204c0384
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619275839 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.619275839
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.332259325
Short name T222
Test name
Test status
Simulation time 1503716416 ps
CPU time 64.44 seconds
Started Mar 07 01:03:31 PM PST 24
Finished Mar 07 01:04:38 PM PST 24
Peak memory 199800 kb
Host smart-860fe8a2-2034-475a-a674-3ab7314c6208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332259325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.332259325
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.928146773
Short name T66
Test name
Test status
Simulation time 21853146429 ps
CPU time 309.52 seconds
Started Mar 07 01:06:05 PM PST 24
Finished Mar 07 01:11:15 PM PST 24
Peak memory 232860 kb
Host smart-341f8a5a-1397-4ae8-91b3-ce1ec2c48a60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928146773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.928146773
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2209381747
Short name T395
Test name
Test status
Simulation time 171495783 ps
CPU time 0.58 seconds
Started Mar 07 01:03:34 PM PST 24
Finished Mar 07 01:03:37 PM PST 24
Peak memory 195244 kb
Host smart-15fd2f4a-460e-4b15-a5bb-2e773390ea8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209381747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2209381747
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.688753706
Short name T590
Test name
Test status
Simulation time 10785540945 ps
CPU time 48.38 seconds
Started Mar 07 01:03:35 PM PST 24
Finished Mar 07 01:04:25 PM PST 24
Peak memory 232348 kb
Host smart-7a2264c7-0093-47ce-8782-b23802d6a219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688753706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.688753706
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.617533602
Short name T414
Test name
Test status
Simulation time 4135595096 ps
CPU time 8.32 seconds
Started Mar 07 01:03:38 PM PST 24
Finished Mar 07 01:03:47 PM PST 24
Peak memory 200004 kb
Host smart-4ce07683-443f-45de-bd68-ff242dc5c120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617533602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.617533602
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3186193296
Short name T235
Test name
Test status
Simulation time 921132817 ps
CPU time 49.22 seconds
Started Mar 07 01:03:32 PM PST 24
Finished Mar 07 01:04:23 PM PST 24
Peak memory 199880 kb
Host smart-034c9629-4af7-4e47-8a6c-745716a5b095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186193296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3186193296
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.667347768
Short name T401
Test name
Test status
Simulation time 42202452 ps
CPU time 0.72 seconds
Started Mar 07 01:03:39 PM PST 24
Finished Mar 07 01:03:40 PM PST 24
Peak memory 195572 kb
Host smart-51e221f5-7769-490b-96f9-3a1588d50c9e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667347768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.667347768
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3985102230
Short name T99
Test name
Test status
Simulation time 953226023 ps
CPU time 13.69 seconds
Started Mar 07 01:03:37 PM PST 24
Finished Mar 07 01:03:50 PM PST 24
Peak memory 199856 kb
Host smart-7ea98478-1ed9-4a4c-9b2f-b701f74e1138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985102230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3985102230
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2104626025
Short name T536
Test name
Test status
Simulation time 623799682 ps
CPU time 7.06 seconds
Started Mar 07 01:03:35 PM PST 24
Finished Mar 07 01:03:43 PM PST 24
Peak memory 199760 kb
Host smart-673ee02c-1022-486c-97a4-9f20c0c834fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104626025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2104626025
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3384658153
Short name T118
Test name
Test status
Simulation time 16595057152 ps
CPU time 60.89 seconds
Started Mar 07 01:03:32 PM PST 24
Finished Mar 07 01:04:35 PM PST 24
Peak memory 200004 kb
Host smart-d67602b7-21a3-4eaa-8839-355f32e877cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384658153 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3384658153
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2587927265
Short name T316
Test name
Test status
Simulation time 460541787 ps
CPU time 1.32 seconds
Started Mar 07 01:03:35 PM PST 24
Finished Mar 07 01:03:38 PM PST 24
Peak memory 199552 kb
Host smart-0d608792-4e54-4cac-90af-6ffb7990cfcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587927265 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2587927265
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2409684644
Short name T553
Test name
Test status
Simulation time 7816704859 ps
CPU time 426.47 seconds
Started Mar 07 01:03:29 PM PST 24
Finished Mar 07 01:10:36 PM PST 24
Peak memory 200036 kb
Host smart-9daba295-396c-4701-af19-7c2c516a5e99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409684644 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2409684644
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2073214107
Short name T2
Test name
Test status
Simulation time 5181727365 ps
CPU time 64.95 seconds
Started Mar 07 01:03:38 PM PST 24
Finished Mar 07 01:04:44 PM PST 24
Peak memory 200012 kb
Host smart-027b187b-f4a2-4d55-9926-3afebbf0302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073214107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2073214107
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.1554905829
Short name T370
Test name
Test status
Simulation time 55243246061 ps
CPU time 1749.81 seconds
Started Mar 07 01:06:05 PM PST 24
Finished Mar 07 01:35:16 PM PST 24
Peak memory 240584 kb
Host smart-91201901-ebf3-4eb9-915f-80d68cdc4706
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1554905829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.1554905829
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.3320760408
Short name T8
Test name
Test status
Simulation time 58403592839 ps
CPU time 2318.09 seconds
Started Mar 07 01:06:03 PM PST 24
Finished Mar 07 01:44:42 PM PST 24
Peak memory 257132 kb
Host smart-3d42a991-10d6-4f56-b8b4-7da783d95d18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3320760408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.3320760408
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1814315270
Short name T85
Test name
Test status
Simulation time 53295475 ps
CPU time 0.57 seconds
Started Mar 07 01:03:30 PM PST 24
Finished Mar 07 01:03:31 PM PST 24
Peak memory 195240 kb
Host smart-92030241-6362-400e-8974-0ee66713edde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814315270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1814315270
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.389197436
Short name T339
Test name
Test status
Simulation time 4015383008 ps
CPU time 34.58 seconds
Started Mar 07 01:03:35 PM PST 24
Finished Mar 07 01:04:11 PM PST 24
Peak memory 215428 kb
Host smart-bdaae5b3-8d10-4ab8-bb77-04367f0e137c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389197436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.389197436
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1493076185
Short name T366
Test name
Test status
Simulation time 7084224720 ps
CPU time 29.73 seconds
Started Mar 07 01:03:33 PM PST 24
Finished Mar 07 01:04:03 PM PST 24
Peak memory 199956 kb
Host smart-5d023024-a07f-4abd-999d-27994e992d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493076185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1493076185
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1163426836
Short name T291
Test name
Test status
Simulation time 4782548400 ps
CPU time 78.62 seconds
Started Mar 07 01:03:36 PM PST 24
Finished Mar 07 01:04:55 PM PST 24
Peak memory 199952 kb
Host smart-961d428a-777d-4e62-acae-f2aec38a4500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1163426836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1163426836
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3134253084
Short name T196
Test name
Test status
Simulation time 35849043311 ps
CPU time 53.89 seconds
Started Mar 07 01:03:31 PM PST 24
Finished Mar 07 01:04:25 PM PST 24
Peak memory 199980 kb
Host smart-0c6edceb-1653-440a-8b8b-a76f293c9b03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134253084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3134253084
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.291931351
Short name T228
Test name
Test status
Simulation time 11501776201 ps
CPU time 119.75 seconds
Started Mar 07 01:03:33 PM PST 24
Finished Mar 07 01:05:33 PM PST 24
Peak memory 199948 kb
Host smart-92e1e82c-1611-46b1-8c81-6c28435c2a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291931351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.291931351
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.907622670
Short name T83
Test name
Test status
Simulation time 656723135 ps
CPU time 3.74 seconds
Started Mar 07 01:03:32 PM PST 24
Finished Mar 07 01:03:37 PM PST 24
Peak memory 199876 kb
Host smart-f1c8c21b-8a85-40c1-ae30-bdbbe9b6ea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907622670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.907622670
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1327323348
Short name T350
Test name
Test status
Simulation time 78297082738 ps
CPU time 1432.47 seconds
Started Mar 07 01:03:31 PM PST 24
Finished Mar 07 01:27:26 PM PST 24
Peak memory 240024 kb
Host smart-929fbcd9-f402-435d-a115-3cda5f92f9ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327323348 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1327323348
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.3413555394
Short name T373
Test name
Test status
Simulation time 174426243400 ps
CPU time 1646.61 seconds
Started Mar 07 01:03:31 PM PST 24
Finished Mar 07 01:30:58 PM PST 24
Peak memory 227952 kb
Host smart-845d3d4d-2def-40ca-a537-cc2a6c8e4c84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413555394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.3413555394
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.254735357
Short name T365
Test name
Test status
Simulation time 66244677 ps
CPU time 1.21 seconds
Started Mar 07 01:03:36 PM PST 24
Finished Mar 07 01:03:38 PM PST 24
Peak memory 199716 kb
Host smart-f51f64d0-7f16-46e4-897c-d59563b6c96d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254735357 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.254735357
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.694568792
Short name T363
Test name
Test status
Simulation time 9333083508 ps
CPU time 481.92 seconds
Started Mar 07 01:03:32 PM PST 24
Finished Mar 07 01:11:36 PM PST 24
Peak memory 199996 kb
Host smart-c35d9a89-46e2-40ec-bd82-a67c02a1e26e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694568792 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.694568792
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3128343022
Short name T360
Test name
Test status
Simulation time 1626891348 ps
CPU time 72.86 seconds
Started Mar 07 01:03:39 PM PST 24
Finished Mar 07 01:04:52 PM PST 24
Peak memory 199872 kb
Host smart-bb6e6ad0-8c49-4b72-873f-a1c4448bc418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128343022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3128343022
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3389503998
Short name T389
Test name
Test status
Simulation time 14744462 ps
CPU time 0.56 seconds
Started Mar 07 01:03:45 PM PST 24
Finished Mar 07 01:03:45 PM PST 24
Peak memory 194296 kb
Host smart-d6a8f1d7-9fea-47c5-b89b-99a318545d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389503998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3389503998
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2038163091
Short name T494
Test name
Test status
Simulation time 6100379183 ps
CPU time 63.39 seconds
Started Mar 07 01:03:32 PM PST 24
Finished Mar 07 01:04:37 PM PST 24
Peak memory 232564 kb
Host smart-f08196c8-0146-4cca-8efc-d83711462079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038163091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2038163091
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2871158913
Short name T440
Test name
Test status
Simulation time 1792162820 ps
CPU time 35.83 seconds
Started Mar 07 01:03:33 PM PST 24
Finished Mar 07 01:04:09 PM PST 24
Peak memory 199956 kb
Host smart-58693f36-88dd-4342-909b-3fcdddc3ea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871158913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2871158913
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1587996115
Short name T314
Test name
Test status
Simulation time 2319555475 ps
CPU time 135.68 seconds
Started Mar 07 01:03:35 PM PST 24
Finished Mar 07 01:05:52 PM PST 24
Peak memory 199736 kb
Host smart-d394a05f-5a33-4207-b669-41d6fabe0c1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1587996115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1587996115
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1353625120
Short name T182
Test name
Test status
Simulation time 5238119338 ps
CPU time 192.29 seconds
Started Mar 07 01:03:33 PM PST 24
Finished Mar 07 01:06:46 PM PST 24
Peak memory 200080 kb
Host smart-037819eb-31fa-434a-a21a-298090b9d44f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353625120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1353625120
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2078060533
Short name T320
Test name
Test status
Simulation time 16314312526 ps
CPU time 46.63 seconds
Started Mar 07 01:03:35 PM PST 24
Finished Mar 07 01:04:23 PM PST 24
Peak memory 199976 kb
Host smart-df976ed8-69c6-4f46-80cc-95be577af9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078060533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2078060533
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2489969573
Short name T272
Test name
Test status
Simulation time 399417160 ps
CPU time 5.79 seconds
Started Mar 07 01:03:31 PM PST 24
Finished Mar 07 01:03:39 PM PST 24
Peak memory 199892 kb
Host smart-d9e78df9-85f6-4ef9-b31b-f1159d787a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489969573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2489969573
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.18855199
Short name T361
Test name
Test status
Simulation time 395842856 ps
CPU time 1.03 seconds
Started Mar 07 01:03:39 PM PST 24
Finished Mar 07 01:03:40 PM PST 24
Peak memory 198988 kb
Host smart-a293ae9c-cc87-4f99-bffa-33eb17ecd084
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18855199 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.hmac_test_hmac_vectors.18855199
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.4291970155
Short name T195
Test name
Test status
Simulation time 35645027441 ps
CPU time 447.37 seconds
Started Mar 07 01:03:40 PM PST 24
Finished Mar 07 01:11:07 PM PST 24
Peak memory 200052 kb
Host smart-0e40cac7-a3a5-4275-805d-b4037f98d73c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291970155 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.4291970155
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3782022343
Short name T180
Test name
Test status
Simulation time 472062467 ps
CPU time 5.85 seconds
Started Mar 07 01:03:36 PM PST 24
Finished Mar 07 01:03:42 PM PST 24
Peak memory 199848 kb
Host smart-8a8c7fb9-9780-4319-8eb4-8c62eb0e3e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782022343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3782022343
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1399561560
Short name T468
Test name
Test status
Simulation time 24560130 ps
CPU time 0.55 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:02:12 PM PST 24
Peak memory 194152 kb
Host smart-eac756ac-7f10-4d95-ace9-8913fcb43873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399561560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1399561560
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.870257948
Short name T426
Test name
Test status
Simulation time 758981575 ps
CPU time 23.45 seconds
Started Mar 07 01:02:12 PM PST 24
Finished Mar 07 01:02:35 PM PST 24
Peak memory 208112 kb
Host smart-d9141a7b-eee5-4f52-9f7d-604d059a5956
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870257948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.870257948
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1639938860
Short name T145
Test name
Test status
Simulation time 2708779465 ps
CPU time 54.95 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:03:06 PM PST 24
Peak memory 199956 kb
Host smart-74783a12-c549-44ac-851d-2061042c3354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639938860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1639938860
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3261314329
Short name T181
Test name
Test status
Simulation time 11427753894 ps
CPU time 62.72 seconds
Started Mar 07 01:02:10 PM PST 24
Finished Mar 07 01:03:13 PM PST 24
Peak memory 200000 kb
Host smart-f94ad45d-c0c6-460e-8b1a-7967b2573e8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261314329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3261314329
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.271828995
Short name T461
Test name
Test status
Simulation time 14317942050 ps
CPU time 177.67 seconds
Started Mar 07 01:02:13 PM PST 24
Finished Mar 07 01:05:10 PM PST 24
Peak memory 199988 kb
Host smart-d76a7d55-d3a0-4232-825d-53fb40363788
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271828995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.271828995
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.202778198
Short name T257
Test name
Test status
Simulation time 122821434 ps
CPU time 6.29 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:02:17 PM PST 24
Peak memory 199804 kb
Host smart-9dc646f5-f392-4f27-99db-4997cf17e0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202778198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.202778198
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.414241480
Short name T37
Test name
Test status
Simulation time 526973011 ps
CPU time 0.8 seconds
Started Mar 07 01:02:08 PM PST 24
Finished Mar 07 01:02:09 PM PST 24
Peak memory 218432 kb
Host smart-1e74d75a-74ee-436d-89a7-2a6897f48fd8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414241480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.414241480
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3289454260
Short name T214
Test name
Test status
Simulation time 803472398 ps
CPU time 1.72 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:02:13 PM PST 24
Peak memory 199872 kb
Host smart-3df797ea-7a01-44dc-a4bf-0f692edd5dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289454260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3289454260
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1215627620
Short name T74
Test name
Test status
Simulation time 176514324846 ps
CPU time 1194.92 seconds
Started Mar 07 01:02:09 PM PST 24
Finished Mar 07 01:22:04 PM PST 24
Peak memory 235296 kb
Host smart-ba642784-fe00-4446-8e24-cdc8db0599d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215627620 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1215627620
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.4158144309
Short name T45
Test name
Test status
Simulation time 101152828 ps
CPU time 0.95 seconds
Started Mar 07 01:02:15 PM PST 24
Finished Mar 07 01:02:16 PM PST 24
Peak memory 199636 kb
Host smart-5a6f1ca3-9c27-4343-a135-5cafe87fbd6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158144309 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.4158144309
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2601306208
Short name T358
Test name
Test status
Simulation time 15874281295 ps
CPU time 409.04 seconds
Started Mar 07 01:02:18 PM PST 24
Finished Mar 07 01:09:08 PM PST 24
Peak memory 199980 kb
Host smart-4e1f46d5-88a5-4f2b-85aa-df81026bab87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601306208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2601306208
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.604983562
Short name T141
Test name
Test status
Simulation time 18009701305 ps
CPU time 74.47 seconds
Started Mar 07 01:02:16 PM PST 24
Finished Mar 07 01:03:31 PM PST 24
Peak memory 199996 kb
Host smart-ca37b980-0ed7-4ece-8adf-a256fe41654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604983562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.604983562
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2459850375
Short name T42
Test name
Test status
Simulation time 29582149 ps
CPU time 0.56 seconds
Started Mar 07 01:03:48 PM PST 24
Finished Mar 07 01:03:49 PM PST 24
Peak memory 195304 kb
Host smart-85fd82f6-efc4-4ba6-9ea0-9e5c246eb050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459850375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2459850375
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3278534694
Short name T548
Test name
Test status
Simulation time 296219485 ps
CPU time 3.3 seconds
Started Mar 07 01:03:54 PM PST 24
Finished Mar 07 01:03:58 PM PST 24
Peak memory 199824 kb
Host smart-71049c05-c28a-4096-ad8e-776d8db52fb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3278534694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3278534694
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2539453058
Short name T197
Test name
Test status
Simulation time 951061548 ps
CPU time 1.71 seconds
Started Mar 07 01:03:46 PM PST 24
Finished Mar 07 01:03:48 PM PST 24
Peak memory 199848 kb
Host smart-3536503c-9658-4be4-aaa1-7aad2c0683ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539453058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2539453058
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2034927667
Short name T287
Test name
Test status
Simulation time 533065302 ps
CPU time 13.8 seconds
Started Mar 07 01:03:42 PM PST 24
Finished Mar 07 01:03:56 PM PST 24
Peak memory 199864 kb
Host smart-7d1a3eec-e7a7-4792-8f20-47a701a8df19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2034927667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2034927667
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.4221765490
Short name T447
Test name
Test status
Simulation time 51712190615 ps
CPU time 148.98 seconds
Started Mar 07 01:03:42 PM PST 24
Finished Mar 07 01:06:11 PM PST 24
Peak memory 199956 kb
Host smart-0a3f85e6-142c-4ad1-8b9c-b4da850d3807
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221765490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.4221765490
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.545768323
Short name T486
Test name
Test status
Simulation time 1159042897 ps
CPU time 16.61 seconds
Started Mar 07 01:03:46 PM PST 24
Finished Mar 07 01:04:03 PM PST 24
Peak memory 199872 kb
Host smart-5beeaa4c-ba61-4c42-9e61-8c75f70c3ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545768323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.545768323
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1089571977
Short name T256
Test name
Test status
Simulation time 97732291 ps
CPU time 1.62 seconds
Started Mar 07 01:03:47 PM PST 24
Finished Mar 07 01:03:49 PM PST 24
Peak memory 199856 kb
Host smart-89aae6f8-ba05-4b3b-8eb0-b1ad6abe4692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089571977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1089571977
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2533461852
Short name T460
Test name
Test status
Simulation time 6265456564 ps
CPU time 286.31 seconds
Started Mar 07 01:03:47 PM PST 24
Finished Mar 07 01:08:34 PM PST 24
Peak memory 227484 kb
Host smart-4473eb2f-8254-4fef-ae87-707dd60d9933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533461852 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2533461852
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1704537900
Short name T506
Test name
Test status
Simulation time 147286481 ps
CPU time 1.02 seconds
Started Mar 07 01:03:46 PM PST 24
Finished Mar 07 01:03:48 PM PST 24
Peak memory 198552 kb
Host smart-199c0982-8634-4c80-b5f7-02944cadeefd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704537900 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1704537900
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3384846337
Short name T428
Test name
Test status
Simulation time 13726598151 ps
CPU time 395.26 seconds
Started Mar 07 01:03:54 PM PST 24
Finished Mar 07 01:10:30 PM PST 24
Peak memory 199992 kb
Host smart-53e973d0-a85d-475f-a7f1-57f4920b7e50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384846337 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3384846337
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.421344125
Short name T495
Test name
Test status
Simulation time 1346220445 ps
CPU time 12.46 seconds
Started Mar 07 01:03:42 PM PST 24
Finished Mar 07 01:03:54 PM PST 24
Peak memory 199860 kb
Host smart-6dca3e7b-d4eb-4b54-acb8-e2beb2555115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421344125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.421344125
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1302743981
Short name T538
Test name
Test status
Simulation time 14176867 ps
CPU time 0.58 seconds
Started Mar 07 01:03:43 PM PST 24
Finished Mar 07 01:03:43 PM PST 24
Peak memory 194860 kb
Host smart-9d588a3a-1dd5-4381-9931-f1e009d621d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302743981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1302743981
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2907660473
Short name T285
Test name
Test status
Simulation time 1883928419 ps
CPU time 28.24 seconds
Started Mar 07 01:03:41 PM PST 24
Finished Mar 07 01:04:10 PM PST 24
Peak memory 199868 kb
Host smart-be8a7084-2b7f-4f63-ab87-6d75915e16cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2907660473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2907660473
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2134040784
Short name T471
Test name
Test status
Simulation time 2285753871 ps
CPU time 13.11 seconds
Started Mar 07 01:03:47 PM PST 24
Finished Mar 07 01:04:00 PM PST 24
Peak memory 199860 kb
Host smart-2ffa3437-9a89-471d-a37a-ac68cd1664df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134040784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2134040784
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1371833339
Short name T262
Test name
Test status
Simulation time 3256214239 ps
CPU time 112.53 seconds
Started Mar 07 01:03:41 PM PST 24
Finished Mar 07 01:05:34 PM PST 24
Peak memory 199920 kb
Host smart-f23c3c61-6cb7-4fe2-99c8-3b456d41238e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1371833339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1371833339
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1819306594
Short name T150
Test name
Test status
Simulation time 5797964395 ps
CPU time 160.49 seconds
Started Mar 07 01:03:42 PM PST 24
Finished Mar 07 01:06:23 PM PST 24
Peak memory 200036 kb
Host smart-6318e8f9-3024-476a-9dd0-49a455e7a11a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819306594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1819306594
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.493063750
Short name T336
Test name
Test status
Simulation time 4508326164 ps
CPU time 44 seconds
Started Mar 07 01:03:43 PM PST 24
Finished Mar 07 01:04:27 PM PST 24
Peak memory 199892 kb
Host smart-3d8ba716-3ff2-46db-a2f2-9ad021cf7c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493063750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.493063750
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1986401208
Short name T31
Test name
Test status
Simulation time 469696134 ps
CPU time 5.38 seconds
Started Mar 07 01:03:42 PM PST 24
Finished Mar 07 01:03:48 PM PST 24
Peak memory 199876 kb
Host smart-590166b6-353e-445d-9ef7-67f1dc5ef7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986401208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1986401208
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3244646778
Short name T340
Test name
Test status
Simulation time 129356244823 ps
CPU time 1612.11 seconds
Started Mar 07 01:03:51 PM PST 24
Finished Mar 07 01:30:44 PM PST 24
Peak memory 200024 kb
Host smart-a859c401-eeae-4817-846f-99569f36ab17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244646778 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3244646778
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2042964896
Short name T520
Test name
Test status
Simulation time 173914616 ps
CPU time 0.94 seconds
Started Mar 07 01:03:43 PM PST 24
Finished Mar 07 01:03:44 PM PST 24
Peak memory 198044 kb
Host smart-120c753b-913f-44d5-bea2-d542952e5ae9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042964896 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2042964896
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2348773457
Short name T508
Test name
Test status
Simulation time 166033896276 ps
CPU time 506.05 seconds
Started Mar 07 01:03:42 PM PST 24
Finished Mar 07 01:12:08 PM PST 24
Peak memory 200016 kb
Host smart-f65db310-6f2d-49b1-af68-add39b660835
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348773457 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2348773457
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.568897431
Short name T542
Test name
Test status
Simulation time 181365070 ps
CPU time 3.68 seconds
Started Mar 07 01:03:43 PM PST 24
Finished Mar 07 01:03:47 PM PST 24
Peak memory 199888 kb
Host smart-3496d4dc-40f5-43f8-9dec-7bf27c0431df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568897431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.568897431
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2476713764
Short name T422
Test name
Test status
Simulation time 40150220 ps
CPU time 0.54 seconds
Started Mar 07 01:03:46 PM PST 24
Finished Mar 07 01:03:47 PM PST 24
Peak memory 194256 kb
Host smart-636f801b-518c-464c-acd2-d56be63762ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476713764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2476713764
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.984755255
Short name T266
Test name
Test status
Simulation time 6349847295 ps
CPU time 56.26 seconds
Started Mar 07 01:03:47 PM PST 24
Finished Mar 07 01:04:43 PM PST 24
Peak memory 240932 kb
Host smart-b03184d8-9308-4e09-9b87-1752639d66b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984755255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.984755255
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2931537502
Short name T70
Test name
Test status
Simulation time 1190620596 ps
CPU time 10.33 seconds
Started Mar 07 01:03:49 PM PST 24
Finished Mar 07 01:03:59 PM PST 24
Peak memory 199828 kb
Host smart-9ea9cd9e-3414-478a-a7dc-691c7d84d6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931537502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2931537502
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.4075669938
Short name T309
Test name
Test status
Simulation time 137473238 ps
CPU time 8.04 seconds
Started Mar 07 01:03:46 PM PST 24
Finished Mar 07 01:03:54 PM PST 24
Peak memory 199852 kb
Host smart-126f2bb9-f99e-4b68-96fd-08c14e3e2ea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4075669938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.4075669938
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.710736684
Short name T467
Test name
Test status
Simulation time 1932658890 ps
CPU time 12.15 seconds
Started Mar 07 01:03:42 PM PST 24
Finished Mar 07 01:03:54 PM PST 24
Peak memory 199856 kb
Host smart-dfd64e92-7b35-4979-824b-17207081466a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710736684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.710736684
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1111110781
Short name T129
Test name
Test status
Simulation time 1615369027 ps
CPU time 22.35 seconds
Started Mar 07 01:03:44 PM PST 24
Finished Mar 07 01:04:07 PM PST 24
Peak memory 199864 kb
Host smart-999fdf54-1288-472a-b64d-ce08cacad9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111110781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1111110781
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2516609392
Short name T307
Test name
Test status
Simulation time 90268382 ps
CPU time 0.93 seconds
Started Mar 07 01:03:46 PM PST 24
Finished Mar 07 01:03:47 PM PST 24
Peak memory 198040 kb
Host smart-2cd00510-ffe3-4a52-b2b7-20539addc286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516609392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2516609392
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3373336844
Short name T218
Test name
Test status
Simulation time 2220709500 ps
CPU time 66.6 seconds
Started Mar 07 01:03:43 PM PST 24
Finished Mar 07 01:04:50 PM PST 24
Peak memory 199956 kb
Host smart-e0982882-c34b-4c13-8eaf-9ff640870b07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373336844 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3373336844
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3687441128
Short name T394
Test name
Test status
Simulation time 62140579 ps
CPU time 1.3 seconds
Started Mar 07 01:03:44 PM PST 24
Finished Mar 07 01:03:45 PM PST 24
Peak memory 199164 kb
Host smart-80daa5c8-962c-45da-b423-8156df0b0268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687441128 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3687441128
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2772425999
Short name T562
Test name
Test status
Simulation time 156002562632 ps
CPU time 424.33 seconds
Started Mar 07 01:03:44 PM PST 24
Finished Mar 07 01:10:48 PM PST 24
Peak memory 200020 kb
Host smart-e8c64e5f-99ad-4584-b052-9ce71c7e0490
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772425999 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2772425999
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2443639927
Short name T474
Test name
Test status
Simulation time 806072012 ps
CPU time 40.21 seconds
Started Mar 07 01:03:43 PM PST 24
Finished Mar 07 01:04:24 PM PST 24
Peak memory 199896 kb
Host smart-1b054e20-4922-4760-89b0-3c56bb168a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443639927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2443639927
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1297163004
Short name T341
Test name
Test status
Simulation time 12938792 ps
CPU time 0.58 seconds
Started Mar 07 01:03:57 PM PST 24
Finished Mar 07 01:04:01 PM PST 24
Peak memory 194896 kb
Host smart-0616ff6b-f520-484a-a73c-d7a976771274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297163004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1297163004
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3411569052
Short name T161
Test name
Test status
Simulation time 952348699 ps
CPU time 8.25 seconds
Started Mar 07 01:03:46 PM PST 24
Finished Mar 07 01:03:55 PM PST 24
Peak memory 199880 kb
Host smart-e6f3b462-fddd-41b5-aa79-0badb24457a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411569052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3411569052
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2440827186
Short name T530
Test name
Test status
Simulation time 13653814675 ps
CPU time 13.5 seconds
Started Mar 07 01:03:54 PM PST 24
Finished Mar 07 01:04:08 PM PST 24
Peak memory 199924 kb
Host smart-3887b2c1-7aa4-430c-bc3a-82a3f568e2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440827186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2440827186
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.509238103
Short name T489
Test name
Test status
Simulation time 2239982015 ps
CPU time 60.87 seconds
Started Mar 07 01:03:43 PM PST 24
Finished Mar 07 01:04:44 PM PST 24
Peak memory 199852 kb
Host smart-45232e74-d7bc-417a-93ca-ad55f89a42b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=509238103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.509238103
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.109992908
Short name T351
Test name
Test status
Simulation time 10687086507 ps
CPU time 128.37 seconds
Started Mar 07 01:03:43 PM PST 24
Finished Mar 07 01:05:51 PM PST 24
Peak memory 199988 kb
Host smart-96f426d9-7028-4349-8ea0-c1571ca21908
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109992908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.109992908
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4075986227
Short name T578
Test name
Test status
Simulation time 5461045635 ps
CPU time 82.02 seconds
Started Mar 07 01:03:43 PM PST 24
Finished Mar 07 01:05:05 PM PST 24
Peak memory 199992 kb
Host smart-16a3767d-7956-4d9f-b77b-178f1b678967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075986227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4075986227
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.4016248070
Short name T187
Test name
Test status
Simulation time 964032406 ps
CPU time 3.74 seconds
Started Mar 07 01:03:42 PM PST 24
Finished Mar 07 01:03:46 PM PST 24
Peak memory 199772 kb
Host smart-3314ea14-cf30-43e1-bd62-d3b9cb05eec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016248070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.4016248070
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2685649543
Short name T29
Test name
Test status
Simulation time 919048599 ps
CPU time 8.67 seconds
Started Mar 07 01:03:56 PM PST 24
Finished Mar 07 01:04:05 PM PST 24
Peak memory 199844 kb
Host smart-7e369700-1794-4199-a8e5-dec11f7c0ddc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685649543 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2685649543
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.772060606
Short name T432
Test name
Test status
Simulation time 144550910 ps
CPU time 0.99 seconds
Started Mar 07 01:03:57 PM PST 24
Finished Mar 07 01:04:01 PM PST 24
Peak memory 197888 kb
Host smart-edeaecca-3cea-4b6c-9024-f6800e98de02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772060606 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.772060606
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.985017992
Short name T342
Test name
Test status
Simulation time 8706564610 ps
CPU time 459.03 seconds
Started Mar 07 01:03:56 PM PST 24
Finished Mar 07 01:11:39 PM PST 24
Peak memory 199836 kb
Host smart-775eafe8-5da3-4bb7-87e9-6b6a546ceb24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985017992 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.985017992
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1684678498
Short name T202
Test name
Test status
Simulation time 10859911260 ps
CPU time 57.74 seconds
Started Mar 07 01:03:55 PM PST 24
Finished Mar 07 01:04:53 PM PST 24
Peak memory 199948 kb
Host smart-fcc08509-ec32-41a2-bc41-62942f737c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684678498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1684678498
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2214196201
Short name T219
Test name
Test status
Simulation time 46628004 ps
CPU time 0.6 seconds
Started Mar 07 01:03:56 PM PST 24
Finished Mar 07 01:03:57 PM PST 24
Peak memory 194284 kb
Host smart-dececcd3-0e1d-4ccc-8028-82eaeefbc17b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214196201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2214196201
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1421695188
Short name T493
Test name
Test status
Simulation time 1614987430 ps
CPU time 62.6 seconds
Started Mar 07 01:03:54 PM PST 24
Finished Mar 07 01:04:57 PM PST 24
Peak memory 225984 kb
Host smart-3cb9a8ff-8403-425d-9103-3d03fcaec34c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421695188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1421695188
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1183966335
Short name T589
Test name
Test status
Simulation time 702027072 ps
CPU time 36.95 seconds
Started Mar 07 01:03:54 PM PST 24
Finished Mar 07 01:04:31 PM PST 24
Peak memory 199884 kb
Host smart-b7d2542e-f09a-4903-a73a-5a0c16f85fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183966335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1183966335
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1013267093
Short name T191
Test name
Test status
Simulation time 4116107266 ps
CPU time 60.14 seconds
Started Mar 07 01:03:57 PM PST 24
Finished Mar 07 01:05:00 PM PST 24
Peak memory 199744 kb
Host smart-8ba7d796-c7bb-44a3-a4ea-0c5875e707d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1013267093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1013267093
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2645997172
Short name T12
Test name
Test status
Simulation time 90142681294 ps
CPU time 118.44 seconds
Started Mar 07 01:03:54 PM PST 24
Finished Mar 07 01:05:53 PM PST 24
Peak memory 200012 kb
Host smart-80d15be0-338c-40b7-aa77-370a3144ab88
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645997172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2645997172
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.358104301
Short name T174
Test name
Test status
Simulation time 5817735300 ps
CPU time 82.33 seconds
Started Mar 07 01:03:57 PM PST 24
Finished Mar 07 01:05:23 PM PST 24
Peak memory 199948 kb
Host smart-6515f0a9-bd6b-4e92-a2db-ab2bdf7b6afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358104301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.358104301
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2002293288
Short name T399
Test name
Test status
Simulation time 65910700 ps
CPU time 2.14 seconds
Started Mar 07 01:03:58 PM PST 24
Finished Mar 07 01:04:02 PM PST 24
Peak memory 199876 kb
Host smart-b7e8d163-1ea1-4022-95b4-333140b05c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002293288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2002293288
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2549141077
Short name T586
Test name
Test status
Simulation time 23884941331 ps
CPU time 439.94 seconds
Started Mar 07 01:03:54 PM PST 24
Finished Mar 07 01:11:15 PM PST 24
Peak memory 200032 kb
Host smart-eceb3297-38cc-4cf7-afdf-cc3d152a4a2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549141077 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2549141077
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3473659402
Short name T546
Test name
Test status
Simulation time 29223730 ps
CPU time 1.01 seconds
Started Mar 07 01:03:56 PM PST 24
Finished Mar 07 01:04:01 PM PST 24
Peak memory 198728 kb
Host smart-a05dc744-bf2e-4846-9b6a-42d43e95e07a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473659402 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3473659402
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1061239219
Short name T557
Test name
Test status
Simulation time 40247060039 ps
CPU time 504.37 seconds
Started Mar 07 01:03:54 PM PST 24
Finished Mar 07 01:12:19 PM PST 24
Peak memory 200020 kb
Host smart-daa8ddb7-413d-450e-9735-827c788ad075
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061239219 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1061239219
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1494006750
Short name T488
Test name
Test status
Simulation time 953389880 ps
CPU time 37.1 seconds
Started Mar 07 01:03:55 PM PST 24
Finished Mar 07 01:04:32 PM PST 24
Peak memory 199892 kb
Host smart-cf1587bd-39f9-43ff-b285-f1f9e4f15d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494006750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1494006750
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.477060755
Short name T38
Test name
Test status
Simulation time 23538228 ps
CPU time 0.57 seconds
Started Mar 07 01:04:12 PM PST 24
Finished Mar 07 01:04:14 PM PST 24
Peak memory 194320 kb
Host smart-662242be-88fb-49ad-91d8-8a3b5cc5d215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477060755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.477060755
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1996907896
Short name T278
Test name
Test status
Simulation time 1678862167 ps
CPU time 28.85 seconds
Started Mar 07 01:03:55 PM PST 24
Finished Mar 07 01:04:24 PM PST 24
Peak memory 208992 kb
Host smart-7f46ed5e-998d-4ccf-9bb7-b8652379a723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996907896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1996907896
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4067250318
Short name T183
Test name
Test status
Simulation time 1290651635 ps
CPU time 60.48 seconds
Started Mar 07 01:03:53 PM PST 24
Finished Mar 07 01:04:54 PM PST 24
Peak memory 199880 kb
Host smart-d004ff74-7d58-499a-b0f2-6caeb12835c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067250318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4067250318
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2313910604
Short name T178
Test name
Test status
Simulation time 1380063527 ps
CPU time 78.65 seconds
Started Mar 07 01:03:57 PM PST 24
Finished Mar 07 01:05:19 PM PST 24
Peak memory 199864 kb
Host smart-e6a030e6-a606-40fd-9fb0-89826add5a05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313910604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2313910604
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.191033080
Short name T581
Test name
Test status
Simulation time 419765195 ps
CPU time 22.63 seconds
Started Mar 07 01:03:55 PM PST 24
Finished Mar 07 01:04:18 PM PST 24
Peak memory 199812 kb
Host smart-38de82ca-8f85-4a80-a57b-24dae6e2f5fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191033080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.191033080
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2781296722
Short name T133
Test name
Test status
Simulation time 2050984581 ps
CPU time 15.06 seconds
Started Mar 07 01:03:58 PM PST 24
Finished Mar 07 01:04:15 PM PST 24
Peak memory 199880 kb
Host smart-e6107fe9-e34e-406f-8dbd-99d4daab2ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781296722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2781296722
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.91866344
Short name T487
Test name
Test status
Simulation time 1679432709 ps
CPU time 6.5 seconds
Started Mar 07 01:03:57 PM PST 24
Finished Mar 07 01:04:07 PM PST 24
Peak memory 199836 kb
Host smart-06293333-35cf-4f79-869a-47c86b394c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91866344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.91866344
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1962220333
Short name T156
Test name
Test status
Simulation time 192699435311 ps
CPU time 949.75 seconds
Started Mar 07 01:04:09 PM PST 24
Finished Mar 07 01:20:00 PM PST 24
Peak memory 239096 kb
Host smart-0f826485-1d1d-4106-9671-b15a7c3f2292
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962220333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1962220333
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1120880970
Short name T163
Test name
Test status
Simulation time 100894799 ps
CPU time 1.08 seconds
Started Mar 07 01:04:13 PM PST 24
Finished Mar 07 01:04:15 PM PST 24
Peak memory 198776 kb
Host smart-d33f4907-81aa-4f88-a470-c51d9e3b7374
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120880970 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1120880970
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2928145413
Short name T478
Test name
Test status
Simulation time 112070298189 ps
CPU time 493.64 seconds
Started Mar 07 01:04:09 PM PST 24
Finished Mar 07 01:12:24 PM PST 24
Peak memory 199952 kb
Host smart-a3efb0f0-9662-4ad0-a557-73eab2815347
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928145413 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2928145413
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1277998597
Short name T349
Test name
Test status
Simulation time 9389160370 ps
CPU time 71.59 seconds
Started Mar 07 01:03:56 PM PST 24
Finished Mar 07 01:05:12 PM PST 24
Peak memory 199996 kb
Host smart-c9a2f691-e50e-45f6-91bf-9852e39e0823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277998597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1277998597
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2836864795
Short name T433
Test name
Test status
Simulation time 18839809 ps
CPU time 0.58 seconds
Started Mar 07 01:04:08 PM PST 24
Finished Mar 07 01:04:11 PM PST 24
Peak memory 194252 kb
Host smart-699d079b-f912-47da-9625-5f29314fccc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836864795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2836864795
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3069519474
Short name T259
Test name
Test status
Simulation time 2227397129 ps
CPU time 58.72 seconds
Started Mar 07 01:04:09 PM PST 24
Finished Mar 07 01:05:09 PM PST 24
Peak memory 209164 kb
Host smart-e11f9969-00d5-42db-9c15-c690f94a4049
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3069519474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3069519474
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1507576262
Short name T162
Test name
Test status
Simulation time 3148550447 ps
CPU time 16.84 seconds
Started Mar 07 01:04:11 PM PST 24
Finished Mar 07 01:04:29 PM PST 24
Peak memory 199676 kb
Host smart-c274131b-8b97-4235-bfee-13dcbff2045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507576262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1507576262
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4229463918
Short name T491
Test name
Test status
Simulation time 166952778 ps
CPU time 9.38 seconds
Started Mar 07 01:04:09 PM PST 24
Finished Mar 07 01:04:20 PM PST 24
Peak memory 199892 kb
Host smart-153f58e6-6dca-4d0f-88b2-a657013b5354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229463918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4229463918
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1894776103
Short name T598
Test name
Test status
Simulation time 4789915702 ps
CPU time 76.9 seconds
Started Mar 07 01:04:07 PM PST 24
Finished Mar 07 01:05:24 PM PST 24
Peak memory 199812 kb
Host smart-c8283502-3e01-4673-8698-3194b7880f7e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894776103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1894776103
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.4245327321
Short name T95
Test name
Test status
Simulation time 5645911762 ps
CPU time 28.27 seconds
Started Mar 07 01:04:08 PM PST 24
Finished Mar 07 01:04:36 PM PST 24
Peak memory 200048 kb
Host smart-1025eec9-46d5-4af8-a739-08adaf97ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245327321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4245327321
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2576329312
Short name T357
Test name
Test status
Simulation time 78895477 ps
CPU time 1.41 seconds
Started Mar 07 01:04:09 PM PST 24
Finished Mar 07 01:04:11 PM PST 24
Peak memory 199860 kb
Host smart-e002c2e8-c81d-4683-a540-fa3518a88a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576329312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2576329312
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2968911846
Short name T596
Test name
Test status
Simulation time 47082692570 ps
CPU time 599.63 seconds
Started Mar 07 01:04:08 PM PST 24
Finished Mar 07 01:14:10 PM PST 24
Peak memory 231036 kb
Host smart-c6f0b716-04db-4b5d-9487-506affb6f04d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968911846 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2968911846
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.3208945941
Short name T364
Test name
Test status
Simulation time 87334671096 ps
CPU time 2996.4 seconds
Started Mar 07 01:04:12 PM PST 24
Finished Mar 07 01:54:10 PM PST 24
Peak memory 258500 kb
Host smart-7ff59b4d-5f7b-4a6e-b386-8449c2ca0ff7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208945941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.3208945941
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1934235130
Short name T545
Test name
Test status
Simulation time 232972037 ps
CPU time 1.3 seconds
Started Mar 07 01:04:08 PM PST 24
Finished Mar 07 01:04:10 PM PST 24
Peak memory 199432 kb
Host smart-b40738dc-950f-45d6-a454-a7ce9904ba25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934235130 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1934235130
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.429956189
Short name T167
Test name
Test status
Simulation time 25753096594 ps
CPU time 475.11 seconds
Started Mar 07 01:04:09 PM PST 24
Finished Mar 07 01:12:06 PM PST 24
Peak memory 199940 kb
Host smart-adefdc09-1ba4-4bdf-b19b-a8374fbb9b30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429956189 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.429956189
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2678486487
Short name T554
Test name
Test status
Simulation time 8799062897 ps
CPU time 40.51 seconds
Started Mar 07 01:04:07 PM PST 24
Finished Mar 07 01:04:48 PM PST 24
Peak memory 199992 kb
Host smart-2d43ddca-90cb-48af-a411-dfc095d10d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678486487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2678486487
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2446478378
Short name T532
Test name
Test status
Simulation time 48704779 ps
CPU time 0.58 seconds
Started Mar 07 01:04:11 PM PST 24
Finished Mar 07 01:04:12 PM PST 24
Peak memory 195084 kb
Host smart-b2d4f091-b7ab-4ea7-ad65-f4cea48824e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446478378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2446478378
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2673064778
Short name T417
Test name
Test status
Simulation time 818561487 ps
CPU time 27.22 seconds
Started Mar 07 01:04:11 PM PST 24
Finished Mar 07 01:04:39 PM PST 24
Peak memory 208060 kb
Host smart-b8dc32af-a540-4d87-9e74-e74dca9ca6e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673064778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2673064778
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1808611427
Short name T574
Test name
Test status
Simulation time 1416336931 ps
CPU time 17.5 seconds
Started Mar 07 01:04:09 PM PST 24
Finished Mar 07 01:04:28 PM PST 24
Peak memory 199988 kb
Host smart-0cdb4085-cb61-4cec-aba9-dd9b6b5d132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808611427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1808611427
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2508152663
Short name T263
Test name
Test status
Simulation time 3536457504 ps
CPU time 99.52 seconds
Started Mar 07 01:04:09 PM PST 24
Finished Mar 07 01:05:50 PM PST 24
Peak memory 199964 kb
Host smart-cd205dcd-5545-49c4-9e57-4f1286c18283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508152663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2508152663
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3979612818
Short name T16
Test name
Test status
Simulation time 6660043042 ps
CPU time 119.83 seconds
Started Mar 07 01:04:07 PM PST 24
Finished Mar 07 01:06:07 PM PST 24
Peak memory 200056 kb
Host smart-8df08115-4f40-4da4-b93f-64eb4ae0a8fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979612818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3979612818
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.4153543974
Short name T410
Test name
Test status
Simulation time 3879384726 ps
CPU time 56.25 seconds
Started Mar 07 01:04:10 PM PST 24
Finished Mar 07 01:05:07 PM PST 24
Peak memory 199952 kb
Host smart-6789972c-5cb5-4911-a5d3-ad138b5b633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153543974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.4153543974
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.93383171
Short name T89
Test name
Test status
Simulation time 390711461 ps
CPU time 3.04 seconds
Started Mar 07 01:04:08 PM PST 24
Finished Mar 07 01:04:11 PM PST 24
Peak memory 199864 kb
Host smart-df56f493-a532-4b05-8a0d-3b2b3c69c90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93383171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.93383171
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2698947524
Short name T526
Test name
Test status
Simulation time 31600220505 ps
CPU time 166 seconds
Started Mar 07 01:04:08 PM PST 24
Finished Mar 07 01:06:56 PM PST 24
Peak memory 199984 kb
Host smart-3afa0979-8538-4af3-b209-8b3e6c7a1d3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698947524 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2698947524
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3173440533
Short name T369
Test name
Test status
Simulation time 115222116 ps
CPU time 1.26 seconds
Started Mar 07 01:04:12 PM PST 24
Finished Mar 07 01:04:14 PM PST 24
Peak memory 199328 kb
Host smart-f3b5f15e-ab7a-44e3-9d78-97063f5a47e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173440533 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3173440533
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3868634683
Short name T258
Test name
Test status
Simulation time 8237785684 ps
CPU time 442.16 seconds
Started Mar 07 01:04:10 PM PST 24
Finished Mar 07 01:11:32 PM PST 24
Peak memory 199928 kb
Host smart-1a72ae00-6fd6-45f5-a0fb-8f5f745fd66b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868634683 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.3868634683
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1437599120
Short name T448
Test name
Test status
Simulation time 6594368895 ps
CPU time 65.29 seconds
Started Mar 07 01:04:09 PM PST 24
Finished Mar 07 01:05:15 PM PST 24
Peak memory 199976 kb
Host smart-41eb5753-9291-464f-8a3c-2236e4af7c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437599120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1437599120
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3121763955
Short name T88
Test name
Test status
Simulation time 52053667 ps
CPU time 0.57 seconds
Started Mar 07 01:04:19 PM PST 24
Finished Mar 07 01:04:20 PM PST 24
Peak memory 194812 kb
Host smart-909d60f1-d320-49f9-b9e5-0abb866ba654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121763955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3121763955
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.593013388
Short name T505
Test name
Test status
Simulation time 1217897306 ps
CPU time 45.9 seconds
Started Mar 07 01:04:08 PM PST 24
Finished Mar 07 01:04:56 PM PST 24
Peak memory 225492 kb
Host smart-214675fd-cae8-4a3b-9754-797471db3889
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593013388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.593013388
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3615079316
Short name T87
Test name
Test status
Simulation time 861061487 ps
CPU time 41.71 seconds
Started Mar 07 01:04:07 PM PST 24
Finished Mar 07 01:04:49 PM PST 24
Peak memory 199868 kb
Host smart-f7e4f200-a432-4ad9-a941-f11acb55e27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615079316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3615079316
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2164268048
Short name T402
Test name
Test status
Simulation time 111290601 ps
CPU time 1.15 seconds
Started Mar 07 01:04:13 PM PST 24
Finished Mar 07 01:04:15 PM PST 24
Peak memory 198232 kb
Host smart-234a7d17-ca28-4481-b4af-19fe8c125f5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164268048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2164268048
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3924394463
Short name T158
Test name
Test status
Simulation time 6964986721 ps
CPU time 125.01 seconds
Started Mar 07 01:04:12 PM PST 24
Finished Mar 07 01:06:17 PM PST 24
Peak memory 199996 kb
Host smart-9079b6cd-8790-4165-b4e1-2d674c4e0ff4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924394463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3924394463
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1892558752
Short name T509
Test name
Test status
Simulation time 1514463830 ps
CPU time 9.12 seconds
Started Mar 07 01:04:08 PM PST 24
Finished Mar 07 01:04:18 PM PST 24
Peak memory 199868 kb
Host smart-4b1cbb4b-3938-4b5f-b2ce-8fa36b1aa14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892558752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1892558752
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2926399307
Short name T396
Test name
Test status
Simulation time 666176603 ps
CPU time 2.47 seconds
Started Mar 07 01:04:10 PM PST 24
Finished Mar 07 01:04:13 PM PST 24
Peak memory 199892 kb
Host smart-935b37ce-e6ac-4535-83a9-0d068252f942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926399307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2926399307
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2098449562
Short name T393
Test name
Test status
Simulation time 81793076739 ps
CPU time 1449.91 seconds
Started Mar 07 01:04:19 PM PST 24
Finished Mar 07 01:28:30 PM PST 24
Peak memory 228792 kb
Host smart-4db94004-2328-44cb-bae0-8754971aeb36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098449562 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2098449562
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.56308771
Short name T381
Test name
Test status
Simulation time 279168678 ps
CPU time 1.26 seconds
Started Mar 07 01:04:10 PM PST 24
Finished Mar 07 01:04:12 PM PST 24
Peak memory 199624 kb
Host smart-24bc9d79-1cfb-400a-81cd-44d2e3fa9000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56308771 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.hmac_test_hmac_vectors.56308771
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2652944624
Short name T283
Test name
Test status
Simulation time 7684749954 ps
CPU time 419.25 seconds
Started Mar 07 01:04:08 PM PST 24
Finished Mar 07 01:11:08 PM PST 24
Peak memory 200012 kb
Host smart-1688b9d0-0cec-485a-8430-29899d867deb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652944624 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.2652944624
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2126095743
Short name T97
Test name
Test status
Simulation time 564516805 ps
CPU time 3.41 seconds
Started Mar 07 01:04:08 PM PST 24
Finished Mar 07 01:04:12 PM PST 24
Peak memory 199752 kb
Host smart-0ca1117b-6c99-4fe1-bcd5-6a5f6d1d06ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126095743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2126095743
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4113682026
Short name T476
Test name
Test status
Simulation time 66950552 ps
CPU time 0.55 seconds
Started Mar 07 01:04:18 PM PST 24
Finished Mar 07 01:04:19 PM PST 24
Peak memory 194272 kb
Host smart-1dadbada-127a-4f25-bd1f-3257ef3df5d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113682026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4113682026
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3308920055
Short name T540
Test name
Test status
Simulation time 4073485478 ps
CPU time 37.36 seconds
Started Mar 07 01:04:21 PM PST 24
Finished Mar 07 01:04:58 PM PST 24
Peak memory 216360 kb
Host smart-566116e5-28ae-4316-8e5c-1395322b9c30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308920055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3308920055
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3581840572
Short name T338
Test name
Test status
Simulation time 2310325673 ps
CPU time 12.75 seconds
Started Mar 07 01:04:19 PM PST 24
Finished Mar 07 01:04:32 PM PST 24
Peak memory 199904 kb
Host smart-bd7c891a-e842-4281-bcd1-e0a68bece660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581840572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3581840572
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.325732965
Short name T91
Test name
Test status
Simulation time 2055557874 ps
CPU time 91.71 seconds
Started Mar 07 01:04:17 PM PST 24
Finished Mar 07 01:05:50 PM PST 24
Peak memory 199872 kb
Host smart-77ec83e7-8b89-4053-8ab7-bd5997ec675e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325732965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.325732965
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3002067706
Short name T579
Test name
Test status
Simulation time 44696839282 ps
CPU time 94.77 seconds
Started Mar 07 01:04:18 PM PST 24
Finished Mar 07 01:05:53 PM PST 24
Peak memory 200040 kb
Host smart-35435e93-28ef-4c73-a96b-3c67cfb582b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002067706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3002067706
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.680943874
Short name T147
Test name
Test status
Simulation time 6664587360 ps
CPU time 103.05 seconds
Started Mar 07 01:04:25 PM PST 24
Finished Mar 07 01:06:08 PM PST 24
Peak memory 199972 kb
Host smart-9e64961d-03fb-40f9-8e69-d9a06eaafc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680943874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.680943874
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1049865513
Short name T137
Test name
Test status
Simulation time 66021647 ps
CPU time 0.98 seconds
Started Mar 07 01:04:21 PM PST 24
Finished Mar 07 01:04:23 PM PST 24
Peak memory 198000 kb
Host smart-22cb9a89-7bd2-4e4a-ab09-03b28c9b7e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049865513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1049865513
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3038473233
Short name T527
Test name
Test status
Simulation time 127481138 ps
CPU time 1.23 seconds
Started Mar 07 01:04:18 PM PST 24
Finished Mar 07 01:04:20 PM PST 24
Peak memory 199472 kb
Host smart-262ef2f7-101c-48f2-9314-18f8a00c681d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038473233 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3038473233
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2198664335
Short name T454
Test name
Test status
Simulation time 63998798877 ps
CPU time 396.01 seconds
Started Mar 07 01:04:18 PM PST 24
Finished Mar 07 01:10:55 PM PST 24
Peak memory 200048 kb
Host smart-2f82a34c-d3a5-4daa-9b7b-e5d75d890888
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198664335 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.2198664335
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.96781928
Short name T427
Test name
Test status
Simulation time 33450877 ps
CPU time 1.7 seconds
Started Mar 07 01:04:16 PM PST 24
Finished Mar 07 01:04:18 PM PST 24
Peak memory 199900 kb
Host smart-2d36e0de-878e-4850-86d0-42d2154ad404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96781928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.96781928
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.535235629
Short name T501
Test name
Test status
Simulation time 22221781 ps
CPU time 0.57 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:02:12 PM PST 24
Peak memory 195312 kb
Host smart-914fac52-7fa5-4d94-a5a3-6184bb230340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535235629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.535235629
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3686435472
Short name T334
Test name
Test status
Simulation time 1844378369 ps
CPU time 67.16 seconds
Started Mar 07 01:02:13 PM PST 24
Finished Mar 07 01:03:20 PM PST 24
Peak memory 218336 kb
Host smart-dc0fa085-3c4d-480f-8b92-800119aa9fc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686435472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3686435472
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.557712172
Short name T292
Test name
Test status
Simulation time 3708674355 ps
CPU time 101.4 seconds
Started Mar 07 01:02:27 PM PST 24
Finished Mar 07 01:04:09 PM PST 24
Peak memory 199744 kb
Host smart-09ab454f-b7a6-43e4-b8e2-ef423843996a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=557712172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.557712172
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2212042599
Short name T435
Test name
Test status
Simulation time 59795482825 ps
CPU time 174.87 seconds
Started Mar 07 01:02:08 PM PST 24
Finished Mar 07 01:05:03 PM PST 24
Peak memory 199972 kb
Host smart-c2920d5b-7def-474b-bfc5-b92f978cf653
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212042599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2212042599
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1203079912
Short name T82
Test name
Test status
Simulation time 8715983438 ps
CPU time 58.48 seconds
Started Mar 07 01:02:07 PM PST 24
Finished Mar 07 01:03:06 PM PST 24
Peak memory 199980 kb
Host smart-f7926a6e-e887-43a5-88d8-085421f83a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203079912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1203079912
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.999517129
Short name T36
Test name
Test status
Simulation time 167660980 ps
CPU time 1 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:02:12 PM PST 24
Peak memory 219388 kb
Host smart-f5d3c949-47ec-4e33-a2aa-85eda3fb85d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999517129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.999517129
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3239918350
Short name T47
Test name
Test status
Simulation time 1155903480 ps
CPU time 5.08 seconds
Started Mar 07 01:02:22 PM PST 24
Finished Mar 07 01:02:27 PM PST 24
Peak memory 199788 kb
Host smart-297752a4-d8f1-445c-95d2-d722d82bc5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239918350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3239918350
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.691166955
Short name T337
Test name
Test status
Simulation time 154546057 ps
CPU time 1.24 seconds
Started Mar 07 01:02:06 PM PST 24
Finished Mar 07 01:02:08 PM PST 24
Peak memory 199868 kb
Host smart-634c5b23-03e9-47df-b8fa-3b3444344ed5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691166955 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.691166955
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.304344929
Short name T252
Test name
Test status
Simulation time 38492845 ps
CPU time 0.99 seconds
Started Mar 07 01:02:15 PM PST 24
Finished Mar 07 01:02:16 PM PST 24
Peak memory 197976 kb
Host smart-40e90771-9599-466b-b2ce-838402dd0675
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304344929 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_hmac_vectors.304344929
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1270108788
Short name T140
Test name
Test status
Simulation time 40535224428 ps
CPU time 507.99 seconds
Started Mar 07 01:02:06 PM PST 24
Finished Mar 07 01:10:34 PM PST 24
Peak memory 200088 kb
Host smart-7019391f-3bc2-44ee-885f-f6aa3b69caa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270108788 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1270108788
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.506715819
Short name T588
Test name
Test status
Simulation time 8889280674 ps
CPU time 59.53 seconds
Started Mar 07 01:02:10 PM PST 24
Finished Mar 07 01:03:10 PM PST 24
Peak memory 200000 kb
Host smart-8f9e7099-a6ab-4dd0-98d4-821c5a95204d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506715819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.506715819
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3758279410
Short name T437
Test name
Test status
Simulation time 18422025 ps
CPU time 0.56 seconds
Started Mar 07 01:04:20 PM PST 24
Finished Mar 07 01:04:20 PM PST 24
Peak memory 195244 kb
Host smart-30db2a96-42d7-40b0-ad5d-4805ec98826a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758279410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3758279410
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3388979235
Short name T57
Test name
Test status
Simulation time 3586942204 ps
CPU time 10.95 seconds
Started Mar 07 01:04:19 PM PST 24
Finished Mar 07 01:04:30 PM PST 24
Peak memory 199812 kb
Host smart-9d40088a-826b-47a3-ba42-3f981c72a8d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388979235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3388979235
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1119789427
Short name T237
Test name
Test status
Simulation time 4686907749 ps
CPU time 47.85 seconds
Started Mar 07 01:04:21 PM PST 24
Finished Mar 07 01:05:09 PM PST 24
Peak memory 199984 kb
Host smart-e592eab9-b3a5-44f2-a6cd-df1f050378b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119789427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1119789427
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.4010020266
Short name T368
Test name
Test status
Simulation time 16335084760 ps
CPU time 49.5 seconds
Started Mar 07 01:04:22 PM PST 24
Finished Mar 07 01:05:12 PM PST 24
Peak memory 200020 kb
Host smart-9d55c347-883f-4769-9fbe-2d6b1106d068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010020266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.4010020266
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3718145096
Short name T503
Test name
Test status
Simulation time 28048891157 ps
CPU time 69.73 seconds
Started Mar 07 01:04:18 PM PST 24
Finished Mar 07 01:05:28 PM PST 24
Peak memory 200056 kb
Host smart-0df1a0ab-c279-4109-b497-72ee50908458
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718145096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3718145096
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2094312387
Short name T306
Test name
Test status
Simulation time 5166556456 ps
CPU time 70.02 seconds
Started Mar 07 01:04:20 PM PST 24
Finished Mar 07 01:05:30 PM PST 24
Peak memory 199964 kb
Host smart-bc1b41be-9210-4b60-88b2-002322ce60ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094312387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2094312387
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.314393075
Short name T184
Test name
Test status
Simulation time 1635464706 ps
CPU time 4.58 seconds
Started Mar 07 01:04:19 PM PST 24
Finished Mar 07 01:04:24 PM PST 24
Peak memory 199876 kb
Host smart-e0c7df6c-cc48-45fe-b7fa-5658f12d0c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314393075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.314393075
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1630780730
Short name T333
Test name
Test status
Simulation time 49458652236 ps
CPU time 882.82 seconds
Started Mar 07 01:04:17 PM PST 24
Finished Mar 07 01:19:01 PM PST 24
Peak memory 200068 kb
Host smart-aa7839ae-0e5b-4db3-8e27-d4541c5db266
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630780730 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1630780730
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.4123617914
Short name T186
Test name
Test status
Simulation time 245015281 ps
CPU time 1.26 seconds
Started Mar 07 01:04:23 PM PST 24
Finished Mar 07 01:04:25 PM PST 24
Peak memory 199344 kb
Host smart-4b996ce9-942d-4a11-8870-f187bc94cca3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123617914 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.4123617914
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3493611575
Short name T242
Test name
Test status
Simulation time 25325142841 ps
CPU time 447.49 seconds
Started Mar 07 01:04:22 PM PST 24
Finished Mar 07 01:11:49 PM PST 24
Peak memory 200024 kb
Host smart-a3933866-efd9-4c36-aa14-b7f2c70d7839
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493611575 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3493611575
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2951028831
Short name T144
Test name
Test status
Simulation time 5837759607 ps
CPU time 28.44 seconds
Started Mar 07 01:04:25 PM PST 24
Finished Mar 07 01:04:54 PM PST 24
Peak memory 199944 kb
Host smart-468e91c7-45d3-4667-a06d-288cafd83b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951028831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2951028831
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2817502278
Short name T284
Test name
Test status
Simulation time 29900447 ps
CPU time 0.58 seconds
Started Mar 07 01:04:30 PM PST 24
Finished Mar 07 01:04:32 PM PST 24
Peak memory 195324 kb
Host smart-6cf3d9bf-27b4-4926-9dc1-bd9af671df69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817502278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2817502278
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3244345373
Short name T367
Test name
Test status
Simulation time 3791637142 ps
CPU time 36.14 seconds
Started Mar 07 01:04:18 PM PST 24
Finished Mar 07 01:04:55 PM PST 24
Peak memory 226796 kb
Host smart-7a09fae7-f4d0-4d6b-a795-92f86c3fcca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244345373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3244345373
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3691397458
Short name T593
Test name
Test status
Simulation time 2705492548 ps
CPU time 26.85 seconds
Started Mar 07 01:04:17 PM PST 24
Finished Mar 07 01:04:44 PM PST 24
Peak memory 200000 kb
Host smart-fb8024e9-2c79-44ea-b3bd-6e379b0257db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691397458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3691397458
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3733830612
Short name T143
Test name
Test status
Simulation time 942910174 ps
CPU time 60.33 seconds
Started Mar 07 01:04:20 PM PST 24
Finished Mar 07 01:05:20 PM PST 24
Peak memory 199800 kb
Host smart-966ad31e-508d-473d-a792-e812b1fa6084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733830612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3733830612
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1473868324
Short name T51
Test name
Test status
Simulation time 10743936430 ps
CPU time 47.87 seconds
Started Mar 07 01:04:18 PM PST 24
Finished Mar 07 01:05:07 PM PST 24
Peak memory 199992 kb
Host smart-4afee45e-901d-4394-aa47-0e8d241e3d71
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473868324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1473868324
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.488658127
Short name T251
Test name
Test status
Simulation time 987638012 ps
CPU time 53.46 seconds
Started Mar 07 01:04:17 PM PST 24
Finished Mar 07 01:05:11 PM PST 24
Peak memory 199872 kb
Host smart-5e1212d4-121f-418d-b9fd-cee0e3a27fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488658127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.488658127
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.610179355
Short name T136
Test name
Test status
Simulation time 31110493 ps
CPU time 0.68 seconds
Started Mar 07 01:04:21 PM PST 24
Finished Mar 07 01:04:22 PM PST 24
Peak memory 196600 kb
Host smart-a929bf13-0e72-41b1-b34b-544e02d2dece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610179355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.610179355
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1705115759
Short name T458
Test name
Test status
Simulation time 50286706494 ps
CPU time 714.03 seconds
Started Mar 07 01:04:19 PM PST 24
Finished Mar 07 01:16:13 PM PST 24
Peak memory 208272 kb
Host smart-ff13426d-a941-40f3-aa71-88a7aa97e984
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705115759 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1705115759
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3528920269
Short name T386
Test name
Test status
Simulation time 139550022 ps
CPU time 0.99 seconds
Started Mar 07 01:04:20 PM PST 24
Finished Mar 07 01:04:21 PM PST 24
Peak memory 198052 kb
Host smart-4c49a2a9-428f-4691-ab9e-4f2c9206fe5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528920269 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3528920269
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.690205025
Short name T215
Test name
Test status
Simulation time 7177766370 ps
CPU time 385.3 seconds
Started Mar 07 01:04:20 PM PST 24
Finished Mar 07 01:10:45 PM PST 24
Peak memory 199988 kb
Host smart-acc4b432-be49-44ae-9dbb-aaff94c841ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690205025 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.690205025
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1019820665
Short name T566
Test name
Test status
Simulation time 5892904495 ps
CPU time 75.3 seconds
Started Mar 07 01:04:19 PM PST 24
Finished Mar 07 01:05:35 PM PST 24
Peak memory 199892 kb
Host smart-aa1a04fc-287c-43ff-aae2-15a730f36b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019820665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1019820665
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2518895818
Short name T497
Test name
Test status
Simulation time 14783506 ps
CPU time 0.58 seconds
Started Mar 07 01:04:29 PM PST 24
Finished Mar 07 01:04:32 PM PST 24
Peak memory 194240 kb
Host smart-c67721ec-bdee-4123-8417-dba9a1bfb27a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518895818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2518895818
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.515497941
Short name T20
Test name
Test status
Simulation time 99534558 ps
CPU time 3.86 seconds
Started Mar 07 01:04:26 PM PST 24
Finished Mar 07 01:04:30 PM PST 24
Peak memory 199880 kb
Host smart-f66045b3-14c8-441b-8e67-2d9ec1e21a76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515497941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.515497941
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3124358401
Short name T164
Test name
Test status
Simulation time 9605501256 ps
CPU time 38.48 seconds
Started Mar 07 01:04:28 PM PST 24
Finished Mar 07 01:05:10 PM PST 24
Peak memory 199968 kb
Host smart-43153895-3c04-4892-9670-48eb19602d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124358401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3124358401
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3358311357
Short name T203
Test name
Test status
Simulation time 2927002742 ps
CPU time 41.43 seconds
Started Mar 07 01:04:28 PM PST 24
Finished Mar 07 01:05:12 PM PST 24
Peak memory 199856 kb
Host smart-7311d382-b1d6-47c2-a729-eeab124c3fda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358311357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3358311357
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3256556086
Short name T567
Test name
Test status
Simulation time 15066632150 ps
CPU time 131.3 seconds
Started Mar 07 01:04:35 PM PST 24
Finished Mar 07 01:06:48 PM PST 24
Peak memory 199916 kb
Host smart-4a25a5f3-b877-452f-9beb-777941acfbe2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256556086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3256556086
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3705599377
Short name T273
Test name
Test status
Simulation time 86065545755 ps
CPU time 115.14 seconds
Started Mar 07 01:04:35 PM PST 24
Finished Mar 07 01:06:32 PM PST 24
Peak memory 199888 kb
Host smart-e96253c6-6fdb-43c9-be75-3faabcb92673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705599377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3705599377
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3429127744
Short name T525
Test name
Test status
Simulation time 1394842399 ps
CPU time 6.03 seconds
Started Mar 07 01:04:30 PM PST 24
Finished Mar 07 01:04:37 PM PST 24
Peak memory 199832 kb
Host smart-0f29be48-e81a-427f-b843-01e18cab52ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429127744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3429127744
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.360664995
Short name T335
Test name
Test status
Simulation time 1849561031 ps
CPU time 44.85 seconds
Started Mar 07 01:04:28 PM PST 24
Finished Mar 07 01:05:16 PM PST 24
Peak memory 208108 kb
Host smart-4ed4896d-8108-4408-a7c0-f37f60db9a02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360664995 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.360664995
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.3782256111
Short name T77
Test name
Test status
Simulation time 29096249673 ps
CPU time 322.62 seconds
Started Mar 07 01:04:29 PM PST 24
Finished Mar 07 01:09:54 PM PST 24
Peak memory 249200 kb
Host smart-e850ea73-a5cc-4006-adab-4928508f9e33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782256111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.3782256111
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.51276107
Short name T535
Test name
Test status
Simulation time 31758713 ps
CPU time 1.17 seconds
Started Mar 07 01:04:28 PM PST 24
Finished Mar 07 01:04:32 PM PST 24
Peak memory 199084 kb
Host smart-8532f083-1049-4235-95d5-fcfa17ce3338
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51276107 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.hmac_test_hmac_vectors.51276107
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2941263366
Short name T521
Test name
Test status
Simulation time 134442450905 ps
CPU time 458.3 seconds
Started Mar 07 01:04:32 PM PST 24
Finished Mar 07 01:12:11 PM PST 24
Peak memory 200012 kb
Host smart-3e803d3d-c514-40ca-bd33-2285d181d555
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941263366 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2941263366
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3911709434
Short name T531
Test name
Test status
Simulation time 11986499194 ps
CPU time 43.83 seconds
Started Mar 07 01:04:27 PM PST 24
Finished Mar 07 01:05:11 PM PST 24
Peak memory 199952 kb
Host smart-646f2c5d-c472-471e-8ab9-30fe49af464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911709434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3911709434
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1492995629
Short name T514
Test name
Test status
Simulation time 16364974 ps
CPU time 0.55 seconds
Started Mar 07 01:04:26 PM PST 24
Finished Mar 07 01:04:27 PM PST 24
Peak memory 195348 kb
Host smart-a14fcf6c-f986-4487-ba9c-40551e41295f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492995629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1492995629
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3558784334
Short name T575
Test name
Test status
Simulation time 2432095478 ps
CPU time 52.61 seconds
Started Mar 07 01:04:35 PM PST 24
Finished Mar 07 01:05:29 PM PST 24
Peak memory 220192 kb
Host smart-3c6d9b26-8ea4-4773-b0c5-0e701f4439aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3558784334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3558784334
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2764031245
Short name T383
Test name
Test status
Simulation time 1808081886 ps
CPU time 37.45 seconds
Started Mar 07 01:04:28 PM PST 24
Finished Mar 07 01:05:09 PM PST 24
Peak memory 199892 kb
Host smart-e2597285-5fbf-4901-9cc3-cfa232695b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764031245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2764031245
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3933459770
Short name T480
Test name
Test status
Simulation time 6556933861 ps
CPU time 107.82 seconds
Started Mar 07 01:04:26 PM PST 24
Finished Mar 07 01:06:15 PM PST 24
Peak memory 199956 kb
Host smart-593483dc-431c-4bac-8139-2f260affb93c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933459770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3933459770
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3798974297
Short name T416
Test name
Test status
Simulation time 973815923 ps
CPU time 24.67 seconds
Started Mar 07 01:04:28 PM PST 24
Finished Mar 07 01:04:56 PM PST 24
Peak memory 199756 kb
Host smart-d610c9cb-da0e-453d-ad48-4bedddc1d33c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798974297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3798974297
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3905231947
Short name T522
Test name
Test status
Simulation time 4763932165 ps
CPU time 27.85 seconds
Started Mar 07 01:04:32 PM PST 24
Finished Mar 07 01:05:01 PM PST 24
Peak memory 199944 kb
Host smart-ab3c4074-9a44-4ffd-8018-3b9e38aa6433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905231947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3905231947
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3074302225
Short name T175
Test name
Test status
Simulation time 165103894 ps
CPU time 5.31 seconds
Started Mar 07 01:04:29 PM PST 24
Finished Mar 07 01:04:37 PM PST 24
Peak memory 199880 kb
Host smart-75839fb8-7d3f-47e8-9b6f-3b8e116cda48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074302225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3074302225
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3616126638
Short name T79
Test name
Test status
Simulation time 246688800394 ps
CPU time 830.57 seconds
Started Mar 07 01:04:29 PM PST 24
Finished Mar 07 01:18:22 PM PST 24
Peak memory 241044 kb
Host smart-47e0e5e2-53a1-4630-af81-7c345f5d68c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616126638 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3616126638
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1403952739
Short name T390
Test name
Test status
Simulation time 29922345 ps
CPU time 1.01 seconds
Started Mar 07 01:04:28 PM PST 24
Finished Mar 07 01:04:32 PM PST 24
Peak memory 198808 kb
Host smart-59165dd7-1ed2-4144-9bee-7560c3f9ec10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403952739 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1403952739
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1862824308
Short name T420
Test name
Test status
Simulation time 240293656955 ps
CPU time 490.99 seconds
Started Mar 07 01:04:31 PM PST 24
Finished Mar 07 01:12:42 PM PST 24
Peak memory 200012 kb
Host smart-f4604e50-3d42-456a-80a3-ee0c2de0225a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862824308 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.1862824308
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4282487718
Short name T208
Test name
Test status
Simulation time 13347430052 ps
CPU time 64.15 seconds
Started Mar 07 01:04:35 PM PST 24
Finished Mar 07 01:05:41 PM PST 24
Peak memory 199896 kb
Host smart-f883511c-6169-4b6e-b0ab-cb8f699a7ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282487718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4282487718
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.915070876
Short name T413
Test name
Test status
Simulation time 26161604 ps
CPU time 0.59 seconds
Started Mar 07 01:04:38 PM PST 24
Finished Mar 07 01:04:39 PM PST 24
Peak memory 195224 kb
Host smart-932bb39c-f80e-4aac-a8ec-27b5618e6cfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915070876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.915070876
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.706508073
Short name T481
Test name
Test status
Simulation time 410066673 ps
CPU time 13.27 seconds
Started Mar 07 01:04:26 PM PST 24
Finished Mar 07 01:04:40 PM PST 24
Peak memory 199868 kb
Host smart-07de1a52-c876-4989-b99b-64a7da21cbba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706508073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.706508073
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3649895064
Short name T264
Test name
Test status
Simulation time 356329951 ps
CPU time 5.63 seconds
Started Mar 07 01:04:29 PM PST 24
Finished Mar 07 01:04:37 PM PST 24
Peak memory 199876 kb
Host smart-910ed108-11b7-45bb-b38c-dfcd14bd79ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649895064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3649895064
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2826645006
Short name T152
Test name
Test status
Simulation time 6221972934 ps
CPU time 86.35 seconds
Started Mar 07 01:04:30 PM PST 24
Finished Mar 07 01:05:58 PM PST 24
Peak memory 199968 kb
Host smart-4469ece6-a568-4acb-98dd-39f187d866ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826645006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2826645006
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3189966375
Short name T603
Test name
Test status
Simulation time 3312852163 ps
CPU time 69.63 seconds
Started Mar 07 01:04:28 PM PST 24
Finished Mar 07 01:05:41 PM PST 24
Peak memory 199908 kb
Host smart-5605fe6f-cf30-425a-aa3f-68b3a967d9ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189966375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3189966375
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3526965958
Short name T479
Test name
Test status
Simulation time 8767852005 ps
CPU time 121.84 seconds
Started Mar 07 01:04:27 PM PST 24
Finished Mar 07 01:06:29 PM PST 24
Peak memory 199988 kb
Host smart-d1a2a121-9b42-4e9c-a0e4-1fb1dfd5d3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526965958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3526965958
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3391267807
Short name T412
Test name
Test status
Simulation time 113510551 ps
CPU time 3.8 seconds
Started Mar 07 01:04:28 PM PST 24
Finished Mar 07 01:04:35 PM PST 24
Peak memory 199828 kb
Host smart-5e84e6eb-f004-4dd8-8c2d-cebd74ea31cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391267807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3391267807
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2427382159
Short name T388
Test name
Test status
Simulation time 132881090 ps
CPU time 1.17 seconds
Started Mar 07 01:04:29 PM PST 24
Finished Mar 07 01:04:33 PM PST 24
Peak memory 199320 kb
Host smart-714d3730-684e-4ca3-a5a5-c8c1019eca28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427382159 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2427382159
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3739489170
Short name T220
Test name
Test status
Simulation time 31650631786 ps
CPU time 524.92 seconds
Started Mar 07 01:04:26 PM PST 24
Finished Mar 07 01:13:12 PM PST 24
Peak memory 199976 kb
Host smart-04d9746d-f38b-4b9c-9c73-787c24d878e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739489170 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.3739489170
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2316319155
Short name T282
Test name
Test status
Simulation time 1467267901 ps
CPU time 64.99 seconds
Started Mar 07 01:04:38 PM PST 24
Finished Mar 07 01:05:44 PM PST 24
Peak memory 199856 kb
Host smart-35e32071-dc07-4671-ab8e-476aef0f5cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316319155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2316319155
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4109787263
Short name T206
Test name
Test status
Simulation time 12391368 ps
CPU time 0.56 seconds
Started Mar 07 01:04:39 PM PST 24
Finished Mar 07 01:04:40 PM PST 24
Peak memory 194284 kb
Host smart-e442ce9a-95b4-4823-86b0-cc2663b4f778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109787263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4109787263
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2772288093
Short name T165
Test name
Test status
Simulation time 1126051747 ps
CPU time 36.35 seconds
Started Mar 07 01:04:39 PM PST 24
Finished Mar 07 01:05:16 PM PST 24
Peak memory 210060 kb
Host smart-c21f832e-40e3-4029-84da-b871e7f68248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772288093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2772288093
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.921256671
Short name T492
Test name
Test status
Simulation time 2917182061 ps
CPU time 39.84 seconds
Started Mar 07 01:04:40 PM PST 24
Finished Mar 07 01:05:20 PM PST 24
Peak memory 199884 kb
Host smart-c3a7b5eb-89ef-4671-8636-faee85a6984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921256671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.921256671
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1554963290
Short name T43
Test name
Test status
Simulation time 5130471709 ps
CPU time 78.12 seconds
Started Mar 07 01:04:38 PM PST 24
Finished Mar 07 01:05:57 PM PST 24
Peak memory 200048 kb
Host smart-2bf41a0b-cf09-460d-b93e-d6b07394c78c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1554963290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1554963290
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2706078563
Short name T179
Test name
Test status
Simulation time 19784354885 ps
CPU time 40.98 seconds
Started Mar 07 01:04:37 PM PST 24
Finished Mar 07 01:05:18 PM PST 24
Peak memory 200000 kb
Host smart-7e3da4aa-a8c1-4bc8-a04d-fe75248eac43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706078563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2706078563
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1259479173
Short name T315
Test name
Test status
Simulation time 1070850331 ps
CPU time 63.35 seconds
Started Mar 07 01:04:41 PM PST 24
Finished Mar 07 01:05:44 PM PST 24
Peak memory 199856 kb
Host smart-799c85b0-91ca-4e0a-b69d-5df9a161a6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259479173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1259479173
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2439857797
Short name T46
Test name
Test status
Simulation time 204204900 ps
CPU time 1.88 seconds
Started Mar 07 01:04:38 PM PST 24
Finished Mar 07 01:04:41 PM PST 24
Peak memory 199876 kb
Host smart-4d688246-335a-4b7c-a679-56a7ff2056c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439857797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2439857797
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3586538789
Short name T226
Test name
Test status
Simulation time 89957903792 ps
CPU time 105.28 seconds
Started Mar 07 01:04:42 PM PST 24
Finished Mar 07 01:06:28 PM PST 24
Peak memory 199948 kb
Host smart-55762f6e-43f2-408b-956e-0c16a20d75df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586538789 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3586538789
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2001863982
Short name T194
Test name
Test status
Simulation time 63722088 ps
CPU time 1.21 seconds
Started Mar 07 01:04:40 PM PST 24
Finished Mar 07 01:04:42 PM PST 24
Peak memory 199604 kb
Host smart-d776da75-4287-4c79-b29d-de51f11593f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001863982 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2001863982
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3671487782
Short name T270
Test name
Test status
Simulation time 243615159304 ps
CPU time 535.44 seconds
Started Mar 07 01:04:38 PM PST 24
Finished Mar 07 01:13:34 PM PST 24
Peak memory 199992 kb
Host smart-8c0a338c-8942-44ea-80ba-5ae2ec689449
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671487782 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.3671487782
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2997998863
Short name T207
Test name
Test status
Simulation time 1757529390 ps
CPU time 68.8 seconds
Started Mar 07 01:04:39 PM PST 24
Finished Mar 07 01:05:48 PM PST 24
Peak memory 199896 kb
Host smart-3d66399f-10e9-410d-bcbf-6c7655f62dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997998863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2997998863
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.167843871
Short name T515
Test name
Test status
Simulation time 31047706 ps
CPU time 0.56 seconds
Started Mar 07 01:04:47 PM PST 24
Finished Mar 07 01:04:48 PM PST 24
Peak memory 194264 kb
Host smart-55305807-796e-497d-808a-af6e94d3fc3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167843871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.167843871
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.449906236
Short name T573
Test name
Test status
Simulation time 216643170 ps
CPU time 7.43 seconds
Started Mar 07 01:04:49 PM PST 24
Finished Mar 07 01:04:57 PM PST 24
Peak memory 199880 kb
Host smart-8bdada16-26af-41f9-b8ab-40e73ea29005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449906236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.449906236
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2322748539
Short name T224
Test name
Test status
Simulation time 1259648843 ps
CPU time 8.49 seconds
Started Mar 07 01:04:47 PM PST 24
Finished Mar 07 01:04:56 PM PST 24
Peak memory 199880 kb
Host smart-60bc713d-e055-482f-b71e-e01497f284c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322748539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2322748539
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2827187661
Short name T441
Test name
Test status
Simulation time 8015992687 ps
CPU time 121.62 seconds
Started Mar 07 01:04:49 PM PST 24
Finished Mar 07 01:06:51 PM PST 24
Peak memory 200012 kb
Host smart-9af8e072-9a7e-4616-b27a-4b60c3dcd28f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827187661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2827187661
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1831610597
Short name T405
Test name
Test status
Simulation time 22836514833 ps
CPU time 104.45 seconds
Started Mar 07 01:04:52 PM PST 24
Finished Mar 07 01:06:39 PM PST 24
Peak memory 199900 kb
Host smart-692b70cc-5519-4575-af52-b198ce0f6692
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831610597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1831610597
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3156898961
Short name T39
Test name
Test status
Simulation time 1362826201 ps
CPU time 81.6 seconds
Started Mar 07 01:04:38 PM PST 24
Finished Mar 07 01:06:00 PM PST 24
Peak memory 199856 kb
Host smart-b47b0cb0-eade-4992-9cd8-cc1d4031e46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156898961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3156898961
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.4068101386
Short name T321
Test name
Test status
Simulation time 104391286 ps
CPU time 2.84 seconds
Started Mar 07 01:04:38 PM PST 24
Finished Mar 07 01:04:42 PM PST 24
Peak memory 199828 kb
Host smart-de5a22b2-268e-4f90-a795-a5f44c553897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068101386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.4068101386
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1666378530
Short name T571
Test name
Test status
Simulation time 8416392073 ps
CPU time 83.79 seconds
Started Mar 07 01:04:47 PM PST 24
Finished Mar 07 01:06:11 PM PST 24
Peak memory 247520 kb
Host smart-5e7d27b7-0ff9-48e9-a6fd-9ce9e0c72927
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666378530 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1666378530
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.4206015502
Short name T359
Test name
Test status
Simulation time 29751621 ps
CPU time 1.01 seconds
Started Mar 07 01:04:50 PM PST 24
Finished Mar 07 01:04:55 PM PST 24
Peak memory 198440 kb
Host smart-c171c274-44e1-469e-95a7-e179fdb7a138
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206015502 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.4206015502
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1604792615
Short name T86
Test name
Test status
Simulation time 25012246178 ps
CPU time 452.53 seconds
Started Mar 07 01:04:48 PM PST 24
Finished Mar 07 01:12:21 PM PST 24
Peak memory 200012 kb
Host smart-1ca0af88-44bb-4457-9a66-a1c465314517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604792615 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1604792615
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2234302495
Short name T168
Test name
Test status
Simulation time 3144925532 ps
CPU time 32.5 seconds
Started Mar 07 01:04:47 PM PST 24
Finished Mar 07 01:05:20 PM PST 24
Peak memory 199928 kb
Host smart-8c228888-498f-4219-b608-e9004df4db25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234302495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2234302495
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3411837936
Short name T277
Test name
Test status
Simulation time 39926177 ps
CPU time 0.57 seconds
Started Mar 07 01:04:49 PM PST 24
Finished Mar 07 01:04:50 PM PST 24
Peak memory 194848 kb
Host smart-aeb54eb1-b3ae-465e-a310-e96fe64f660e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411837936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3411837936
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2523475736
Short name T304
Test name
Test status
Simulation time 2234291678 ps
CPU time 48.92 seconds
Started Mar 07 01:04:47 PM PST 24
Finished Mar 07 01:05:36 PM PST 24
Peak memory 227660 kb
Host smart-c3cf1ee1-f9c6-4b90-bb16-6b117e435709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523475736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2523475736
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4281399559
Short name T550
Test name
Test status
Simulation time 2390744628 ps
CPU time 10.09 seconds
Started Mar 07 01:04:48 PM PST 24
Finished Mar 07 01:04:58 PM PST 24
Peak memory 199920 kb
Host smart-3289b616-bea6-4b53-ac01-22b44a01daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281399559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4281399559
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.49023809
Short name T431
Test name
Test status
Simulation time 253033086 ps
CPU time 14.3 seconds
Started Mar 07 01:04:51 PM PST 24
Finished Mar 07 01:05:09 PM PST 24
Peak memory 199860 kb
Host smart-c7f02268-94ea-492f-9b07-16f685f30e91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49023809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.49023809
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3742556940
Short name T563
Test name
Test status
Simulation time 213668608 ps
CPU time 11.12 seconds
Started Mar 07 01:04:48 PM PST 24
Finished Mar 07 01:04:59 PM PST 24
Peak memory 199964 kb
Host smart-bde58710-9c5e-4a53-b255-ae45cbf9fe13
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742556940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3742556940
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2519402761
Short name T62
Test name
Test status
Simulation time 1399550975 ps
CPU time 25.83 seconds
Started Mar 07 01:04:49 PM PST 24
Finished Mar 07 01:05:16 PM PST 24
Peak memory 199888 kb
Host smart-1e3ec482-77e6-44f5-b1df-a9a36502bbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519402761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2519402761
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.4125231382
Short name T172
Test name
Test status
Simulation time 550952644 ps
CPU time 4.36 seconds
Started Mar 07 01:04:51 PM PST 24
Finished Mar 07 01:04:59 PM PST 24
Peak memory 199884 kb
Host smart-8dc01ce9-f2d1-4c6d-9b81-a2b3794c7eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125231382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.4125231382
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4114257658
Short name T477
Test name
Test status
Simulation time 11262084205 ps
CPU time 164.27 seconds
Started Mar 07 01:04:52 PM PST 24
Finished Mar 07 01:07:39 PM PST 24
Peak memory 231536 kb
Host smart-17d6908c-5d00-4f95-b670-30f0ab422b95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114257658 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4114257658
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3444605461
Short name T94
Test name
Test status
Simulation time 29591989 ps
CPU time 1.16 seconds
Started Mar 07 01:04:50 PM PST 24
Finished Mar 07 01:04:52 PM PST 24
Peak memory 199532 kb
Host smart-de119360-47cd-426b-a7a1-6f6fed6738eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444605461 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3444605461
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1837060702
Short name T322
Test name
Test status
Simulation time 7518298302 ps
CPU time 409.06 seconds
Started Mar 07 01:04:51 PM PST 24
Finished Mar 07 01:11:43 PM PST 24
Peak memory 200016 kb
Host smart-764c6333-ae24-4f27-95cb-99bd7443d0e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837060702 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1837060702
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2551025873
Short name T580
Test name
Test status
Simulation time 5692607213 ps
CPU time 60.79 seconds
Started Mar 07 01:04:48 PM PST 24
Finished Mar 07 01:05:49 PM PST 24
Peak memory 199912 kb
Host smart-a425bdf4-c7bd-4472-b96b-8142036b4b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551025873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2551025873
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2704120768
Short name T25
Test name
Test status
Simulation time 10696277 ps
CPU time 0.58 seconds
Started Mar 07 01:04:51 PM PST 24
Finished Mar 07 01:04:55 PM PST 24
Peak memory 194136 kb
Host smart-167625f6-9f0e-4419-8a96-a6f42840fd10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704120768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2704120768
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3175801623
Short name T261
Test name
Test status
Simulation time 81637730 ps
CPU time 3.03 seconds
Started Mar 07 01:04:48 PM PST 24
Finished Mar 07 01:04:51 PM PST 24
Peak memory 199772 kb
Host smart-ce6fb690-452d-4339-8505-c7837a297881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175801623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3175801623
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1714367425
Short name T455
Test name
Test status
Simulation time 181973648 ps
CPU time 9.38 seconds
Started Mar 07 01:04:50 PM PST 24
Finished Mar 07 01:05:04 PM PST 24
Peak memory 199848 kb
Host smart-c9906d2c-62ff-4667-8842-2b31bb80a4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714367425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1714367425
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3505057508
Short name T324
Test name
Test status
Simulation time 5265662958 ps
CPU time 79.09 seconds
Started Mar 07 01:04:50 PM PST 24
Finished Mar 07 01:06:09 PM PST 24
Peak memory 200012 kb
Host smart-7ce8b7cf-d803-4986-adf1-74b4df1efe96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505057508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3505057508
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2052050381
Short name T155
Test name
Test status
Simulation time 1197014826 ps
CPU time 63.63 seconds
Started Mar 07 01:04:51 PM PST 24
Finished Mar 07 01:05:58 PM PST 24
Peak memory 199888 kb
Host smart-37ead3a1-c0ff-47de-be33-d0c8acbb6969
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052050381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2052050381
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1996639467
Short name T421
Test name
Test status
Simulation time 1821899009 ps
CPU time 36.91 seconds
Started Mar 07 01:04:48 PM PST 24
Finished Mar 07 01:05:25 PM PST 24
Peak memory 199860 kb
Host smart-3d5c13cd-d049-4e1d-901a-ca563dd62e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996639467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1996639467
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1666238667
Short name T319
Test name
Test status
Simulation time 68560134 ps
CPU time 0.63 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:04:59 PM PST 24
Peak memory 195728 kb
Host smart-d8bfb51e-f46c-43b9-84f9-2bd3e1c5feaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666238667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1666238667
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3739731363
Short name T78
Test name
Test status
Simulation time 85268260187 ps
CPU time 330.93 seconds
Started Mar 07 01:04:51 PM PST 24
Finished Mar 07 01:10:25 PM PST 24
Peak memory 224600 kb
Host smart-d8daf12d-97b0-4668-97a1-2771514782c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739731363 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3739731363
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.223369210
Short name T92
Test name
Test status
Simulation time 53126112074 ps
CPU time 1983.63 seconds
Started Mar 07 01:04:47 PM PST 24
Finished Mar 07 01:37:51 PM PST 24
Peak memory 226608 kb
Host smart-c86dd49e-2e20-4510-9f09-c660f975327b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223369210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.223369210
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1043076407
Short name T379
Test name
Test status
Simulation time 88671096 ps
CPU time 1.19 seconds
Started Mar 07 01:04:47 PM PST 24
Finished Mar 07 01:04:49 PM PST 24
Peak memory 199528 kb
Host smart-a07f75d3-ca3b-482d-841c-4f5acd2ac6e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043076407 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1043076407
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1093374291
Short name T534
Test name
Test status
Simulation time 11640671652 ps
CPU time 340.92 seconds
Started Mar 07 01:04:47 PM PST 24
Finished Mar 07 01:10:28 PM PST 24
Peak memory 200020 kb
Host smart-9e814363-5a27-40e8-9c46-0b06719f215b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093374291 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1093374291
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.105981666
Short name T265
Test name
Test status
Simulation time 9503835695 ps
CPU time 79.68 seconds
Started Mar 07 01:04:46 PM PST 24
Finished Mar 07 01:06:06 PM PST 24
Peak memory 199912 kb
Host smart-c6ff5e69-7f2b-44f0-aa25-7452123875e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105981666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.105981666
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1610888304
Short name T519
Test name
Test status
Simulation time 14238778 ps
CPU time 0.58 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:04:59 PM PST 24
Peak memory 194284 kb
Host smart-112a02cc-bdc2-4c9e-9e5f-7969a79ec559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610888304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1610888304
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.507681256
Short name T330
Test name
Test status
Simulation time 239547130 ps
CPU time 8.39 seconds
Started Mar 07 01:04:51 PM PST 24
Finished Mar 07 01:05:03 PM PST 24
Peak memory 199856 kb
Host smart-3046a8fe-e0a1-49fa-b344-188cf6fd9a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=507681256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.507681256
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.15344817
Short name T552
Test name
Test status
Simulation time 709714577 ps
CPU time 3 seconds
Started Mar 07 01:04:49 PM PST 24
Finished Mar 07 01:04:53 PM PST 24
Peak memory 199868 kb
Host smart-c71b1907-c378-4ff9-bf75-5437651f3fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15344817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.15344817
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2486159031
Short name T499
Test name
Test status
Simulation time 707608246 ps
CPU time 42.33 seconds
Started Mar 07 01:04:53 PM PST 24
Finished Mar 07 01:05:37 PM PST 24
Peak memory 199884 kb
Host smart-16da871f-1d29-4185-9020-db2e66b1543c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486159031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2486159031
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2822043350
Short name T153
Test name
Test status
Simulation time 21256892471 ps
CPU time 126.16 seconds
Started Mar 07 01:04:48 PM PST 24
Finished Mar 07 01:06:54 PM PST 24
Peak memory 199948 kb
Host smart-1f130062-3ede-4e23-8924-b6207ef78a83
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822043350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2822043350
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1487702439
Short name T485
Test name
Test status
Simulation time 2123934437 ps
CPU time 41.88 seconds
Started Mar 07 01:04:52 PM PST 24
Finished Mar 07 01:05:36 PM PST 24
Peak memory 199868 kb
Host smart-d3137156-2efb-4064-ae6c-33d6fa9bc164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487702439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1487702439
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3063225497
Short name T371
Test name
Test status
Simulation time 742747574 ps
CPU time 2.63 seconds
Started Mar 07 01:04:48 PM PST 24
Finished Mar 07 01:04:51 PM PST 24
Peak memory 199884 kb
Host smart-72941ded-3531-492b-81ff-097e4ece9afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063225497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3063225497
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2049808952
Short name T73
Test name
Test status
Simulation time 180420016983 ps
CPU time 1566.27 seconds
Started Mar 07 01:04:49 PM PST 24
Finished Mar 07 01:30:56 PM PST 24
Peak memory 200008 kb
Host smart-60646067-1399-4850-b91d-555c3cf7016b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049808952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2049808952
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.947164175
Short name T65
Test name
Test status
Simulation time 9839795061 ps
CPU time 512.15 seconds
Started Mar 07 01:04:52 PM PST 24
Finished Mar 07 01:13:26 PM PST 24
Peak memory 232860 kb
Host smart-22e2f9ec-5da2-47ae-b58f-9c55a25bd1a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947164175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.947164175
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1976309193
Short name T561
Test name
Test status
Simulation time 28727538 ps
CPU time 1.02 seconds
Started Mar 07 01:04:49 PM PST 24
Finished Mar 07 01:04:51 PM PST 24
Peak memory 198928 kb
Host smart-ad9e794c-c113-4a8e-b532-20dcac47c3f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976309193 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1976309193
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2175523250
Short name T288
Test name
Test status
Simulation time 156273822941 ps
CPU time 503.27 seconds
Started Mar 07 01:04:48 PM PST 24
Finished Mar 07 01:13:13 PM PST 24
Peak memory 200012 kb
Host smart-75e2abd8-283d-4475-83c1-442440e4ca1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175523250 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.2175523250
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3776094355
Short name T451
Test name
Test status
Simulation time 2042108623 ps
CPU time 69.42 seconds
Started Mar 07 01:04:49 PM PST 24
Finished Mar 07 01:05:59 PM PST 24
Peak memory 199864 kb
Host smart-c72715ee-0c29-4dab-8717-8d55c93b306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776094355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3776094355
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2217960510
Short name T496
Test name
Test status
Simulation time 185318315 ps
CPU time 0.54 seconds
Started Mar 07 01:02:23 PM PST 24
Finished Mar 07 01:02:23 PM PST 24
Peak memory 195268 kb
Host smart-3fee74ae-efcc-44ff-b921-a29389fde9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217960510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2217960510
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2611313695
Short name T345
Test name
Test status
Simulation time 533056602 ps
CPU time 21.05 seconds
Started Mar 07 01:02:09 PM PST 24
Finished Mar 07 01:02:30 PM PST 24
Peak memory 228640 kb
Host smart-d8e40afb-bb5a-474b-b7dd-5d20c6038b49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611313695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2611313695
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.295122309
Short name T355
Test name
Test status
Simulation time 1946836537 ps
CPU time 31.14 seconds
Started Mar 07 01:02:14 PM PST 24
Finished Mar 07 01:02:46 PM PST 24
Peak memory 199900 kb
Host smart-493bd86e-9871-45f7-b03f-7bcb7fdf081b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295122309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.295122309
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2089748926
Short name T377
Test name
Test status
Simulation time 108680154 ps
CPU time 0.63 seconds
Started Mar 07 01:02:08 PM PST 24
Finished Mar 07 01:02:09 PM PST 24
Peak memory 196600 kb
Host smart-3b87c404-d137-46ed-9cd5-721a156856ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089748926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2089748926
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.632815537
Short name T301
Test name
Test status
Simulation time 5814807861 ps
CPU time 150.95 seconds
Started Mar 07 01:02:15 PM PST 24
Finished Mar 07 01:04:46 PM PST 24
Peak memory 200000 kb
Host smart-84c7fc7a-0746-4a71-9c85-be850c1dcb11
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632815537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.632815537
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.238727845
Short name T71
Test name
Test status
Simulation time 11062188889 ps
CPU time 112.92 seconds
Started Mar 07 01:02:10 PM PST 24
Finished Mar 07 01:04:03 PM PST 24
Peak memory 199976 kb
Host smart-fef5477f-5c30-404b-83d3-7f6f124ffc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238727845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.238727845
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4076362352
Short name T35
Test name
Test status
Simulation time 412490348 ps
CPU time 0.95 seconds
Started Mar 07 01:02:21 PM PST 24
Finished Mar 07 01:02:22 PM PST 24
Peak memory 219440 kb
Host smart-af4117aa-299e-4cf9-bc5c-ebde6962d19e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076362352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4076362352
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.726950416
Short name T332
Test name
Test status
Simulation time 1650240527 ps
CPU time 6.02 seconds
Started Mar 07 01:02:18 PM PST 24
Finished Mar 07 01:02:24 PM PST 24
Peak memory 199692 kb
Host smart-141eccfd-746c-4ddd-afae-90e71f3efc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726950416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.726950416
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2932943837
Short name T408
Test name
Test status
Simulation time 52140289631 ps
CPU time 769.96 seconds
Started Mar 07 01:02:17 PM PST 24
Finished Mar 07 01:15:07 PM PST 24
Peak memory 217440 kb
Host smart-12637bcf-741f-45b8-a54b-578e52405882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932943837 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2932943837
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3280424808
Short name T286
Test name
Test status
Simulation time 54975027 ps
CPU time 0.96 seconds
Started Mar 07 01:02:14 PM PST 24
Finished Mar 07 01:02:15 PM PST 24
Peak memory 198924 kb
Host smart-ecf525a9-68c1-442a-b647-d65894cfeb14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280424808 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3280424808
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3971834566
Short name T185
Test name
Test status
Simulation time 137204699411 ps
CPU time 577.54 seconds
Started Mar 07 01:02:17 PM PST 24
Finished Mar 07 01:11:55 PM PST 24
Peak memory 200024 kb
Host smart-b8259fb2-47d2-4b9d-be9d-0291f602df16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971834566 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3971834566
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3561978865
Short name T255
Test name
Test status
Simulation time 2240018372 ps
CPU time 25.32 seconds
Started Mar 07 01:02:12 PM PST 24
Finished Mar 07 01:02:38 PM PST 24
Peak memory 199952 kb
Host smart-40c3b887-3489-4fdb-8fc6-0ace2134edfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561978865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3561978865
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.162478290
Short name T217
Test name
Test status
Simulation time 16090667 ps
CPU time 0.57 seconds
Started Mar 07 01:04:58 PM PST 24
Finished Mar 07 01:04:58 PM PST 24
Peak memory 194284 kb
Host smart-316013d5-564e-43bc-b28d-6165ba97186e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162478290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.162478290
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1685348707
Short name T246
Test name
Test status
Simulation time 1363834337 ps
CPU time 47.08 seconds
Started Mar 07 01:04:58 PM PST 24
Finished Mar 07 01:05:46 PM PST 24
Peak memory 235300 kb
Host smart-aea25b4c-0e15-4273-8855-fb1abd83ad75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685348707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1685348707
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1276317130
Short name T528
Test name
Test status
Simulation time 162354115 ps
CPU time 3.6 seconds
Started Mar 07 01:05:04 PM PST 24
Finished Mar 07 01:05:09 PM PST 24
Peak memory 199716 kb
Host smart-eaf1c309-63b0-4f36-b61c-6abc1d749641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276317130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1276317130
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1750460567
Short name T210
Test name
Test status
Simulation time 83680322 ps
CPU time 0.84 seconds
Started Mar 07 01:05:01 PM PST 24
Finished Mar 07 01:05:02 PM PST 24
Peak memory 197540 kb
Host smart-5f1d4722-df60-431a-95f0-a6e1df78a580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750460567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1750460567
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2127751496
Short name T44
Test name
Test status
Simulation time 9206719976 ps
CPU time 124.8 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:07:04 PM PST 24
Peak memory 200032 kb
Host smart-67b7b8bd-0dac-4e86-8fe7-451ecb7dc70d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127751496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2127751496
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.815677620
Short name T419
Test name
Test status
Simulation time 982607886 ps
CPU time 62.25 seconds
Started Mar 07 01:05:00 PM PST 24
Finished Mar 07 01:06:03 PM PST 24
Peak memory 199852 kb
Host smart-a182ab29-4442-4b21-a4f2-72a34e9766cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815677620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.815677620
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3387735246
Short name T544
Test name
Test status
Simulation time 73643690 ps
CPU time 0.93 seconds
Started Mar 07 01:05:00 PM PST 24
Finished Mar 07 01:05:01 PM PST 24
Peak memory 198408 kb
Host smart-a090016a-1409-4d74-9fb1-c1ae70a60184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387735246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3387735246
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.239879122
Short name T452
Test name
Test status
Simulation time 198340161675 ps
CPU time 547.87 seconds
Started Mar 07 01:05:00 PM PST 24
Finished Mar 07 01:14:08 PM PST 24
Peak memory 199848 kb
Host smart-71552b83-9334-4d34-aab5-4b0b083e1265
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239879122 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.239879122
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2726565984
Short name T443
Test name
Test status
Simulation time 30014602 ps
CPU time 0.95 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:05:00 PM PST 24
Peak memory 199064 kb
Host smart-98291f05-ebdf-4fd7-a0d4-cf0ef48da727
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726565984 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2726565984
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2632802774
Short name T313
Test name
Test status
Simulation time 130561737277 ps
CPU time 402.14 seconds
Started Mar 07 01:05:04 PM PST 24
Finished Mar 07 01:11:47 PM PST 24
Peak memory 199848 kb
Host smart-8f59076c-e91c-483f-a6a3-737f31b5ddea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632802774 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2632802774
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1388333550
Short name T281
Test name
Test status
Simulation time 10470714308 ps
CPU time 76.08 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:06:15 PM PST 24
Peak memory 200000 kb
Host smart-1d0e7d44-aa10-4eb2-bec9-18c3551f151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388333550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1388333550
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2885292017
Short name T425
Test name
Test status
Simulation time 43890084 ps
CPU time 0.61 seconds
Started Mar 07 01:05:00 PM PST 24
Finished Mar 07 01:05:01 PM PST 24
Peak memory 195248 kb
Host smart-613690c7-c11a-409f-92d5-ced57f498b77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885292017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2885292017
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1777949373
Short name T232
Test name
Test status
Simulation time 5651113215 ps
CPU time 46.62 seconds
Started Mar 07 01:04:58 PM PST 24
Finished Mar 07 01:05:44 PM PST 24
Peak memory 216344 kb
Host smart-6eddf6aa-30bf-4b3c-a39a-881d13cd9bdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1777949373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1777949373
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.4232225214
Short name T32
Test name
Test status
Simulation time 718935286 ps
CPU time 17.47 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:05:17 PM PST 24
Peak memory 199884 kb
Host smart-6d4ee8ae-7a72-4c46-a216-00bab5862583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232225214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.4232225214
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1633726640
Short name T523
Test name
Test status
Simulation time 1536411591 ps
CPU time 82.24 seconds
Started Mar 07 01:04:58 PM PST 24
Finished Mar 07 01:06:21 PM PST 24
Peak memory 199836 kb
Host smart-6295c925-ba26-4d42-b2e1-f8d852857eb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1633726640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1633726640
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3380377650
Short name T169
Test name
Test status
Simulation time 1075193342 ps
CPU time 54.5 seconds
Started Mar 07 01:04:58 PM PST 24
Finished Mar 07 01:05:52 PM PST 24
Peak memory 199892 kb
Host smart-ca720736-60d4-4b58-9cf6-ba6b0c22e0fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380377650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3380377650
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.107452569
Short name T310
Test name
Test status
Simulation time 320680755 ps
CPU time 5.35 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:05:05 PM PST 24
Peak memory 199764 kb
Host smart-ad2e9a55-ad24-408a-9564-1f050813c71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107452569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.107452569
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.255137748
Short name T139
Test name
Test status
Simulation time 126645358 ps
CPU time 4.07 seconds
Started Mar 07 01:04:58 PM PST 24
Finished Mar 07 01:05:02 PM PST 24
Peak memory 199860 kb
Host smart-94222659-3252-472d-94f1-0322da93acfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255137748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.255137748
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.356279879
Short name T50
Test name
Test status
Simulation time 25405066683 ps
CPU time 1336.74 seconds
Started Mar 07 01:05:01 PM PST 24
Finished Mar 07 01:27:18 PM PST 24
Peak memory 229568 kb
Host smart-6078e0c9-4e28-418e-b6d9-47f50b728a0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356279879 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.356279879
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.599915320
Short name T484
Test name
Test status
Simulation time 31667667 ps
CPU time 1.14 seconds
Started Mar 07 01:04:58 PM PST 24
Finished Mar 07 01:04:59 PM PST 24
Peak memory 199660 kb
Host smart-1af0fe02-a34e-4fbf-a8fa-5c8c7e0edce3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599915320 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.599915320
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3185579600
Short name T463
Test name
Test status
Simulation time 38168519671 ps
CPU time 488.78 seconds
Started Mar 07 01:04:57 PM PST 24
Finished Mar 07 01:13:06 PM PST 24
Peak memory 200024 kb
Host smart-6fc311b1-9446-4cb9-aa9b-d389b76f4b6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185579600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3185579600
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2354892038
Short name T403
Test name
Test status
Simulation time 2336635035 ps
CPU time 50.96 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:05:50 PM PST 24
Peak memory 199916 kb
Host smart-7be64701-3191-4d4a-a09c-e159a28d677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354892038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2354892038
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2391421434
Short name T438
Test name
Test status
Simulation time 12871658 ps
CPU time 0.59 seconds
Started Mar 07 01:05:13 PM PST 24
Finished Mar 07 01:05:13 PM PST 24
Peak memory 195324 kb
Host smart-f17b6d0a-ada3-4418-84b4-2eb30475b902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391421434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2391421434
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1739446523
Short name T296
Test name
Test status
Simulation time 3798589761 ps
CPU time 53.03 seconds
Started Mar 07 01:05:00 PM PST 24
Finished Mar 07 01:05:54 PM PST 24
Peak memory 208152 kb
Host smart-1604189c-0952-4f08-92d0-6f8618600053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739446523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1739446523
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.4166714571
Short name T331
Test name
Test status
Simulation time 856947539 ps
CPU time 7.12 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:05:06 PM PST 24
Peak memory 199852 kb
Host smart-0f6e82c0-97b8-48da-a044-2c84f0f8370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166714571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.4166714571
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.479791726
Short name T48
Test name
Test status
Simulation time 168571907 ps
CPU time 2.55 seconds
Started Mar 07 01:05:03 PM PST 24
Finished Mar 07 01:05:05 PM PST 24
Peak memory 199872 kb
Host smart-b69d56a6-1918-4479-bfe2-ec83b553fd67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479791726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.479791726
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1428326147
Short name T326
Test name
Test status
Simulation time 5541280600 ps
CPU time 102.59 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:06:41 PM PST 24
Peak memory 199984 kb
Host smart-aabba381-5aad-4872-b479-9a09d1479114
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428326147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1428326147
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1548268031
Short name T160
Test name
Test status
Simulation time 4091002507 ps
CPU time 73.21 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:06:13 PM PST 24
Peak memory 199960 kb
Host smart-e45ba61d-5bdb-4b6c-9e95-ba5be8a8ff8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548268031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1548268031
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1017465931
Short name T462
Test name
Test status
Simulation time 839104934 ps
CPU time 6.42 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:05:05 PM PST 24
Peak memory 199892 kb
Host smart-8cbecc0d-b5bc-41c1-91b5-9b6fd70ae62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017465931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1017465931
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2577506328
Short name T200
Test name
Test status
Simulation time 117623187040 ps
CPU time 740.71 seconds
Started Mar 07 01:05:11 PM PST 24
Finished Mar 07 01:17:32 PM PST 24
Peak memory 200096 kb
Host smart-28250ad1-feb3-4ef4-9d63-aed32c00cd9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577506328 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2577506328
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2839734999
Short name T267
Test name
Test status
Simulation time 59957523 ps
CPU time 0.98 seconds
Started Mar 07 01:05:11 PM PST 24
Finished Mar 07 01:05:12 PM PST 24
Peak memory 198840 kb
Host smart-355fecec-f17b-4744-8cd1-99393e5c8c9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839734999 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2839734999
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3503083421
Short name T568
Test name
Test status
Simulation time 160056932574 ps
CPU time 516.41 seconds
Started Mar 07 01:05:03 PM PST 24
Finished Mar 07 01:13:39 PM PST 24
Peak memory 200000 kb
Host smart-2111f2ad-2d31-4364-a9ca-2633c649ea8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503083421 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.3503083421
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.370275012
Short name T423
Test name
Test status
Simulation time 10730746333 ps
CPU time 74.03 seconds
Started Mar 07 01:04:59 PM PST 24
Finished Mar 07 01:06:13 PM PST 24
Peak memory 199968 kb
Host smart-d1b0d137-c662-4825-970f-9ff967f5a0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370275012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.370275012
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.83453587
Short name T231
Test name
Test status
Simulation time 12546820 ps
CPU time 0.59 seconds
Started Mar 07 01:05:10 PM PST 24
Finished Mar 07 01:05:11 PM PST 24
Peak memory 195312 kb
Host smart-389b1276-7136-4932-9697-048eb5522608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83453587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.83453587
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3891139822
Short name T54
Test name
Test status
Simulation time 502578820 ps
CPU time 21.81 seconds
Started Mar 07 01:05:13 PM PST 24
Finished Mar 07 01:05:35 PM PST 24
Peak memory 224980 kb
Host smart-1d6b8fbf-d49e-4e36-b6dc-f06d0016bcc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891139822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3891139822
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3537432045
Short name T130
Test name
Test status
Simulation time 1280617270 ps
CPU time 16.04 seconds
Started Mar 07 01:05:10 PM PST 24
Finished Mar 07 01:05:26 PM PST 24
Peak memory 199852 kb
Host smart-57765631-e605-4dcf-a77d-9a0d2fcc0406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537432045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3537432045
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2618589429
Short name T166
Test name
Test status
Simulation time 333644047 ps
CPU time 20.14 seconds
Started Mar 07 01:05:11 PM PST 24
Finished Mar 07 01:05:32 PM PST 24
Peak memory 199868 kb
Host smart-bbd4a319-a38a-469b-ac12-6bbcefbe73a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618589429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2618589429
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.559213828
Short name T547
Test name
Test status
Simulation time 7067748271 ps
CPU time 52.55 seconds
Started Mar 07 01:05:18 PM PST 24
Finished Mar 07 01:06:13 PM PST 24
Peak memory 199960 kb
Host smart-28d6f693-873a-4693-95d9-a538fbec2bf6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559213828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.559213828
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2164542864
Short name T135
Test name
Test status
Simulation time 3253193231 ps
CPU time 65.23 seconds
Started Mar 07 01:05:11 PM PST 24
Finished Mar 07 01:06:17 PM PST 24
Peak memory 199948 kb
Host smart-20382efd-d5a3-43da-aeb2-4299ce5294e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164542864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2164542864
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2259462330
Short name T387
Test name
Test status
Simulation time 601460649 ps
CPU time 2.25 seconds
Started Mar 07 01:05:13 PM PST 24
Finished Mar 07 01:05:15 PM PST 24
Peak memory 199868 kb
Host smart-9e0b3356-243d-4312-b7b0-76ebd438ea4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259462330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2259462330
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.530499906
Short name T76
Test name
Test status
Simulation time 40322635186 ps
CPU time 613.58 seconds
Started Mar 07 01:05:13 PM PST 24
Finished Mar 07 01:15:27 PM PST 24
Peak memory 247944 kb
Host smart-fec34bf1-8c69-4b68-943b-a70674570816
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530499906 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.530499906
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1622363772
Short name T595
Test name
Test status
Simulation time 227668722 ps
CPU time 1.06 seconds
Started Mar 07 01:05:10 PM PST 24
Finished Mar 07 01:05:11 PM PST 24
Peak memory 198664 kb
Host smart-053c0d94-8e1e-4f0c-801a-48c2576632eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622363772 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1622363772
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2959783334
Short name T583
Test name
Test status
Simulation time 14886428089 ps
CPU time 420.17 seconds
Started Mar 07 01:05:14 PM PST 24
Finished Mar 07 01:12:14 PM PST 24
Peak memory 199928 kb
Host smart-95917fb7-79f0-4f88-84ce-25a3bfd06893
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959783334 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.2959783334
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3814817557
Short name T176
Test name
Test status
Simulation time 4686313042 ps
CPU time 75.83 seconds
Started Mar 07 01:05:14 PM PST 24
Finished Mar 07 01:06:30 PM PST 24
Peak memory 199988 kb
Host smart-2519b7b0-d7c9-4799-9131-7a9419187d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814817557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3814817557
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.752002048
Short name T445
Test name
Test status
Simulation time 11970973 ps
CPU time 0.6 seconds
Started Mar 07 01:05:15 PM PST 24
Finished Mar 07 01:05:17 PM PST 24
Peak memory 195312 kb
Host smart-9c674391-e84c-4424-80b8-729beec135c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752002048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.752002048
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3832038470
Short name T223
Test name
Test status
Simulation time 295989200 ps
CPU time 9.65 seconds
Started Mar 07 01:05:13 PM PST 24
Finished Mar 07 01:05:23 PM PST 24
Peak memory 208044 kb
Host smart-5b13452b-88ff-4e20-9f9b-fef9c44ca024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832038470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3832038470
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1087452706
Short name T352
Test name
Test status
Simulation time 5329419038 ps
CPU time 23.99 seconds
Started Mar 07 01:05:10 PM PST 24
Finished Mar 07 01:05:34 PM PST 24
Peak memory 199976 kb
Host smart-a008e0a9-addf-4b3a-91dd-35f794e9a4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087452706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1087452706
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3412797699
Short name T556
Test name
Test status
Simulation time 1287146209 ps
CPU time 73.19 seconds
Started Mar 07 01:05:11 PM PST 24
Finished Mar 07 01:06:24 PM PST 24
Peak memory 199796 kb
Host smart-642bdf53-95e1-424f-8073-0dfb1afde58e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412797699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3412797699
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2676329595
Short name T15
Test name
Test status
Simulation time 82963769855 ps
CPU time 275.5 seconds
Started Mar 07 01:05:11 PM PST 24
Finished Mar 07 01:09:47 PM PST 24
Peak memory 199988 kb
Host smart-53d3670d-12b8-4875-a3ab-600d62f67d59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676329595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2676329595
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3629817423
Short name T211
Test name
Test status
Simulation time 22439263403 ps
CPU time 77.65 seconds
Started Mar 07 01:05:14 PM PST 24
Finished Mar 07 01:06:32 PM PST 24
Peak memory 199984 kb
Host smart-d73ead62-409c-4ffd-89e1-bebbc8882e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629817423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3629817423
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1546037115
Short name T233
Test name
Test status
Simulation time 357511440 ps
CPU time 4.09 seconds
Started Mar 07 01:05:13 PM PST 24
Finished Mar 07 01:05:17 PM PST 24
Peak memory 199856 kb
Host smart-8a0d8fe6-01ce-4a1b-85fe-f31559dc054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546037115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1546037115
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1825029021
Short name T290
Test name
Test status
Simulation time 239855001859 ps
CPU time 532.53 seconds
Started Mar 07 01:05:14 PM PST 24
Finished Mar 07 01:14:07 PM PST 24
Peak memory 200068 kb
Host smart-fb7da27f-87e4-4e27-8516-59e7dea0713f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825029021 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1825029021
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.641801108
Short name T559
Test name
Test status
Simulation time 29125853 ps
CPU time 1.09 seconds
Started Mar 07 01:05:12 PM PST 24
Finished Mar 07 01:05:14 PM PST 24
Peak memory 198940 kb
Host smart-45e830a2-bd7e-4bbd-848c-d3ba44829f31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641801108 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.641801108
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3565056219
Short name T311
Test name
Test status
Simulation time 106891425849 ps
CPU time 481.74 seconds
Started Mar 07 01:05:13 PM PST 24
Finished Mar 07 01:13:15 PM PST 24
Peak memory 199928 kb
Host smart-9c30f91f-a0be-480d-89cf-056c7a25a5fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565056219 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3565056219
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1938979957
Short name T192
Test name
Test status
Simulation time 2823612853 ps
CPU time 55.02 seconds
Started Mar 07 01:05:12 PM PST 24
Finished Mar 07 01:06:07 PM PST 24
Peak memory 200000 kb
Host smart-48bf8c60-3ffb-46de-9377-b72c249a0fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938979957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1938979957
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2550427647
Short name T490
Test name
Test status
Simulation time 35936789 ps
CPU time 0.56 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:05:23 PM PST 24
Peak memory 195304 kb
Host smart-1785328c-3300-46cd-99df-1862b654e73e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550427647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2550427647
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3755608210
Short name T58
Test name
Test status
Simulation time 461323523 ps
CPU time 5.94 seconds
Started Mar 07 01:05:12 PM PST 24
Finished Mar 07 01:05:19 PM PST 24
Peak memory 199896 kb
Host smart-3d83109d-3225-433c-a99c-2bf54825ea8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755608210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3755608210
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.427757512
Short name T276
Test name
Test status
Simulation time 20051680430 ps
CPU time 62.76 seconds
Started Mar 07 01:05:23 PM PST 24
Finished Mar 07 01:06:27 PM PST 24
Peak memory 199880 kb
Host smart-dfe10533-1dd7-44c0-85a2-6a83ea19a697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427757512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.427757512
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.165645171
Short name T212
Test name
Test status
Simulation time 942379038 ps
CPU time 52.33 seconds
Started Mar 07 01:05:22 PM PST 24
Finished Mar 07 01:06:15 PM PST 24
Peak memory 199876 kb
Host smart-e0142bde-9769-481d-bf48-2024cbbedead
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165645171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.165645171
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.76867709
Short name T317
Test name
Test status
Simulation time 3957374401 ps
CPU time 69.44 seconds
Started Mar 07 01:05:22 PM PST 24
Finished Mar 07 01:06:32 PM PST 24
Peak memory 199952 kb
Host smart-a80ded70-5b67-467e-a331-9882618df779
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76867709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.76867709
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.801085902
Short name T584
Test name
Test status
Simulation time 3054756554 ps
CPU time 65.34 seconds
Started Mar 07 01:05:11 PM PST 24
Finished Mar 07 01:06:17 PM PST 24
Peak memory 199860 kb
Host smart-f0d58d05-3113-4f8d-b954-5958c18f272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801085902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.801085902
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.4134618450
Short name T297
Test name
Test status
Simulation time 802454142 ps
CPU time 6.05 seconds
Started Mar 07 01:05:18 PM PST 24
Finished Mar 07 01:05:26 PM PST 24
Peak memory 199852 kb
Host smart-a44bb4b4-4f7d-4673-8d06-93d6671d38a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134618450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.4134618450
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2348828110
Short name T4
Test name
Test status
Simulation time 9086105342 ps
CPU time 87.27 seconds
Started Mar 07 01:05:27 PM PST 24
Finished Mar 07 01:06:55 PM PST 24
Peak memory 230720 kb
Host smart-30a446f0-d3a7-4165-b005-54a55aebb52e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348828110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2348828110
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1328668298
Short name T254
Test name
Test status
Simulation time 141647297 ps
CPU time 0.99 seconds
Started Mar 07 01:05:20 PM PST 24
Finished Mar 07 01:05:21 PM PST 24
Peak memory 198352 kb
Host smart-3408b8cc-f2e3-4d7e-a7ab-13cf6458e7af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328668298 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.1328668298
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.621779830
Short name T253
Test name
Test status
Simulation time 27710744123 ps
CPU time 484.03 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:13:26 PM PST 24
Peak memory 200028 kb
Host smart-549f1af1-36d3-49c0-9f69-0f5519a149a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621779830 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.621779830
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3555506267
Short name T260
Test name
Test status
Simulation time 1115626400 ps
CPU time 11.82 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:05:33 PM PST 24
Peak memory 199916 kb
Host smart-f980de5f-ba01-4f17-9f3d-4dbc72953507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555506267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3555506267
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1868010249
Short name T517
Test name
Test status
Simulation time 43540090 ps
CPU time 0.58 seconds
Started Mar 07 01:05:22 PM PST 24
Finished Mar 07 01:05:23 PM PST 24
Peak memory 195300 kb
Host smart-7b94d2a4-e90a-4afc-8fd0-bb5a296966cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868010249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1868010249
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.329474461
Short name T275
Test name
Test status
Simulation time 4543717509 ps
CPU time 23.09 seconds
Started Mar 07 01:05:23 PM PST 24
Finished Mar 07 01:05:46 PM PST 24
Peak memory 216340 kb
Host smart-89e21cc8-0b5c-4eb3-a169-30bb67a65155
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329474461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.329474461
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.956152854
Short name T171
Test name
Test status
Simulation time 1349332821 ps
CPU time 65.28 seconds
Started Mar 07 01:05:24 PM PST 24
Finished Mar 07 01:06:30 PM PST 24
Peak memory 199812 kb
Host smart-70396cd6-5d1a-4020-9e39-523fc8270653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956152854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.956152854
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3522837298
Short name T555
Test name
Test status
Simulation time 1472466382 ps
CPU time 82.22 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:06:43 PM PST 24
Peak memory 199832 kb
Host smart-3f9f1a79-1826-4dd0-b050-d9336b40a1d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522837298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3522837298
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.643191003
Short name T378
Test name
Test status
Simulation time 15441834112 ps
CPU time 131.54 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:07:33 PM PST 24
Peak memory 199992 kb
Host smart-4e0b6ba1-04f1-4b86-a82c-9df6dd0caabb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643191003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.643191003
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3135737333
Short name T436
Test name
Test status
Simulation time 37316055685 ps
CPU time 53.42 seconds
Started Mar 07 01:05:23 PM PST 24
Finished Mar 07 01:06:16 PM PST 24
Peak memory 200020 kb
Host smart-8c5a12cb-052b-4c04-8412-ce8b78ce14c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135737333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3135737333
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.92534650
Short name T376
Test name
Test status
Simulation time 95276619 ps
CPU time 1.86 seconds
Started Mar 07 01:05:24 PM PST 24
Finished Mar 07 01:05:27 PM PST 24
Peak memory 199856 kb
Host smart-44dbce70-57e8-42e9-95e2-e20ac0acae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92534650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.92534650
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1998677103
Short name T173
Test name
Test status
Simulation time 45284621351 ps
CPU time 2468.33 seconds
Started Mar 07 01:05:22 PM PST 24
Finished Mar 07 01:46:31 PM PST 24
Peak memory 240600 kb
Host smart-4b740579-ee88-46da-9fd8-c9dbe0612add
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998677103 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1998677103
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.820923137
Short name T465
Test name
Test status
Simulation time 1068460943 ps
CPU time 1.39 seconds
Started Mar 07 01:05:27 PM PST 24
Finished Mar 07 01:05:28 PM PST 24
Peak memory 199856 kb
Host smart-c5420099-8883-4dda-b4ae-35749e23a397
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820923137 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.820923137
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2347328924
Short name T449
Test name
Test status
Simulation time 180606532106 ps
CPU time 558.28 seconds
Started Mar 07 01:05:31 PM PST 24
Finished Mar 07 01:14:49 PM PST 24
Peak memory 199932 kb
Host smart-8b684bd5-e7c5-4a23-985f-4203dcfb22ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347328924 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2347328924
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.311286971
Short name T84
Test name
Test status
Simulation time 7636402463 ps
CPU time 51.3 seconds
Started Mar 07 01:05:31 PM PST 24
Finished Mar 07 01:06:22 PM PST 24
Peak memory 200008 kb
Host smart-e5ae0704-1538-4500-8f03-70c48fec0c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311286971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.311286971
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1640759408
Short name T312
Test name
Test status
Simulation time 12186068 ps
CPU time 0.59 seconds
Started Mar 07 01:05:24 PM PST 24
Finished Mar 07 01:05:26 PM PST 24
Peak memory 195280 kb
Host smart-059110bc-c7d3-4f1e-9c73-3d85097cf667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640759408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1640759408
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2219403313
Short name T466
Test name
Test status
Simulation time 6200835337 ps
CPU time 37.65 seconds
Started Mar 07 01:05:28 PM PST 24
Finished Mar 07 01:06:06 PM PST 24
Peak memory 214128 kb
Host smart-8e4e4494-da2a-4106-b709-4421ac6d46c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219403313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2219403313
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2164886965
Short name T507
Test name
Test status
Simulation time 5467805529 ps
CPU time 42.01 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:06:03 PM PST 24
Peak memory 200040 kb
Host smart-2088f68b-cbeb-438f-ae8d-70112ff99f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164886965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2164886965
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.874487688
Short name T380
Test name
Test status
Simulation time 3693307335 ps
CPU time 74.84 seconds
Started Mar 07 01:05:24 PM PST 24
Finished Mar 07 01:06:39 PM PST 24
Peak memory 199888 kb
Host smart-b3f97997-c7f5-4cb1-b3c4-591d2bbda2a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874487688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.874487688
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2854176724
Short name T577
Test name
Test status
Simulation time 18697089055 ps
CPU time 165.13 seconds
Started Mar 07 01:05:22 PM PST 24
Finished Mar 07 01:08:07 PM PST 24
Peak memory 200060 kb
Host smart-263cd8c8-2942-4396-b711-07bec5871ca7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854176724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2854176724
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1510527077
Short name T418
Test name
Test status
Simulation time 5047342223 ps
CPU time 48.82 seconds
Started Mar 07 01:05:25 PM PST 24
Finished Mar 07 01:06:15 PM PST 24
Peak memory 200056 kb
Host smart-61ea0d3a-6d90-46b9-b26a-55bb39157db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510527077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1510527077
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1920762267
Short name T280
Test name
Test status
Simulation time 673727538 ps
CPU time 5.14 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:05:26 PM PST 24
Peak memory 199832 kb
Host smart-33f05bff-ae33-4034-a667-8524229e5964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920762267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1920762267
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2764068753
Short name T551
Test name
Test status
Simulation time 189530467664 ps
CPU time 666.59 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:16:28 PM PST 24
Peak memory 240436 kb
Host smart-00fa9331-9968-4681-803b-d547cbae2534
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764068753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2764068753
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.4191522368
Short name T570
Test name
Test status
Simulation time 262084916 ps
CPU time 1.21 seconds
Started Mar 07 01:05:23 PM PST 24
Finished Mar 07 01:05:26 PM PST 24
Peak memory 199916 kb
Host smart-939c7501-15d8-4cac-9288-2768d542a15f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191522368 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.4191522368
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1234129691
Short name T298
Test name
Test status
Simulation time 9900166959 ps
CPU time 496.04 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:13:37 PM PST 24
Peak memory 200032 kb
Host smart-9d8372a5-5971-40e7-a491-683edfd27fd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234129691 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1234129691
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2197660722
Short name T41
Test name
Test status
Simulation time 21537045059 ps
CPU time 53.08 seconds
Started Mar 07 01:05:25 PM PST 24
Finished Mar 07 01:06:18 PM PST 24
Peak memory 199908 kb
Host smart-f84e109e-3652-4c5e-b558-104968b35137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197660722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2197660722
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3385832919
Short name T274
Test name
Test status
Simulation time 44748275 ps
CPU time 0.59 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:05:22 PM PST 24
Peak memory 195336 kb
Host smart-99e32a0b-0812-438f-a605-c841d8972594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385832919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3385832919
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3142507657
Short name T482
Test name
Test status
Simulation time 1409971849 ps
CPU time 60.53 seconds
Started Mar 07 01:05:22 PM PST 24
Finished Mar 07 01:06:23 PM PST 24
Peak memory 232652 kb
Host smart-25c46ca0-98e4-4875-820e-d4298b9a83ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3142507657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3142507657
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2438327536
Short name T560
Test name
Test status
Simulation time 5526498396 ps
CPU time 52.35 seconds
Started Mar 07 01:05:25 PM PST 24
Finished Mar 07 01:06:18 PM PST 24
Peak memory 199940 kb
Host smart-3c11c4b6-f10c-436c-b003-262a16845a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438327536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2438327536
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2116287907
Short name T391
Test name
Test status
Simulation time 2589818173 ps
CPU time 23.41 seconds
Started Mar 07 01:05:20 PM PST 24
Finished Mar 07 01:05:44 PM PST 24
Peak memory 199960 kb
Host smart-f80c8717-d8c8-4eeb-8c85-a8fc16d45ddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2116287907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2116287907
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1574522585
Short name T17
Test name
Test status
Simulation time 25649747396 ps
CPU time 94.17 seconds
Started Mar 07 01:05:21 PM PST 24
Finished Mar 07 01:06:56 PM PST 24
Peak memory 199952 kb
Host smart-781ad47c-1459-477a-8648-b12a9fab41cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574522585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1574522585
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2932659087
Short name T170
Test name
Test status
Simulation time 4396459578 ps
CPU time 61.11 seconds
Started Mar 07 01:05:27 PM PST 24
Finished Mar 07 01:06:29 PM PST 24
Peak memory 199976 kb
Host smart-79643fb0-0ebf-4142-9b58-cfce7c1619a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932659087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2932659087
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3636365504
Short name T68
Test name
Test status
Simulation time 70542212 ps
CPU time 0.71 seconds
Started Mar 07 01:05:22 PM PST 24
Finished Mar 07 01:05:23 PM PST 24
Peak memory 196712 kb
Host smart-98d50ab7-05a3-4230-b17d-f9bea144536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636365504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3636365504
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.39576489
Short name T75
Test name
Test status
Simulation time 15130104461 ps
CPU time 240.79 seconds
Started Mar 07 01:05:31 PM PST 24
Finished Mar 07 01:09:32 PM PST 24
Peak memory 239040 kb
Host smart-e30c9f24-cfbb-4ec6-9554-6c4ae121b8ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39576489 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.39576489
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.11667242
Short name T93
Test name
Test status
Simulation time 59733821 ps
CPU time 0.92 seconds
Started Mar 07 01:05:23 PM PST 24
Finished Mar 07 01:05:25 PM PST 24
Peak memory 198348 kb
Host smart-ccde7ca6-6722-4ebf-a3c1-0d37d180b752
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11667242 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.hmac_test_hmac_vectors.11667242
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2403523580
Short name T236
Test name
Test status
Simulation time 9218378579 ps
CPU time 488.37 seconds
Started Mar 07 01:05:22 PM PST 24
Finished Mar 07 01:13:31 PM PST 24
Peak memory 200000 kb
Host smart-481c1169-c03f-41a6-9cdf-e1ffdf6ee08a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403523580 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.2403523580
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1527425185
Short name T409
Test name
Test status
Simulation time 2247219678 ps
CPU time 17.02 seconds
Started Mar 07 01:05:29 PM PST 24
Finished Mar 07 01:05:46 PM PST 24
Peak memory 199904 kb
Host smart-d45418e1-b4b1-48a9-aa27-1d353611f8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527425185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1527425185
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1605866237
Short name T510
Test name
Test status
Simulation time 27843925 ps
CPU time 0.59 seconds
Started Mar 07 01:05:33 PM PST 24
Finished Mar 07 01:05:34 PM PST 24
Peak memory 195340 kb
Host smart-d7da826e-3d23-4e31-bf4d-50cfe780de4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605866237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1605866237
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.253467083
Short name T327
Test name
Test status
Simulation time 2730939256 ps
CPU time 45.73 seconds
Started Mar 07 01:05:31 PM PST 24
Finished Mar 07 01:06:17 PM PST 24
Peak memory 216308 kb
Host smart-b74d9f4d-743a-4169-bf3c-cbad2bbf0dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253467083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.253467083
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3967305466
Short name T558
Test name
Test status
Simulation time 5350671602 ps
CPU time 18.29 seconds
Started Mar 07 01:05:31 PM PST 24
Finished Mar 07 01:05:49 PM PST 24
Peak memory 199884 kb
Host smart-e3a365cd-7300-49c1-a2e6-b961ce59888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967305466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3967305466
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1200902036
Short name T516
Test name
Test status
Simulation time 2451517683 ps
CPU time 77.92 seconds
Started Mar 07 01:05:35 PM PST 24
Finished Mar 07 01:06:53 PM PST 24
Peak memory 199952 kb
Host smart-6acd38c8-47a6-42ff-b1da-7ea7b802f379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1200902036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1200902036
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.44102014
Short name T96
Test name
Test status
Simulation time 7107899222 ps
CPU time 130.1 seconds
Started Mar 07 01:05:32 PM PST 24
Finished Mar 07 01:07:43 PM PST 24
Peak memory 200024 kb
Host smart-65cda9b6-74cc-4ed5-833f-0a496f084dcb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44102014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.44102014
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2284563492
Short name T594
Test name
Test status
Simulation time 2082209410 ps
CPU time 28.25 seconds
Started Mar 07 01:05:31 PM PST 24
Finished Mar 07 01:05:59 PM PST 24
Peak memory 199856 kb
Host smart-22ab52c3-c12f-495e-b226-a6b54c399877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284563492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2284563492
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1645251383
Short name T269
Test name
Test status
Simulation time 220441523 ps
CPU time 1.08 seconds
Started Mar 07 01:05:32 PM PST 24
Finished Mar 07 01:05:33 PM PST 24
Peak memory 199360 kb
Host smart-db7e1c7b-19f5-489e-a83f-18a4b4ee219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645251383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1645251383
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1096411680
Short name T456
Test name
Test status
Simulation time 50493561483 ps
CPU time 626.9 seconds
Started Mar 07 01:05:32 PM PST 24
Finished Mar 07 01:16:00 PM PST 24
Peak memory 224632 kb
Host smart-9045453e-b01f-4b79-a7cb-99dbab53fa94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096411680 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1096411680
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3110813691
Short name T347
Test name
Test status
Simulation time 53274540 ps
CPU time 1.27 seconds
Started Mar 07 01:05:33 PM PST 24
Finished Mar 07 01:05:35 PM PST 24
Peak memory 199812 kb
Host smart-80b4f88f-645d-4a10-865e-1d52a28e0055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110813691 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3110813691
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.3601520820
Short name T146
Test name
Test status
Simulation time 88419066263 ps
CPU time 544.27 seconds
Started Mar 07 01:05:34 PM PST 24
Finished Mar 07 01:14:38 PM PST 24
Peak memory 200064 kb
Host smart-948d53e0-5127-4f7e-8b50-9c28aceac077
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601520820 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.3601520820
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1645021397
Short name T404
Test name
Test status
Simulation time 1329059547 ps
CPU time 54.57 seconds
Started Mar 07 01:05:32 PM PST 24
Finished Mar 07 01:06:27 PM PST 24
Peak memory 199824 kb
Host smart-d834e956-2afe-4806-a6d5-da0a10559f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645021397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1645021397
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1128903319
Short name T24
Test name
Test status
Simulation time 29068910 ps
CPU time 0.54 seconds
Started Mar 07 01:02:25 PM PST 24
Finished Mar 07 01:02:26 PM PST 24
Peak memory 194280 kb
Host smart-06ca7090-bf0e-4dda-80b9-912a28d76ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128903319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1128903319
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3186175079
Short name T343
Test name
Test status
Simulation time 5688258081 ps
CPU time 45.3 seconds
Started Mar 07 01:02:26 PM PST 24
Finished Mar 07 01:03:11 PM PST 24
Peak memory 208188 kb
Host smart-84300819-72ba-42d0-ba80-1ec5f1a89187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186175079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3186175079
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1399972910
Short name T472
Test name
Test status
Simulation time 1567855942 ps
CPU time 6.19 seconds
Started Mar 07 01:02:21 PM PST 24
Finished Mar 07 01:02:27 PM PST 24
Peak memory 199832 kb
Host smart-78e5da73-6fb5-44aa-8501-8c29f68af92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399972910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1399972910
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2230773736
Short name T600
Test name
Test status
Simulation time 6543163382 ps
CPU time 133.08 seconds
Started Mar 07 01:02:29 PM PST 24
Finished Mar 07 01:04:42 PM PST 24
Peak memory 200012 kb
Host smart-0462d8ca-4312-4ffd-91ae-f5af897b15d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230773736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2230773736
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2321572406
Short name T601
Test name
Test status
Simulation time 9957906163 ps
CPU time 170.85 seconds
Started Mar 07 01:02:24 PM PST 24
Finished Mar 07 01:05:15 PM PST 24
Peak memory 199928 kb
Host smart-c99e7821-47a2-4595-9407-c3e6f6c68b33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321572406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2321572406
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2388780
Short name T323
Test name
Test status
Simulation time 2618211970 ps
CPU time 18.83 seconds
Started Mar 07 01:02:21 PM PST 24
Finished Mar 07 01:02:40 PM PST 24
Peak memory 199912 kb
Host smart-abff1423-3ce4-45c1-9f92-e60ced9d0b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2388780
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3677338466
Short name T308
Test name
Test status
Simulation time 2050756855 ps
CPU time 5.81 seconds
Started Mar 07 01:02:23 PM PST 24
Finished Mar 07 01:02:29 PM PST 24
Peak memory 199880 kb
Host smart-addb5738-e6ab-4fa4-a1fd-77b2eb0fdda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677338466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3677338466
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4178343177
Short name T374
Test name
Test status
Simulation time 34683079398 ps
CPU time 673.92 seconds
Started Mar 07 01:02:19 PM PST 24
Finished Mar 07 01:13:33 PM PST 24
Peak memory 248132 kb
Host smart-adc2e434-24c8-4a4e-97c0-1325849f0114
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178343177 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4178343177
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3419574243
Short name T539
Test name
Test status
Simulation time 106651011 ps
CPU time 0.94 seconds
Started Mar 07 01:02:24 PM PST 24
Finished Mar 07 01:02:25 PM PST 24
Peak memory 197916 kb
Host smart-9856528d-e327-4eea-ad7e-925bb2be7333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419574243 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3419574243
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1584649404
Short name T407
Test name
Test status
Simulation time 98392619055 ps
CPU time 449.25 seconds
Started Mar 07 01:02:29 PM PST 24
Finished Mar 07 01:09:58 PM PST 24
Peak memory 199976 kb
Host smart-9df7b814-21a4-4fc0-ad47-e9ac9d6beb38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584649404 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1584649404
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3726946818
Short name T190
Test name
Test status
Simulation time 2121911958 ps
CPU time 46.24 seconds
Started Mar 07 01:02:20 PM PST 24
Finished Mar 07 01:03:06 PM PST 24
Peak memory 199908 kb
Host smart-bdd892b4-a62b-4bbd-b511-f3c1f15bbad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726946818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3726946818
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2755160192
Short name T238
Test name
Test status
Simulation time 23476364 ps
CPU time 0.56 seconds
Started Mar 07 01:02:21 PM PST 24
Finished Mar 07 01:02:22 PM PST 24
Peak memory 194272 kb
Host smart-a4b93062-acb1-4436-a662-3bbef68fb4f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755160192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2755160192
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2413925398
Short name T372
Test name
Test status
Simulation time 1138224602 ps
CPU time 42.3 seconds
Started Mar 07 01:02:23 PM PST 24
Finished Mar 07 01:03:06 PM PST 24
Peak memory 232336 kb
Host smart-5f7bc840-5267-4a8b-8e5e-37d7abe42eb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413925398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2413925398
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.968158520
Short name T225
Test name
Test status
Simulation time 11606093332 ps
CPU time 57.25 seconds
Started Mar 07 01:02:22 PM PST 24
Finished Mar 07 01:03:20 PM PST 24
Peak memory 199900 kb
Host smart-64b09fcd-aa33-491c-a41f-a4b253472354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968158520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.968158520
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.691185601
Short name T385
Test name
Test status
Simulation time 4843470128 ps
CPU time 54.48 seconds
Started Mar 07 01:02:24 PM PST 24
Finished Mar 07 01:03:19 PM PST 24
Peak memory 199956 kb
Host smart-1cc084c9-0c16-4465-9095-91b5d4b42099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691185601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.691185601
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.871950799
Short name T21
Test name
Test status
Simulation time 178252083 ps
CPU time 3.9 seconds
Started Mar 07 01:02:29 PM PST 24
Finished Mar 07 01:02:33 PM PST 24
Peak memory 199696 kb
Host smart-e3af7604-ecdc-4139-800d-2f1fdad9dbe5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871950799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.871950799
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3461903239
Short name T475
Test name
Test status
Simulation time 24732399451 ps
CPU time 108.06 seconds
Started Mar 07 01:02:27 PM PST 24
Finished Mar 07 01:04:16 PM PST 24
Peak memory 200060 kb
Host smart-923cbdb8-9f7c-4e86-bb73-38f16d814906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461903239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3461903239
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1778457597
Short name T329
Test name
Test status
Simulation time 62532741 ps
CPU time 0.88 seconds
Started Mar 07 01:02:21 PM PST 24
Finished Mar 07 01:02:22 PM PST 24
Peak memory 198284 kb
Host smart-a9086164-b1b4-41da-986e-1ca034b346da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778457597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1778457597
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3204115137
Short name T234
Test name
Test status
Simulation time 170132605586 ps
CPU time 3071.38 seconds
Started Mar 07 01:02:25 PM PST 24
Finished Mar 07 01:53:37 PM PST 24
Peak memory 215760 kb
Host smart-baa97822-4c66-4993-9bc9-ac5e0121117f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204115137 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3204115137
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.813074333
Short name T142
Test name
Test status
Simulation time 53510032 ps
CPU time 1.18 seconds
Started Mar 07 01:02:26 PM PST 24
Finished Mar 07 01:02:27 PM PST 24
Peak memory 199388 kb
Host smart-5545a90c-5d10-472d-b92a-470e71d9df57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813074333 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.813074333
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3533675743
Short name T18
Test name
Test status
Simulation time 15993132383 ps
CPU time 440.86 seconds
Started Mar 07 01:02:25 PM PST 24
Finished Mar 07 01:09:46 PM PST 24
Peak memory 200008 kb
Host smart-f9fcc6d8-4111-4ee4-941c-97d4f0c571f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533675743 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3533675743
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3896683908
Short name T564
Test name
Test status
Simulation time 5558047199 ps
CPU time 82.61 seconds
Started Mar 07 01:02:29 PM PST 24
Finished Mar 07 01:03:52 PM PST 24
Peak memory 199940 kb
Host smart-185c9a03-63a7-40f8-a933-128c5066db23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896683908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3896683908
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.407833239
Short name T209
Test name
Test status
Simulation time 16285369 ps
CPU time 0.59 seconds
Started Mar 07 01:02:38 PM PST 24
Finished Mar 07 01:02:38 PM PST 24
Peak memory 195316 kb
Host smart-8ece7636-aaca-4b93-88f3-7868688b3dcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407833239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.407833239
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1577016828
Short name T193
Test name
Test status
Simulation time 12235658491 ps
CPU time 58.47 seconds
Started Mar 07 01:02:39 PM PST 24
Finished Mar 07 01:03:37 PM PST 24
Peak memory 216356 kb
Host smart-2ad56912-75cf-4e42-a3a4-3bbc2e8f0da9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577016828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1577016828
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1475935960
Short name T271
Test name
Test status
Simulation time 3525853515 ps
CPU time 45.01 seconds
Started Mar 07 01:02:38 PM PST 24
Finished Mar 07 01:03:23 PM PST 24
Peak memory 199880 kb
Host smart-0fae60a1-82f1-4730-a77c-e27f9a62b4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475935960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1475935960
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3370359493
Short name T582
Test name
Test status
Simulation time 5562832273 ps
CPU time 68.95 seconds
Started Mar 07 01:02:35 PM PST 24
Finished Mar 07 01:03:45 PM PST 24
Peak memory 200048 kb
Host smart-9dec4c1b-22d7-4404-922c-b0c6f787e296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370359493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3370359493
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3131644807
Short name T227
Test name
Test status
Simulation time 12750746841 ps
CPU time 228.85 seconds
Started Mar 07 01:02:38 PM PST 24
Finished Mar 07 01:06:27 PM PST 24
Peak memory 200004 kb
Host smart-2db169be-275a-46ab-849a-fa55c9717a8e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131644807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3131644807
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2523960271
Short name T576
Test name
Test status
Simulation time 392361589 ps
CPU time 7.49 seconds
Started Mar 07 01:02:36 PM PST 24
Finished Mar 07 01:02:44 PM PST 24
Peak memory 199872 kb
Host smart-a43e2545-91ce-4120-a719-2c8ea68badcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523960271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2523960271
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.333584606
Short name T149
Test name
Test status
Simulation time 557480413 ps
CPU time 1.07 seconds
Started Mar 07 01:02:37 PM PST 24
Finished Mar 07 01:02:39 PM PST 24
Peak memory 199868 kb
Host smart-ff6ae317-d43b-4b68-86c0-7a538aba6cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333584606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.333584606
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.845691683
Short name T569
Test name
Test status
Simulation time 39657805326 ps
CPU time 1119.18 seconds
Started Mar 07 01:02:42 PM PST 24
Finished Mar 07 01:21:22 PM PST 24
Peak memory 200000 kb
Host smart-4399fce4-546b-43f6-9dfb-ee26009ba285
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845691683 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.845691683
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3963180622
Short name T177
Test name
Test status
Simulation time 316709325 ps
CPU time 1.03 seconds
Started Mar 07 01:02:43 PM PST 24
Finished Mar 07 01:02:44 PM PST 24
Peak memory 198688 kb
Host smart-dd2714bf-3810-4f36-8cfc-4ba7150dc5d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963180622 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3963180622
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1750341445
Short name T72
Test name
Test status
Simulation time 29705444819 ps
CPU time 397.58 seconds
Started Mar 07 01:02:40 PM PST 24
Finished Mar 07 01:09:18 PM PST 24
Peak memory 199888 kb
Host smart-1cad41e1-ced2-4412-9a7c-d7175cf0a08a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750341445 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1750341445
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2995451786
Short name T40
Test name
Test status
Simulation time 7042119099 ps
CPU time 71.66 seconds
Started Mar 07 01:02:36 PM PST 24
Finished Mar 07 01:03:48 PM PST 24
Peak memory 199996 kb
Host smart-4a68da0a-c4e3-44e0-aeb8-88f71f401d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995451786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2995451786
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.468177879
Short name T518
Test name
Test status
Simulation time 33347066 ps
CPU time 0.56 seconds
Started Mar 07 01:02:38 PM PST 24
Finished Mar 07 01:02:38 PM PST 24
Peak memory 195308 kb
Host smart-a99cf4b9-2b45-4cac-ab75-76792ef6e19c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468177879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.468177879
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3261921886
Short name T216
Test name
Test status
Simulation time 1355116286 ps
CPU time 52.02 seconds
Started Mar 07 01:02:38 PM PST 24
Finished Mar 07 01:03:30 PM PST 24
Peak memory 232668 kb
Host smart-223f0d24-5f77-4b53-858d-bc70bab15b48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261921886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3261921886
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2889600155
Short name T328
Test name
Test status
Simulation time 792770518 ps
CPU time 18.4 seconds
Started Mar 07 01:02:37 PM PST 24
Finished Mar 07 01:02:56 PM PST 24
Peak memory 199856 kb
Host smart-d6744668-b1be-41ab-acf4-cf1377645776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889600155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2889600155
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1468422815
Short name T303
Test name
Test status
Simulation time 984814137 ps
CPU time 12.79 seconds
Started Mar 07 01:02:38 PM PST 24
Finished Mar 07 01:02:51 PM PST 24
Peak memory 199872 kb
Host smart-2d6cddab-40b5-493b-a6ea-7698807e5c34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468422815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1468422815
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1876650440
Short name T533
Test name
Test status
Simulation time 3029245935 ps
CPU time 51.29 seconds
Started Mar 07 01:02:37 PM PST 24
Finished Mar 07 01:03:29 PM PST 24
Peak memory 199892 kb
Host smart-15b3ddd1-4c99-466e-837d-40e02955068d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876650440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1876650440
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3444691898
Short name T138
Test name
Test status
Simulation time 9070433114 ps
CPU time 116.39 seconds
Started Mar 07 01:02:35 PM PST 24
Finished Mar 07 01:04:33 PM PST 24
Peak memory 199960 kb
Host smart-12dc1bd9-072f-4b74-bbd1-14bb24516e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444691898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3444691898
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2139561043
Short name T90
Test name
Test status
Simulation time 106568894 ps
CPU time 0.93 seconds
Started Mar 07 01:02:43 PM PST 24
Finished Mar 07 01:02:44 PM PST 24
Peak memory 198732 kb
Host smart-ffc33a27-1f91-4ba4-8e16-51996e47c996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139561043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2139561043
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1363520257
Short name T249
Test name
Test status
Simulation time 13083988955 ps
CPU time 168.82 seconds
Started Mar 07 01:02:39 PM PST 24
Finished Mar 07 01:05:28 PM PST 24
Peak memory 199936 kb
Host smart-74141583-564c-4f78-ae06-ef4ff33081b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363520257 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1363520257
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2814388130
Short name T289
Test name
Test status
Simulation time 29397633 ps
CPU time 1.09 seconds
Started Mar 07 01:02:42 PM PST 24
Finished Mar 07 01:02:43 PM PST 24
Peak memory 199048 kb
Host smart-6f75d051-0373-4d33-80a8-78e9e24f0718
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814388130 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2814388130
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3016710657
Short name T230
Test name
Test status
Simulation time 33672239827 ps
CPU time 458.96 seconds
Started Mar 07 01:02:38 PM PST 24
Finished Mar 07 01:10:17 PM PST 24
Peak memory 200012 kb
Host smart-e28bf7f1-ddc5-4666-aecb-c3e2db26324a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016710657 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3016710657
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.990259029
Short name T239
Test name
Test status
Simulation time 2699977528 ps
CPU time 35.99 seconds
Started Mar 07 01:02:37 PM PST 24
Finished Mar 07 01:03:13 PM PST 24
Peak memory 199896 kb
Host smart-ce8d461b-1d38-4c4c-b0a7-6aee80edbf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990259029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.990259029
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.3356129745
Short name T9
Test name
Test status
Simulation time 526109845988 ps
CPU time 2014.05 seconds
Started Mar 07 01:05:46 PM PST 24
Finished Mar 07 01:39:20 PM PST 24
Peak memory 256348 kb
Host smart-513f1fdc-5abe-4f38-98b1-3e33f1d27bc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356129745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.3356129745
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3529320619
Short name T22
Test name
Test status
Simulation time 20580888 ps
CPU time 0.56 seconds
Started Mar 07 01:02:52 PM PST 24
Finished Mar 07 01:02:53 PM PST 24
Peak memory 195268 kb
Host smart-61fa2a56-df8f-408f-972b-d2fd96ab3085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529320619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3529320619
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.4256011868
Short name T268
Test name
Test status
Simulation time 151130910 ps
CPU time 2.68 seconds
Started Mar 07 01:02:37 PM PST 24
Finished Mar 07 01:02:40 PM PST 24
Peak memory 199880 kb
Host smart-4e37ccbe-3d76-4288-ad78-2a99b1246cf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256011868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.4256011868
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.56733506
Short name T346
Test name
Test status
Simulation time 722254791 ps
CPU time 3.09 seconds
Started Mar 07 01:02:38 PM PST 24
Finished Mar 07 01:02:41 PM PST 24
Peak memory 199936 kb
Host smart-35dc64b3-62d1-47eb-9be4-d0bd7c23ce57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56733506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.56733506
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.814125848
Short name T434
Test name
Test status
Simulation time 1390974642 ps
CPU time 81.86 seconds
Started Mar 07 01:02:37 PM PST 24
Finished Mar 07 01:04:00 PM PST 24
Peak memory 199868 kb
Host smart-2a71385a-bb2f-4254-a82a-e026142e39d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814125848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.814125848
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.4288926562
Short name T504
Test name
Test status
Simulation time 7939423370 ps
CPU time 111.52 seconds
Started Mar 07 01:02:42 PM PST 24
Finished Mar 07 01:04:34 PM PST 24
Peak memory 199992 kb
Host smart-381ae9ce-4b20-483f-b238-7117d9c99f36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288926562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.4288926562
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2816831086
Short name T189
Test name
Test status
Simulation time 5263828858 ps
CPU time 72.04 seconds
Started Mar 07 01:02:40 PM PST 24
Finished Mar 07 01:03:52 PM PST 24
Peak memory 199884 kb
Host smart-0b8bf8c6-00db-49ed-b10b-a3f158083281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816831086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2816831086
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2818539177
Short name T354
Test name
Test status
Simulation time 1459189973 ps
CPU time 4.75 seconds
Started Mar 07 01:02:37 PM PST 24
Finished Mar 07 01:02:42 PM PST 24
Peak memory 199772 kb
Host smart-659226e7-d77b-4a03-9723-9b79f4d5412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818539177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2818539177
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.896746373
Short name T100
Test name
Test status
Simulation time 229232577725 ps
CPU time 1070.41 seconds
Started Mar 07 01:02:54 PM PST 24
Finished Mar 07 01:20:44 PM PST 24
Peak memory 227656 kb
Host smart-8ee4205b-f29e-44ef-8f72-44f26b1975e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896746373 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.896746373
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1207464324
Short name T502
Test name
Test status
Simulation time 49354906 ps
CPU time 0.99 seconds
Started Mar 07 01:02:53 PM PST 24
Finished Mar 07 01:02:54 PM PST 24
Peak memory 198880 kb
Host smart-298ad215-c797-41c6-b96c-9d7a2ee4ebc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207464324 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1207464324
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3698277107
Short name T537
Test name
Test status
Simulation time 58436331279 ps
CPU time 512.88 seconds
Started Mar 07 01:02:37 PM PST 24
Finished Mar 07 01:11:11 PM PST 24
Peak memory 199980 kb
Host smart-85219e34-938a-4ed7-9058-e733dd5a2505
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698277107 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3698277107
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3515911329
Short name T28
Test name
Test status
Simulation time 3434130284 ps
CPU time 40.67 seconds
Started Mar 07 01:02:40 PM PST 24
Finished Mar 07 01:03:21 PM PST 24
Peak memory 199816 kb
Host smart-858c6443-91d4-4667-a1db-256071af50e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515911329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3515911329
Directory /workspace/9.hmac_wipe_secret/latest
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