Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13569458	1			T1	98782		T2	11089		T3	4635
all_values[1]	13569458	1			T1	98782		T2	11089		T3	4635
all_values[2]	13569458	1			T1	98782		T2	11089		T3	4635

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118974

1

T1

20

T2

855

T3

26

auto[1]

40589400

1

T1

296326

T2

32412

T3

13879

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38440388

1

T1

256855

T2

33215

T3

13885

auto[1]

2267986

1

T1

39491

T2

52

T3

20

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	40024	1			T1	4		T2	851		T11	301
all_values[0]	auto[0]	auto[1]	491	1			T1	4		T2	4		T11	8
all_values[0]	auto[1]	auto[0]	13482535	1			T1	98309		T2	10186		T3	4615
all_values[0]	auto[1]	auto[1]	46408	1			T1	465		T2	48		T3	20
all_values[1]	auto[0]	auto[0]	37303	1			T1	2		T3	26		T11	242
all_values[1]	auto[0]	auto[1]	208	1			T1	3		T12	2		T22	2
all_values[1]	auto[1]	auto[0]	13531412	1			T1	98746		T2	11089		T3	4609
all_values[1]	auto[1]	auto[1]	535	1			T1	31		T12	1		T4	86
all_values[2]	auto[0]	auto[0]	31914	1			T1	5		T11	2		T40	2
all_values[2]	auto[0]	auto[1]	9034	1			T1	2		T12	2		T49	619
all_values[2]	auto[1]	auto[0]	11317200	1			T1	59789		T2	11089		T3	4635
all_values[2]	auto[1]	auto[1]	2211310	1			T1	38986		T11	12019		T13	9997