Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6664404

1

T1

77848

T2

6087

T3

3336

auto[1]

2676949

1

T1

81185

T2

4494

T3

1117

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2655002

1

T1

86725

T2

5325

T3

310

auto[1]

6686351

1

T1

72308

T2

5256

T3

4143

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5994383

1

T1

82230

T2

6305

T3

1014

auto[1]

3346970

1

T1

76803

T2

4276

T3

3439

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5728960	1			T1	36066		T2	3815		T3	1560
fifo_depth[1]	447787	1			T1	3160		T2	781		T3	348
fifo_depth[2]	380977	1			T1	3218		T2	767		T3	333
fifo_depth[3]	317486	1			T1	3061		T2	774		T3	304
fifo_depth[4]	280036	1			T1	3498		T2	766		T3	326
fifo_depth[5]	250175	1			T1	3035		T2	734		T3	313
fifo_depth[6]	240516	1			T1	3506		T2	720		T3	344
fifo_depth[7]	210888	1			T1	3232		T2	672		T3	273
fifo_depth[8]	195615	1			T1	4551		T2	577		T3	223
fifo_depth[9]	131952	1			T1	2718		T2	418		T3	185
fifo_depth[10]	105751	1			T1	3717		T2	267		T3	121
fifo_depth[11]	64413	1			T1	2329		T2	159		T3	59
fifo_depth[12]	70445	1			T1	4609		T2	78		T3	36
fifo_depth[13]	35270	1			T1	2495		T2	34		T3	17
fifo_depth[14]	48741	1			T1	4659		T2	15		T3	6
fifo_depth[15]	30443	1			T1	2906		T2	2		T3	5
fifo_depth[16]	114184	1			T1	12435		T2	2		T11	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3766409

1

T1

133814

T2

6766

T3

2893

auto[1]

5574944

1

T1

25219

T2

3815

T3

1560

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9187337

1

T1

148186

T2

10581

T3

4453

auto[1]

154016

1

T1

10847

T11

2

T14

3

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

259247

1

T1

16924

T2

1062

T11

1340

auto[0]

auto[0]

auto[0]

auto[1]

283991

1

T1

19766

T2

888

T3

199

auto[0]

auto[0]

auto[1]

auto[0]

1081003

1

T1

16785

T2

951

T3

427

auto[0]

auto[0]

auto[1]

auto[1]

265468

1

T1

15309

T2

1085

T11

2278

auto[0]

auto[1]

auto[0]

auto[0]

456550

1

T1

18095

T2

1064

T11

2630

auto[0]

auto[1]

auto[0]

auto[1]

466117

1

T1

17034

T2

386

T11

1862

auto[0]

auto[1]

auto[1]

auto[0]

481395

1

T1

11675

T2

851

T3

1717

auto[0]

auto[1]

auto[1]

auto[1]

472638

1

T1

18226

T2

479

T3

550

auto[1]

auto[0]

auto[0]

auto[0]

220387

1

T1

4341

T2

590

T11

854

auto[1]

auto[0]

auto[0]

auto[1]

238135

1

T1

2705

T2

565

T3

111

auto[1]

auto[0]

auto[1]

auto[0]

3416476

1

T1

2726

T2

526

T3

277

auto[1]

auto[0]

auto[1]

auto[1]

229676

1

T1

3674

T2

638

T11

1384

auto[1]

auto[1]

auto[0]

auto[0]

379939

1

T1

6620

T2

590

T11

2384

auto[1]

auto[1]

auto[0]

auto[1]

350636

1

T1

1240

T2

180

T11

1156

auto[1]

auto[1]

auto[1]

auto[0]

369407

1

T1

682

T2

453

T3

915

auto[1]

auto[1]

auto[1]

auto[1]

370288

1

T1

3231

T2

273

T3

257

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

461114

1

T1

18582

T2

1652

T11

2193

auto[0]

auto[0]

auto[0]

auto[1]

501926

1

T1

21557

T2

1453

T3

310

auto[0]

auto[0]

auto[1]

auto[0]

4474265

1

T1

19184

T2

1477

T3

704

auto[0]

auto[0]

auto[1]

auto[1]

477085

1

T1

18588

T2

1723

T11

3662

auto[0]

auto[1]

auto[0]

auto[0]

821870

1

T1

22323

T2

1654

T11

5014

auto[0]

auto[1]

auto[0]

auto[1]

792813

1

T1

15811

T2

566

T11

3018

auto[0]

auto[1]

auto[1]

auto[0]

832168

1

T1

11500

T2

1304

T3

2632

auto[0]

auto[1]

auto[1]

auto[1]

826096

1

T1

20641

T2

752

T3

807

auto[1]

auto[0]

auto[0]

auto[0]

18520

1

T1

2683

T11

1

T50

1

auto[1]

auto[0]

auto[0]

auto[1]

20200

1

T1

914

T11

1

T50

1

auto[1]

auto[0]

auto[1]

auto[0]

23214

1

T1

327

T14

1

T52

1

auto[1]

auto[0]

auto[1]

auto[1]

18059

1

T1

395

T52

1

T12

74

auto[1]

auto[1]

auto[0]

auto[0]

14619

1

T1

2392

T52

1

T12

318

auto[1]

auto[1]

auto[0]

auto[1]

23940

1

T1

2463

T12

172

T53

1

auto[1]

auto[1]

auto[1]

auto[0]

18634

1

T1

857

T51

1

T52

1

auto[1]

auto[1]

auto[1]

auto[1]

16830

1

T1

816

T14

2

T51

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	238907	1			T1	7024		T2	590		T11	855
fifo_depth[0]	auto[0]	auto[0]	auto[1]	258335	1			T1	3619		T2	565		T3	111
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3439690	1			T1	3053		T2	526		T3	277
fifo_depth[0]	auto[0]	auto[1]	auto[1]	247735	1			T1	4069		T2	638		T11	1384
fifo_depth[0]	auto[1]	auto[0]	auto[0]	394558	1			T1	9012		T2	590		T11	2384
fifo_depth[0]	auto[1]	auto[0]	auto[1]	374576	1			T1	3703		T2	180		T11	1156
fifo_depth[0]	auto[1]	auto[1]	auto[0]	388041	1			T1	1539		T2	453		T3	915
fifo_depth[0]	auto[1]	auto[1]	auto[1]	387118	1			T1	4047		T2	273		T3	257
fifo_depth[1]	auto[0]	auto[0]	auto[0]	18266	1			T1	410		T2	131		T11	142
fifo_depth[1]	auto[0]	auto[0]	auto[1]	20398	1			T1	358		T2	105		T3	24
fifo_depth[1]	auto[0]	auto[1]	auto[0]	214948	1			T1	379		T2	120		T3	56
fifo_depth[1]	auto[0]	auto[1]	auto[1]	20098	1			T1	489		T2	123		T11	255
fifo_depth[1]	auto[1]	auto[0]	auto[0]	43622	1			T1	669		T2	110		T11	334
fifo_depth[1]	auto[1]	auto[0]	auto[1]	42117	1			T1	273		T2	37		T11	224
fifo_depth[1]	auto[1]	auto[1]	auto[0]	44373	1			T1	140		T2	101		T3	202
fifo_depth[1]	auto[1]	auto[1]	auto[1]	43965	1			T1	442		T2	54		T3	66
fifo_depth[2]	auto[0]	auto[0]	auto[0]	15873	1			T1	399		T2	113		T11	168
fifo_depth[2]	auto[0]	auto[0]	auto[1]	17766	1			T1	514		T2	106		T3	23
fifo_depth[2]	auto[0]	auto[1]	auto[0]	169120	1			T1	403		T2	112		T3	50
fifo_depth[2]	auto[0]	auto[1]	auto[1]	17432	1			T1	402		T2	125		T11	270
fifo_depth[2]	auto[1]	auto[0]	auto[0]	40682	1			T1	668		T2	122		T11	359
fifo_depth[2]	auto[1]	auto[0]	auto[1]	38563	1			T1	237		T2	37		T11	228
fifo_depth[2]	auto[1]	auto[1]	auto[0]	40367	1			T1	131		T2	101		T3	209
fifo_depth[2]	auto[1]	auto[1]	auto[1]	41174	1			T1	464		T2	51		T3	51
fifo_depth[3]	auto[0]	auto[0]	auto[0]	13408	1			T1	366		T2	116		T11	143
fifo_depth[3]	auto[0]	auto[0]	auto[1]	14758	1			T1	460		T2	93		T3	21
fifo_depth[3]	auto[0]	auto[1]	auto[0]	129674	1			T1	401		T2	102		T3	40
fifo_depth[3]	auto[0]	auto[1]	auto[1]	14702	1			T1	406		T2	145		T11	259
fifo_depth[3]	auto[1]	auto[0]	auto[0]	36530	1			T1	575		T2	127		T11	342
fifo_depth[3]	auto[1]	auto[0]	auto[1]	34917	1			T1	268		T2	36		T11	200
fifo_depth[3]	auto[1]	auto[1]	auto[0]	36019	1			T1	128		T2	99		T3	184
fifo_depth[3]	auto[1]	auto[1]	auto[1]	37478	1			T1	457		T2	56		T3	59
fifo_depth[4]	auto[0]	auto[0]	auto[0]	12839	1			T1	310		T2	113		T11	140
fifo_depth[4]	auto[0]	auto[0]	auto[1]	14882	1			T1	895		T2	110		T3	15
fifo_depth[4]	auto[0]	auto[1]	auto[0]	96580	1			T1	383		T2	109		T3	54
fifo_depth[4]	auto[0]	auto[1]	auto[1]	14171	1			T1	338		T2	117		T11	263
fifo_depth[4]	auto[1]	auto[0]	auto[0]	35050	1			T1	615		T2	119		T11	289
fifo_depth[4]	auto[1]	auto[0]	auto[1]	34903	1			T1	273		T2	49		T11	216
fifo_depth[4]	auto[1]	auto[1]	auto[0]	35102	1			T1	211		T2	92		T3	195
fifo_depth[4]	auto[1]	auto[1]	auto[1]	36509	1			T1	473		T2	57		T3	62
fifo_depth[5]	auto[0]	auto[0]	auto[0]	11630	1			T1	246		T2	106		T11	160
fifo_depth[5]	auto[0]	auto[0]	auto[1]	12304	1			T1	511		T2	88		T3	26
fifo_depth[5]	auto[0]	auto[1]	auto[0]	79945	1			T1	487		T2	110		T3	46
fifo_depth[5]	auto[0]	auto[1]	auto[1]	12678	1			T1	427		T2	124		T11	247
fifo_depth[5]	auto[1]	auto[0]	auto[0]	33306	1			T1	463		T2	121		T11	262
fifo_depth[5]	auto[1]	auto[0]	auto[1]	32600	1			T1	297		T2	51		T11	214
fifo_depth[5]	auto[1]	auto[1]	auto[0]	33115	1			T1	133		T2	87		T3	182
fifo_depth[5]	auto[1]	auto[1]	auto[1]	34597	1			T1	471		T2	47		T3	59
fifo_depth[6]	auto[0]	auto[0]	auto[0]	11515	1			T1	352		T2	128		T11	138
fifo_depth[6]	auto[0]	auto[0]	auto[1]	13269	1			T1	939		T2	102		T3	22
fifo_depth[6]	auto[0]	auto[1]	auto[0]	69957	1			T1	338		T2	91		T3	50
fifo_depth[6]	auto[0]	auto[1]	auto[1]	12712	1			T1	317		T2	99		T11	248
fifo_depth[6]	auto[1]	auto[0]	auto[0]	32647	1			T1	638		T2	114		T11	248
fifo_depth[6]	auto[1]	auto[0]	auto[1]	33239	1			T1	247		T2	42		T11	188
fifo_depth[6]	auto[1]	auto[1]	auto[0]	32988	1			T1	221		T2	96		T3	204
fifo_depth[6]	auto[1]	auto[1]	auto[1]	34189	1			T1	454		T2	48		T3	68
fifo_depth[7]	auto[0]	auto[0]	auto[0]	10630	1			T1	303		T2	113		T11	139
fifo_depth[7]	auto[0]	auto[0]	auto[1]	11197	1			T1	561		T2	85		T3	16
fifo_depth[7]	auto[0]	auto[1]	auto[0]	55656	1			T1	470		T2	87		T3	43
fifo_depth[7]	auto[0]	auto[1]	auto[1]	11589	1			T1	412		T2	112		T11	211
fifo_depth[7]	auto[1]	auto[0]	auto[0]	30545	1			T1	509		T2	117		T11	229
fifo_depth[7]	auto[1]	auto[0]	auto[1]	29734	1			T1	325		T2	38		T11	184
fifo_depth[7]	auto[1]	auto[1]	auto[0]	30085	1			T1	152		T2	84		T3	165
fifo_depth[7]	auto[1]	auto[1]	auto[1]	31452	1			T1	500		T2	36		T3	49
fifo_depth[8]	auto[0]	auto[0]	auto[0]	11363	1			T1	323		T2	92		T11	104
fifo_depth[8]	auto[0]	auto[0]	auto[1]	13629	1			T1	957		T2	77		T3	16
fifo_depth[8]	auto[0]	auto[1]	auto[0]	43681	1			T1	944		T2	86		T3	32
fifo_depth[8]	auto[0]	auto[1]	auto[1]	12042	1			T1	352		T2	82		T11	195
fifo_depth[8]	auto[1]	auto[0]	auto[0]	27229	1			T1	526		T2	86		T11	209
fifo_depth[8]	auto[1]	auto[0]	auto[1]	28491	1			T1	563		T2	33		T11	150
fifo_depth[8]	auto[1]	auto[1]	auto[0]	30131	1			T1	225		T2	78		T3	128
fifo_depth[8]	auto[1]	auto[1]	auto[1]	29049	1			T1	661		T2	43		T3	47
fifo_depth[9]	auto[0]	auto[0]	auto[0]	7414	1			T1	228		T2	61		T11	85
fifo_depth[9]	auto[0]	auto[0]	auto[1]	7846	1			T1	440		T2	54		T3	10
fifo_depth[9]	auto[0]	auto[1]	auto[0]	28818	1			T1	403		T2	53		T3	27
fifo_depth[9]	auto[0]	auto[1]	auto[1]	8113	1			T1	363		T2	71		T11	142
fifo_depth[9]	auto[1]	auto[0]	auto[0]	19781	1			T1	337		T2	64		T11	148
fifo_depth[9]	auto[1]	auto[0]	auto[1]	19543	1			T1	264		T2	21		T11	110
fifo_depth[9]	auto[1]	auto[1]	auto[0]	19618	1			T1	194		T2	54		T3	108
fifo_depth[9]	auto[1]	auto[1]	auto[1]	20819	1			T1	489		T2	40		T3	40
fifo_depth[10]	auto[0]	auto[0]	auto[0]	7165	1			T1	241		T2	40		T11	57
fifo_depth[10]	auto[0]	auto[0]	auto[1]	7601	1			T1	900		T2	32		T3	12
fifo_depth[10]	auto[0]	auto[1]	auto[0]	20817	1			T1	915		T2	40		T3	16
fifo_depth[10]	auto[0]	auto[1]	auto[1]	7588	1			T1	427		T2	50		T11	91
fifo_depth[10]	auto[1]	auto[0]	auto[0]	15155	1			T1	358		T2	38		T11	104
fifo_depth[10]	auto[1]	auto[0]	auto[1]	15594	1			T1	307		T2	14		T11	76
fifo_depth[10]	auto[1]	auto[1]	auto[0]	16153	1			T1	156		T2	32		T3	70
fifo_depth[10]	auto[1]	auto[1]	auto[1]	15678	1			T1	413		T2	21		T3	23
fifo_depth[11]	auto[0]	auto[0]	auto[0]	4512	1			T1	181		T2	25		T11	32
fifo_depth[11]	auto[0]	auto[0]	auto[1]	4650	1			T1	395		T2	22		T3	8
fifo_depth[11]	auto[0]	auto[1]	auto[0]	12283	1			T1	493		T2	20		T3	7
fifo_depth[11]	auto[0]	auto[1]	auto[1]	4898	1			T1	434		T2	22		T11	44
fifo_depth[11]	auto[1]	auto[0]	auto[0]	9399	1			T1	242		T2	27		T11	54
fifo_depth[11]	auto[1]	auto[0]	auto[1]	9268	1			T1	165		T2	16		T11	46
fifo_depth[11]	auto[1]	auto[1]	auto[0]	9644	1			T1	135		T2	14		T3	34
fifo_depth[11]	auto[1]	auto[1]	auto[1]	9759	1			T1	284		T2	13		T3	10
fifo_depth[12]	auto[0]	auto[0]	auto[0]	6035	1			T1	309		T2	11		T11	16
fifo_depth[12]	auto[0]	auto[0]	auto[1]	7888	1			T1	1104		T2	7		T3	4
fifo_depth[12]	auto[0]	auto[1]	auto[0]	10918	1			T1	1268		T2	14		T3	3
fifo_depth[12]	auto[0]	auto[1]	auto[1]	6189	1			T1	402		T2	12		T11	29
fifo_depth[12]	auto[1]	auto[0]	auto[0]	9100	1			T1	450		T2	10		T11	30
fifo_depth[12]	auto[1]	auto[0]	auto[1]	10053	1			T1	424		T2	5		T11	19
fifo_depth[12]	auto[1]	auto[1]	auto[0]	11625	1			T1	212		T2	9		T3	20
fifo_depth[12]	auto[1]	auto[1]	auto[1]	8637	1			T1	440		T2	10		T3	9
fifo_depth[13]	auto[0]	auto[0]	auto[0]	3182	1			T1	237		T2	5		T11	9
fifo_depth[13]	auto[0]	auto[0]	auto[1]	3555	1			T1	439		T2	4		T3	2
fifo_depth[13]	auto[0]	auto[1]	auto[0]	5918	1			T1	525		T2	5		T3	2
fifo_depth[13]	auto[0]	auto[1]	auto[1]	3534	1			T1	458		T2	1		T11	14
fifo_depth[13]	auto[1]	auto[0]	auto[0]	4975	1			T1	198		T2	7		T11	10
fifo_depth[13]	auto[1]	auto[0]	auto[1]	4304	1			T1	175		T2	6		T11	3
fifo_depth[13]	auto[1]	auto[1]	auto[0]	5283	1			T1	176		T2	4		T3	10
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4519	1			T1	287		T2	2		T3	3
fifo_depth[14]	auto[0]	auto[0]	auto[0]	4862	1			T1	337		T2	5		T11	3
fifo_depth[14]	auto[0]	auto[0]	auto[1]	5558	1			T1	1049		T2	2		T11	2
fifo_depth[14]	auto[0]	auto[1]	auto[0]	6777	1			T1	1155		T2	2		T3	1
fifo_depth[14]	auto[0]	auto[1]	auto[1]	4903	1			T1	390		T2	2		T11	3
fifo_depth[14]	auto[1]	auto[0]	auto[0]	6031	1			T1	368		T2	2		T11	6
fifo_depth[14]	auto[1]	auto[0]	auto[1]	7045	1			T1	572		T2	1		T11	1
fifo_depth[14]	auto[1]	auto[1]	auto[0]	7699	1			T1	312		T3	2		T11	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	5866	1			T1	476		T2	1		T3	3
fifo_depth[15]	auto[0]	auto[0]	auto[0]	3365	1			T1	290		T2	2		T12	52
fifo_depth[15]	auto[0]	auto[0]	auto[1]	3301	1			T1	373		T38	1		T12	14
fifo_depth[15]	auto[0]	auto[1]	auto[0]	4292	1			T1	484		T27	3		T34	3
fifo_depth[15]	auto[0]	auto[1]	auto[1]	3392	1			T1	458		T11	2		T12	44
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3760	1			T1	189		T11	1		T38	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	3901	1			T1	392		T11	1		T39	3
fifo_depth[15]	auto[1]	auto[1]	auto[0]	4876	1			T1	299		T3	4		T38	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	3556	1			T1	421		T3	1		T11	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	11952	1			T1	1484		T2	1		T12	447
fifo_depth[16]	auto[0]	auto[0]	auto[1]	16061	1			T1	1796		T2	1		T12	34
fifo_depth[16]	auto[0]	auto[1]	auto[0]	13816	1			T1	1349		T11	1		T27	1
fifo_depth[16]	auto[0]	auto[1]	auto[1]	14430	1			T1	4030		T12	7		T22	5
fifo_depth[16]	auto[1]	auto[0]	auto[0]	14593	1			T1	1150		T12	1381		T22	2
fifo_depth[16]	auto[1]	auto[0]	auto[1]	13057	1			T1	1258		T11	1		T39	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	17621	1			T1	734		T39	1		T22	398
fifo_depth[16]	auto[1]	auto[1]	auto[1]	12654	1			T1	634		T81	1		T12	79