Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13569458	1			T1	98782		T2	11089		T3	4635
all_pins[1]	13569458	1			T1	98782		T2	11089		T3	4635
all_pins[2]	13569458	1			T1	98782		T2	11089		T3	4635

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	38448894	1			T1	256835		T2	33217		T3	13882
values[0x1]	2259480	1			T1	39511		T2	50		T3	23
transitions[0x0=>0x1]	2259304	1			T1	39508		T2	50		T3	23
transitions[0x1=>0x0]	2259323	1			T1	39508		T2	50		T3	23

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13521846	1			T1	98290		T2	11039		T3	4612
all_pins[0]	values[0x1]	47612	1			T1	492		T2	50		T3	23
all_pins[0]	transitions[0x0=>0x1]	47539	1			T1	491		T2	50		T3	23
all_pins[0]	transitions[0x1=>0x0]	2211256	1			T1	38985		T11	12019		T13	9997
all_pins[1]	values[0x0]	13568900	1			T1	98749		T2	11089		T3	4635
all_pins[1]	values[0x1]	558	1			T1	33		T12	1		T4	89
all_pins[1]	transitions[0x0=>0x1]	505	1			T1	32		T4	89		T109	1
all_pins[1]	transitions[0x1=>0x0]	47559	1			T1	491		T2	50		T3	23
all_pins[2]	values[0x0]	11358148	1			T1	59796		T2	11089		T3	4635
all_pins[2]	values[0x1]	2211310	1			T1	38986		T11	12019		T13	9997
all_pins[2]	transitions[0x0=>0x1]	2211260	1			T1	38985		T11	12019		T13	9997
all_pins[2]	transitions[0x1=>0x0]	508	1			T1	32		T12	1		T4	89