Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 988 1 T1 10 T12 7 T4 39
all_values[1] 988 1 T1 10 T12 7 T4 39
all_values[2] 988 1 T1 10 T12 7 T4 39


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1489 1 T1 11 T12 10 T4 62
auto[1] 1475 1 T1 19 T12 11 T4 55


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1034 1 T1 8 T12 2 T4 55
auto[1] 1930 1 T1 22 T12 19 T4 62


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1643 1 T1 13 T12 11 T4 76
auto[1] 1321 1 T1 17 T12 10 T4 41


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 170 1 T1 1 T4 12 T109 4
all_values[0] auto[0] auto[0] auto[1] 96 1 T1 3 T12 2 T4 3
all_values[0] auto[0] auto[1] auto[0] 179 1 T1 1 T4 6 T109 1
all_values[0] auto[0] auto[1] auto[1] 90 1 T4 3 T109 3 T26 4
all_values[0] auto[1] auto[0] auto[1] 219 1 T1 1 T12 1 T4 7
all_values[0] auto[1] auto[1] auto[1] 234 1 T1 4 T12 4 T4 8
all_values[1] auto[0] auto[0] auto[0] 188 1 T1 1 T12 1 T4 5
all_values[1] auto[0] auto[0] auto[1] 124 1 T12 2 T4 8 T109 1
all_values[1] auto[0] auto[1] auto[0] 158 1 T1 1 T4 10 T109 7
all_values[1] auto[0] auto[1] auto[1] 107 1 T1 2 T12 1 T4 2
all_values[1] auto[1] auto[0] auto[1] 207 1 T1 2 T12 2 T4 5
all_values[1] auto[1] auto[1] auto[1] 204 1 T1 4 T12 1 T4 9
all_values[2] auto[0] auto[0] auto[0] 177 1 T1 1 T4 13 T26 7
all_values[2] auto[0] auto[0] auto[1] 99 1 T12 1 T4 4 T109 3
all_values[2] auto[0] auto[1] auto[0] 162 1 T1 3 T12 1 T4 9
all_values[2] auto[0] auto[1] auto[1] 93 1 T12 3 T4 1 T109 3
all_values[2] auto[1] auto[0] auto[1] 209 1 T1 2 T12 1 T4 5
all_values[2] auto[1] auto[1] auto[1] 248 1 T1 4 T12 1 T4 7


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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