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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.39 92.80 85.92 100.00 76.32 88.15 99.49 69.08


Total test records in report: 733
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T31 /workspace/coverage/default/1.hmac_sec_cm.3271495199 Mar 12 01:44:37 PM PDT 24 Mar 12 01:44:38 PM PDT 24 643437139 ps
T540 /workspace/coverage/default/30.hmac_wipe_secret.1148155214 Mar 12 01:50:29 PM PDT 24 Mar 12 01:50:52 PM PDT 24 2169284268 ps
T541 /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.3125581647 Mar 12 01:52:15 PM PDT 24 Mar 12 02:00:30 PM PDT 24 52067843500 ps
T542 /workspace/coverage/default/38.hmac_datapath_stress.4063831899 Mar 12 01:51:05 PM PDT 24 Mar 12 01:53:19 PM PDT 24 9231723431 ps
T543 /workspace/coverage/default/45.hmac_back_pressure.4253809992 Mar 12 01:52:04 PM PDT 24 Mar 12 01:52:17 PM PDT 24 307475062 ps
T544 /workspace/coverage/default/26.hmac_datapath_stress.1615793412 Mar 12 01:50:25 PM PDT 24 Mar 12 01:52:27 PM PDT 24 8368765895 ps
T545 /workspace/coverage/default/7.hmac_back_pressure.3095645302 Mar 12 01:45:00 PM PDT 24 Mar 12 01:45:46 PM PDT 24 18827372660 ps
T546 /workspace/coverage/default/22.hmac_smoke.3607820826 Mar 12 01:49:40 PM PDT 24 Mar 12 01:49:45 PM PDT 24 6518411235 ps
T547 /workspace/coverage/default/9.hmac_smoke.1424518317 Mar 12 01:45:07 PM PDT 24 Mar 12 01:45:14 PM PDT 24 1616672610 ps
T548 /workspace/coverage/default/17.hmac_wipe_secret.1916134586 Mar 12 01:49:58 PM PDT 24 Mar 12 01:51:17 PM PDT 24 4192459574 ps
T549 /workspace/coverage/default/25.hmac_alert_test.3082717053 Mar 12 01:50:24 PM PDT 24 Mar 12 01:50:26 PM PDT 24 13963893 ps
T550 /workspace/coverage/default/8.hmac_test_sha_vectors.2405206185 Mar 12 01:45:08 PM PDT 24 Mar 12 01:54:28 PM PDT 24 85417274849 ps
T551 /workspace/coverage/default/31.hmac_long_msg.1990695913 Mar 12 01:50:23 PM PDT 24 Mar 12 01:51:57 PM PDT 24 6992136846 ps
T552 /workspace/coverage/default/36.hmac_smoke.3842913873 Mar 12 01:50:56 PM PDT 24 Mar 12 01:50:59 PM PDT 24 226496660 ps
T553 /workspace/coverage/default/37.hmac_long_msg.1234753271 Mar 12 01:51:05 PM PDT 24 Mar 12 01:53:09 PM PDT 24 6483964550 ps
T554 /workspace/coverage/default/41.hmac_back_pressure.454878640 Mar 12 01:51:31 PM PDT 24 Mar 12 01:51:56 PM PDT 24 489395911 ps
T555 /workspace/coverage/default/17.hmac_alert_test.1050792261 Mar 12 01:50:06 PM PDT 24 Mar 12 01:50:07 PM PDT 24 84639366 ps
T556 /workspace/coverage/default/7.hmac_wipe_secret.3201567525 Mar 12 01:45:00 PM PDT 24 Mar 12 01:45:09 PM PDT 24 592541906 ps
T557 /workspace/coverage/default/3.hmac_smoke.928070308 Mar 12 01:44:39 PM PDT 24 Mar 12 01:44:45 PM PDT 24 354697680 ps
T558 /workspace/coverage/default/29.hmac_test_sha_vectors.773896674 Mar 12 01:50:26 PM PDT 24 Mar 12 01:57:33 PM PDT 24 30025840127 ps
T559 /workspace/coverage/default/34.hmac_back_pressure.542681111 Mar 12 01:50:37 PM PDT 24 Mar 12 01:50:53 PM PDT 24 378577346 ps
T560 /workspace/coverage/default/31.hmac_error.3098074192 Mar 12 01:50:33 PM PDT 24 Mar 12 01:53:16 PM PDT 24 24644397500 ps
T561 /workspace/coverage/default/37.hmac_burst_wr.3269741718 Mar 12 01:51:06 PM PDT 24 Mar 12 01:51:32 PM PDT 24 4835952587 ps
T562 /workspace/coverage/default/22.hmac_long_msg.695759073 Mar 12 01:50:06 PM PDT 24 Mar 12 01:50:23 PM PDT 24 671081193 ps
T563 /workspace/coverage/default/39.hmac_wipe_secret.2249181771 Mar 12 01:51:15 PM PDT 24 Mar 12 01:51:44 PM PDT 24 3972963334 ps
T564 /workspace/coverage/default/36.hmac_long_msg.2465401210 Mar 12 01:50:56 PM PDT 24 Mar 12 01:52:05 PM PDT 24 6701904164 ps
T565 /workspace/coverage/default/30.hmac_stress_all.2932048952 Mar 12 01:50:32 PM PDT 24 Mar 12 02:20:43 PM PDT 24 362000931374 ps
T566 /workspace/coverage/default/24.hmac_burst_wr.2489226075 Mar 12 01:50:24 PM PDT 24 Mar 12 01:50:52 PM PDT 24 2577686918 ps
T567 /workspace/coverage/default/49.hmac_alert_test.3861825902 Mar 12 01:52:12 PM PDT 24 Mar 12 01:52:13 PM PDT 24 57644863 ps
T568 /workspace/coverage/default/0.hmac_stress_all.2774917017 Mar 12 01:44:29 PM PDT 24 Mar 12 02:16:27 PM PDT 24 100308408500 ps
T569 /workspace/coverage/default/39.hmac_stress_all.3528706498 Mar 12 01:51:16 PM PDT 24 Mar 12 01:54:46 PM PDT 24 10576243456 ps
T570 /workspace/coverage/default/49.hmac_long_msg.4141977351 Mar 12 01:52:02 PM PDT 24 Mar 12 01:53:36 PM PDT 24 21525130891 ps
T571 /workspace/coverage/default/4.hmac_datapath_stress.1201951843 Mar 12 01:44:47 PM PDT 24 Mar 12 01:46:08 PM PDT 24 1327969466 ps
T572 /workspace/coverage/default/10.hmac_datapath_stress.2534027695 Mar 12 01:45:18 PM PDT 24 Mar 12 01:47:37 PM PDT 24 2200406643 ps
T573 /workspace/coverage/default/14.hmac_test_sha_vectors.1303998195 Mar 12 01:45:50 PM PDT 24 Mar 12 01:54:05 PM PDT 24 103225731135 ps
T574 /workspace/coverage/default/21.hmac_stress_all.3519277923 Mar 12 01:50:00 PM PDT 24 Mar 12 02:32:40 PM PDT 24 132445665085 ps
T575 /workspace/coverage/default/15.hmac_burst_wr.853650827 Mar 12 01:45:57 PM PDT 24 Mar 12 01:46:06 PM PDT 24 162632787 ps
T576 /workspace/coverage/default/40.hmac_datapath_stress.70212904 Mar 12 01:51:15 PM PDT 24 Mar 12 01:53:55 PM PDT 24 2543769210 ps
T577 /workspace/coverage/default/7.hmac_test_sha_vectors.2229222626 Mar 12 01:45:01 PM PDT 24 Mar 12 01:53:49 PM PDT 24 116459436298 ps
T578 /workspace/coverage/default/3.hmac_test_hmac_vectors.3068166840 Mar 12 01:44:39 PM PDT 24 Mar 12 01:44:41 PM PDT 24 265706578 ps
T579 /workspace/coverage/default/13.hmac_smoke.3411694652 Mar 12 01:45:36 PM PDT 24 Mar 12 01:45:43 PM PDT 24 3443923309 ps
T580 /workspace/coverage/default/4.hmac_wipe_secret.3621178147 Mar 12 01:44:47 PM PDT 24 Mar 12 01:45:13 PM PDT 24 6679526443 ps
T581 /workspace/coverage/default/3.hmac_back_pressure.352156671 Mar 12 01:44:39 PM PDT 24 Mar 12 01:45:07 PM PDT 24 6437524159 ps
T582 /workspace/coverage/default/24.hmac_datapath_stress.3581760292 Mar 12 01:50:24 PM PDT 24 Mar 12 01:51:53 PM PDT 24 6005690555 ps
T583 /workspace/coverage/default/23.hmac_stress_all.133149390 Mar 12 01:50:25 PM PDT 24 Mar 12 02:00:40 PM PDT 24 47877265519 ps
T584 /workspace/coverage/default/40.hmac_test_hmac_vectors.3056368011 Mar 12 01:51:15 PM PDT 24 Mar 12 01:51:17 PM PDT 24 108694131 ps
T585 /workspace/coverage/default/43.hmac_error.2044074412 Mar 12 01:51:41 PM PDT 24 Mar 12 01:51:52 PM PDT 24 1981598238 ps
T586 /workspace/coverage/default/29.hmac_alert_test.3361100567 Mar 12 01:50:24 PM PDT 24 Mar 12 01:50:26 PM PDT 24 44953509 ps
T587 /workspace/coverage/default/4.hmac_smoke.286676214 Mar 12 01:44:44 PM PDT 24 Mar 12 01:44:49 PM PDT 24 1556859906 ps
T48 /workspace/coverage/default/20.hmac_error.2303794970 Mar 12 01:49:56 PM PDT 24 Mar 12 01:50:45 PM PDT 24 3654930763 ps
T588 /workspace/coverage/default/19.hmac_long_msg.131284998 Mar 12 01:49:33 PM PDT 24 Mar 12 01:51:23 PM PDT 24 30086875538 ps
T589 /workspace/coverage/default/17.hmac_back_pressure.4234710432 Mar 12 01:49:55 PM PDT 24 Mar 12 01:50:03 PM PDT 24 313083783 ps
T590 /workspace/coverage/default/48.hmac_error.659312736 Mar 12 01:52:02 PM PDT 24 Mar 12 01:54:32 PM PDT 24 5240005435 ps
T591 /workspace/coverage/default/38.hmac_burst_wr.3128662863 Mar 12 01:51:06 PM PDT 24 Mar 12 01:51:36 PM PDT 24 1364194982 ps
T592 /workspace/coverage/default/7.hmac_test_hmac_vectors.1045683123 Mar 12 01:45:02 PM PDT 24 Mar 12 01:45:03 PM PDT 24 210023624 ps
T593 /workspace/coverage/default/4.hmac_stress_all.379678202 Mar 12 01:44:49 PM PDT 24 Mar 12 02:01:04 PM PDT 24 110104667687 ps
T594 /workspace/coverage/default/8.hmac_smoke.2045147556 Mar 12 01:45:01 PM PDT 24 Mar 12 01:45:07 PM PDT 24 188983921 ps
T595 /workspace/coverage/default/27.hmac_stress_all.3628905747 Mar 12 01:50:27 PM PDT 24 Mar 12 02:05:35 PM PDT 24 64572791176 ps
T596 /workspace/coverage/default/36.hmac_test_sha_vectors.4051412193 Mar 12 01:50:55 PM PDT 24 Mar 12 02:00:03 PM PDT 24 72310135253 ps
T32 /workspace/coverage/default/0.hmac_sec_cm.2300770910 Mar 12 01:44:29 PM PDT 24 Mar 12 01:44:30 PM PDT 24 90858435 ps
T597 /workspace/coverage/default/24.hmac_test_hmac_vectors.2813791942 Mar 12 01:50:12 PM PDT 24 Mar 12 01:50:13 PM PDT 24 41302284 ps
T598 /workspace/coverage/default/28.hmac_burst_wr.130685478 Mar 12 01:50:25 PM PDT 24 Mar 12 01:51:44 PM PDT 24 1616091169 ps
T599 /workspace/coverage/default/4.hmac_long_msg.1721713071 Mar 12 01:44:47 PM PDT 24 Mar 12 01:45:30 PM PDT 24 2702049291 ps
T600 /workspace/coverage/default/19.hmac_alert_test.3686037437 Mar 12 01:49:58 PM PDT 24 Mar 12 01:49:59 PM PDT 24 38922095 ps
T601 /workspace/coverage/default/48.hmac_back_pressure.3851206919 Mar 12 01:52:03 PM PDT 24 Mar 12 01:52:10 PM PDT 24 1139834921 ps
T602 /workspace/coverage/default/42.hmac_test_sha_vectors.2317374614 Mar 12 01:51:34 PM PDT 24 Mar 12 01:59:03 PM PDT 24 7952501262 ps
T603 /workspace/coverage/default/9.hmac_burst_wr.4022845377 Mar 12 01:45:08 PM PDT 24 Mar 12 01:45:58 PM PDT 24 13559525451 ps
T66 /workspace/coverage/default/24.hmac_stress_all.417945189 Mar 12 01:50:24 PM PDT 24 Mar 12 02:07:08 PM PDT 24 286163044677 ps
T604 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1172860956 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:03 PM PDT 24 16360684 ps
T58 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.106509034 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:04 PM PDT 24 304120876 ps
T59 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.428897631 Mar 12 12:29:27 PM PDT 24 Mar 12 12:29:30 PM PDT 24 365470016 ps
T60 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1431951724 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:19 PM PDT 24 28825454 ps
T54 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1416077973 Mar 12 12:29:04 PM PDT 24 Mar 12 12:29:07 PM PDT 24 325654976 ps
T605 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.613759209 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:05 PM PDT 24 39441372 ps
T606 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3699374701 Mar 12 12:28:59 PM PDT 24 Mar 12 12:29:00 PM PDT 24 56878499 ps
T55 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2176036133 Mar 12 12:29:20 PM PDT 24 Mar 12 12:29:24 PM PDT 24 233398065 ps
T607 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1402725022 Mar 12 12:29:03 PM PDT 24 Mar 12 12:29:04 PM PDT 24 34059882 ps
T608 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4131324240 Mar 12 12:29:20 PM PDT 24 Mar 12 12:29:24 PM PDT 24 173097712 ps
T609 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.211932357 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:04 PM PDT 24 234248963 ps
T610 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1736842915 Mar 12 12:28:59 PM PDT 24 Mar 12 12:28:59 PM PDT 24 57452006 ps
T611 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1754570036 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 148345418 ps
T67 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4188205007 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:19 PM PDT 24 985338696 ps
T68 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2177819662 Mar 12 12:28:58 PM PDT 24 Mar 12 12:28:59 PM PDT 24 208005202 ps
T612 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1412708130 Mar 12 12:29:20 PM PDT 24 Mar 12 12:29:21 PM PDT 24 89751358 ps
T69 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.909850549 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:18 PM PDT 24 389093775 ps
T70 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2913697900 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 17282671 ps
T56 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1047485912 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:20 PM PDT 24 548066370 ps
T93 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3251374664 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:11 PM PDT 24 417439113 ps
T613 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2379752675 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 35410581 ps
T614 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1052617790 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:20 PM PDT 24 214701220 ps
T615 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3785939457 Mar 12 12:29:10 PM PDT 24 Mar 12 12:29:11 PM PDT 24 129044778 ps
T616 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1528929791 Mar 12 12:29:13 PM PDT 24 Mar 12 12:29:14 PM PDT 24 107612149 ps
T617 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.758314543 Mar 12 12:29:33 PM PDT 24 Mar 12 12:29:35 PM PDT 24 48091801 ps
T618 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3408892635 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:18 PM PDT 24 42694417 ps
T619 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1991026934 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:19 PM PDT 24 36270286 ps
T620 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3434387702 Mar 12 12:29:19 PM PDT 24 Mar 12 12:29:22 PM PDT 24 49074286 ps
T621 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.255308227 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:21 PM PDT 24 67520383 ps
T622 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1979189507 Mar 12 12:29:14 PM PDT 24 Mar 12 12:29:15 PM PDT 24 42318937 ps
T71 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3236724983 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:02 PM PDT 24 73522068 ps
T623 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1806481081 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:18 PM PDT 24 17854658 ps
T112 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2286673093 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:20 PM PDT 24 320766881 ps
T624 /workspace/coverage/cover_reg_top/32.hmac_intr_test.752306336 Mar 12 12:29:14 PM PDT 24 Mar 12 12:29:15 PM PDT 24 12049541 ps
T94 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2943026170 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:18 PM PDT 24 29501068 ps
T625 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2972308681 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:12 PM PDT 24 730289322 ps
T626 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1043466554 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:02 PM PDT 24 286638854 ps
T95 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1950342622 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 32972734 ps
T110 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3680270111 Mar 12 12:29:07 PM PDT 24 Mar 12 12:29:10 PM PDT 24 362472126 ps
T627 /workspace/coverage/cover_reg_top/44.hmac_intr_test.683651879 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 39058476 ps
T116 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3378717889 Mar 12 12:29:03 PM PDT 24 Mar 12 12:29:07 PM PDT 24 763177576 ps
T628 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3244961014 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:04 PM PDT 24 378246329 ps
T629 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3952549262 Mar 12 12:28:58 PM PDT 24 Mar 12 12:29:01 PM PDT 24 863035795 ps
T630 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1830238912 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:02 PM PDT 24 13808707 ps
T631 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2390761187 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:19 PM PDT 24 14362771 ps
T632 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3082516249 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:03 PM PDT 24 35658148 ps
T633 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.516133581 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:02 PM PDT 24 62673948 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1445347357 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:01 PM PDT 24 169787853 ps
T635 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2233664849 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:04 PM PDT 24 156555670 ps
T636 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2586829976 Mar 12 12:29:11 PM PDT 24 Mar 12 12:29:11 PM PDT 24 15442783 ps
T637 /workspace/coverage/cover_reg_top/19.hmac_intr_test.890337254 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:19 PM PDT 24 242313630 ps
T115 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3391637697 Mar 12 12:29:19 PM PDT 24 Mar 12 12:29:21 PM PDT 24 1159566044 ps
T638 /workspace/coverage/cover_reg_top/10.hmac_intr_test.76616063 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:18 PM PDT 24 19718801 ps
T639 /workspace/coverage/cover_reg_top/7.hmac_intr_test.196411811 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:02 PM PDT 24 16754714 ps
T640 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2123953719 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:20 PM PDT 24 62773777 ps
T641 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1399193384 Mar 12 12:29:11 PM PDT 24 Mar 12 12:29:11 PM PDT 24 33301299 ps
T96 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.458174600 Mar 12 12:29:18 PM PDT 24 Mar 12 12:29:19 PM PDT 24 28295981 ps
T97 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2060460837 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:03 PM PDT 24 206343442 ps
T642 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.4046514312 Mar 12 12:29:14 PM PDT 24 Mar 12 12:29:15 PM PDT 24 12608276 ps
T643 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2484951616 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:01 PM PDT 24 12689895 ps
T644 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2416202037 Mar 12 12:29:14 PM PDT 24 Mar 12 12:29:15 PM PDT 24 15565919 ps
T645 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1042033554 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:04 PM PDT 24 89578480 ps
T646 /workspace/coverage/cover_reg_top/37.hmac_intr_test.686643776 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:18 PM PDT 24 86699765 ps
T647 /workspace/coverage/cover_reg_top/38.hmac_intr_test.416972629 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:19 PM PDT 24 32873237 ps
T648 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2564617173 Mar 12 12:29:09 PM PDT 24 Mar 12 12:29:10 PM PDT 24 37289479 ps
T649 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.626614181 Mar 12 12:28:59 PM PDT 24 Mar 12 12:29:01 PM PDT 24 210261708 ps
T650 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1805218342 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:21 PM PDT 24 122650573 ps
T651 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2625355514 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 45186197 ps
T98 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.869661428 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:10 PM PDT 24 2929420129 ps
T652 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4084199673 Mar 12 12:29:19 PM PDT 24 Mar 12 12:41:35 PM PDT 24 158609185684 ps
T653 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2871365666 Mar 12 12:29:13 PM PDT 24 Mar 12 12:29:14 PM PDT 24 12040689 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.88253580 Mar 12 12:28:59 PM PDT 24 Mar 12 12:29:05 PM PDT 24 104568939 ps
T654 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.589216777 Mar 12 12:29:19 PM PDT 24 Mar 12 12:29:28 PM PDT 24 66998051 ps
T655 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1516945088 Mar 12 12:29:13 PM PDT 24 Mar 12 12:29:13 PM PDT 24 12915903 ps
T113 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.294225635 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:06 PM PDT 24 422155124 ps
T656 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3001291816 Mar 12 12:29:11 PM PDT 24 Mar 12 12:29:12 PM PDT 24 13472895 ps
T657 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2802246267 Mar 12 12:29:03 PM PDT 24 Mar 12 12:29:05 PM PDT 24 63102607 ps
T658 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.203652702 Mar 12 12:28:59 PM PDT 24 Mar 12 12:29:00 PM PDT 24 34711304 ps
T659 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1841976321 Mar 12 12:29:03 PM PDT 24 Mar 12 12:29:04 PM PDT 24 21170545 ps
T100 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.305472258 Mar 12 12:28:58 PM PDT 24 Mar 12 12:28:59 PM PDT 24 208219036 ps
T660 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3165102168 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:03 PM PDT 24 205777454 ps
T661 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2591674561 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:05 PM PDT 24 116966930 ps
T662 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1448011247 Mar 12 12:29:06 PM PDT 24 Mar 12 12:29:10 PM PDT 24 66363586 ps
T101 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2670729815 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:07 PM PDT 24 219215770 ps
T663 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3639308574 Mar 12 12:29:14 PM PDT 24 Mar 12 12:29:15 PM PDT 24 15517743 ps
T111 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.686277993 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:20 PM PDT 24 176153718 ps
T664 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2278057622 Mar 12 12:29:18 PM PDT 24 Mar 12 12:29:20 PM PDT 24 144782968 ps
T114 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2804303620 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:19 PM PDT 24 193299930 ps
T665 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3926538128 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:01 PM PDT 24 1001090572 ps
T666 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.708141631 Mar 12 12:29:27 PM PDT 24 Mar 12 12:29:30 PM PDT 24 32930839 ps
T102 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2086990806 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:01 PM PDT 24 124965467 ps
T667 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3137761746 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:01 PM PDT 24 19203117 ps
T668 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3822332820 Mar 12 12:29:13 PM PDT 24 Mar 12 12:29:16 PM PDT 24 128748618 ps
T669 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1733394386 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:02 PM PDT 24 65980032 ps
T670 /workspace/coverage/cover_reg_top/36.hmac_intr_test.976292474 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:17 PM PDT 24 16959096 ps
T671 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1788366117 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:21 PM PDT 24 136787311 ps
T672 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1327088441 Mar 12 12:29:04 PM PDT 24 Mar 12 12:29:06 PM PDT 24 67870343 ps
T673 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.914883942 Mar 12 12:29:07 PM PDT 24 Mar 12 12:29:09 PM PDT 24 199378378 ps
T674 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2703002391 Mar 12 12:29:05 PM PDT 24 Mar 12 12:29:07 PM PDT 24 271205056 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3213586917 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:01 PM PDT 24 18882848 ps
T675 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2797147055 Mar 12 12:29:06 PM PDT 24 Mar 12 12:29:06 PM PDT 24 26867281 ps
T676 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2554729848 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:05 PM PDT 24 153523262 ps
T677 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3576933668 Mar 12 12:29:10 PM PDT 24 Mar 12 12:29:10 PM PDT 24 44104823 ps
T678 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3757677339 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:03 PM PDT 24 183647966 ps
T679 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.52448432 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 42313971 ps
T680 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1568633717 Mar 12 12:29:13 PM PDT 24 Mar 12 12:29:13 PM PDT 24 12478638 ps
T57 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1634942063 Mar 12 12:29:13 PM PDT 24 Mar 12 12:29:18 PM PDT 24 246215558 ps
T104 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4019922648 Mar 12 12:29:03 PM PDT 24 Mar 12 12:29:12 PM PDT 24 1064363095 ps
T681 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1643254808 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:19 PM PDT 24 429145539 ps
T105 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3211272154 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:19 PM PDT 24 112203480 ps
T682 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3133766454 Mar 12 12:29:19 PM PDT 24 Mar 12 12:29:20 PM PDT 24 18047566 ps
T683 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3512190715 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:12 PM PDT 24 3729689178 ps
T684 /workspace/coverage/cover_reg_top/13.hmac_intr_test.357920070 Mar 12 12:29:20 PM PDT 24 Mar 12 12:29:21 PM PDT 24 23205915 ps
T106 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3866640851 Mar 12 12:28:59 PM PDT 24 Mar 12 12:29:00 PM PDT 24 35214005 ps
T685 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1997386977 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:01 PM PDT 24 30242862 ps
T686 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2838004793 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:13 PM PDT 24 2807151119 ps
T687 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1242191897 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:20 PM PDT 24 213701348 ps
T688 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2194940861 Mar 12 12:29:32 PM PDT 24 Mar 12 12:29:34 PM PDT 24 406500696 ps
T689 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3355912016 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:04 PM PDT 24 136415492 ps
T690 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3555469085 Mar 12 12:29:12 PM PDT 24 Mar 12 12:29:13 PM PDT 24 17580904 ps
T691 /workspace/coverage/cover_reg_top/22.hmac_intr_test.812003287 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:15 PM PDT 24 48434775 ps
T107 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1862348452 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:03 PM PDT 24 29994710 ps
T692 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3197641688 Mar 12 12:29:03 PM PDT 24 Mar 12 12:29:05 PM PDT 24 26303311 ps
T693 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1050364714 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:18 PM PDT 24 120360985 ps
T694 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3471995493 Mar 12 12:29:20 PM PDT 24 Mar 12 12:29:21 PM PDT 24 27558282 ps
T695 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1734383322 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:19 PM PDT 24 437017521 ps
T696 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1203218746 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:21 PM PDT 24 180211466 ps
T697 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3822756969 Mar 12 12:29:03 PM PDT 24 Mar 12 12:29:08 PM PDT 24 1037268035 ps
T698 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2339632289 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:20 PM PDT 24 106070255 ps
T699 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3602625897 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:04 PM PDT 24 181364521 ps
T700 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.4048857364 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 81402746 ps
T701 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2904067947 Mar 12 12:29:02 PM PDT 24 Mar 12 12:29:06 PM PDT 24 524573891 ps
T702 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2478508865 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:04 PM PDT 24 169061886 ps
T703 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3777482760 Mar 12 12:29:12 PM PDT 24 Mar 12 12:29:13 PM PDT 24 12811584 ps
T108 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4257056791 Mar 12 12:29:13 PM PDT 24 Mar 12 12:29:14 PM PDT 24 138558544 ps
T704 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3567795167 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:21 PM PDT 24 116957242 ps
T705 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1914847054 Mar 12 12:28:59 PM PDT 24 Mar 12 12:29:00 PM PDT 24 31822874 ps
T706 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3516891792 Mar 12 12:29:19 PM PDT 24 Mar 12 12:29:22 PM PDT 24 67710170 ps
T707 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2945789815 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:19 PM PDT 24 84256953 ps
T708 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3741572191 Mar 12 12:29:11 PM PDT 24 Mar 12 12:29:12 PM PDT 24 27685267 ps
T709 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.874860511 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:19 PM PDT 24 33823577 ps
T710 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.637273786 Mar 12 12:29:17 PM PDT 24 Mar 12 12:29:20 PM PDT 24 296913545 ps
T711 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2386281881 Mar 12 12:29:19 PM PDT 24 Mar 12 12:29:20 PM PDT 24 33749206 ps
T712 /workspace/coverage/cover_reg_top/16.hmac_intr_test.931679614 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 19286226 ps
T713 /workspace/coverage/cover_reg_top/29.hmac_intr_test.343505619 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:16 PM PDT 24 25122029 ps
T714 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2062323744 Mar 12 12:29:13 PM PDT 24 Mar 12 12:29:14 PM PDT 24 17278583 ps
T715 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2134315772 Mar 12 12:29:05 PM PDT 24 Mar 12 12:29:06 PM PDT 24 510053799 ps
T716 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3975609470 Mar 12 12:30:19 PM PDT 24 Mar 12 12:30:20 PM PDT 24 48162496 ps
T717 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1615680733 Mar 12 12:29:13 PM PDT 24 Mar 12 12:29:14 PM PDT 24 160487598 ps
T718 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3844784809 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:17 PM PDT 24 15071206 ps
T719 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.936580587 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:18 PM PDT 24 23501860 ps
T720 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2228628314 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:05 PM PDT 24 267652478 ps
T721 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1544092834 Mar 12 12:29:15 PM PDT 24 Mar 12 12:29:19 PM PDT 24 331078696 ps
T722 /workspace/coverage/cover_reg_top/0.hmac_intr_test.964413156 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:02 PM PDT 24 55213470 ps
T723 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2867320644 Mar 12 12:29:05 PM PDT 24 Mar 12 12:29:09 PM PDT 24 139972197 ps
T724 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2482259667 Mar 12 12:29:16 PM PDT 24 Mar 12 12:29:18 PM PDT 24 56745230 ps
T725 /workspace/coverage/cover_reg_top/11.hmac_intr_test.745769745 Mar 12 12:29:18 PM PDT 24 Mar 12 12:29:19 PM PDT 24 83313095 ps
T726 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1385015937 Mar 12 12:29:33 PM PDT 24 Mar 12 12:29:34 PM PDT 24 25371183 ps
T727 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1497352762 Mar 12 12:29:07 PM PDT 24 Mar 12 12:29:08 PM PDT 24 21095738 ps
T728 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1903998240 Mar 12 12:29:20 PM PDT 24 Mar 12 12:29:23 PM PDT 24 227625296 ps
T729 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2114086977 Mar 12 12:29:14 PM PDT 24 Mar 12 12:29:18 PM PDT 24 726586453 ps
T730 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1013227923 Mar 12 12:28:58 PM PDT 24 Mar 12 12:29:02 PM PDT 24 60434720 ps
T731 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1616741946 Mar 12 12:29:14 PM PDT 24 Mar 12 12:29:15 PM PDT 24 83133516 ps
T732 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2818660540 Mar 12 12:29:01 PM PDT 24 Mar 12 12:29:02 PM PDT 24 189931315 ps
T733 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4023764932 Mar 12 12:29:19 PM PDT 24 Mar 12 12:29:20 PM PDT 24 32358935 ps

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.2348021393
Short name T1
Test name
Test status
Simulation time 193668156580 ps
CPU time 1521.87 seconds
Started Mar 12 01:52:16 PM PDT 24
Finished Mar 12 02:17:38 PM PDT 24
Peak memory 247300 kb
Host smart-3199c7c4-e5b7-4825-aa57-1e4bde68eb37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348021393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.2348021393
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.1484454537
Short name T4
Test name
Test status
Simulation time 266164049911 ps
CPU time 6766.87 seconds
Started Mar 12 01:51:20 PM PDT 24
Finished Mar 12 03:44:08 PM PDT 24
Peak memory 273888 kb
Host smart-50265f08-f296-4e61-b350-288731c75d1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1484454537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.1484454537
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2637407871
Short name T29
Test name
Test status
Simulation time 151860390 ps
CPU time 0.91 seconds
Started Mar 12 01:44:42 PM PDT 24
Finished Mar 12 01:44:44 PM PDT 24
Peak memory 218432 kb
Host smart-eb3494ac-906b-4e8e-bf99-aa69f4d3b189
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637407871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2637407871
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2176036133
Short name T55
Test name
Test status
Simulation time 233398065 ps
CPU time 4.75 seconds
Started Mar 12 12:29:20 PM PDT 24
Finished Mar 12 12:29:24 PM PDT 24
Peak memory 198996 kb
Host smart-e57b63f1-6ea5-4f65-956d-177666de728c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176036133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2176036133
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.2978215171
Short name T8
Test name
Test status
Simulation time 127000719301 ps
CPU time 1526.27 seconds
Started Mar 12 01:53:23 PM PDT 24
Finished Mar 12 02:18:50 PM PDT 24
Peak memory 261536 kb
Host smart-2759efca-5493-4821-bb54-c4b8262e681d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978215171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.2978215171
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3236724983
Short name T71
Test name
Test status
Simulation time 73522068 ps
CPU time 0.79 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:02 PM PDT 24
Peak memory 196612 kb
Host smart-e70c37a3-f9b6-43d5-bcd8-f51b9559885d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236724983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3236724983
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1244621402
Short name T2
Test name
Test status
Simulation time 5051887798 ps
CPU time 75.24 seconds
Started Mar 12 01:50:05 PM PDT 24
Finished Mar 12 01:51:21 PM PDT 24
Peak memory 200044 kb
Host smart-ff787536-d130-4c5a-84d6-8923f9924e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244621402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1244621402
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_stress_all.207116968
Short name T12
Test name
Test status
Simulation time 13127637426 ps
CPU time 694.76 seconds
Started Mar 12 01:52:00 PM PDT 24
Finished Mar 12 02:03:36 PM PDT 24
Peak memory 232684 kb
Host smart-866d34f3-bcd7-4132-a1a9-31e453c78432
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207116968 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.207116968
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1047485912
Short name T56
Test name
Test status
Simulation time 548066370 ps
CPU time 4.4 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 198988 kb
Host smart-db4bfe0b-ea93-4bfd-b363-01c3cc99de16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047485912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1047485912
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1456783870
Short name T18
Test name
Test status
Simulation time 15468162 ps
CPU time 0.61 seconds
Started Mar 12 01:45:54 PM PDT 24
Finished Mar 12 01:45:55 PM PDT 24
Peak memory 195340 kb
Host smart-a0831b7f-023d-448d-85de-908b6d4cd1f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456783870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1456783870
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1634942063
Short name T57
Test name
Test status
Simulation time 246215558 ps
CPU time 4.25 seconds
Started Mar 12 12:29:13 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 198980 kb
Host smart-3403674a-cb46-470a-82b7-77e4864ccd64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634942063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1634942063
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1622265863
Short name T25
Test name
Test status
Simulation time 5536566163 ps
CPU time 74.78 seconds
Started Mar 12 01:45:35 PM PDT 24
Finished Mar 12 01:46:50 PM PDT 24
Peak memory 200056 kb
Host smart-7c08083f-4052-477e-95c5-94bceab291c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622265863 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1622265863
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_error.2303794970
Short name T48
Test name
Test status
Simulation time 3654930763 ps
CPU time 48.56 seconds
Started Mar 12 01:49:56 PM PDT 24
Finished Mar 12 01:50:45 PM PDT 24
Peak memory 199928 kb
Host smart-d11824d5-d3c2-4e07-8490-715b4aa98cc9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303794970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2303794970
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.869661428
Short name T98
Test name
Test status
Simulation time 2929420129 ps
CPU time 8.64 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:10 PM PDT 24
Peak memory 198228 kb
Host smart-94c4e652-a0bc-449a-a30e-a35392d88f04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869661428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.869661428
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3512190715
Short name T683
Test name
Test status
Simulation time 3729689178 ps
CPU time 11.32 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:12 PM PDT 24
Peak memory 197592 kb
Host smart-300e1bfb-2748-43b5-b00c-0213125d4bbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512190715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3512190715
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.914883942
Short name T673
Test name
Test status
Simulation time 199378378 ps
CPU time 1.3 seconds
Started Mar 12 12:29:07 PM PDT 24
Finished Mar 12 12:29:09 PM PDT 24
Peak memory 199016 kb
Host smart-a6e55a3f-27a7-4552-b664-589eefc8a0eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914883942 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.914883942
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.305472258
Short name T100
Test name
Test status
Simulation time 208219036 ps
CPU time 0.84 seconds
Started Mar 12 12:28:58 PM PDT 24
Finished Mar 12 12:28:59 PM PDT 24
Peak memory 198832 kb
Host smart-8b96766d-8c41-49a9-8ed5-252441fb598f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305472258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.305472258
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.964413156
Short name T722
Test name
Test status
Simulation time 55213470 ps
CPU time 0.63 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:02 PM PDT 24
Peak memory 193472 kb
Host smart-43408a8e-68f9-4dc3-aa36-cae9e05715bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964413156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.964413156
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2177819662
Short name T68
Test name
Test status
Simulation time 208005202 ps
CPU time 1.13 seconds
Started Mar 12 12:28:58 PM PDT 24
Finished Mar 12 12:28:59 PM PDT 24
Peak memory 197388 kb
Host smart-4789b499-ca02-41ce-97d1-189b48d46c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177819662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2177819662
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.516133581
Short name T633
Test name
Test status
Simulation time 62673948 ps
CPU time 1.13 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:02 PM PDT 24
Peak memory 198916 kb
Host smart-656bd75e-6499-49eb-8a64-813f54d2e4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516133581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.516133581
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3378717889
Short name T116
Test name
Test status
Simulation time 763177576 ps
CPU time 3.27 seconds
Started Mar 12 12:29:03 PM PDT 24
Finished Mar 12 12:29:07 PM PDT 24
Peak memory 199024 kb
Host smart-47c1989f-5ce9-4ecd-99c0-5bfd814eda38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378717889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3378717889
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.88253580
Short name T99
Test name
Test status
Simulation time 104568939 ps
CPU time 5.63 seconds
Started Mar 12 12:28:59 PM PDT 24
Finished Mar 12 12:29:05 PM PDT 24
Peak memory 197816 kb
Host smart-13674c68-3704-4b44-9343-7b9cde6c72cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88253580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.88253580
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2670729815
Short name T101
Test name
Test status
Simulation time 219215770 ps
CPU time 5.28 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:07 PM PDT 24
Peak memory 198968 kb
Host smart-dd6a5313-81cb-4010-af16-e87a8d717a49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670729815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2670729815
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2086990806
Short name T102
Test name
Test status
Simulation time 124965467 ps
CPU time 0.98 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:01 PM PDT 24
Peak memory 198516 kb
Host smart-a0826069-c5c4-44d3-b4d5-191af04eb118
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086990806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2086990806
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1042033554
Short name T645
Test name
Test status
Simulation time 89578480 ps
CPU time 2.32 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:04 PM PDT 24
Peak memory 199052 kb
Host smart-7c5487c2-eaac-4399-a237-78c71ffd99ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042033554 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1042033554
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.203652702
Short name T658
Test name
Test status
Simulation time 34711304 ps
CPU time 0.97 seconds
Started Mar 12 12:28:59 PM PDT 24
Finished Mar 12 12:29:00 PM PDT 24
Peak memory 197644 kb
Host smart-8170852f-73f0-4b29-b576-ce4d82b91c28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203652702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.203652702
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1497352762
Short name T727
Test name
Test status
Simulation time 21095738 ps
CPU time 0.63 seconds
Started Mar 12 12:29:07 PM PDT 24
Finished Mar 12 12:29:08 PM PDT 24
Peak memory 193492 kb
Host smart-fff3eba7-16e5-4fb6-9c50-1c78481e35fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497352762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1497352762
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2818660540
Short name T732
Test name
Test status
Simulation time 189931315 ps
CPU time 1.22 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:02 PM PDT 24
Peak memory 196988 kb
Host smart-2646ee07-685d-4bee-bb85-4e1353f9007e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818660540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2818660540
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.626614181
Short name T649
Test name
Test status
Simulation time 210261708 ps
CPU time 1.86 seconds
Started Mar 12 12:28:59 PM PDT 24
Finished Mar 12 12:29:01 PM PDT 24
Peak memory 199004 kb
Host smart-4ed5ec74-127b-4a3d-92d1-9a37d647c104
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626614181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.626614181
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2591674561
Short name T661
Test name
Test status
Simulation time 116966930 ps
CPU time 2.89 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:05 PM PDT 24
Peak memory 199024 kb
Host smart-db3b881b-aef5-4304-aea5-f907826263ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591674561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2591674561
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2278057622
Short name T664
Test name
Test status
Simulation time 144782968 ps
CPU time 1.72 seconds
Started Mar 12 12:29:18 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 199028 kb
Host smart-8ecc5de0-babe-48f3-bbcc-c652d33d0be6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278057622 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2278057622
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2943026170
Short name T94
Test name
Test status
Simulation time 29501068 ps
CPU time 0.82 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 198040 kb
Host smart-3d7571d0-1b94-422c-834a-f78430f51d5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943026170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2943026170
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.76616063
Short name T638
Test name
Test status
Simulation time 19718801 ps
CPU time 0.61 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 193548 kb
Host smart-9eb5e5a9-0234-4b4c-a86f-43416107451e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76616063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.76616063
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.936580587
Short name T719
Test name
Test status
Simulation time 23501860 ps
CPU time 1.12 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 198936 kb
Host smart-9cfa3140-737e-4e9f-a2b7-12a157a39a0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936580587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.936580587
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1805218342
Short name T650
Test name
Test status
Simulation time 122650573 ps
CPU time 3.68 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:21 PM PDT 24
Peak memory 198992 kb
Host smart-d40e36f1-fc9d-4a99-a744-435619c3f847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805218342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1805218342
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2286673093
Short name T112
Test name
Test status
Simulation time 320766881 ps
CPU time 2.9 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 198956 kb
Host smart-e5f5c665-1abf-4fa4-90bd-b577ef62823b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286673093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2286673093
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4131324240
Short name T608
Test name
Test status
Simulation time 173097712 ps
CPU time 3.07 seconds
Started Mar 12 12:29:20 PM PDT 24
Finished Mar 12 12:29:24 PM PDT 24
Peak memory 199100 kb
Host smart-3fa4355a-39d7-4870-a730-ab43926c8056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131324240 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.4131324240
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4257056791
Short name T108
Test name
Test status
Simulation time 138558544 ps
CPU time 0.78 seconds
Started Mar 12 12:29:13 PM PDT 24
Finished Mar 12 12:29:14 PM PDT 24
Peak memory 197576 kb
Host smart-0dcef1a8-e94c-4e40-8376-856b915ffb7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257056791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.4257056791
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.745769745
Short name T725
Test name
Test status
Simulation time 83313095 ps
CPU time 0.58 seconds
Started Mar 12 12:29:18 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 193580 kb
Host smart-dfc649df-87fe-4b13-be54-462b47611c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745769745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.745769745
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.758314543
Short name T617
Test name
Test status
Simulation time 48091801 ps
CPU time 1.38 seconds
Started Mar 12 12:29:33 PM PDT 24
Finished Mar 12 12:29:35 PM PDT 24
Peak memory 197556 kb
Host smart-cdcfb06a-8d77-41d6-8cd8-8fd97c43cc60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758314543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.758314543
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2339632289
Short name T698
Test name
Test status
Simulation time 106070255 ps
CPU time 2.92 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 198992 kb
Host smart-238981d5-7c27-456c-86d6-27cec3f02765
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339632289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2339632289
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1203218746
Short name T696
Test name
Test status
Simulation time 180211466 ps
CPU time 3.06 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:21 PM PDT 24
Peak memory 198920 kb
Host smart-4783a1a8-1d3e-4638-86a0-5d155f80209e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203218746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1203218746
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3567795167
Short name T704
Test name
Test status
Simulation time 116957242 ps
CPU time 3.86 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:21 PM PDT 24
Peak memory 199008 kb
Host smart-3bba5ef7-5ea3-4825-a5ea-b78fd0865c94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567795167 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3567795167
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1950342622
Short name T95
Test name
Test status
Simulation time 32972734 ps
CPU time 0.68 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 196236 kb
Host smart-07ae92a3-085a-476a-a44d-985d79f2b340
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950342622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1950342622
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2390761187
Short name T631
Test name
Test status
Simulation time 14362771 ps
CPU time 0.6 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 193484 kb
Host smart-f12575bc-dd5f-4686-92a8-101e0245edbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390761187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2390761187
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1903998240
Short name T728
Test name
Test status
Simulation time 227625296 ps
CPU time 2.33 seconds
Started Mar 12 12:29:20 PM PDT 24
Finished Mar 12 12:29:23 PM PDT 24
Peak memory 198856 kb
Host smart-4042cf8f-91f1-46bf-8a15-36485a7087d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903998240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1903998240
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.637273786
Short name T710
Test name
Test status
Simulation time 296913545 ps
CPU time 1.68 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 199008 kb
Host smart-7726489f-834e-496f-8b77-bb1970d44b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637273786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.637273786
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2804303620
Short name T114
Test name
Test status
Simulation time 193299930 ps
CPU time 1.94 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 198972 kb
Host smart-273cddd0-58b7-4649-8161-d66c2a8c4dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804303620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2804303620
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3471995493
Short name T694
Test name
Test status
Simulation time 27558282 ps
CPU time 1.57 seconds
Started Mar 12 12:29:20 PM PDT 24
Finished Mar 12 12:29:21 PM PDT 24
Peak memory 199044 kb
Host smart-0a7b1e00-57b1-433d-b056-c1bbbe1617f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471995493 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3471995493
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2386281881
Short name T711
Test name
Test status
Simulation time 33749206 ps
CPU time 0.7 seconds
Started Mar 12 12:29:19 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 195784 kb
Host smart-f490c1a1-6663-45fb-98c9-867503a4b0c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386281881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2386281881
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.357920070
Short name T684
Test name
Test status
Simulation time 23205915 ps
CPU time 0.56 seconds
Started Mar 12 12:29:20 PM PDT 24
Finished Mar 12 12:29:21 PM PDT 24
Peak memory 193536 kb
Host smart-4cf2d209-4310-4a4b-9c77-2815b417d26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357920070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.357920070
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2482259667
Short name T724
Test name
Test status
Simulation time 56745230 ps
CPU time 1.35 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 198576 kb
Host smart-c0cd0562-1ab8-4b7a-92a5-a4ad790f58ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482259667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2482259667
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1052617790
Short name T614
Test name
Test status
Simulation time 214701220 ps
CPU time 3.96 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 199004 kb
Host smart-af687f84-d211-47b3-8537-2d7cb29cbd17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052617790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1052617790
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1544092834
Short name T721
Test name
Test status
Simulation time 331078696 ps
CPU time 3.02 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 199008 kb
Host smart-008d4cdd-0f51-40ed-8afc-23a8a2a35116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544092834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1544092834
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1991026934
Short name T619
Test name
Test status
Simulation time 36270286 ps
CPU time 2.18 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 199084 kb
Host smart-4f619150-bc7e-42c5-8018-19b0fe4e6a1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991026934 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1991026934
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1385015937
Short name T726
Test name
Test status
Simulation time 25371183 ps
CPU time 0.86 seconds
Started Mar 12 12:29:33 PM PDT 24
Finished Mar 12 12:29:34 PM PDT 24
Peak memory 197348 kb
Host smart-16bc9396-8bc2-4536-acf9-c61237794da5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385015937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1385015937
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1615680733
Short name T717
Test name
Test status
Simulation time 160487598 ps
CPU time 0.6 seconds
Started Mar 12 12:29:13 PM PDT 24
Finished Mar 12 12:29:14 PM PDT 24
Peak memory 193544 kb
Host smart-e6864188-9745-4d4f-b757-f9bf8b4eed81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615680733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1615680733
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1242191897
Short name T687
Test name
Test status
Simulation time 213701348 ps
CPU time 2.14 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 198796 kb
Host smart-0149137d-eef5-4a80-9982-b6c9cc4133ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242191897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1242191897
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3822332820
Short name T668
Test name
Test status
Simulation time 128748618 ps
CPU time 2.75 seconds
Started Mar 12 12:29:13 PM PDT 24
Finished Mar 12 12:29:16 PM PDT 24
Peak memory 199152 kb
Host smart-e9a4ae60-19a0-4ab0-b332-5ee696a8a161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822332820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3822332820
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1788366117
Short name T671
Test name
Test status
Simulation time 136787311 ps
CPU time 4.08 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:21 PM PDT 24
Peak memory 198916 kb
Host smart-830fe819-23ba-4980-9e6a-05ad12d2a10c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788366117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1788366117
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1050364714
Short name T693
Test name
Test status
Simulation time 120360985 ps
CPU time 1.13 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 198956 kb
Host smart-fff48f0a-b77f-4b4c-9deb-8fb8dee6d3b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050364714 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1050364714
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3211272154
Short name T105
Test name
Test status
Simulation time 112203480 ps
CPU time 0.97 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 198336 kb
Host smart-dfc13fab-e219-4a0d-bcd9-400710a0e0ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211272154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3211272154
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3975609470
Short name T716
Test name
Test status
Simulation time 48162496 ps
CPU time 0.63 seconds
Started Mar 12 12:30:19 PM PDT 24
Finished Mar 12 12:30:20 PM PDT 24
Peak memory 192772 kb
Host smart-72159973-1e08-4b43-8dcb-5591578ed37d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975609470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3975609470
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.874860511
Short name T709
Test name
Test status
Simulation time 33823577 ps
CPU time 1.56 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 198200 kb
Host smart-0f60d567-c31d-4fba-868a-918809533ee9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874860511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.874860511
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3516891792
Short name T706
Test name
Test status
Simulation time 67710170 ps
CPU time 3.41 seconds
Started Mar 12 12:29:19 PM PDT 24
Finished Mar 12 12:29:22 PM PDT 24
Peak memory 199064 kb
Host smart-84ef6fd6-2419-4576-9953-f02c8e0b638b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516891792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3516891792
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.708141631
Short name T666
Test name
Test status
Simulation time 32930839 ps
CPU time 1.93 seconds
Started Mar 12 12:29:27 PM PDT 24
Finished Mar 12 12:29:30 PM PDT 24
Peak memory 199000 kb
Host smart-9f572e33-7f25-47bf-99bd-bcd624cd58fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708141631 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.708141631
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.458174600
Short name T96
Test name
Test status
Simulation time 28295981 ps
CPU time 0.86 seconds
Started Mar 12 12:29:18 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 197712 kb
Host smart-4885c1a0-5137-4abb-ba38-0a1c53decfaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458174600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.458174600
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.931679614
Short name T712
Test name
Test status
Simulation time 19286226 ps
CPU time 0.62 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 193560 kb
Host smart-7d6e0a65-a0b7-44a7-85ac-01e2a8b7c64b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931679614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.931679614
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.909850549
Short name T69
Test name
Test status
Simulation time 389093775 ps
CPU time 1.17 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 196780 kb
Host smart-83b0e0e5-0b39-49d1-ac80-dffaa8208f63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909850549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.909850549
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2123953719
Short name T640
Test name
Test status
Simulation time 62773777 ps
CPU time 3.45 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 198996 kb
Host smart-afe26edc-97f5-476e-b607-7c7cb4935cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123953719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2123953719
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4084199673
Short name T652
Test name
Test status
Simulation time 158609185684 ps
CPU time 735.42 seconds
Started Mar 12 12:29:19 PM PDT 24
Finished Mar 12 12:41:35 PM PDT 24
Peak memory 217292 kb
Host smart-a6ed3bc7-3410-4e72-a92d-c87b43549a3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084199673 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4084199673
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3844784809
Short name T718
Test name
Test status
Simulation time 15071206 ps
CPU time 0.69 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 195848 kb
Host smart-8e8a8287-ea57-486b-a233-043cd8d3aa7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844784809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3844784809
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3785939457
Short name T615
Test name
Test status
Simulation time 129044778 ps
CPU time 0.57 seconds
Started Mar 12 12:29:10 PM PDT 24
Finished Mar 12 12:29:11 PM PDT 24
Peak memory 193972 kb
Host smart-26d3e7d6-8f69-4881-9945-279a873982e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785939457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3785939457
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1643254808
Short name T681
Test name
Test status
Simulation time 429145539 ps
CPU time 1.96 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 198612 kb
Host smart-52459668-b57a-4c0d-8749-1bf8dbfb9a6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643254808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1643254808
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.589216777
Short name T654
Test name
Test status
Simulation time 66998051 ps
CPU time 3.6 seconds
Started Mar 12 12:29:19 PM PDT 24
Finished Mar 12 12:29:28 PM PDT 24
Peak memory 199072 kb
Host smart-bdd02624-21be-4b05-9867-6afcf0b4804e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589216777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.589216777
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2945789815
Short name T707
Test name
Test status
Simulation time 84256953 ps
CPU time 1.98 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 198956 kb
Host smart-a600af41-ec5a-4808-9d18-9bdc7070b440
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945789815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2945789815
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1431951724
Short name T60
Test name
Test status
Simulation time 28825454 ps
CPU time 2.02 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 198988 kb
Host smart-bcf5d705-4b9f-41ac-841b-c27749b3e47d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431951724 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1431951724
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4023764932
Short name T733
Test name
Test status
Simulation time 32358935 ps
CPU time 0.69 seconds
Started Mar 12 12:29:19 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 196088 kb
Host smart-08125bcd-345e-42d0-8add-94e0bcfdb031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023764932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4023764932
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1412708130
Short name T612
Test name
Test status
Simulation time 89751358 ps
CPU time 0.57 seconds
Started Mar 12 12:29:20 PM PDT 24
Finished Mar 12 12:29:21 PM PDT 24
Peak memory 193548 kb
Host smart-cb572f30-9637-43b6-988a-35530c93d001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412708130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1412708130
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.4048857364
Short name T700
Test name
Test status
Simulation time 81402746 ps
CPU time 1.12 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 196752 kb
Host smart-ab5a2b2a-a48a-4a18-a9b7-37afeca99642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048857364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.4048857364
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3434387702
Short name T620
Test name
Test status
Simulation time 49074286 ps
CPU time 2.75 seconds
Started Mar 12 12:29:19 PM PDT 24
Finished Mar 12 12:29:22 PM PDT 24
Peak memory 199060 kb
Host smart-8de0e346-c3c2-47a3-8fe6-29c5c9ca1263
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434387702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3434387702
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.686277993
Short name T111
Test name
Test status
Simulation time 176153718 ps
CPU time 3.03 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 199016 kb
Host smart-e1bd2bcd-900b-469c-b1a7-41f3b37fa168
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686277993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.686277993
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.428897631
Short name T59
Test name
Test status
Simulation time 365470016 ps
CPU time 2.49 seconds
Started Mar 12 12:29:27 PM PDT 24
Finished Mar 12 12:29:30 PM PDT 24
Peak memory 198996 kb
Host smart-546e751b-e032-4971-81e1-fd4eac5590f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428897631 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.428897631
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.4046514312
Short name T642
Test name
Test status
Simulation time 12608276 ps
CPU time 0.72 seconds
Started Mar 12 12:29:14 PM PDT 24
Finished Mar 12 12:29:15 PM PDT 24
Peak memory 196140 kb
Host smart-10f3b52a-4e4d-4816-9c92-f95c9bb8c84a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046514312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.4046514312
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.890337254
Short name T637
Test name
Test status
Simulation time 242313630 ps
CPU time 0.66 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 193480 kb
Host smart-533b1d07-754d-4c10-8385-947f56a1f912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890337254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.890337254
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2194940861
Short name T688
Test name
Test status
Simulation time 406500696 ps
CPU time 1.68 seconds
Started Mar 12 12:29:32 PM PDT 24
Finished Mar 12 12:29:34 PM PDT 24
Peak memory 197748 kb
Host smart-ae1191ed-9779-408d-8106-4e1db55d18e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194940861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2194940861
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2114086977
Short name T729
Test name
Test status
Simulation time 726586453 ps
CPU time 4.06 seconds
Started Mar 12 12:29:14 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 199060 kb
Host smart-be7853af-47f9-4a59-93bd-bfce1002d494
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114086977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2114086977
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3391637697
Short name T115
Test name
Test status
Simulation time 1159566044 ps
CPU time 2.02 seconds
Started Mar 12 12:29:19 PM PDT 24
Finished Mar 12 12:29:21 PM PDT 24
Peak memory 198928 kb
Host smart-213e58ed-e7e0-4ac8-a22d-b2d77d9634ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391637697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3391637697
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1013227923
Short name T730
Test name
Test status
Simulation time 60434720 ps
CPU time 3.1 seconds
Started Mar 12 12:28:58 PM PDT 24
Finished Mar 12 12:29:02 PM PDT 24
Peak memory 198048 kb
Host smart-907e6792-e4a4-4640-8c87-c12e7c63887b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013227923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1013227923
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3251374664
Short name T93
Test name
Test status
Simulation time 417439113 ps
CPU time 9.89 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:11 PM PDT 24
Peak memory 197516 kb
Host smart-b26f972b-0afb-428c-9f4a-593a4a0cfb4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251374664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3251374664
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1862348452
Short name T107
Test name
Test status
Simulation time 29994710 ps
CPU time 0.97 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:03 PM PDT 24
Peak memory 197696 kb
Host smart-f1c1a120-b520-4019-a065-bdedd8106aeb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862348452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1862348452
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.613759209
Short name T605
Test name
Test status
Simulation time 39441372 ps
CPU time 2.57 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:05 PM PDT 24
Peak memory 199032 kb
Host smart-9cfae611-bbd0-4ca1-81ea-b09348077347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613759209 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.613759209
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3699374701
Short name T606
Test name
Test status
Simulation time 56878499 ps
CPU time 0.66 seconds
Started Mar 12 12:28:59 PM PDT 24
Finished Mar 12 12:29:00 PM PDT 24
Peak memory 196156 kb
Host smart-b57b9de9-8554-4ee3-8139-720b8bd97eb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699374701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3699374701
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1172860956
Short name T604
Test name
Test status
Simulation time 16360684 ps
CPU time 0.66 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:03 PM PDT 24
Peak memory 193560 kb
Host smart-5bab7f72-f41b-4325-b5cc-c409303b6323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172860956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1172860956
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1445347357
Short name T634
Test name
Test status
Simulation time 169787853 ps
CPU time 1.19 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:01 PM PDT 24
Peak memory 198152 kb
Host smart-15677de4-2963-4e15-a4ac-aa4e4f8aeefd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445347357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1445347357
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3952549262
Short name T629
Test name
Test status
Simulation time 863035795 ps
CPU time 3.29 seconds
Started Mar 12 12:28:58 PM PDT 24
Finished Mar 12 12:29:01 PM PDT 24
Peak memory 199044 kb
Host smart-99bd826f-6402-491b-81d9-fb9b8e8d42d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952549262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3952549262
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3680270111
Short name T110
Test name
Test status
Simulation time 362472126 ps
CPU time 2.81 seconds
Started Mar 12 12:29:07 PM PDT 24
Finished Mar 12 12:29:10 PM PDT 24
Peak memory 198908 kb
Host smart-f1255745-2d2d-4051-bc55-e46500e09d67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680270111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3680270111
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3408892635
Short name T618
Test name
Test status
Simulation time 42694417 ps
CPU time 0.61 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 193504 kb
Host smart-422c1032-1a83-4be4-b2c1-09f9388f1689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408892635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3408892635
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2416202037
Short name T644
Test name
Test status
Simulation time 15565919 ps
CPU time 0.66 seconds
Started Mar 12 12:29:14 PM PDT 24
Finished Mar 12 12:29:15 PM PDT 24
Peak memory 193500 kb
Host smart-1b8b1141-a3bf-4cf0-bed5-ebceb90b1f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416202037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2416202037
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.812003287
Short name T691
Test name
Test status
Simulation time 48434775 ps
CPU time 0.65 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:15 PM PDT 24
Peak memory 193496 kb
Host smart-ef505b4a-fab3-4a00-9362-da4e496c47fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812003287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.812003287
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3639308574
Short name T663
Test name
Test status
Simulation time 15517743 ps
CPU time 0.57 seconds
Started Mar 12 12:29:14 PM PDT 24
Finished Mar 12 12:29:15 PM PDT 24
Peak memory 193500 kb
Host smart-aa5b01d4-7567-4870-b278-86c63416b50b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639308574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3639308574
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2871365666
Short name T653
Test name
Test status
Simulation time 12040689 ps
CPU time 0.63 seconds
Started Mar 12 12:29:13 PM PDT 24
Finished Mar 12 12:29:14 PM PDT 24
Peak memory 193624 kb
Host smart-7a3776ec-6ec7-412d-a4db-a1fff26567bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871365666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2871365666
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1979189507
Short name T622
Test name
Test status
Simulation time 42318937 ps
CPU time 0.65 seconds
Started Mar 12 12:29:14 PM PDT 24
Finished Mar 12 12:29:15 PM PDT 24
Peak memory 193648 kb
Host smart-fc1c59b5-7744-4df1-8e73-c82633488208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979189507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1979189507
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1528929791
Short name T616
Test name
Test status
Simulation time 107612149 ps
CPU time 0.65 seconds
Started Mar 12 12:29:13 PM PDT 24
Finished Mar 12 12:29:14 PM PDT 24
Peak memory 193572 kb
Host smart-dded5bc1-22dc-4d48-868d-cd6ddc79978f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528929791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1528929791
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3741572191
Short name T708
Test name
Test status
Simulation time 27685267 ps
CPU time 0.61 seconds
Started Mar 12 12:29:11 PM PDT 24
Finished Mar 12 12:29:12 PM PDT 24
Peak memory 193516 kb
Host smart-050ce7ee-a1b6-43e2-bb52-1a9d5dab6fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741572191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3741572191
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1568633717
Short name T680
Test name
Test status
Simulation time 12478638 ps
CPU time 0.62 seconds
Started Mar 12 12:29:13 PM PDT 24
Finished Mar 12 12:29:13 PM PDT 24
Peak memory 193728 kb
Host smart-f6010b3d-e7ee-42a7-ba1d-790c4700b29d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568633717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1568633717
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.343505619
Short name T713
Test name
Test status
Simulation time 25122029 ps
CPU time 0.63 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:16 PM PDT 24
Peak memory 193584 kb
Host smart-fadcbd98-5814-4b34-986b-620b3babcfe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343505619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.343505619
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4019922648
Short name T104
Test name
Test status
Simulation time 1064363095 ps
CPU time 8.93 seconds
Started Mar 12 12:29:03 PM PDT 24
Finished Mar 12 12:29:12 PM PDT 24
Peak memory 198148 kb
Host smart-bd9453be-b93a-4cf1-8a10-f8c17826db1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019922648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4019922648
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2838004793
Short name T686
Test name
Test status
Simulation time 2807151119 ps
CPU time 10.89 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:13 PM PDT 24
Peak memory 197948 kb
Host smart-aa360ea0-8b22-4fd2-a972-8ef411aecbd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838004793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2838004793
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1914847054
Short name T705
Test name
Test status
Simulation time 31822874 ps
CPU time 0.88 seconds
Started Mar 12 12:28:59 PM PDT 24
Finished Mar 12 12:29:00 PM PDT 24
Peak memory 197764 kb
Host smart-2177e165-05b6-400a-88d8-45bbf986fc19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914847054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1914847054
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3355912016
Short name T689
Test name
Test status
Simulation time 136415492 ps
CPU time 1.73 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:04 PM PDT 24
Peak memory 199052 kb
Host smart-66aeee78-6752-4bb5-a4fa-c3acb6aedcbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355912016 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3355912016
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1997386977
Short name T685
Test name
Test status
Simulation time 30242862 ps
CPU time 0.85 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:01 PM PDT 24
Peak memory 198540 kb
Host smart-5b6be3b6-7457-4d81-8324-b43544414e3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997386977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1997386977
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1736842915
Short name T610
Test name
Test status
Simulation time 57452006 ps
CPU time 0.62 seconds
Started Mar 12 12:28:59 PM PDT 24
Finished Mar 12 12:28:59 PM PDT 24
Peak memory 193584 kb
Host smart-7d4f191b-8f8a-4def-a8f2-1ee68b56c93c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736842915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1736842915
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1043466554
Short name T626
Test name
Test status
Simulation time 286638854 ps
CPU time 1.8 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:02 PM PDT 24
Peak memory 198616 kb
Host smart-6184b220-fcfb-401e-8c79-ef682a1599b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043466554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1043466554
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2478508865
Short name T702
Test name
Test status
Simulation time 169061886 ps
CPU time 2.91 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:04 PM PDT 24
Peak memory 199072 kb
Host smart-5fb57e25-a3ba-46c2-a321-7c7fc5d5a10b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478508865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2478508865
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2904067947
Short name T701
Test name
Test status
Simulation time 524573891 ps
CPU time 4.61 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:06 PM PDT 24
Peak memory 199024 kb
Host smart-15ba7bfe-558e-44d4-b364-587801cfab14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904067947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2904067947
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1806481081
Short name T623
Test name
Test status
Simulation time 17854658 ps
CPU time 0.67 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 193496 kb
Host smart-6a739d6f-35fc-497b-a4af-0c4cbae5c672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806481081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1806481081
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2625355514
Short name T651
Test name
Test status
Simulation time 45186197 ps
CPU time 0.67 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 193452 kb
Host smart-9f1b0bcb-45a4-4118-a158-be69d56f1215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625355514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2625355514
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.752306336
Short name T624
Test name
Test status
Simulation time 12049541 ps
CPU time 0.56 seconds
Started Mar 12 12:29:14 PM PDT 24
Finished Mar 12 12:29:15 PM PDT 24
Peak memory 193536 kb
Host smart-eb731e93-3383-403b-922c-3d421e1101a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752306336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.752306336
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1616741946
Short name T731
Test name
Test status
Simulation time 83133516 ps
CPU time 0.59 seconds
Started Mar 12 12:29:14 PM PDT 24
Finished Mar 12 12:29:15 PM PDT 24
Peak memory 193496 kb
Host smart-c429891d-b1c8-4505-8e2c-6424fbd55978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616741946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1616741946
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3777482760
Short name T703
Test name
Test status
Simulation time 12811584 ps
CPU time 0.65 seconds
Started Mar 12 12:29:12 PM PDT 24
Finished Mar 12 12:29:13 PM PDT 24
Peak memory 193480 kb
Host smart-d52c5b11-980c-47b9-9716-e15ad5906aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777482760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3777482760
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3555469085
Short name T690
Test name
Test status
Simulation time 17580904 ps
CPU time 0.65 seconds
Started Mar 12 12:29:12 PM PDT 24
Finished Mar 12 12:29:13 PM PDT 24
Peak memory 193528 kb
Host smart-7cc57d81-24dc-44dc-b48b-e8518d893fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555469085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3555469085
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.976292474
Short name T670
Test name
Test status
Simulation time 16959096 ps
CPU time 0.62 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 193540 kb
Host smart-f2708338-c58a-4bd7-82f1-25f601122b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976292474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.976292474
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.686643776
Short name T646
Test name
Test status
Simulation time 86699765 ps
CPU time 0.68 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:18 PM PDT 24
Peak memory 193544 kb
Host smart-bc36db5a-3579-4ee8-89fc-757638c18512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686643776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.686643776
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.416972629
Short name T647
Test name
Test status
Simulation time 32873237 ps
CPU time 0.58 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 193504 kb
Host smart-ec95dd7c-2bb3-4dc0-a130-5367d864fb5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416972629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.416972629
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2062323744
Short name T714
Test name
Test status
Simulation time 17278583 ps
CPU time 0.67 seconds
Started Mar 12 12:29:13 PM PDT 24
Finished Mar 12 12:29:14 PM PDT 24
Peak memory 193500 kb
Host smart-0798b28d-a7fc-4584-a823-657111c9a37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062323744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2062323744
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3602625897
Short name T699
Test name
Test status
Simulation time 181364521 ps
CPU time 3.44 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:04 PM PDT 24
Peak memory 197524 kb
Host smart-b48dbfd1-fe72-4bd8-83a9-5e69d4ad07d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602625897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3602625897
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2972308681
Short name T625
Test name
Test status
Simulation time 730289322 ps
CPU time 10.63 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:12 PM PDT 24
Peak memory 197576 kb
Host smart-683b1777-57ec-4cd9-bb63-edc7fa9b794b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972308681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2972308681
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1402725022
Short name T607
Test name
Test status
Simulation time 34059882 ps
CPU time 1.04 seconds
Started Mar 12 12:29:03 PM PDT 24
Finished Mar 12 12:29:04 PM PDT 24
Peak memory 198924 kb
Host smart-49cdbdd1-20ed-4d60-b93b-8d646b0f7c18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402725022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1402725022
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1733394386
Short name T669
Test name
Test status
Simulation time 65980032 ps
CPU time 1.16 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:02 PM PDT 24
Peak memory 198956 kb
Host smart-c25acf7f-2d96-468e-855e-3b6e9ba1b0b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733394386 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1733394386
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3213586917
Short name T103
Test name
Test status
Simulation time 18882848 ps
CPU time 0.84 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:01 PM PDT 24
Peak memory 197436 kb
Host smart-52dac661-d52e-4acb-8252-5cbe413175ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213586917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3213586917
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2797147055
Short name T675
Test name
Test status
Simulation time 26867281 ps
CPU time 0.53 seconds
Started Mar 12 12:29:06 PM PDT 24
Finished Mar 12 12:29:06 PM PDT 24
Peak memory 193492 kb
Host smart-e625a19e-0dc4-486d-bb71-167036322354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797147055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2797147055
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3244961014
Short name T628
Test name
Test status
Simulation time 378246329 ps
CPU time 1.88 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:04 PM PDT 24
Peak memory 198624 kb
Host smart-a10aecbb-808e-4f8e-9c58-2eb10ec0333b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244961014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3244961014
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2228628314
Short name T720
Test name
Test status
Simulation time 267652478 ps
CPU time 3.23 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:05 PM PDT 24
Peak memory 199056 kb
Host smart-af2dc766-0856-4358-8a0a-de8c81723a47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228628314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2228628314
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3822756969
Short name T697
Test name
Test status
Simulation time 1037268035 ps
CPU time 4.23 seconds
Started Mar 12 12:29:03 PM PDT 24
Finished Mar 12 12:29:08 PM PDT 24
Peak memory 198992 kb
Host smart-c6d669fd-1348-4a08-b560-ab6770681d08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822756969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3822756969
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2564617173
Short name T648
Test name
Test status
Simulation time 37289479 ps
CPU time 0.57 seconds
Started Mar 12 12:29:09 PM PDT 24
Finished Mar 12 12:29:10 PM PDT 24
Peak memory 193476 kb
Host smart-852a1418-a5a5-4c37-a2de-4cf39122a5fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564617173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2564617173
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1399193384
Short name T641
Test name
Test status
Simulation time 33301299 ps
CPU time 0.65 seconds
Started Mar 12 12:29:11 PM PDT 24
Finished Mar 12 12:29:11 PM PDT 24
Peak memory 193556 kb
Host smart-2322c6c0-1f7f-4a5b-89c5-fea5568921e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399193384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1399193384
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2586829976
Short name T636
Test name
Test status
Simulation time 15442783 ps
CPU time 0.56 seconds
Started Mar 12 12:29:11 PM PDT 24
Finished Mar 12 12:29:11 PM PDT 24
Peak memory 193492 kb
Host smart-4fb4fe5d-4e04-4539-95d0-a43738d7791e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586829976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2586829976
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3001291816
Short name T656
Test name
Test status
Simulation time 13472895 ps
CPU time 0.57 seconds
Started Mar 12 12:29:11 PM PDT 24
Finished Mar 12 12:29:12 PM PDT 24
Peak memory 193500 kb
Host smart-f9ec3312-0261-47bb-a894-8c518bf8879d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001291816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3001291816
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.683651879
Short name T627
Test name
Test status
Simulation time 39058476 ps
CPU time 0.64 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 193444 kb
Host smart-ee2de37c-be92-4666-a6bb-d70e5f9e1a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683651879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.683651879
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1516945088
Short name T655
Test name
Test status
Simulation time 12915903 ps
CPU time 0.58 seconds
Started Mar 12 12:29:13 PM PDT 24
Finished Mar 12 12:29:13 PM PDT 24
Peak memory 193520 kb
Host smart-0f6995aa-8dee-4f7a-9f10-7c2510e9acb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516945088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1516945088
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3576933668
Short name T677
Test name
Test status
Simulation time 44104823 ps
CPU time 0.58 seconds
Started Mar 12 12:29:10 PM PDT 24
Finished Mar 12 12:29:10 PM PDT 24
Peak memory 193564 kb
Host smart-f6fa6fe0-a29d-443e-99d9-bfbc5738ad33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576933668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3576933668
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3133766454
Short name T682
Test name
Test status
Simulation time 18047566 ps
CPU time 0.6 seconds
Started Mar 12 12:29:19 PM PDT 24
Finished Mar 12 12:29:20 PM PDT 24
Peak memory 193520 kb
Host smart-fb44e3ed-4f49-4a2a-9192-43e87689154b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133766454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3133766454
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2913697900
Short name T70
Test name
Test status
Simulation time 17282671 ps
CPU time 0.62 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 193492 kb
Host smart-cf7239d8-e277-4682-a8d8-3fe748222c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913697900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2913697900
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1754570036
Short name T611
Test name
Test status
Simulation time 148345418 ps
CPU time 0.56 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 193504 kb
Host smart-5d1c2806-f997-4101-8f9d-b11b1db74900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754570036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1754570036
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3197641688
Short name T692
Test name
Test status
Simulation time 26303311 ps
CPU time 1.55 seconds
Started Mar 12 12:29:03 PM PDT 24
Finished Mar 12 12:29:05 PM PDT 24
Peak memory 199084 kb
Host smart-c3854cd7-4df6-468b-b779-56e88454744a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197641688 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3197641688
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2060460837
Short name T97
Test name
Test status
Simulation time 206343442 ps
CPU time 0.8 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:03 PM PDT 24
Peak memory 197320 kb
Host smart-32da7cea-c23a-4aed-8d74-595beb708fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060460837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2060460837
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2484951616
Short name T643
Test name
Test status
Simulation time 12689895 ps
CPU time 0.6 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:01 PM PDT 24
Peak memory 193484 kb
Host smart-86718b90-6cff-4497-9ecf-4027c64964d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484951616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2484951616
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.106509034
Short name T58
Test name
Test status
Simulation time 304120876 ps
CPU time 2.05 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:04 PM PDT 24
Peak memory 198224 kb
Host smart-1273e1d4-5cd4-4ceb-8096-bbaf5a58aef9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106509034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.106509034
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1448011247
Short name T662
Test name
Test status
Simulation time 66363586 ps
CPU time 3.77 seconds
Started Mar 12 12:29:06 PM PDT 24
Finished Mar 12 12:29:10 PM PDT 24
Peak memory 199040 kb
Host smart-cfe1d52a-94a2-49e9-9638-c001f2af2d30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448011247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1448011247
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2554729848
Short name T676
Test name
Test status
Simulation time 153523262 ps
CPU time 2.96 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:05 PM PDT 24
Peak memory 198996 kb
Host smart-edd93842-3384-4b8c-9860-95dcac5e325b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554729848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2554729848
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2703002391
Short name T674
Test name
Test status
Simulation time 271205056 ps
CPU time 1.73 seconds
Started Mar 12 12:29:05 PM PDT 24
Finished Mar 12 12:29:07 PM PDT 24
Peak memory 199044 kb
Host smart-20db872e-215a-4c1a-a5d4-34791eb49103
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703002391 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2703002391
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3137761746
Short name T667
Test name
Test status
Simulation time 19203117 ps
CPU time 0.72 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:01 PM PDT 24
Peak memory 196180 kb
Host smart-28b1f962-992b-4aa0-8ee2-11dbe2602410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137761746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3137761746
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1841976321
Short name T659
Test name
Test status
Simulation time 21170545 ps
CPU time 0.58 seconds
Started Mar 12 12:29:03 PM PDT 24
Finished Mar 12 12:29:04 PM PDT 24
Peak memory 193500 kb
Host smart-7a05d478-4e52-4f08-8493-27d3fa16c266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841976321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1841976321
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3926538128
Short name T665
Test name
Test status
Simulation time 1001090572 ps
CPU time 1.71 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:01 PM PDT 24
Peak memory 198940 kb
Host smart-1584eeeb-becd-4aed-804b-96c8f22e9df2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926538128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3926538128
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1327088441
Short name T672
Test name
Test status
Simulation time 67870343 ps
CPU time 1.6 seconds
Started Mar 12 12:29:04 PM PDT 24
Finished Mar 12 12:29:06 PM PDT 24
Peak memory 199052 kb
Host smart-a498b409-a5f8-4aa9-b358-5c9c5260939c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327088441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1327088441
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1416077973
Short name T54
Test name
Test status
Simulation time 325654976 ps
CPU time 2.77 seconds
Started Mar 12 12:29:04 PM PDT 24
Finished Mar 12 12:29:07 PM PDT 24
Peak memory 198980 kb
Host smart-80ff0dfb-a819-45fb-81a8-0210a0df6d83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416077973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1416077973
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2233664849
Short name T635
Test name
Test status
Simulation time 156555670 ps
CPU time 2.64 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:04 PM PDT 24
Peak memory 199096 kb
Host smart-dd14ead9-fe19-47bb-9977-6d029dce6a3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233664849 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2233664849
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2134315772
Short name T715
Test name
Test status
Simulation time 510053799 ps
CPU time 0.94 seconds
Started Mar 12 12:29:05 PM PDT 24
Finished Mar 12 12:29:06 PM PDT 24
Peak memory 197792 kb
Host smart-d8792320-0cab-4651-8402-4522c9253409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134315772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2134315772
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.196411811
Short name T639
Test name
Test status
Simulation time 16754714 ps
CPU time 0.63 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:02 PM PDT 24
Peak memory 193488 kb
Host smart-3d55ed19-d916-4c22-b0c9-cef7ad760713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196411811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.196411811
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.211932357
Short name T609
Test name
Test status
Simulation time 234248963 ps
CPU time 2.6 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:04 PM PDT 24
Peak memory 198592 kb
Host smart-16a4ae73-96a0-47a0-bddd-5519bfd2593c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211932357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.211932357
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3165102168
Short name T660
Test name
Test status
Simulation time 205777454 ps
CPU time 1.56 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:03 PM PDT 24
Peak memory 199032 kb
Host smart-a2e9dc41-a761-4944-8ee1-24719ccc8244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165102168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3165102168
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.294225635
Short name T113
Test name
Test status
Simulation time 422155124 ps
CPU time 3.84 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:06 PM PDT 24
Peak memory 198944 kb
Host smart-7f3a3a8a-5647-4971-8295-4e62dc3395f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294225635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.294225635
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3757677339
Short name T678
Test name
Test status
Simulation time 183647966 ps
CPU time 1.55 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:03 PM PDT 24
Peak memory 199072 kb
Host smart-6171bf98-d974-4ea7-8fb5-f533c031ba4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757677339 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3757677339
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3866640851
Short name T106
Test name
Test status
Simulation time 35214005 ps
CPU time 0.94 seconds
Started Mar 12 12:28:59 PM PDT 24
Finished Mar 12 12:29:00 PM PDT 24
Peak memory 198112 kb
Host smart-706c6e6f-a8af-44e9-ba19-1fdce3ca8ef5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866640851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3866640851
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1830238912
Short name T630
Test name
Test status
Simulation time 13808707 ps
CPU time 0.64 seconds
Started Mar 12 12:29:01 PM PDT 24
Finished Mar 12 12:29:02 PM PDT 24
Peak memory 193548 kb
Host smart-eeafdcdc-8741-493b-b3b2-30295b1bad53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830238912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1830238912
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3082516249
Short name T632
Test name
Test status
Simulation time 35658148 ps
CPU time 1.68 seconds
Started Mar 12 12:29:02 PM PDT 24
Finished Mar 12 12:29:03 PM PDT 24
Peak memory 197908 kb
Host smart-83da97a4-1053-4349-992a-607dffc1160a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082516249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3082516249
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2802246267
Short name T657
Test name
Test status
Simulation time 63102607 ps
CPU time 1.75 seconds
Started Mar 12 12:29:03 PM PDT 24
Finished Mar 12 12:29:05 PM PDT 24
Peak memory 199064 kb
Host smart-030b9e87-3e6c-4af7-9449-717a021ab22e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802246267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2802246267
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2867320644
Short name T723
Test name
Test status
Simulation time 139972197 ps
CPU time 4.17 seconds
Started Mar 12 12:29:05 PM PDT 24
Finished Mar 12 12:29:09 PM PDT 24
Peak memory 198988 kb
Host smart-726cdd75-e5d9-414a-8f7e-8aecc55a87d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867320644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2867320644
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.52448432
Short name T679
Test name
Test status
Simulation time 42313971 ps
CPU time 1.15 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 198900 kb
Host smart-615bbf7c-df8e-4bb0-9c45-29e8cebbcf72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52448432 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.52448432
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1734383322
Short name T695
Test name
Test status
Simulation time 437017521 ps
CPU time 0.97 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 198768 kb
Host smart-59325b10-3f26-43f4-82ad-fd9e9682ac9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734383322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1734383322
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2379752675
Short name T613
Test name
Test status
Simulation time 35410581 ps
CPU time 0.59 seconds
Started Mar 12 12:29:15 PM PDT 24
Finished Mar 12 12:29:17 PM PDT 24
Peak memory 193500 kb
Host smart-802aa17a-8f60-4546-a1d6-679169616a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379752675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2379752675
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4188205007
Short name T67
Test name
Test status
Simulation time 985338696 ps
CPU time 1.25 seconds
Started Mar 12 12:29:16 PM PDT 24
Finished Mar 12 12:29:19 PM PDT 24
Peak memory 198404 kb
Host smart-3763a5b2-3b30-4e52-98da-354fd2c32d9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188205007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4188205007
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.255308227
Short name T621
Test name
Test status
Simulation time 67520383 ps
CPU time 3.71 seconds
Started Mar 12 12:29:17 PM PDT 24
Finished Mar 12 12:29:21 PM PDT 24
Peak memory 199044 kb
Host smart-2f959e4a-8702-4d70-a053-8b98c7e3f03f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255308227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.255308227
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3467452447
Short name T325
Test name
Test status
Simulation time 10918713 ps
CPU time 0.58 seconds
Started Mar 12 01:44:28 PM PDT 24
Finished Mar 12 01:44:29 PM PDT 24
Peak memory 194328 kb
Host smart-a87baefa-c026-4ab9-a96b-1d00606d727d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467452447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3467452447
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1100421209
Short name T147
Test name
Test status
Simulation time 3067737176 ps
CPU time 57.45 seconds
Started Mar 12 01:44:28 PM PDT 24
Finished Mar 12 01:45:26 PM PDT 24
Peak memory 224592 kb
Host smart-2dd54263-b822-44e0-9111-634f579fbbfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1100421209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1100421209
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2210627676
Short name T476
Test name
Test status
Simulation time 2362683294 ps
CPU time 9.54 seconds
Started Mar 12 01:44:31 PM PDT 24
Finished Mar 12 01:44:41 PM PDT 24
Peak memory 199980 kb
Host smart-e2fadbc8-14c4-429f-8ac9-2243b9e6a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210627676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2210627676
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.43058820
Short name T312
Test name
Test status
Simulation time 1461944636 ps
CPU time 85.59 seconds
Started Mar 12 01:44:28 PM PDT 24
Finished Mar 12 01:45:55 PM PDT 24
Peak memory 199912 kb
Host smart-94e60737-22cb-4a7f-acad-9e46d5c173fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43058820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.43058820
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.683669008
Short name T152
Test name
Test status
Simulation time 7335009776 ps
CPU time 94.03 seconds
Started Mar 12 01:44:30 PM PDT 24
Finished Mar 12 01:46:04 PM PDT 24
Peak memory 200044 kb
Host smart-c829cb7a-c492-4736-bbe4-b5bc769c5b2c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683669008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.683669008
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.959172734
Short name T38
Test name
Test status
Simulation time 3231009469 ps
CPU time 101.29 seconds
Started Mar 12 01:44:27 PM PDT 24
Finished Mar 12 01:46:09 PM PDT 24
Peak memory 200012 kb
Host smart-0d8e35bc-c385-489c-9965-9f75579f4ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959172734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.959172734
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2300770910
Short name T32
Test name
Test status
Simulation time 90858435 ps
CPU time 0.99 seconds
Started Mar 12 01:44:29 PM PDT 24
Finished Mar 12 01:44:30 PM PDT 24
Peak memory 219440 kb
Host smart-0d0efbe3-3e4d-4788-83fb-9823a37927c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300770910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2300770910
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1914241761
Short name T79
Test name
Test status
Simulation time 84150848 ps
CPU time 3.15 seconds
Started Mar 12 01:44:26 PM PDT 24
Finished Mar 12 01:44:30 PM PDT 24
Peak memory 199932 kb
Host smart-96fac735-63c9-452d-aa8a-0f71b7e30888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914241761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1914241761
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2774917017
Short name T568
Test name
Test status
Simulation time 100308408500 ps
CPU time 1917.67 seconds
Started Mar 12 01:44:29 PM PDT 24
Finished Mar 12 02:16:27 PM PDT 24
Peak memory 200028 kb
Host smart-7ebd8096-2069-42b2-a3ac-411b9cb19aa3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774917017 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2774917017
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.479676034
Short name T482
Test name
Test status
Simulation time 128314500 ps
CPU time 1.29 seconds
Started Mar 12 01:44:28 PM PDT 24
Finished Mar 12 01:44:29 PM PDT 24
Peak memory 199896 kb
Host smart-e8523039-ed75-4c87-865b-13979772ef41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479676034 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.479676034
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3956037709
Short name T372
Test name
Test status
Simulation time 8059735468 ps
CPU time 427.39 seconds
Started Mar 12 01:44:30 PM PDT 24
Finished Mar 12 01:51:38 PM PDT 24
Peak memory 200044 kb
Host smart-9627b701-188f-4799-b18a-f99881a46f69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956037709 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3956037709
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2173501727
Short name T485
Test name
Test status
Simulation time 563049017 ps
CPU time 9.21 seconds
Started Mar 12 01:44:29 PM PDT 24
Finished Mar 12 01:44:39 PM PDT 24
Peak memory 199888 kb
Host smart-c4a7166c-cbf0-4195-ace7-034cb78fea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173501727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2173501727
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3978276633
Short name T383
Test name
Test status
Simulation time 42093393 ps
CPU time 0.62 seconds
Started Mar 12 01:44:39 PM PDT 24
Finished Mar 12 01:44:41 PM PDT 24
Peak memory 194308 kb
Host smart-7eb3e434-180e-471a-824a-4cc24e4b7797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978276633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3978276633
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2942195407
Short name T368
Test name
Test status
Simulation time 22985735659 ps
CPU time 54.4 seconds
Started Mar 12 01:44:29 PM PDT 24
Finished Mar 12 01:45:24 PM PDT 24
Peak memory 246100 kb
Host smart-a20d69fc-48b3-4a1b-8d0e-644c99369865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942195407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2942195407
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.644495075
Short name T504
Test name
Test status
Simulation time 18445510658 ps
CPU time 39.49 seconds
Started Mar 12 01:44:28 PM PDT 24
Finished Mar 12 01:45:08 PM PDT 24
Peak memory 199972 kb
Host smart-62656059-aabc-4aed-ab86-350d75fd13b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644495075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.644495075
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2265969088
Short name T155
Test name
Test status
Simulation time 2119680965 ps
CPU time 128.22 seconds
Started Mar 12 01:44:31 PM PDT 24
Finished Mar 12 01:46:40 PM PDT 24
Peak memory 199916 kb
Host smart-1873e35c-907c-4128-925f-6bba34d7460b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265969088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2265969088
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1661669517
Short name T496
Test name
Test status
Simulation time 3508961646 ps
CPU time 47.91 seconds
Started Mar 12 01:44:27 PM PDT 24
Finished Mar 12 01:45:15 PM PDT 24
Peak memory 199980 kb
Host smart-1e0f40a4-0462-472b-a317-160705a5cad2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661669517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1661669517
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2838823899
Short name T435
Test name
Test status
Simulation time 541184097 ps
CPU time 13.21 seconds
Started Mar 12 01:44:30 PM PDT 24
Finished Mar 12 01:44:43 PM PDT 24
Peak memory 199916 kb
Host smart-80275606-33e8-4e76-a2a2-d418b858b412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838823899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2838823899
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3271495199
Short name T31
Test name
Test status
Simulation time 643437139 ps
CPU time 0.91 seconds
Started Mar 12 01:44:37 PM PDT 24
Finished Mar 12 01:44:38 PM PDT 24
Peak memory 218392 kb
Host smart-30cf9605-0903-4014-bd2f-3612cf0a86a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271495199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3271495199
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2061231398
Short name T531
Test name
Test status
Simulation time 103884233 ps
CPU time 1.6 seconds
Started Mar 12 01:44:28 PM PDT 24
Finished Mar 12 01:44:30 PM PDT 24
Peak memory 199900 kb
Host smart-0db855a2-e0a5-4425-930e-aab4b6849c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061231398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2061231398
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1540334272
Short name T471
Test name
Test status
Simulation time 15854222029 ps
CPU time 920.18 seconds
Started Mar 12 01:44:38 PM PDT 24
Finished Mar 12 02:00:00 PM PDT 24
Peak memory 200056 kb
Host smart-8c63e556-2134-4da0-8816-02d16e2a4700
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540334272 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1540334272
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.419894835
Short name T139
Test name
Test status
Simulation time 61358068 ps
CPU time 1.35 seconds
Started Mar 12 01:44:37 PM PDT 24
Finished Mar 12 01:44:39 PM PDT 24
Peak memory 199276 kb
Host smart-991ff36e-9705-417b-baa6-e736c1bea67a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419894835 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.419894835
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.902459567
Short name T27
Test name
Test status
Simulation time 42701962599 ps
CPU time 436.97 seconds
Started Mar 12 01:44:27 PM PDT 24
Finished Mar 12 01:51:44 PM PDT 24
Peak memory 199964 kb
Host smart-b1ce9deb-df26-4703-b3bf-b6ba49bb3ed3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902459567 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.902459567
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1225733973
Short name T433
Test name
Test status
Simulation time 7966938127 ps
CPU time 96.59 seconds
Started Mar 12 01:44:27 PM PDT 24
Finished Mar 12 01:46:04 PM PDT 24
Peak memory 200040 kb
Host smart-76c0e830-857a-47d8-b82b-9ff84c269464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225733973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1225733973
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2510038310
Short name T221
Test name
Test status
Simulation time 15052933 ps
CPU time 0.59 seconds
Started Mar 12 01:45:17 PM PDT 24
Finished Mar 12 01:45:18 PM PDT 24
Peak memory 195316 kb
Host smart-ce3ac8a8-54ca-49d6-8ba9-10bc9fd65bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510038310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2510038310
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3919705864
Short name T510
Test name
Test status
Simulation time 2913747306 ps
CPU time 51.14 seconds
Started Mar 12 01:45:10 PM PDT 24
Finished Mar 12 01:46:01 PM PDT 24
Peak memory 215596 kb
Host smart-843c2683-6d96-4601-b0b6-40a7d2f6c981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919705864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3919705864
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3638047148
Short name T534
Test name
Test status
Simulation time 279194095 ps
CPU time 6.15 seconds
Started Mar 12 01:45:18 PM PDT 24
Finished Mar 12 01:45:24 PM PDT 24
Peak memory 199728 kb
Host smart-10082fdf-00b1-4e37-b290-8961e501112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638047148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3638047148
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2534027695
Short name T572
Test name
Test status
Simulation time 2200406643 ps
CPU time 139.55 seconds
Started Mar 12 01:45:18 PM PDT 24
Finished Mar 12 01:47:37 PM PDT 24
Peak memory 199956 kb
Host smart-25ae1f58-bd9e-49fb-9bf7-bf180f479bae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534027695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2534027695
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1226720940
Short name T156
Test name
Test status
Simulation time 8735871044 ps
CPU time 149.17 seconds
Started Mar 12 01:45:16 PM PDT 24
Finished Mar 12 01:47:45 PM PDT 24
Peak memory 199976 kb
Host smart-a064ff55-becf-470e-9ecd-a743ec0d781e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226720940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1226720940
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1566198447
Short name T151
Test name
Test status
Simulation time 675791285 ps
CPU time 40.87 seconds
Started Mar 12 01:45:11 PM PDT 24
Finished Mar 12 01:45:52 PM PDT 24
Peak memory 199928 kb
Host smart-a28c317c-77af-4672-8924-4551ee4705eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566198447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1566198447
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.401833859
Short name T441
Test name
Test status
Simulation time 1476602275 ps
CPU time 5.91 seconds
Started Mar 12 01:45:08 PM PDT 24
Finished Mar 12 01:45:14 PM PDT 24
Peak memory 199948 kb
Host smart-410c50e2-ec93-4614-a97d-ed918bc4b1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401833859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.401833859
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3043789205
Short name T65
Test name
Test status
Simulation time 51408278313 ps
CPU time 208.44 seconds
Started Mar 12 01:45:18 PM PDT 24
Finished Mar 12 01:48:47 PM PDT 24
Peak memory 199896 kb
Host smart-7162a1c6-3130-42c2-86bb-3a445248bae1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043789205 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3043789205
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.227652537
Short name T165
Test name
Test status
Simulation time 63110714 ps
CPU time 1.43 seconds
Started Mar 12 01:45:17 PM PDT 24
Finished Mar 12 01:45:18 PM PDT 24
Peak memory 199388 kb
Host smart-04401777-8d95-4bdb-87c4-5117e42fef32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227652537 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_hmac_vectors.227652537
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3032424298
Short name T118
Test name
Test status
Simulation time 64447029661 ps
CPU time 507.35 seconds
Started Mar 12 01:45:18 PM PDT 24
Finished Mar 12 01:53:46 PM PDT 24
Peak memory 200080 kb
Host smart-247e0dc4-67eb-4615-a568-595ab72c7aea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032424298 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3032424298
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.4078437487
Short name T533
Test name
Test status
Simulation time 9607905723 ps
CPU time 76.84 seconds
Started Mar 12 01:45:19 PM PDT 24
Finished Mar 12 01:46:36 PM PDT 24
Peak memory 200012 kb
Host smart-ed181dc5-26e3-4d37-8664-f2cf9a078e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078437487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.4078437487
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2544186393
Short name T332
Test name
Test status
Simulation time 26319684 ps
CPU time 0.58 seconds
Started Mar 12 01:45:26 PM PDT 24
Finished Mar 12 01:45:27 PM PDT 24
Peak memory 195324 kb
Host smart-d4276ff4-3f2c-4348-8f14-a217bae0190f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544186393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2544186393
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.697222275
Short name T408
Test name
Test status
Simulation time 1405962108 ps
CPU time 54.73 seconds
Started Mar 12 01:45:28 PM PDT 24
Finished Mar 12 01:46:23 PM PDT 24
Peak memory 215580 kb
Host smart-130177a7-8bd7-4852-9810-62373c892648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697222275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.697222275
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3201815309
Short name T384
Test name
Test status
Simulation time 3205807133 ps
CPU time 41.37 seconds
Started Mar 12 01:45:28 PM PDT 24
Finished Mar 12 01:46:09 PM PDT 24
Peak memory 199988 kb
Host smart-9bfdab31-48a0-4e45-a408-7ddc1b38b108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201815309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3201815309
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1270915298
Short name T267
Test name
Test status
Simulation time 1897283786 ps
CPU time 100.48 seconds
Started Mar 12 01:45:29 PM PDT 24
Finished Mar 12 01:47:09 PM PDT 24
Peak memory 199900 kb
Host smart-a05b43e6-311c-49f2-8788-060717db2066
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1270915298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1270915298
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.360631624
Short name T248
Test name
Test status
Simulation time 28465923718 ps
CPU time 197.06 seconds
Started Mar 12 01:45:26 PM PDT 24
Finished Mar 12 01:48:44 PM PDT 24
Peak memory 200016 kb
Host smart-7c8c1f13-6f3f-4479-acef-b7f6c37bafc6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360631624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.360631624
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3466236760
Short name T262
Test name
Test status
Simulation time 1823956557 ps
CPU time 110.46 seconds
Started Mar 12 01:45:26 PM PDT 24
Finished Mar 12 01:47:17 PM PDT 24
Peak memory 199848 kb
Host smart-2a0118e9-4847-4cbb-adc4-a123b36a7388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466236760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3466236760
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3432705528
Short name T73
Test name
Test status
Simulation time 228201344 ps
CPU time 1.2 seconds
Started Mar 12 01:45:27 PM PDT 24
Finished Mar 12 01:45:28 PM PDT 24
Peak memory 199924 kb
Host smart-9a77f6a0-c0fb-4b47-8994-378aae017874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432705528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3432705528
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.488357509
Short name T402
Test name
Test status
Simulation time 146090588622 ps
CPU time 1041.04 seconds
Started Mar 12 01:45:27 PM PDT 24
Finished Mar 12 02:02:48 PM PDT 24
Peak memory 220488 kb
Host smart-d27020a6-cf7c-4c94-bfcd-8c961978ae8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488357509 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.488357509
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3167506411
Short name T407
Test name
Test status
Simulation time 74245876 ps
CPU time 1.28 seconds
Started Mar 12 01:45:27 PM PDT 24
Finished Mar 12 01:45:29 PM PDT 24
Peak memory 199600 kb
Host smart-91b80132-cfca-4213-a9a8-8e568496b73b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167506411 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3167506411
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3810219519
Short name T192
Test name
Test status
Simulation time 7120080818 ps
CPU time 373.37 seconds
Started Mar 12 01:45:29 PM PDT 24
Finished Mar 12 01:51:42 PM PDT 24
Peak memory 200052 kb
Host smart-ad68a706-8fcb-4d10-ae89-e21b84b023fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810219519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3810219519
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.4006967541
Short name T369
Test name
Test status
Simulation time 738528035 ps
CPU time 40.33 seconds
Started Mar 12 01:45:27 PM PDT 24
Finished Mar 12 01:46:07 PM PDT 24
Peak memory 199960 kb
Host smart-7b6f330c-340a-4c32-ad71-b20dbd31f8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006967541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.4006967541
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3164333676
Short name T373
Test name
Test status
Simulation time 39640660 ps
CPU time 0.57 seconds
Started Mar 12 01:45:36 PM PDT 24
Finished Mar 12 01:45:36 PM PDT 24
Peak memory 194924 kb
Host smart-9e8bb931-bd32-4a47-8a31-7bec389f4941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164333676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3164333676
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.83838446
Short name T412
Test name
Test status
Simulation time 5382332935 ps
CPU time 44.73 seconds
Started Mar 12 01:45:28 PM PDT 24
Finished Mar 12 01:46:13 PM PDT 24
Peak memory 208252 kb
Host smart-73db434d-3b89-439d-b1b7-c5973362f686
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83838446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.83838446
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2533599392
Short name T367
Test name
Test status
Simulation time 1609174907 ps
CPU time 41.16 seconds
Started Mar 12 01:45:28 PM PDT 24
Finished Mar 12 01:46:09 PM PDT 24
Peak memory 199924 kb
Host smart-4fc313af-f480-4c1e-a995-10d7b06230b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533599392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2533599392
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3523552442
Short name T477
Test name
Test status
Simulation time 31466127259 ps
CPU time 120.6 seconds
Started Mar 12 01:45:28 PM PDT 24
Finished Mar 12 01:47:29 PM PDT 24
Peak memory 200032 kb
Host smart-9cd5ca2e-ca9c-43a2-86fc-19eed85ae20c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523552442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3523552442
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2726993571
Short name T212
Test name
Test status
Simulation time 30633719631 ps
CPU time 200.93 seconds
Started Mar 12 01:45:28 PM PDT 24
Finished Mar 12 01:48:49 PM PDT 24
Peak memory 200040 kb
Host smart-4ad4c346-c6bb-4403-82ec-5834631b8824
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726993571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2726993571
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3682870487
Short name T244
Test name
Test status
Simulation time 23730429261 ps
CPU time 91.84 seconds
Started Mar 12 01:45:29 PM PDT 24
Finished Mar 12 01:47:01 PM PDT 24
Peak memory 200028 kb
Host smart-b7567360-0c36-4a8a-90a9-e704396c0a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682870487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3682870487
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.269661928
Short name T498
Test name
Test status
Simulation time 3087999032 ps
CPU time 7.85 seconds
Started Mar 12 01:45:27 PM PDT 24
Finished Mar 12 01:45:35 PM PDT 24
Peak memory 199968 kb
Host smart-bc9248dd-f9b8-487d-8366-d37d35f1f24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269661928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.269661928
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.784793771
Short name T233
Test name
Test status
Simulation time 29213357 ps
CPU time 0.99 seconds
Started Mar 12 01:45:37 PM PDT 24
Finished Mar 12 01:45:38 PM PDT 24
Peak memory 199076 kb
Host smart-ec35811b-c826-4ae6-ba93-189a3dccd2b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784793771 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.784793771
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.677280256
Short name T500
Test name
Test status
Simulation time 54779662633 ps
CPU time 501.24 seconds
Started Mar 12 01:45:34 PM PDT 24
Finished Mar 12 01:53:57 PM PDT 24
Peak memory 200048 kb
Host smart-abffeac3-7d20-487a-8bbc-d474fa48ed50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677280256 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.677280256
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.4223325638
Short name T293
Test name
Test status
Simulation time 1147849095 ps
CPU time 18.09 seconds
Started Mar 12 01:45:35 PM PDT 24
Finished Mar 12 01:45:54 PM PDT 24
Peak memory 199924 kb
Host smart-a95a64b3-75c0-40a8-b789-3cbae4bcb47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223325638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.4223325638
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3152001305
Short name T357
Test name
Test status
Simulation time 13087739 ps
CPU time 0.62 seconds
Started Mar 12 01:45:43 PM PDT 24
Finished Mar 12 01:45:43 PM PDT 24
Peak memory 195304 kb
Host smart-43def061-4a7f-4ef1-9a1c-034c1e790408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152001305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3152001305
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2198124771
Short name T351
Test name
Test status
Simulation time 3316755239 ps
CPU time 39 seconds
Started Mar 12 01:45:36 PM PDT 24
Finished Mar 12 01:46:15 PM PDT 24
Peak memory 217392 kb
Host smart-7938ea4b-163f-4fff-87ea-382f478b9b13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198124771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2198124771
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1419970049
Short name T363
Test name
Test status
Simulation time 4314545100 ps
CPU time 22.56 seconds
Started Mar 12 01:45:43 PM PDT 24
Finished Mar 12 01:46:05 PM PDT 24
Peak memory 199992 kb
Host smart-a21ae377-1917-43bd-8833-39848b57da5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419970049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1419970049
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3516552897
Short name T397
Test name
Test status
Simulation time 2517803282 ps
CPU time 157.24 seconds
Started Mar 12 01:45:44 PM PDT 24
Finished Mar 12 01:48:22 PM PDT 24
Peak memory 199960 kb
Host smart-05d192b7-f7ef-4720-83c6-5bd514a1e7d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3516552897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3516552897
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.4162388888
Short name T198
Test name
Test status
Simulation time 9845929766 ps
CPU time 142.48 seconds
Started Mar 12 01:45:43 PM PDT 24
Finished Mar 12 01:48:06 PM PDT 24
Peak memory 200036 kb
Host smart-d03efe6c-f66c-4c2f-b9ef-5c41a102c0e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162388888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.4162388888
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2034190215
Short name T454
Test name
Test status
Simulation time 8653100000 ps
CPU time 41.82 seconds
Started Mar 12 01:45:35 PM PDT 24
Finished Mar 12 01:46:17 PM PDT 24
Peak memory 200040 kb
Host smart-315430a3-34be-42b1-ae73-fc3b5e41bf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034190215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2034190215
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3411694652
Short name T579
Test name
Test status
Simulation time 3443923309 ps
CPU time 7.39 seconds
Started Mar 12 01:45:36 PM PDT 24
Finished Mar 12 01:45:43 PM PDT 24
Peak memory 199976 kb
Host smart-fc446ceb-f85d-46f3-995a-f23344fc9c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411694652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3411694652
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3205472672
Short name T353
Test name
Test status
Simulation time 165963470107 ps
CPU time 516.87 seconds
Started Mar 12 01:45:42 PM PDT 24
Finished Mar 12 01:54:19 PM PDT 24
Peak memory 200064 kb
Host smart-6e1b84f6-46f1-4cbd-aa87-b54d7df9df5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205472672 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3205472672
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.682407710
Short name T86
Test name
Test status
Simulation time 49173116 ps
CPU time 1.03 seconds
Started Mar 12 01:45:43 PM PDT 24
Finished Mar 12 01:45:44 PM PDT 24
Peak memory 197712 kb
Host smart-7d859bc4-68dd-4e52-bde5-23e0ad99d2e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682407710 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.682407710
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1363297430
Short name T349
Test name
Test status
Simulation time 7916468623 ps
CPU time 458.33 seconds
Started Mar 12 01:45:43 PM PDT 24
Finished Mar 12 01:53:21 PM PDT 24
Peak memory 200084 kb
Host smart-1ed4e8ec-c725-4b4c-b148-424775763abe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363297430 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.1363297430
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3378509511
Short name T171
Test name
Test status
Simulation time 2962742977 ps
CPU time 46.36 seconds
Started Mar 12 01:45:43 PM PDT 24
Finished Mar 12 01:46:30 PM PDT 24
Peak memory 200004 kb
Host smart-269b7e89-180b-4dd7-b0d3-f46a23c61a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378509511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3378509511
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.1118204027
Short name T537
Test name
Test status
Simulation time 68303224815 ps
CPU time 577.05 seconds
Started Mar 12 01:52:52 PM PDT 24
Finished Mar 12 02:02:29 PM PDT 24
Peak memory 216520 kb
Host smart-49b82756-79b1-46bd-bad5-7f0ce468f0da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118204027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.1118204027
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.1759244114
Short name T7
Test name
Test status
Simulation time 115717966596 ps
CPU time 1003.25 seconds
Started Mar 12 01:53:03 PM PDT 24
Finished Mar 12 02:09:47 PM PDT 24
Peak memory 210392 kb
Host smart-133ec76c-5f0b-4a20-9c4a-a6e105967b7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1759244114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.1759244114
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1381568653
Short name T184
Test name
Test status
Simulation time 2660999320 ps
CPU time 35.39 seconds
Started Mar 12 01:45:57 PM PDT 24
Finished Mar 12 01:46:35 PM PDT 24
Peak memory 223824 kb
Host smart-61cddd01-1346-4c30-bf60-55837ec22829
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381568653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1381568653
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4097707677
Short name T243
Test name
Test status
Simulation time 2898524112 ps
CPU time 41.4 seconds
Started Mar 12 01:45:57 PM PDT 24
Finished Mar 12 01:46:39 PM PDT 24
Peak memory 199880 kb
Host smart-57cfc110-2e18-4fda-948e-1e1886837977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097707677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4097707677
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.778971168
Short name T374
Test name
Test status
Simulation time 4337256703 ps
CPU time 143.81 seconds
Started Mar 12 01:45:52 PM PDT 24
Finished Mar 12 01:48:16 PM PDT 24
Peak memory 199968 kb
Host smart-4ffcc4e2-b139-4a15-87f5-6867e4bdda88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=778971168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.778971168
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.29501536
Short name T224
Test name
Test status
Simulation time 52131897863 ps
CPU time 163.62 seconds
Started Mar 12 01:45:52 PM PDT 24
Finished Mar 12 01:48:35 PM PDT 24
Peak memory 200072 kb
Host smart-6211f6a0-29de-4d7c-a3fd-0f3b8366df0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29501536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.29501536
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1835842491
Short name T294
Test name
Test status
Simulation time 2185144020 ps
CPU time 63.33 seconds
Started Mar 12 01:45:52 PM PDT 24
Finished Mar 12 01:46:55 PM PDT 24
Peak memory 199972 kb
Host smart-0e45091b-aa23-4aaf-b94b-6c63a87e4df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835842491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1835842491
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.850260030
Short name T168
Test name
Test status
Simulation time 42809215 ps
CPU time 1.62 seconds
Started Mar 12 01:45:57 PM PDT 24
Finished Mar 12 01:46:00 PM PDT 24
Peak memory 199884 kb
Host smart-34949169-f743-4bd5-aa9a-ea605af22a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850260030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.850260030
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1148786557
Short name T468
Test name
Test status
Simulation time 14302130104 ps
CPU time 159.99 seconds
Started Mar 12 01:45:57 PM PDT 24
Finished Mar 12 01:48:39 PM PDT 24
Peak memory 234492 kb
Host smart-f0180aa1-b795-424a-bbf6-81723c7d59f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148786557 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1148786557
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3448334464
Short name T215
Test name
Test status
Simulation time 41296431 ps
CPU time 1.03 seconds
Started Mar 12 01:45:52 PM PDT 24
Finished Mar 12 01:45:53 PM PDT 24
Peak memory 199032 kb
Host smart-a54f0436-6b56-4f65-a5d9-ecd63cf448ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448334464 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.3448334464
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1303998195
Short name T573
Test name
Test status
Simulation time 103225731135 ps
CPU time 494.85 seconds
Started Mar 12 01:45:50 PM PDT 24
Finished Mar 12 01:54:05 PM PDT 24
Peak memory 200056 kb
Host smart-0a218971-419c-46af-b7d1-6f58e89c4e47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303998195 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1303998195
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.641311813
Short name T3
Test name
Test status
Simulation time 2738610286 ps
CPU time 31.2 seconds
Started Mar 12 01:45:58 PM PDT 24
Finished Mar 12 01:46:30 PM PDT 24
Peak memory 199984 kb
Host smart-ded94473-ff52-427d-bc98-bbcab56863bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641311813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.641311813
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1332592899
Short name T411
Test name
Test status
Simulation time 39332964 ps
CPU time 0.57 seconds
Started Mar 12 01:45:59 PM PDT 24
Finished Mar 12 01:46:01 PM PDT 24
Peak memory 194944 kb
Host smart-ba89abde-5bd0-40ec-8d23-223f0edf72d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332592899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1332592899
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2236604105
Short name T130
Test name
Test status
Simulation time 1318414783 ps
CPU time 55.21 seconds
Started Mar 12 01:45:52 PM PDT 24
Finished Mar 12 01:46:47 PM PDT 24
Peak memory 226576 kb
Host smart-ab2ea4f9-439e-40e5-8f81-1df65106d6cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2236604105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2236604105
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.853650827
Short name T575
Test name
Test status
Simulation time 162632787 ps
CPU time 8.2 seconds
Started Mar 12 01:45:57 PM PDT 24
Finished Mar 12 01:46:06 PM PDT 24
Peak memory 199800 kb
Host smart-102adb09-1a0c-4160-a459-8fb76c336523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853650827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.853650827
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2072554975
Short name T169
Test name
Test status
Simulation time 5152582198 ps
CPU time 177.12 seconds
Started Mar 12 01:45:58 PM PDT 24
Finished Mar 12 01:48:56 PM PDT 24
Peak memory 200016 kb
Host smart-8007b83b-4374-4ecf-ac33-19183b238146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072554975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2072554975
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.4050309135
Short name T148
Test name
Test status
Simulation time 8290651391 ps
CPU time 37.97 seconds
Started Mar 12 01:45:59 PM PDT 24
Finished Mar 12 01:46:38 PM PDT 24
Peak memory 200036 kb
Host smart-cfd672e8-5c77-4f15-a7b6-1bf26f690fcf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050309135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.4050309135
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1501305545
Short name T475
Test name
Test status
Simulation time 12522659055 ps
CPU time 80.19 seconds
Started Mar 12 01:45:52 PM PDT 24
Finished Mar 12 01:47:12 PM PDT 24
Peak memory 200044 kb
Host smart-eb7144f5-cf60-4c4c-a026-f18cbd6da839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501305545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1501305545
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2020577260
Short name T453
Test name
Test status
Simulation time 22318105 ps
CPU time 0.98 seconds
Started Mar 12 01:45:50 PM PDT 24
Finished Mar 12 01:45:51 PM PDT 24
Peak memory 198820 kb
Host smart-b240bf75-879a-4877-aa77-7aa6535f9a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020577260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2020577260
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1686217758
Short name T230
Test name
Test status
Simulation time 15123384104 ps
CPU time 740.82 seconds
Started Mar 12 01:45:58 PM PDT 24
Finished Mar 12 01:58:21 PM PDT 24
Peak memory 211316 kb
Host smart-2e1d9804-27c1-41a8-a9a0-be917a54da74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686217758 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1686217758
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.644552391
Short name T465
Test name
Test status
Simulation time 27842253 ps
CPU time 1.09 seconds
Started Mar 12 01:45:59 PM PDT 24
Finished Mar 12 01:46:02 PM PDT 24
Peak memory 198832 kb
Host smart-62238b2c-2968-4ae1-a9ee-105697629569
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644552391 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.644552391
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1823019333
Short name T269
Test name
Test status
Simulation time 29882266227 ps
CPU time 538.81 seconds
Started Mar 12 01:45:59 PM PDT 24
Finished Mar 12 01:54:59 PM PDT 24
Peak memory 200040 kb
Host smart-fc8c3078-eca1-4a22-9171-7e8ed40c58b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823019333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.1823019333
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1926866489
Short name T85
Test name
Test status
Simulation time 2547535190 ps
CPU time 10.33 seconds
Started Mar 12 01:45:59 PM PDT 24
Finished Mar 12 01:46:11 PM PDT 24
Peak memory 199920 kb
Host smart-715af3df-1c70-4a3b-b7ed-a183d7851f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926866489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1926866489
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.313439852
Short name T256
Test name
Test status
Simulation time 45693829 ps
CPU time 0.58 seconds
Started Mar 12 01:50:05 PM PDT 24
Finished Mar 12 01:50:06 PM PDT 24
Peak memory 195356 kb
Host smart-911272f9-7c74-4610-8e6c-23e93386c42b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313439852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.313439852
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2845280938
Short name T40
Test name
Test status
Simulation time 550371564 ps
CPU time 11.12 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:50:17 PM PDT 24
Peak memory 215764 kb
Host smart-7baa9153-b214-4a58-abdd-c38ab382258d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845280938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2845280938
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3931027952
Short name T398
Test name
Test status
Simulation time 7505412515 ps
CPU time 36.92 seconds
Started Mar 12 01:49:54 PM PDT 24
Finished Mar 12 01:50:31 PM PDT 24
Peak memory 200036 kb
Host smart-c8ba550c-487e-4280-aee8-2b02d47c02e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931027952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3931027952
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2599292617
Short name T122
Test name
Test status
Simulation time 5535190743 ps
CPU time 20.17 seconds
Started Mar 12 01:50:05 PM PDT 24
Finished Mar 12 01:50:26 PM PDT 24
Peak memory 200044 kb
Host smart-7c83f531-9016-4e34-b0e8-f3af6e76097f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599292617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2599292617
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3194734669
Short name T45
Test name
Test status
Simulation time 13488996180 ps
CPU time 195.7 seconds
Started Mar 12 01:50:03 PM PDT 24
Finished Mar 12 01:53:19 PM PDT 24
Peak memory 200016 kb
Host smart-6b46a20c-4db7-4289-ba8e-fccabb5767cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194734669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3194734669
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_smoke.3746587567
Short name T432
Test name
Test status
Simulation time 454612802 ps
CPU time 7.18 seconds
Started Mar 12 01:49:05 PM PDT 24
Finished Mar 12 01:49:12 PM PDT 24
Peak memory 199924 kb
Host smart-c5be58b1-9f63-43c1-813b-5b80c619d7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746587567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3746587567
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3353298411
Short name T247
Test name
Test status
Simulation time 98855629012 ps
CPU time 554.89 seconds
Started Mar 12 01:49:59 PM PDT 24
Finished Mar 12 01:59:14 PM PDT 24
Peak memory 199996 kb
Host smart-0c29532d-dd44-4d02-9475-7cd7974625ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353298411 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3353298411
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3189296056
Short name T461
Test name
Test status
Simulation time 43044097 ps
CPU time 1.09 seconds
Started Mar 12 01:49:57 PM PDT 24
Finished Mar 12 01:49:59 PM PDT 24
Peak memory 199604 kb
Host smart-e398bc8d-8c21-4288-ac66-9c3546e95673
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189296056 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3189296056
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.99279490
Short name T34
Test name
Test status
Simulation time 32690299182 ps
CPU time 504.97 seconds
Started Mar 12 01:50:07 PM PDT 24
Finished Mar 12 01:58:32 PM PDT 24
Peak memory 200076 kb
Host smart-70f47de1-503f-4eb7-8785-f7c2f45e142c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99279490 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.99279490
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2177141430
Short name T355
Test name
Test status
Simulation time 2992983125 ps
CPU time 46.16 seconds
Started Mar 12 01:50:05 PM PDT 24
Finished Mar 12 01:50:51 PM PDT 24
Peak memory 200012 kb
Host smart-93bef4b6-1da3-46e5-8154-d0740d576e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177141430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2177141430
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.2167162686
Short name T62
Test name
Test status
Simulation time 190833159394 ps
CPU time 528.12 seconds
Started Mar 12 01:53:14 PM PDT 24
Finished Mar 12 02:02:02 PM PDT 24
Peak memory 216116 kb
Host smart-a8d0043f-1394-4248-bcb0-1ac42b59a3a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167162686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.2167162686
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1050792261
Short name T555
Test name
Test status
Simulation time 84639366 ps
CPU time 0.6 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:50:07 PM PDT 24
Peak memory 195328 kb
Host smart-4efe70bb-1f21-4505-9e99-65d0df4fd903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050792261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1050792261
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.4234710432
Short name T589
Test name
Test status
Simulation time 313083783 ps
CPU time 7.71 seconds
Started Mar 12 01:49:55 PM PDT 24
Finished Mar 12 01:50:03 PM PDT 24
Peak memory 224516 kb
Host smart-1a26a68b-bd5a-4ab1-af90-cd6742ae36c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234710432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.4234710432
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2918280872
Short name T142
Test name
Test status
Simulation time 844370388 ps
CPU time 7.11 seconds
Started Mar 12 01:50:07 PM PDT 24
Finished Mar 12 01:50:14 PM PDT 24
Peak memory 199824 kb
Host smart-81efa71b-8e3a-40c5-8ceb-d376e1683d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918280872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2918280872
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3785205742
Short name T316
Test name
Test status
Simulation time 2610148845 ps
CPU time 35.67 seconds
Started Mar 12 01:49:14 PM PDT 24
Finished Mar 12 01:49:49 PM PDT 24
Peak memory 199812 kb
Host smart-2650f57c-ec16-42cc-be9b-01cc4220f242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3785205742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3785205742
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2087445335
Short name T386
Test name
Test status
Simulation time 32398251266 ps
CPU time 94.23 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:51:40 PM PDT 24
Peak memory 200048 kb
Host smart-9e3cc196-42c9-474f-a461-49f556ae689e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087445335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2087445335
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2014962581
Short name T250
Test name
Test status
Simulation time 31209844405 ps
CPU time 99.2 seconds
Started Mar 12 01:50:01 PM PDT 24
Finished Mar 12 01:51:40 PM PDT 24
Peak memory 199996 kb
Host smart-5115a86d-b95c-464f-887d-fe6f8b2b24a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014962581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2014962581
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.91681442
Short name T164
Test name
Test status
Simulation time 799854456 ps
CPU time 5.14 seconds
Started Mar 12 01:49:45 PM PDT 24
Finished Mar 12 01:49:50 PM PDT 24
Peak memory 199896 kb
Host smart-b5ce98d5-eb97-4091-b2b4-45bbbae99710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91681442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.91681442
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.493606782
Short name T249
Test name
Test status
Simulation time 24593036958 ps
CPU time 246.77 seconds
Started Mar 12 01:49:35 PM PDT 24
Finished Mar 12 01:53:42 PM PDT 24
Peak memory 199984 kb
Host smart-9336acdd-279e-4ecb-9d05-f2a40a7d99eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493606782 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.493606782
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.168914091
Short name T33
Test name
Test status
Simulation time 58226558 ps
CPU time 1.06 seconds
Started Mar 12 01:49:49 PM PDT 24
Finished Mar 12 01:49:50 PM PDT 24
Peak memory 198876 kb
Host smart-d855f7d2-51c5-4628-b3c3-f6b728fbcda0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168914091 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_hmac_vectors.168914091
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.338769908
Short name T21
Test name
Test status
Simulation time 163420317579 ps
CPU time 610.45 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 02:00:17 PM PDT 24
Peak memory 200060 kb
Host smart-28123c4b-948c-422e-b1c8-1e39a6dc3ef3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338769908 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.338769908
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1916134586
Short name T548
Test name
Test status
Simulation time 4192459574 ps
CPU time 78.59 seconds
Started Mar 12 01:49:58 PM PDT 24
Finished Mar 12 01:51:17 PM PDT 24
Peak memory 199972 kb
Host smart-3a300058-6a5d-4e0d-a1ba-6905d214db7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916134586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1916134586
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.2798728329
Short name T5
Test name
Test status
Simulation time 168928952205 ps
CPU time 2468.42 seconds
Started Mar 12 01:53:26 PM PDT 24
Finished Mar 12 02:34:35 PM PDT 24
Peak memory 249284 kb
Host smart-cf4392d7-2336-4453-a101-1ba6b1bc56dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798728329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.2798728329
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.906442154
Short name T522
Test name
Test status
Simulation time 33866590 ps
CPU time 0.6 seconds
Started Mar 12 01:50:03 PM PDT 24
Finished Mar 12 01:50:04 PM PDT 24
Peak memory 195320 kb
Host smart-90943a5e-c004-4696-8fda-315a3df2bb6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906442154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.906442154
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1401446902
Short name T52
Test name
Test status
Simulation time 563928000 ps
CPU time 21.27 seconds
Started Mar 12 01:49:27 PM PDT 24
Finished Mar 12 01:49:49 PM PDT 24
Peak memory 230752 kb
Host smart-e31f36bb-ce01-4f59-bb2a-0c15ee19e3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401446902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1401446902
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.4050389516
Short name T83
Test name
Test status
Simulation time 1299333768 ps
CPU time 14.88 seconds
Started Mar 12 01:50:07 PM PDT 24
Finished Mar 12 01:50:22 PM PDT 24
Peak memory 199728 kb
Host smart-99639836-1f67-4fe4-86d6-21a17c76ec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050389516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.4050389516
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1176004320
Short name T231
Test name
Test status
Simulation time 1261376569 ps
CPU time 72.89 seconds
Started Mar 12 01:50:07 PM PDT 24
Finished Mar 12 01:51:20 PM PDT 24
Peak memory 199928 kb
Host smart-4f0ffdee-2dbb-4e7d-9b9d-7f7f73665c23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176004320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1176004320
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3052174228
Short name T319
Test name
Test status
Simulation time 11630057436 ps
CPU time 84.81 seconds
Started Mar 12 01:49:42 PM PDT 24
Finished Mar 12 01:51:07 PM PDT 24
Peak memory 199872 kb
Host smart-cacd2805-b82a-4f76-983a-6c82718c770d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052174228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3052174228
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1639073949
Short name T529
Test name
Test status
Simulation time 617863243 ps
CPU time 39.57 seconds
Started Mar 12 01:49:22 PM PDT 24
Finished Mar 12 01:50:02 PM PDT 24
Peak memory 199884 kb
Host smart-a9dcbbd9-fc24-45e0-8473-cb34211e1794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639073949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1639073949
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2549592873
Short name T80
Test name
Test status
Simulation time 612997140 ps
CPU time 7.94 seconds
Started Mar 12 01:49:11 PM PDT 24
Finished Mar 12 01:49:19 PM PDT 24
Peak memory 199836 kb
Host smart-611aab70-c077-49cd-8942-28b5c0f806c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549592873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2549592873
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.863128328
Short name T333
Test name
Test status
Simulation time 144680036876 ps
CPU time 779.85 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 02:03:06 PM PDT 24
Peak memory 199948 kb
Host smart-f0350a4e-306d-4fef-8274-ac9a621bb103
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863128328 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.863128328
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.72089773
Short name T76
Test name
Test status
Simulation time 29381265 ps
CPU time 1 seconds
Started Mar 12 01:49:56 PM PDT 24
Finished Mar 12 01:49:57 PM PDT 24
Peak memory 198960 kb
Host smart-e92fd739-f005-4894-bbfe-a334f679bf51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72089773 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.hmac_test_hmac_vectors.72089773
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.259720300
Short name T136
Test name
Test status
Simulation time 31976678468 ps
CPU time 490.78 seconds
Started Mar 12 01:49:51 PM PDT 24
Finished Mar 12 01:58:02 PM PDT 24
Peak memory 200068 kb
Host smart-57e271da-a74e-4946-9c9d-ec0f3f600194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259720300 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.259720300
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.536464162
Short name T183
Test name
Test status
Simulation time 362881258 ps
CPU time 16.83 seconds
Started Mar 12 01:49:38 PM PDT 24
Finished Mar 12 01:49:55 PM PDT 24
Peak memory 199812 kb
Host smart-c2d7b992-8ec3-4c6b-a1e5-1ba432eb04db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536464162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.536464162
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.2540311510
Short name T41
Test name
Test status
Simulation time 301740420018 ps
CPU time 2483.05 seconds
Started Mar 12 01:53:39 PM PDT 24
Finished Mar 12 02:35:02 PM PDT 24
Peak memory 263532 kb
Host smart-d6ed5148-9c1f-4db3-894c-b839f8dce3ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540311510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.2540311510
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3686037437
Short name T600
Test name
Test status
Simulation time 38922095 ps
CPU time 0.59 seconds
Started Mar 12 01:49:58 PM PDT 24
Finished Mar 12 01:49:59 PM PDT 24
Peak memory 195288 kb
Host smart-af41d222-1124-4b2c-b302-8b583630dcd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686037437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3686037437
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2626997941
Short name T214
Test name
Test status
Simulation time 3695556958 ps
CPU time 34.45 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:50:40 PM PDT 24
Peak memory 221476 kb
Host smart-2f96ea05-6eee-4b79-be37-c6bb2fa6f896
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626997941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2626997941
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1165386678
Short name T328
Test name
Test status
Simulation time 10631837957 ps
CPU time 45.15 seconds
Started Mar 12 01:50:05 PM PDT 24
Finished Mar 12 01:50:50 PM PDT 24
Peak memory 200064 kb
Host smart-e850c0a0-89c2-4d5b-a2c5-dcc8a6d27e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165386678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1165386678
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.383624806
Short name T317
Test name
Test status
Simulation time 1217864699 ps
CPU time 33.22 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:50:39 PM PDT 24
Peak memory 199824 kb
Host smart-4190b836-74c1-4e0a-b392-cb614e5d5240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=383624806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.383624806
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1417046127
Short name T464
Test name
Test status
Simulation time 149433584936 ps
CPU time 118.34 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:52:04 PM PDT 24
Peak memory 200060 kb
Host smart-0d9eebf9-7d73-4a12-b361-ca6708bf3759
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417046127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1417046127
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.131284998
Short name T588
Test name
Test status
Simulation time 30086875538 ps
CPU time 109.64 seconds
Started Mar 12 01:49:33 PM PDT 24
Finished Mar 12 01:51:23 PM PDT 24
Peak memory 200020 kb
Host smart-f8ca8575-8bcd-4cc1-a6af-b2871e286331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131284998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.131284998
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.642018669
Short name T382
Test name
Test status
Simulation time 892779295 ps
CPU time 7.05 seconds
Started Mar 12 01:50:07 PM PDT 24
Finished Mar 12 01:50:14 PM PDT 24
Peak memory 199784 kb
Host smart-89baa8ee-6341-4bab-99ea-c7663e214924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642018669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.642018669
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2989240787
Short name T339
Test name
Test status
Simulation time 111123203089 ps
CPU time 1084.26 seconds
Started Mar 12 01:49:09 PM PDT 24
Finished Mar 12 02:07:14 PM PDT 24
Peak memory 200040 kb
Host smart-65d8ccdb-d657-47d4-8855-c5a385be44bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989240787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2989240787
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2616878030
Short name T163
Test name
Test status
Simulation time 108337667 ps
CPU time 1.14 seconds
Started Mar 12 01:50:04 PM PDT 24
Finished Mar 12 01:50:05 PM PDT 24
Peak memory 199008 kb
Host smart-128ef141-26bf-43e3-9512-1cc713a6af7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616878030 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2616878030
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1261925921
Short name T404
Test name
Test status
Simulation time 118500743835 ps
CPU time 500.18 seconds
Started Mar 12 01:50:01 PM PDT 24
Finished Mar 12 01:58:22 PM PDT 24
Peak memory 200052 kb
Host smart-81c89f35-3818-4faa-864a-7d13a474103a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261925921 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.1261925921
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1161132947
Short name T133
Test name
Test status
Simulation time 21078176370 ps
CPU time 107.86 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:51:54 PM PDT 24
Peak memory 200060 kb
Host smart-91ff06e7-784b-42f7-9f51-6488da2bd780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161132947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1161132947
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.512963827
Short name T9
Test name
Test status
Simulation time 19521881243 ps
CPU time 503.68 seconds
Started Mar 12 01:53:51 PM PDT 24
Finished Mar 12 02:02:17 PM PDT 24
Peak memory 224668 kb
Host smart-52ca7b37-cc0b-4c30-b3c3-c9a664bfb21b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512963827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.512963827
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1305196087
Short name T157
Test name
Test status
Simulation time 39639595 ps
CPU time 0.57 seconds
Started Mar 12 01:44:38 PM PDT 24
Finished Mar 12 01:44:40 PM PDT 24
Peak memory 195340 kb
Host smart-aa73091a-8334-4f5a-81db-8dab7d465708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305196087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1305196087
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1795650585
Short name T423
Test name
Test status
Simulation time 1871128492 ps
CPU time 28.84 seconds
Started Mar 12 01:44:38 PM PDT 24
Finished Mar 12 01:45:08 PM PDT 24
Peak memory 208128 kb
Host smart-28413d78-9062-43d2-b0f4-8c735887fe67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795650585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1795650585
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.577512139
Short name T331
Test name
Test status
Simulation time 687262552 ps
CPU time 34.42 seconds
Started Mar 12 01:44:36 PM PDT 24
Finished Mar 12 01:45:11 PM PDT 24
Peak memory 199896 kb
Host smart-2a3e7948-e144-43e2-b62d-4155bde967d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577512139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.577512139
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3091755952
Short name T375
Test name
Test status
Simulation time 734103265 ps
CPU time 46.13 seconds
Started Mar 12 01:44:38 PM PDT 24
Finished Mar 12 01:45:25 PM PDT 24
Peak memory 199932 kb
Host smart-1867cd63-0271-44eb-a9df-f0812934d2a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091755952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3091755952
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3848278520
Short name T348
Test name
Test status
Simulation time 7193915879 ps
CPU time 100.8 seconds
Started Mar 12 01:44:37 PM PDT 24
Finished Mar 12 01:46:19 PM PDT 24
Peak memory 200044 kb
Host smart-cc084bcb-6511-459c-8f06-0647a6308913
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848278520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3848278520
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.4127208068
Short name T291
Test name
Test status
Simulation time 3963427078 ps
CPU time 14.2 seconds
Started Mar 12 01:44:38 PM PDT 24
Finished Mar 12 01:44:54 PM PDT 24
Peak memory 200032 kb
Host smart-499ca43a-6c1f-4437-95ce-feb1cef41e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127208068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.4127208068
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2728787460
Short name T30
Test name
Test status
Simulation time 87759165 ps
CPU time 1 seconds
Started Mar 12 01:44:36 PM PDT 24
Finished Mar 12 01:44:37 PM PDT 24
Peak memory 219456 kb
Host smart-633f9514-d8b1-4bdf-b733-a56247fd257c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728787460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2728787460
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.304717837
Short name T284
Test name
Test status
Simulation time 113397673 ps
CPU time 3.57 seconds
Started Mar 12 01:44:37 PM PDT 24
Finished Mar 12 01:44:41 PM PDT 24
Peak memory 199948 kb
Host smart-68eb0dee-d83f-43df-aa27-751cf358c487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304717837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.304717837
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1406659460
Short name T512
Test name
Test status
Simulation time 999923824 ps
CPU time 15.07 seconds
Started Mar 12 01:44:37 PM PDT 24
Finished Mar 12 01:44:53 PM PDT 24
Peak memory 208144 kb
Host smart-e6fadd25-e94b-49a6-b0fc-43d7e9eff98f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406659460 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1406659460
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.507032744
Short name T391
Test name
Test status
Simulation time 143937029 ps
CPU time 1.28 seconds
Started Mar 12 01:44:38 PM PDT 24
Finished Mar 12 01:44:40 PM PDT 24
Peak memory 198548 kb
Host smart-85641ab2-4a56-4d31-b863-49487cf3c9fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507032744 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.507032744
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2050074020
Short name T447
Test name
Test status
Simulation time 190176639684 ps
CPU time 461.87 seconds
Started Mar 12 01:44:37 PM PDT 24
Finished Mar 12 01:52:20 PM PDT 24
Peak memory 199996 kb
Host smart-eaf9a953-ed57-4f8e-bbe9-ee96191bfbeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050074020 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2050074020
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1352954832
Short name T345
Test name
Test status
Simulation time 2852516872 ps
CPU time 82.16 seconds
Started Mar 12 01:44:34 PM PDT 24
Finished Mar 12 01:45:57 PM PDT 24
Peak memory 199956 kb
Host smart-730d7215-5a9e-419c-8a47-3474387cf694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352954832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1352954832
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3303342738
Short name T17
Test name
Test status
Simulation time 27458581 ps
CPU time 0.56 seconds
Started Mar 12 01:49:58 PM PDT 24
Finished Mar 12 01:49:58 PM PDT 24
Peak memory 194312 kb
Host smart-61188f64-0ff6-4147-b6c9-6eafeb67cb4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303342738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3303342738
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3613026071
Short name T499
Test name
Test status
Simulation time 230183606 ps
CPU time 10.01 seconds
Started Mar 12 01:50:07 PM PDT 24
Finished Mar 12 01:50:17 PM PDT 24
Peak memory 224532 kb
Host smart-fdc62e45-100b-4447-9408-4c348280fc44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613026071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3613026071
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3061040930
Short name T305
Test name
Test status
Simulation time 297252629 ps
CPU time 5.83 seconds
Started Mar 12 01:49:56 PM PDT 24
Finished Mar 12 01:50:02 PM PDT 24
Peak memory 199824 kb
Host smart-4a8adcc8-ab41-4813-81bf-d1b445c327c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061040930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3061040930
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3317104341
Short name T135
Test name
Test status
Simulation time 2639164932 ps
CPU time 149.62 seconds
Started Mar 12 01:50:07 PM PDT 24
Finished Mar 12 01:52:37 PM PDT 24
Peak memory 199992 kb
Host smart-054e0138-9823-4100-a43b-a1c8e391351e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3317104341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3317104341
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_long_msg.281422248
Short name T277
Test name
Test status
Simulation time 1965773581 ps
CPU time 60.25 seconds
Started Mar 12 01:49:47 PM PDT 24
Finished Mar 12 01:50:48 PM PDT 24
Peak memory 199884 kb
Host smart-9b437d65-2c4e-447a-a189-4725176dca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281422248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.281422248
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1771925397
Short name T390
Test name
Test status
Simulation time 304653463 ps
CPU time 4 seconds
Started Mar 12 01:50:03 PM PDT 24
Finished Mar 12 01:50:07 PM PDT 24
Peak memory 199896 kb
Host smart-8f7380b8-2cea-4c71-a5f1-fd83d396fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771925397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1771925397
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.627006489
Short name T434
Test name
Test status
Simulation time 588824139379 ps
CPU time 1905.68 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 02:21:52 PM PDT 24
Peak memory 230180 kb
Host smart-cd690ba0-a4df-43fb-a032-5764e81aaac7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627006489 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.627006489
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1283506310
Short name T341
Test name
Test status
Simulation time 226609437 ps
CPU time 0.97 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:50:07 PM PDT 24
Peak memory 199680 kb
Host smart-2632dd90-ef35-4a97-8e19-bd92f0321777
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283506310 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1283506310
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2349950790
Short name T178
Test name
Test status
Simulation time 20580810265 ps
CPU time 416.69 seconds
Started Mar 12 01:49:49 PM PDT 24
Finished Mar 12 01:56:46 PM PDT 24
Peak memory 200028 kb
Host smart-6b3977f1-13e5-4c49-9151-44a2083cdea0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349950790 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2349950790
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4147505889
Short name T194
Test name
Test status
Simulation time 2659241522 ps
CPU time 58.63 seconds
Started Mar 12 01:49:38 PM PDT 24
Finished Mar 12 01:50:37 PM PDT 24
Peak memory 199968 kb
Host smart-c914fe1b-d6c3-4967-8333-dc86597a4280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147505889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4147505889
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.786640342
Short name T209
Test name
Test status
Simulation time 13714053 ps
CPU time 0.59 seconds
Started Mar 12 01:50:07 PM PDT 24
Finished Mar 12 01:50:07 PM PDT 24
Peak memory 194312 kb
Host smart-4dcbf3aa-6114-4179-8dc8-4efa8656d79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786640342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.786640342
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.101745239
Short name T260
Test name
Test status
Simulation time 505176129 ps
CPU time 19.83 seconds
Started Mar 12 01:50:05 PM PDT 24
Finished Mar 12 01:50:25 PM PDT 24
Peak memory 208128 kb
Host smart-a39dca9e-b808-4639-9a6e-f760c5d4e113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101745239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.101745239
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3639779425
Short name T239
Test name
Test status
Simulation time 7103600683 ps
CPU time 28.85 seconds
Started Mar 12 01:49:39 PM PDT 24
Finished Mar 12 01:50:08 PM PDT 24
Peak memory 199984 kb
Host smart-e088f1af-efac-42b2-9c21-4e07ceda09e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639779425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3639779425
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2483064775
Short name T81
Test name
Test status
Simulation time 5153036018 ps
CPU time 101.12 seconds
Started Mar 12 01:49:51 PM PDT 24
Finished Mar 12 01:51:32 PM PDT 24
Peak memory 199956 kb
Host smart-c32580ea-cda9-437d-9383-2e65613d9c3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483064775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2483064775
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2928903268
Short name T160
Test name
Test status
Simulation time 4959837198 ps
CPU time 13.63 seconds
Started Mar 12 01:50:08 PM PDT 24
Finished Mar 12 01:50:22 PM PDT 24
Peak memory 200060 kb
Host smart-ed0dc108-d9de-428a-b6e7-90c6a5704d2c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928903268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2928903268
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2355230342
Short name T259
Test name
Test status
Simulation time 5032266993 ps
CPU time 74.77 seconds
Started Mar 12 01:50:04 PM PDT 24
Finished Mar 12 01:51:18 PM PDT 24
Peak memory 200028 kb
Host smart-10742a95-f896-439d-8f17-bcac861adfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355230342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2355230342
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2750822781
Short name T220
Test name
Test status
Simulation time 1584437218 ps
CPU time 4.74 seconds
Started Mar 12 01:49:17 PM PDT 24
Finished Mar 12 01:49:22 PM PDT 24
Peak memory 199868 kb
Host smart-9b40c718-fb14-4a6d-bf0e-30a8ba17eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750822781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2750822781
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3519277923
Short name T574
Test name
Test status
Simulation time 132445665085 ps
CPU time 2559.73 seconds
Started Mar 12 01:50:00 PM PDT 24
Finished Mar 12 02:32:40 PM PDT 24
Peak memory 224580 kb
Host smart-f51e39c1-8e77-4b2b-8412-bf94d81a831c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519277923 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3519277923
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1610404096
Short name T274
Test name
Test status
Simulation time 74639442 ps
CPU time 1.42 seconds
Started Mar 12 01:49:50 PM PDT 24
Finished Mar 12 01:49:52 PM PDT 24
Peak memory 199352 kb
Host smart-b64268fe-0c0f-4820-82e6-2ead70912512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610404096 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1610404096
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.996945092
Short name T361
Test name
Test status
Simulation time 44224895518 ps
CPU time 559.37 seconds
Started Mar 12 01:49:19 PM PDT 24
Finished Mar 12 01:58:39 PM PDT 24
Peak memory 200020 kb
Host smart-0dd9a720-2b3e-49c1-99ef-f50d2d9e0e9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996945092 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.996945092
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4293260812
Short name T308
Test name
Test status
Simulation time 2645795439 ps
CPU time 4.01 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:50:10 PM PDT 24
Peak memory 199924 kb
Host smart-d2aef255-892d-42d7-92e8-cb7eb8e61792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293260812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4293260812
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2945039974
Short name T153
Test name
Test status
Simulation time 40546795 ps
CPU time 0.57 seconds
Started Mar 12 01:50:04 PM PDT 24
Finished Mar 12 01:50:05 PM PDT 24
Peak memory 195304 kb
Host smart-4d6d0d6a-0c0b-40fd-9b18-82aa9d1db27a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945039974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2945039974
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.55906195
Short name T399
Test name
Test status
Simulation time 890691638 ps
CPU time 8.33 seconds
Started Mar 12 01:49:37 PM PDT 24
Finished Mar 12 01:49:45 PM PDT 24
Peak memory 208112 kb
Host smart-7c13e8c1-47cd-4ee8-b982-40db66765ade
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55906195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.55906195
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.384639666
Short name T140
Test name
Test status
Simulation time 820992047 ps
CPU time 10.69 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:50:17 PM PDT 24
Peak memory 199928 kb
Host smart-5bed726d-0df7-4bfe-b903-1d094a9b8f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384639666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.384639666
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1809366201
Short name T158
Test name
Test status
Simulation time 7920256032 ps
CPU time 112.25 seconds
Started Mar 12 01:50:03 PM PDT 24
Finished Mar 12 01:51:56 PM PDT 24
Peak memory 200008 kb
Host smart-4a281e9d-dbce-4ed5-8c58-28007c1610e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809366201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1809366201
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3480300393
Short name T497
Test name
Test status
Simulation time 714422233 ps
CPU time 38.25 seconds
Started Mar 12 01:50:03 PM PDT 24
Finished Mar 12 01:50:41 PM PDT 24
Peak memory 199912 kb
Host smart-4773d564-0f1a-4d73-9d70-f8e56d2a2db6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480300393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3480300393
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.695759073
Short name T562
Test name
Test status
Simulation time 671081193 ps
CPU time 16.97 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:50:23 PM PDT 24
Peak memory 199852 kb
Host smart-2c66f39b-ef6d-4d33-b99f-0e5cbc73002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695759073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.695759073
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3607820826
Short name T546
Test name
Test status
Simulation time 6518411235 ps
CPU time 5.64 seconds
Started Mar 12 01:49:40 PM PDT 24
Finished Mar 12 01:49:45 PM PDT 24
Peak memory 200016 kb
Host smart-15b7eb46-b66b-4156-936c-a09905622753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607820826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3607820826
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1656610579
Short name T109
Test name
Test status
Simulation time 15351545171 ps
CPU time 841.92 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 02:04:08 PM PDT 24
Peak memory 230140 kb
Host smart-fdf43b30-2417-43ad-833f-0f0955f3a32b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656610579 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1656610579
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.260406184
Short name T10
Test name
Test status
Simulation time 38293159818 ps
CPU time 291.87 seconds
Started Mar 12 01:49:55 PM PDT 24
Finished Mar 12 01:54:47 PM PDT 24
Peak memory 216492 kb
Host smart-441b8292-27b5-43bb-9513-566715db6fbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260406184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.260406184
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.433925175
Short name T381
Test name
Test status
Simulation time 113001007 ps
CPU time 1.15 seconds
Started Mar 12 01:50:06 PM PDT 24
Finished Mar 12 01:50:07 PM PDT 24
Peak memory 198676 kb
Host smart-b6d0537c-e5aa-4925-914f-5d0a5644e8a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433925175 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.433925175
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.203977298
Short name T126
Test name
Test status
Simulation time 53282630682 ps
CPU time 468 seconds
Started Mar 12 01:50:07 PM PDT 24
Finished Mar 12 01:57:55 PM PDT 24
Peak memory 199964 kb
Host smart-c306553d-a0ba-46c6-8109-1ec09a5e3b4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203977298 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.203977298
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3861262868
Short name T466
Test name
Test status
Simulation time 9604728763 ps
CPU time 74.26 seconds
Started Mar 12 01:50:04 PM PDT 24
Finished Mar 12 01:51:18 PM PDT 24
Peak memory 200028 kb
Host smart-0de08fef-4665-4e60-98f0-6702dd05a728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861262868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3861262868
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2364657280
Short name T302
Test name
Test status
Simulation time 14818531 ps
CPU time 0.55 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:50:26 PM PDT 24
Peak memory 195344 kb
Host smart-1cfbb5ca-b422-4227-b154-1404fa6fdc8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364657280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2364657280
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2903272781
Short name T37
Test name
Test status
Simulation time 276310156 ps
CPU time 14.26 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:50:40 PM PDT 24
Peak memory 231576 kb
Host smart-4dbb3a12-cf20-42de-98a7-c537db90a9fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903272781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2903272781
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3063062598
Short name T460
Test name
Test status
Simulation time 9327386372 ps
CPU time 68.17 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:51:34 PM PDT 24
Peak memory 200072 kb
Host smart-d83c605c-10ca-4243-8131-2060d94e663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063062598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3063062598
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.484096743
Short name T359
Test name
Test status
Simulation time 3237396589 ps
CPU time 54.73 seconds
Started Mar 12 01:50:15 PM PDT 24
Finished Mar 12 01:51:10 PM PDT 24
Peak memory 199984 kb
Host smart-e308dd75-ab77-490e-a2a3-3c893530903c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484096743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.484096743
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1267428572
Short name T44
Test name
Test status
Simulation time 6454628559 ps
CPU time 67.51 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:51:33 PM PDT 24
Peak memory 199968 kb
Host smart-6a328ed8-f668-461e-abca-7d0e75c347d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267428572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1267428572
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.854937062
Short name T226
Test name
Test status
Simulation time 548509904 ps
CPU time 32.72 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:50:58 PM PDT 24
Peak memory 199912 kb
Host smart-56620d4c-714e-458d-9363-538fecbb7349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854937062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.854937062
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2320994143
Short name T417
Test name
Test status
Simulation time 21649289 ps
CPU time 0.9 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:50:26 PM PDT 24
Peak memory 198048 kb
Host smart-10e0321e-d134-4179-b25d-fe60c8ba9053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320994143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2320994143
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.133149390
Short name T583
Test name
Test status
Simulation time 47877265519 ps
CPU time 614.52 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 02:00:40 PM PDT 24
Peak memory 200100 kb
Host smart-79ec34bb-49d5-45d9-946b-b6dafeeb37ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133149390 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.133149390
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1764180812
Short name T131
Test name
Test status
Simulation time 107193193 ps
CPU time 1.16 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:50:27 PM PDT 24
Peak memory 198944 kb
Host smart-fd645def-1fee-4733-8bb4-b04b5ef9b751
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764180812 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1764180812
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3194017060
Short name T518
Test name
Test status
Simulation time 47400973894 ps
CPU time 430.37 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:57:36 PM PDT 24
Peak memory 200040 kb
Host smart-8d490dfa-b04d-42a8-8062-3c18d42ad2b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194017060 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3194017060
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1439612173
Short name T526
Test name
Test status
Simulation time 2130680313 ps
CPU time 40.81 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:51:07 PM PDT 24
Peak memory 199952 kb
Host smart-aec88672-2f94-405b-98b2-8bce88aee9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439612173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1439612173
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3770395360
Short name T463
Test name
Test status
Simulation time 12118083 ps
CPU time 0.56 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:50:26 PM PDT 24
Peak memory 194336 kb
Host smart-c7315e95-f633-4b55-be6c-2a7c05699f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770395360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3770395360
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2644833410
Short name T14
Test name
Test status
Simulation time 2162514783 ps
CPU time 19.58 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:50:45 PM PDT 24
Peak memory 215612 kb
Host smart-bcad472d-36ee-4f1c-9efd-abd102ba95b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644833410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2644833410
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2489226075
Short name T566
Test name
Test status
Simulation time 2577686918 ps
CPU time 27.02 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:50:52 PM PDT 24
Peak memory 199996 kb
Host smart-54a467ac-ad5b-485f-854a-512134a99d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489226075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2489226075
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3581760292
Short name T582
Test name
Test status
Simulation time 6005690555 ps
CPU time 87.01 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:51:53 PM PDT 24
Peak memory 200084 kb
Host smart-9fa27c49-aa07-4621-a003-c92b30800d01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581760292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3581760292
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.135401875
Short name T24
Test name
Test status
Simulation time 34935135020 ps
CPU time 135.5 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:52:42 PM PDT 24
Peak memory 200028 kb
Host smart-84492bb2-f253-4d93-80b6-26d1ee9736a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135401875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.135401875
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1435148791
Short name T377
Test name
Test status
Simulation time 3207770308 ps
CPU time 34.27 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:50:59 PM PDT 24
Peak memory 199888 kb
Host smart-319e97c9-d991-4fc6-aa88-7dd7b376e8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435148791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1435148791
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2517237136
Short name T72
Test name
Test status
Simulation time 218101298 ps
CPU time 6.81 seconds
Started Mar 12 01:50:21 PM PDT 24
Finished Mar 12 01:50:29 PM PDT 24
Peak memory 199896 kb
Host smart-9e5519fa-d758-49ff-a3eb-6dba09d505e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517237136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2517237136
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.417945189
Short name T66
Test name
Test status
Simulation time 286163044677 ps
CPU time 1002.71 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 02:07:08 PM PDT 24
Peak memory 200076 kb
Host smart-9fb38a3a-12c8-4360-8449-3a38a21dfc9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417945189 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.417945189
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2813791942
Short name T597
Test name
Test status
Simulation time 41302284 ps
CPU time 1.29 seconds
Started Mar 12 01:50:12 PM PDT 24
Finished Mar 12 01:50:13 PM PDT 24
Peak memory 199500 kb
Host smart-21fe0e71-0d34-4693-ba6f-d68ada3c5912
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813791942 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2813791942
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2251591700
Short name T234
Test name
Test status
Simulation time 40409474534 ps
CPU time 552.87 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:59:39 PM PDT 24
Peak memory 200024 kb
Host smart-f876b602-a863-489e-abb5-54cfd8a8c835
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251591700 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.2251591700
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3933860969
Short name T528
Test name
Test status
Simulation time 25487633670 ps
CPU time 90.36 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:51:57 PM PDT 24
Peak memory 200020 kb
Host smart-cc7e7541-fecc-4d03-9d4f-89a9faf07452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933860969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3933860969
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3082717053
Short name T549
Test name
Test status
Simulation time 13963893 ps
CPU time 0.6 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:50:26 PM PDT 24
Peak memory 195348 kb
Host smart-8962cd6d-fcd2-4050-b193-76149c6a55e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082717053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3082717053
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1984344814
Short name T207
Test name
Test status
Simulation time 1322578745 ps
CPU time 54.19 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:51:20 PM PDT 24
Peak memory 234740 kb
Host smart-0e1870e9-369e-4cd4-a44d-d6d7ceb548b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1984344814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1984344814
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.87004174
Short name T173
Test name
Test status
Simulation time 802203593 ps
CPU time 16.83 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:50:43 PM PDT 24
Peak memory 199876 kb
Host smart-aea6f5bc-6d2e-4209-b55d-478705e7bcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87004174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.87004174
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1643503748
Short name T360
Test name
Test status
Simulation time 975063500 ps
CPU time 55.38 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:51:21 PM PDT 24
Peak memory 199920 kb
Host smart-030d59f4-a5d3-42eb-890c-6c789ca15ec2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643503748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1643503748
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3614656382
Short name T530
Test name
Test status
Simulation time 10811790236 ps
CPU time 139.25 seconds
Started Mar 12 01:50:11 PM PDT 24
Finished Mar 12 01:52:30 PM PDT 24
Peak memory 199976 kb
Host smart-a1400c45-0df7-4efa-80bd-553cd9fa5eb2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614656382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3614656382
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.14656571
Short name T458
Test name
Test status
Simulation time 216750272 ps
CPU time 4.9 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:50:30 PM PDT 24
Peak memory 199936 kb
Host smart-ccfbd4b3-eea5-4d42-a775-99c1419eed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14656571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.14656571
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3040900337
Short name T418
Test name
Test status
Simulation time 352446188 ps
CPU time 2.16 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:50:28 PM PDT 24
Peak memory 199928 kb
Host smart-a7a29e77-b9d9-486d-8714-4d91c2817ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040900337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3040900337
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.417418078
Short name T196
Test name
Test status
Simulation time 24522066051 ps
CPU time 336.87 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:56:03 PM PDT 24
Peak memory 200060 kb
Host smart-da958265-cbc2-4f4b-bb3e-f043d5602a87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417418078 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.417418078
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3422340591
Short name T514
Test name
Test status
Simulation time 59451644 ps
CPU time 1.47 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:50:27 PM PDT 24
Peak memory 199828 kb
Host smart-e8d3f3f6-77bd-492b-8c3c-0b7204ae0220
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422340591 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3422340591
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.4044013675
Short name T414
Test name
Test status
Simulation time 26309155591 ps
CPU time 454.66 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:58:00 PM PDT 24
Peak memory 200032 kb
Host smart-4bb9534d-dbb5-4c9b-a53a-d63e9f201dec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044013675 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.4044013675
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.224968255
Short name T343
Test name
Test status
Simulation time 364488859 ps
CPU time 5.94 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:50:32 PM PDT 24
Peak memory 199896 kb
Host smart-80e8afd2-75a1-4fc3-aaa5-53a705152aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224968255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.224968255
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2197120810
Short name T427
Test name
Test status
Simulation time 24831723 ps
CPU time 0.56 seconds
Started Mar 12 01:50:22 PM PDT 24
Finished Mar 12 01:50:23 PM PDT 24
Peak memory 194312 kb
Host smart-5c44976a-35b9-4eb4-a749-392622685f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197120810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2197120810
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1170468127
Short name T401
Test name
Test status
Simulation time 2778828309 ps
CPU time 46.75 seconds
Started Mar 12 01:50:27 PM PDT 24
Finished Mar 12 01:51:14 PM PDT 24
Peak memory 216336 kb
Host smart-2865a52f-0c58-4776-a52d-bf3366fccd4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170468127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1170468127
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1527167301
Short name T507
Test name
Test status
Simulation time 3228868385 ps
CPU time 52.12 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:51:18 PM PDT 24
Peak memory 199988 kb
Host smart-d35533e0-d63e-4e3a-a356-d5ee8aff6c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527167301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1527167301
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1615793412
Short name T544
Test name
Test status
Simulation time 8368765895 ps
CPU time 121.5 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:52:27 PM PDT 24
Peak memory 199984 kb
Host smart-14d944c6-0dd2-4524-8e17-17ef3ed55c82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615793412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1615793412
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3127185423
Short name T23
Test name
Test status
Simulation time 10421680288 ps
CPU time 139.55 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:52:46 PM PDT 24
Peak memory 200044 kb
Host smart-c1d02eaa-11e1-4186-b1a4-c751be00ffd0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127185423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3127185423
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.306907030
Short name T145
Test name
Test status
Simulation time 27070506179 ps
CPU time 114.59 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:52:20 PM PDT 24
Peak memory 200004 kb
Host smart-a8e381ca-863f-416b-bd0b-ae1bd577d274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306907030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.306907030
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3216916026
Short name T473
Test name
Test status
Simulation time 831058384 ps
CPU time 4.36 seconds
Started Mar 12 01:50:19 PM PDT 24
Finished Mar 12 01:50:24 PM PDT 24
Peak memory 199908 kb
Host smart-c1f9419a-f44f-4e68-86f1-4718f5beedc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216916026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3216916026
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3133040893
Short name T494
Test name
Test status
Simulation time 48254022143 ps
CPU time 684.83 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 02:01:51 PM PDT 24
Peak memory 200048 kb
Host smart-c9f26ad3-b202-4f3c-96fb-8b2cef1f2308
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133040893 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3133040893
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3883398423
Short name T525
Test name
Test status
Simulation time 49065524 ps
CPU time 1.06 seconds
Started Mar 12 01:50:29 PM PDT 24
Finished Mar 12 01:50:30 PM PDT 24
Peak memory 198892 kb
Host smart-bef85498-1921-4b87-bc45-682d6b59fa6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883398423 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.3883398423
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1439504797
Short name T385
Test name
Test status
Simulation time 249506369077 ps
CPU time 551.15 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:59:38 PM PDT 24
Peak memory 200020 kb
Host smart-e79957ae-1a22-40e7-8249-885b4b978c38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439504797 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1439504797
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3957750457
Short name T462
Test name
Test status
Simulation time 819684026 ps
CPU time 26.98 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:50:52 PM PDT 24
Peak memory 199932 kb
Host smart-7fed3018-6ece-4142-9903-7e60de68b650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957750457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3957750457
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1971134772
Short name T409
Test name
Test status
Simulation time 28155708 ps
CPU time 0.58 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:50:27 PM PDT 24
Peak memory 195352 kb
Host smart-253ab92d-1bcc-4cbc-84ea-5cd35142d259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971134772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1971134772
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2732089939
Short name T228
Test name
Test status
Simulation time 5984954129 ps
CPU time 28.97 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:50:54 PM PDT 24
Peak memory 208244 kb
Host smart-2a21d5de-3593-48b6-92f7-000f3f8c5c79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2732089939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2732089939
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3342974209
Short name T352
Test name
Test status
Simulation time 1097893490 ps
CPU time 9.39 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:50:35 PM PDT 24
Peak memory 200180 kb
Host smart-1d82ae52-06b6-4d54-bd73-9126e0ee0b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342974209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3342974209
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.853237407
Short name T187
Test name
Test status
Simulation time 2181855750 ps
CPU time 136.13 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:52:42 PM PDT 24
Peak memory 199952 kb
Host smart-6d68d086-f7f5-409d-9de7-c6977f9695b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853237407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.853237407
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2873238019
Short name T508
Test name
Test status
Simulation time 2313245239 ps
CPU time 125.65 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:52:32 PM PDT 24
Peak memory 199984 kb
Host smart-7cdbc5a6-97aa-40ad-90d6-ab8ac6a252ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873238019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2873238019
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1853851161
Short name T127
Test name
Test status
Simulation time 1045512942 ps
CPU time 31.4 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:50:56 PM PDT 24
Peak memory 199912 kb
Host smart-4604bb3f-a84a-4bca-b06c-5059f1c70a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853851161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1853851161
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.915101226
Short name T344
Test name
Test status
Simulation time 235042498 ps
CPU time 3.99 seconds
Started Mar 12 01:50:27 PM PDT 24
Finished Mar 12 01:50:31 PM PDT 24
Peak memory 199912 kb
Host smart-84e67aa4-0636-4711-8b5e-dfbd22c10704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915101226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.915101226
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3628905747
Short name T595
Test name
Test status
Simulation time 64572791176 ps
CPU time 908.29 seconds
Started Mar 12 01:50:27 PM PDT 24
Finished Mar 12 02:05:35 PM PDT 24
Peak memory 231652 kb
Host smart-258bb116-0280-475c-b844-6506dbbf759a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628905747 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3628905747
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1932891456
Short name T236
Test name
Test status
Simulation time 57114732 ps
CPU time 0.98 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:50:26 PM PDT 24
Peak memory 198196 kb
Host smart-3ba1fcae-88b2-4219-a3d4-9a0bb56763a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932891456 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1932891456
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.481275022
Short name T469
Test name
Test status
Simulation time 85894395952 ps
CPU time 401.23 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:57:06 PM PDT 24
Peak memory 200068 kb
Host smart-f571e8eb-7d18-4b2b-87e9-c418ff3a9014
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481275022 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.481275022
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1664062890
Short name T175
Test name
Test status
Simulation time 5846471866 ps
CPU time 51.12 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:51:17 PM PDT 24
Peak memory 200020 kb
Host smart-c52f999e-eb1a-4507-b894-3ab5ea425051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664062890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1664062890
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1142304460
Short name T74
Test name
Test status
Simulation time 37655012 ps
CPU time 0.57 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:50:27 PM PDT 24
Peak memory 195340 kb
Host smart-c1c76271-68a6-4f75-b970-2e5bcd7859f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142304460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1142304460
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1770197427
Short name T268
Test name
Test status
Simulation time 1018906283 ps
CPU time 21.89 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:50:48 PM PDT 24
Peak memory 228984 kb
Host smart-fd2f6b8b-68e5-4291-a41b-ad31849f1cd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770197427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1770197427
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.130685478
Short name T598
Test name
Test status
Simulation time 1616091169 ps
CPU time 77.38 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:51:44 PM PDT 24
Peak memory 199896 kb
Host smart-baf9e131-a6ae-41ae-9725-7d22e858ecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130685478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.130685478
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3023580545
Short name T276
Test name
Test status
Simulation time 1565597537 ps
CPU time 92.32 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:51:59 PM PDT 24
Peak memory 199868 kb
Host smart-4eecdfc4-b10a-4df1-a082-7a90cec62bcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023580545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3023580545
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3787669766
Short name T46
Test name
Test status
Simulation time 6782063372 ps
CPU time 132.12 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:52:38 PM PDT 24
Peak memory 200016 kb
Host smart-b12a5aad-9fc3-40e4-b0ec-7df0337548ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787669766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3787669766
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.272318133
Short name T501
Test name
Test status
Simulation time 4593466124 ps
CPU time 24.81 seconds
Started Mar 12 01:50:27 PM PDT 24
Finished Mar 12 01:50:52 PM PDT 24
Peak memory 200036 kb
Host smart-3f896dc4-530e-463a-84a6-89dda15c8d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272318133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.272318133
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.811770159
Short name T205
Test name
Test status
Simulation time 400345845 ps
CPU time 3.43 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:50:29 PM PDT 24
Peak memory 199924 kb
Host smart-21539e51-3a57-4e6e-93ce-e7107391c624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811770159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.811770159
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3335676005
Short name T413
Test name
Test status
Simulation time 246018481603 ps
CPU time 1158.03 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 02:09:44 PM PDT 24
Peak memory 200044 kb
Host smart-5c71f007-6e59-483f-a4d1-4f93d79d5b30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335676005 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3335676005
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1395797909
Short name T520
Test name
Test status
Simulation time 571334838 ps
CPU time 1.26 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:50:27 PM PDT 24
Peak memory 199664 kb
Host smart-9b60e46f-66e0-4f07-a291-85b6e1c35d98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395797909 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1395797909
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.715564414
Short name T219
Test name
Test status
Simulation time 71100964002 ps
CPU time 406.32 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:57:12 PM PDT 24
Peak memory 200024 kb
Host smart-fbee9441-5597-455c-b4d9-0550c0df14f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715564414 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.715564414
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3073028413
Short name T149
Test name
Test status
Simulation time 886606744 ps
CPU time 33.99 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:51:00 PM PDT 24
Peak memory 199932 kb
Host smart-bc01c4e7-2f5a-4d0d-bc1b-82226d4b8ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073028413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3073028413
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3361100567
Short name T586
Test name
Test status
Simulation time 44953509 ps
CPU time 0.59 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:50:26 PM PDT 24
Peak memory 195360 kb
Host smart-bf6cbeaf-ad92-4a32-b206-fe9d8499f1b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361100567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3361100567
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1276075319
Short name T280
Test name
Test status
Simulation time 1890893930 ps
CPU time 33 seconds
Started Mar 12 01:50:10 PM PDT 24
Finished Mar 12 01:50:44 PM PDT 24
Peak memory 208104 kb
Host smart-2c32eaca-e506-4d1a-8b74-a4c40f514dea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1276075319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1276075319
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1737706608
Short name T132
Test name
Test status
Simulation time 1503157612 ps
CPU time 38.46 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:51:03 PM PDT 24
Peak memory 199872 kb
Host smart-4640dcc1-aa83-483d-8d14-735d97293978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737706608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1737706608
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4266429077
Short name T323
Test name
Test status
Simulation time 1706580756 ps
CPU time 102.43 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:52:08 PM PDT 24
Peak memory 199892 kb
Host smart-5e8749bf-f936-4b0e-bbd8-6d6c42535132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266429077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4266429077
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3766245792
Short name T356
Test name
Test status
Simulation time 3105735105 ps
CPU time 60.1 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:51:26 PM PDT 24
Peak memory 199984 kb
Host smart-774d9864-9200-43a0-9b8e-9670b5467fdf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766245792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3766245792
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1246616145
Short name T20
Test name
Test status
Simulation time 4633638011 ps
CPU time 46.02 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:51:12 PM PDT 24
Peak memory 200084 kb
Host smart-3e649481-1b5d-48d2-8b90-b7eb633dbc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246616145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1246616145
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3778727310
Short name T437
Test name
Test status
Simulation time 109209356 ps
CPU time 1.81 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:50:28 PM PDT 24
Peak memory 199908 kb
Host smart-1ffd8dbf-a02c-4319-9309-488ccf483957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778727310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3778727310
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1956244576
Short name T137
Test name
Test status
Simulation time 11877734161 ps
CPU time 66.22 seconds
Started Mar 12 01:50:28 PM PDT 24
Finished Mar 12 01:51:35 PM PDT 24
Peak memory 216124 kb
Host smart-6d2f4fa0-5992-4230-8f9d-a280dbf8cb2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956244576 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1956244576
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1786618144
Short name T285
Test name
Test status
Simulation time 166617263 ps
CPU time 1.09 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:50:27 PM PDT 24
Peak memory 199152 kb
Host smart-79a1c141-3455-4f3e-8cc3-4b81a371ef4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786618144 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1786618144
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.773896674
Short name T558
Test name
Test status
Simulation time 30025840127 ps
CPU time 426.58 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:57:33 PM PDT 24
Peak memory 200088 kb
Host smart-9df9dc1c-5086-494f-b6c6-5d4191127be7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773896674 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.773896674
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2804595999
Short name T225
Test name
Test status
Simulation time 1695399583 ps
CPU time 37.07 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:51:03 PM PDT 24
Peak memory 199960 kb
Host smart-e3552f6e-1bfd-4333-8b4d-2cd67d1bea6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804595999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2804595999
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.555710617
Short name T405
Test name
Test status
Simulation time 41592848 ps
CPU time 0.56 seconds
Started Mar 12 01:44:45 PM PDT 24
Finished Mar 12 01:44:47 PM PDT 24
Peak memory 194284 kb
Host smart-a2a45e4a-3dc1-461f-93f4-21748e8b9657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555710617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.555710617
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.352156671
Short name T581
Test name
Test status
Simulation time 6437524159 ps
CPU time 27.72 seconds
Started Mar 12 01:44:39 PM PDT 24
Finished Mar 12 01:45:07 PM PDT 24
Peak memory 224632 kb
Host smart-391f2d8e-870e-4491-b318-a82fb4ec138d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352156671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.352156671
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.503089596
Short name T299
Test name
Test status
Simulation time 340291686 ps
CPU time 16.58 seconds
Started Mar 12 01:44:37 PM PDT 24
Finished Mar 12 01:44:54 PM PDT 24
Peak memory 199900 kb
Host smart-3266c922-5ad9-4847-9fe8-437a43a377f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503089596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.503089596
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2414039495
Short name T521
Test name
Test status
Simulation time 759226013 ps
CPU time 53.26 seconds
Started Mar 12 01:44:39 PM PDT 24
Finished Mar 12 01:45:34 PM PDT 24
Peak memory 199888 kb
Host smart-4452d564-7ee9-42a8-af18-fe671693b14c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414039495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2414039495
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.4081603411
Short name T141
Test name
Test status
Simulation time 3005932757 ps
CPU time 159.41 seconds
Started Mar 12 01:44:36 PM PDT 24
Finished Mar 12 01:47:16 PM PDT 24
Peak memory 199972 kb
Host smart-94087e2c-7eed-4434-8cff-cebe0d35dc21
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081603411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.4081603411
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2463231674
Short name T362
Test name
Test status
Simulation time 3097849902 ps
CPU time 51.01 seconds
Started Mar 12 01:44:39 PM PDT 24
Finished Mar 12 01:45:31 PM PDT 24
Peak memory 199968 kb
Host smart-2cc56bcd-1f55-4e3f-b6a0-7c1d37d60d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463231674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2463231674
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.928070308
Short name T557
Test name
Test status
Simulation time 354697680 ps
CPU time 5.74 seconds
Started Mar 12 01:44:39 PM PDT 24
Finished Mar 12 01:44:45 PM PDT 24
Peak memory 199944 kb
Host smart-3f4a6211-71b5-4b37-a26d-c271c3253617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928070308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.928070308
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.668283850
Short name T334
Test name
Test status
Simulation time 8636132026 ps
CPU time 467.89 seconds
Started Mar 12 01:44:39 PM PDT 24
Finished Mar 12 01:52:27 PM PDT 24
Peak memory 200068 kb
Host smart-d92d4534-fb53-41f6-ba52-6f8e5c6a28b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668283850 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.668283850
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3068166840
Short name T578
Test name
Test status
Simulation time 265706578 ps
CPU time 1.06 seconds
Started Mar 12 01:44:39 PM PDT 24
Finished Mar 12 01:44:41 PM PDT 24
Peak memory 199044 kb
Host smart-a920e66b-03e4-4c90-8cff-d9c4ce957d2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068166840 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3068166840
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2772976373
Short name T410
Test name
Test status
Simulation time 83973866511 ps
CPU time 577.35 seconds
Started Mar 12 01:44:38 PM PDT 24
Finished Mar 12 01:54:16 PM PDT 24
Peak memory 200020 kb
Host smart-24e15ad0-261c-4945-8b2f-4d10cdccabeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772976373 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2772976373
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2956606551
Short name T286
Test name
Test status
Simulation time 4915894358 ps
CPU time 42.8 seconds
Started Mar 12 01:44:36 PM PDT 24
Finished Mar 12 01:45:19 PM PDT 24
Peak memory 200008 kb
Host smart-900dc278-0d1e-402b-907e-9e8262a6e042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956606551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2956606551
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.884411833
Short name T15
Test name
Test status
Simulation time 11777089 ps
CPU time 0.58 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:50:27 PM PDT 24
Peak memory 194228 kb
Host smart-78f48c0d-1391-419f-9144-1378ed33a89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884411833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.884411833
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3244726126
Short name T53
Test name
Test status
Simulation time 888113045 ps
CPU time 40.12 seconds
Started Mar 12 01:50:27 PM PDT 24
Finished Mar 12 01:51:07 PM PDT 24
Peak memory 231992 kb
Host smart-e7f2ca7d-055e-470a-9e1b-43da7c546efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244726126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3244726126
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3701221905
Short name T258
Test name
Test status
Simulation time 7681563648 ps
CPU time 27.4 seconds
Started Mar 12 01:50:28 PM PDT 24
Finished Mar 12 01:50:56 PM PDT 24
Peak memory 200012 kb
Host smart-3f2d046c-6af9-493c-8566-6296afd9f290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701221905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3701221905
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.424720341
Short name T232
Test name
Test status
Simulation time 4119878312 ps
CPU time 121.94 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:52:27 PM PDT 24
Peak memory 199968 kb
Host smart-2d87e46b-989e-41f6-a9c0-dae36ea8306d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424720341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.424720341
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2472512614
Short name T493
Test name
Test status
Simulation time 6632862633 ps
CPU time 92.83 seconds
Started Mar 12 01:50:28 PM PDT 24
Finished Mar 12 01:52:01 PM PDT 24
Peak memory 200020 kb
Host smart-27b26055-b991-475b-9166-24795f1c7a2c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472512614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2472512614
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2157419726
Short name T479
Test name
Test status
Simulation time 4544810046 ps
CPU time 44.72 seconds
Started Mar 12 01:50:28 PM PDT 24
Finished Mar 12 01:51:13 PM PDT 24
Peak memory 199968 kb
Host smart-c71fcbbe-81f4-4113-b310-c48b74060e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157419726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2157419726
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2964829098
Short name T452
Test name
Test status
Simulation time 180075522 ps
CPU time 3.02 seconds
Started Mar 12 01:50:26 PM PDT 24
Finished Mar 12 01:50:29 PM PDT 24
Peak memory 199864 kb
Host smart-5dd2b335-3b88-4c08-925a-8a51f3733b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964829098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2964829098
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2932048952
Short name T565
Test name
Test status
Simulation time 362000931374 ps
CPU time 1810.58 seconds
Started Mar 12 01:50:32 PM PDT 24
Finished Mar 12 02:20:43 PM PDT 24
Peak memory 215844 kb
Host smart-a4734edc-eb48-4cab-b4e9-3d7f250abd24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932048952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2932048952
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2157386222
Short name T310
Test name
Test status
Simulation time 231893132 ps
CPU time 1.02 seconds
Started Mar 12 01:50:28 PM PDT 24
Finished Mar 12 01:50:30 PM PDT 24
Peak memory 197852 kb
Host smart-d860fe72-2170-4854-90e7-a28238107469
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157386222 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2157386222
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1832567979
Short name T251
Test name
Test status
Simulation time 8388767860 ps
CPU time 436.79 seconds
Started Mar 12 01:50:28 PM PDT 24
Finished Mar 12 01:57:46 PM PDT 24
Peak memory 200004 kb
Host smart-14a45474-381c-4a37-b66c-238deb55c364
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832567979 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.1832567979
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1148155214
Short name T540
Test name
Test status
Simulation time 2169284268 ps
CPU time 22.27 seconds
Started Mar 12 01:50:29 PM PDT 24
Finished Mar 12 01:50:52 PM PDT 24
Peak memory 200020 kb
Host smart-4a4a7b3d-ea68-45cf-bba4-77b133a51e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148155214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1148155214
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1247594934
Short name T539
Test name
Test status
Simulation time 17240736 ps
CPU time 0.61 seconds
Started Mar 12 01:50:31 PM PDT 24
Finished Mar 12 01:50:32 PM PDT 24
Peak memory 195336 kb
Host smart-a3a3aa89-42ce-436b-b659-62c7e7d3175f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247594934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1247594934
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.4206775418
Short name T303
Test name
Test status
Simulation time 1616234025 ps
CPU time 36.56 seconds
Started Mar 12 01:50:32 PM PDT 24
Finished Mar 12 01:51:08 PM PDT 24
Peak memory 216280 kb
Host smart-f34d3f18-88b4-4f21-94ab-0685d8bda500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4206775418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.4206775418
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1933645343
Short name T395
Test name
Test status
Simulation time 4519132339 ps
CPU time 20.22 seconds
Started Mar 12 01:50:32 PM PDT 24
Finished Mar 12 01:50:52 PM PDT 24
Peak memory 199992 kb
Host smart-66771fea-3fda-4205-9c3d-b4cc4949650d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933645343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1933645343
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2680313657
Short name T185
Test name
Test status
Simulation time 2099140421 ps
CPU time 24.89 seconds
Started Mar 12 01:50:32 PM PDT 24
Finished Mar 12 01:50:57 PM PDT 24
Peak memory 199912 kb
Host smart-480da8de-61dd-490c-adf7-686332a2e873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2680313657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2680313657
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3098074192
Short name T560
Test name
Test status
Simulation time 24644397500 ps
CPU time 163.01 seconds
Started Mar 12 01:50:33 PM PDT 24
Finished Mar 12 01:53:16 PM PDT 24
Peak memory 200012 kb
Host smart-ed47e79c-3cd1-445b-9913-320ce821b5ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098074192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3098074192
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1990695913
Short name T551
Test name
Test status
Simulation time 6992136846 ps
CPU time 91.72 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:51:57 PM PDT 24
Peak memory 200284 kb
Host smart-6a743406-ea21-4db1-b05b-ac83376bf31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990695913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1990695913
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4294182288
Short name T91
Test name
Test status
Simulation time 194309001 ps
CPU time 0.63 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:50:27 PM PDT 24
Peak memory 196732 kb
Host smart-33aff0e4-6bd3-4e3f-881b-7021424c17ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294182288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4294182288
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1807953393
Short name T42
Test name
Test status
Simulation time 7037613913 ps
CPU time 99.47 seconds
Started Mar 12 01:50:33 PM PDT 24
Finished Mar 12 01:52:13 PM PDT 24
Peak memory 232792 kb
Host smart-e2fab83a-2c7b-4d98-968b-e8dc1265a9b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807953393 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1807953393
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1110756949
Short name T89
Test name
Test status
Simulation time 108844443 ps
CPU time 1.25 seconds
Started Mar 12 01:50:32 PM PDT 24
Finished Mar 12 01:50:34 PM PDT 24
Peak memory 199860 kb
Host smart-5c9ee68f-c4f9-48b9-87fb-9c369c527586
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110756949 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1110756949
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2380057611
Short name T159
Test name
Test status
Simulation time 132919218793 ps
CPU time 443.63 seconds
Started Mar 12 01:50:34 PM PDT 24
Finished Mar 12 01:57:58 PM PDT 24
Peak memory 200024 kb
Host smart-c0e6e6e3-20e5-4303-84d8-623ae8e40e18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380057611 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2380057611
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2993423127
Short name T538
Test name
Test status
Simulation time 5975854441 ps
CPU time 83.7 seconds
Started Mar 12 01:50:33 PM PDT 24
Finished Mar 12 01:51:57 PM PDT 24
Peak memory 200016 kb
Host smart-325161c2-f3de-4830-b8a5-7da876b25bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993423127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2993423127
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3009611700
Short name T16
Test name
Test status
Simulation time 37366690 ps
CPU time 0.56 seconds
Started Mar 12 01:50:27 PM PDT 24
Finished Mar 12 01:50:28 PM PDT 24
Peak memory 194348 kb
Host smart-93081fe4-cbbb-49ea-a59f-4e7656ca27b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009611700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3009611700
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1988952465
Short name T318
Test name
Test status
Simulation time 399211298 ps
CPU time 16.63 seconds
Started Mar 12 01:50:34 PM PDT 24
Finished Mar 12 01:50:51 PM PDT 24
Peak memory 226536 kb
Host smart-2bfe432e-0138-41dd-85d4-c99737972a1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988952465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1988952465
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2205815148
Short name T438
Test name
Test status
Simulation time 5168701502 ps
CPU time 44.66 seconds
Started Mar 12 01:50:21 PM PDT 24
Finished Mar 12 01:51:07 PM PDT 24
Peak memory 199980 kb
Host smart-ccc1fef8-6cd4-43fb-9afa-b375c75a988d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205815148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2205815148
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.163717726
Short name T449
Test name
Test status
Simulation time 1510983003 ps
CPU time 80.08 seconds
Started Mar 12 01:50:37 PM PDT 24
Finished Mar 12 01:51:58 PM PDT 24
Peak memory 199768 kb
Host smart-09ae5c61-165a-4afd-96a4-bbbf9e517371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163717726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.163717726
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1389936535
Short name T439
Test name
Test status
Simulation time 10008577990 ps
CPU time 182.41 seconds
Started Mar 12 01:50:11 PM PDT 24
Finished Mar 12 01:53:14 PM PDT 24
Peak memory 200028 kb
Host smart-ca440803-8e01-48f0-82fc-c9aecdc9fd2e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389936535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1389936535
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.979984279
Short name T36
Test name
Test status
Simulation time 577478193 ps
CPU time 12.73 seconds
Started Mar 12 01:50:29 PM PDT 24
Finished Mar 12 01:50:42 PM PDT 24
Peak memory 199952 kb
Host smart-a3ecb9a7-64e2-4a21-a9d0-8ad405fa2690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979984279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.979984279
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3488609106
Short name T252
Test name
Test status
Simulation time 4247416737 ps
CPU time 6.48 seconds
Started Mar 12 01:50:33 PM PDT 24
Finished Mar 12 01:50:40 PM PDT 24
Peak memory 199960 kb
Host smart-90ed51a3-b4c7-4662-995d-6d1ba6a7f2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488609106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3488609106
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.208950131
Short name T77
Test name
Test status
Simulation time 3539857567 ps
CPU time 176.58 seconds
Started Mar 12 01:50:28 PM PDT 24
Finished Mar 12 01:53:25 PM PDT 24
Peak memory 240992 kb
Host smart-f14036e9-7853-4924-aff6-d50830887183
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208950131 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.208950131
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.37335329
Short name T478
Test name
Test status
Simulation time 116666266 ps
CPU time 1.24 seconds
Started Mar 12 01:50:36 PM PDT 24
Finished Mar 12 01:50:38 PM PDT 24
Peak memory 199608 kb
Host smart-079ee0a5-a4fd-4355-a06e-f32be308aaf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37335329 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.hmac_test_hmac_vectors.37335329
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.585240790
Short name T532
Test name
Test status
Simulation time 17688662700 ps
CPU time 450.1 seconds
Started Mar 12 01:50:28 PM PDT 24
Finished Mar 12 01:57:59 PM PDT 24
Peak memory 200032 kb
Host smart-191cc7e6-0742-49e8-9520-cbf3d06f218d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585240790 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.585240790
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1470715350
Short name T270
Test name
Test status
Simulation time 3283567818 ps
CPU time 56.92 seconds
Started Mar 12 01:50:27 PM PDT 24
Finished Mar 12 01:51:24 PM PDT 24
Peak memory 199992 kb
Host smart-7fa0aa3c-3fd2-4f5e-9257-d584799e8872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470715350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1470715350
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2688279573
Short name T380
Test name
Test status
Simulation time 74271150 ps
CPU time 0.6 seconds
Started Mar 12 01:50:37 PM PDT 24
Finished Mar 12 01:50:38 PM PDT 24
Peak memory 195188 kb
Host smart-b1fd24a7-f668-4504-9cc1-a064eac4f9c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688279573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2688279573
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3869495799
Short name T467
Test name
Test status
Simulation time 6164912889 ps
CPU time 65.66 seconds
Started Mar 12 01:50:25 PM PDT 24
Finished Mar 12 01:51:32 PM PDT 24
Peak memory 240988 kb
Host smart-8fdd9930-a0e1-4e2b-a975-c9de58ef74ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869495799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3869495799
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3722493888
Short name T272
Test name
Test status
Simulation time 4455903230 ps
CPU time 35.04 seconds
Started Mar 12 01:50:37 PM PDT 24
Finished Mar 12 01:51:13 PM PDT 24
Peak memory 199956 kb
Host smart-1f6b5aa8-f894-419f-bfc1-880ee4af10b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722493888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3722493888
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3500497158
Short name T511
Test name
Test status
Simulation time 4573211703 ps
CPU time 62.68 seconds
Started Mar 12 01:50:27 PM PDT 24
Finished Mar 12 01:51:31 PM PDT 24
Peak memory 200056 kb
Host smart-163f104d-117f-4069-ac00-77354616b021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500497158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3500497158
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1783794080
Short name T515
Test name
Test status
Simulation time 10014119732 ps
CPU time 44.46 seconds
Started Mar 12 01:50:23 PM PDT 24
Finished Mar 12 01:51:09 PM PDT 24
Peak memory 200000 kb
Host smart-76f45e5a-6c30-4349-b275-9e7318545276
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783794080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1783794080
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2899699548
Short name T119
Test name
Test status
Simulation time 2143025848 ps
CPU time 14.55 seconds
Started Mar 12 01:50:24 PM PDT 24
Finished Mar 12 01:50:40 PM PDT 24
Peak memory 199896 kb
Host smart-ce42b625-c50f-4a11-9ddb-ff35d7e1a73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899699548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2899699548
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1526201513
Short name T35
Test name
Test status
Simulation time 159746043 ps
CPU time 5.15 seconds
Started Mar 12 01:50:37 PM PDT 24
Finished Mar 12 01:50:42 PM PDT 24
Peak memory 199864 kb
Host smart-7d545a68-e719-4f16-9086-118bd075a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526201513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1526201513
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.7582745
Short name T295
Test name
Test status
Simulation time 448880958609 ps
CPU time 1207.57 seconds
Started Mar 12 01:50:35 PM PDT 24
Finished Mar 12 02:10:43 PM PDT 24
Peak memory 215440 kb
Host smart-18a3a788-b0f5-47a0-805b-b1e102fb6f04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7582745 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.7582745
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3666667764
Short name T128
Test name
Test status
Simulation time 39446381 ps
CPU time 0.93 seconds
Started Mar 12 01:50:35 PM PDT 24
Finished Mar 12 01:50:37 PM PDT 24
Peak memory 197968 kb
Host smart-2fbd3031-feeb-4315-a849-ae23140bb3c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666667764 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3666667764
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3735373519
Short name T426
Test name
Test status
Simulation time 74650150075 ps
CPU time 511.95 seconds
Started Mar 12 01:50:35 PM PDT 24
Finished Mar 12 01:59:07 PM PDT 24
Peak memory 200044 kb
Host smart-5bb56b21-2afd-47f6-b376-ac3d697567eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735373519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3735373519
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4130687391
Short name T495
Test name
Test status
Simulation time 4923799231 ps
CPU time 35.66 seconds
Started Mar 12 01:50:37 PM PDT 24
Finished Mar 12 01:51:13 PM PDT 24
Peak memory 199896 kb
Host smart-a2573ce2-5c8c-4eb6-8dea-e386585fe161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130687391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4130687391
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.924631786
Short name T257
Test name
Test status
Simulation time 20156418 ps
CPU time 0.57 seconds
Started Mar 12 01:50:46 PM PDT 24
Finished Mar 12 01:50:47 PM PDT 24
Peak memory 194288 kb
Host smart-1a05d639-76db-4782-88ec-4e19103ef9bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924631786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.924631786
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.542681111
Short name T559
Test name
Test status
Simulation time 378577346 ps
CPU time 15.52 seconds
Started Mar 12 01:50:37 PM PDT 24
Finished Mar 12 01:50:53 PM PDT 24
Peak memory 221448 kb
Host smart-b1fa3a78-690b-440b-932c-b2d3aabf6ef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542681111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.542681111
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.142791853
Short name T492
Test name
Test status
Simulation time 896655474 ps
CPU time 13.15 seconds
Started Mar 12 01:50:38 PM PDT 24
Finished Mar 12 01:50:51 PM PDT 24
Peak memory 199836 kb
Host smart-20d4cf54-9404-4076-b92b-ceacc58e2330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142791853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.142791853
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1561795787
Short name T387
Test name
Test status
Simulation time 1131752760 ps
CPU time 51.34 seconds
Started Mar 12 01:50:35 PM PDT 24
Finished Mar 12 01:51:27 PM PDT 24
Peak memory 199844 kb
Host smart-aaae5f0b-a2f0-4c66-be9f-04bd6387d352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1561795787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1561795787
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2510706208
Short name T47
Test name
Test status
Simulation time 27602104944 ps
CPU time 30.41 seconds
Started Mar 12 01:50:35 PM PDT 24
Finished Mar 12 01:51:06 PM PDT 24
Peak memory 200056 kb
Host smart-a3c4d1a1-6176-4abf-a401-98192809fdbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510706208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2510706208
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1428504552
Short name T283
Test name
Test status
Simulation time 13418296801 ps
CPU time 48.6 seconds
Started Mar 12 01:50:46 PM PDT 24
Finished Mar 12 01:51:35 PM PDT 24
Peak memory 199980 kb
Host smart-1af18e4f-a346-4f7d-aaa3-7bd5e339f54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428504552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1428504552
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2233898151
Short name T338
Test name
Test status
Simulation time 137140612 ps
CPU time 4.31 seconds
Started Mar 12 01:50:34 PM PDT 24
Finished Mar 12 01:50:39 PM PDT 24
Peak memory 199748 kb
Host smart-6037c3e6-1d7f-4b99-a33d-43bc818450f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233898151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2233898151
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.290012832
Short name T416
Test name
Test status
Simulation time 7767692391 ps
CPU time 387.63 seconds
Started Mar 12 01:50:45 PM PDT 24
Finished Mar 12 01:57:13 PM PDT 24
Peak memory 241004 kb
Host smart-6283fa1c-c985-4121-92ef-e27eba01a2ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290012832 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.290012832
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3012790196
Short name T378
Test name
Test status
Simulation time 196857838 ps
CPU time 1.09 seconds
Started Mar 12 01:50:45 PM PDT 24
Finished Mar 12 01:50:46 PM PDT 24
Peak memory 197900 kb
Host smart-86984f6d-6adb-4ef0-b4c9-4d8121648cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012790196 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3012790196
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1840224407
Short name T190
Test name
Test status
Simulation time 52697921255 ps
CPU time 496.74 seconds
Started Mar 12 01:50:45 PM PDT 24
Finished Mar 12 01:59:02 PM PDT 24
Peak memory 200012 kb
Host smart-700e7b55-d818-4549-83c2-458ffda03647
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840224407 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1840224407
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3156925906
Short name T229
Test name
Test status
Simulation time 1485610478 ps
CPU time 75.81 seconds
Started Mar 12 01:50:47 PM PDT 24
Finished Mar 12 01:52:04 PM PDT 24
Peak memory 199880 kb
Host smart-033f3242-84f2-4c6e-b206-0f95404dcbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156925906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3156925906
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2363783396
Short name T278
Test name
Test status
Simulation time 11148165 ps
CPU time 0.58 seconds
Started Mar 12 01:50:44 PM PDT 24
Finished Mar 12 01:50:45 PM PDT 24
Peak memory 194296 kb
Host smart-606b8849-25c8-4d7b-b05a-61fb49ee1612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363783396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2363783396
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3048273935
Short name T481
Test name
Test status
Simulation time 1295234459 ps
CPU time 46.52 seconds
Started Mar 12 01:50:47 PM PDT 24
Finished Mar 12 01:51:33 PM PDT 24
Peak memory 232472 kb
Host smart-d7a9fa68-11e9-4dbd-8389-905042478ebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3048273935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3048273935
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1838561219
Short name T489
Test name
Test status
Simulation time 810876571 ps
CPU time 20.95 seconds
Started Mar 12 01:50:47 PM PDT 24
Finished Mar 12 01:51:08 PM PDT 24
Peak memory 199916 kb
Host smart-2735a0b5-49bd-43db-a253-b390252ce8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838561219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1838561219
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1904022453
Short name T161
Test name
Test status
Simulation time 3953973980 ps
CPU time 63.25 seconds
Started Mar 12 01:50:46 PM PDT 24
Finished Mar 12 01:51:49 PM PDT 24
Peak memory 199920 kb
Host smart-64e741e8-e503-4fa3-9e06-dcf49d1c8a82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904022453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1904022453
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.295046247
Short name T210
Test name
Test status
Simulation time 5987590848 ps
CPU time 19.14 seconds
Started Mar 12 01:50:46 PM PDT 24
Finished Mar 12 01:51:05 PM PDT 24
Peak memory 199868 kb
Host smart-6bb459a0-a047-40d2-a6ad-1473a504fe50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295046247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.295046247
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.264665724
Short name T275
Test name
Test status
Simulation time 53983437088 ps
CPU time 142.23 seconds
Started Mar 12 01:50:47 PM PDT 24
Finished Mar 12 01:53:10 PM PDT 24
Peak memory 200020 kb
Host smart-f0703df6-7e9f-4c9c-8444-c5b0a1bf18ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264665724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.264665724
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.158049013
Short name T292
Test name
Test status
Simulation time 107793980 ps
CPU time 1.18 seconds
Started Mar 12 01:50:46 PM PDT 24
Finished Mar 12 01:50:47 PM PDT 24
Peak memory 199564 kb
Host smart-407b7165-c61e-4f72-9b86-6ec96560cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158049013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.158049013
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3854838005
Short name T92
Test name
Test status
Simulation time 9885948054 ps
CPU time 304.75 seconds
Started Mar 12 01:50:46 PM PDT 24
Finished Mar 12 01:55:51 PM PDT 24
Peak memory 230592 kb
Host smart-aa6a7222-8e21-4463-bedf-bf9e8ad3146c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854838005 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3854838005
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2658339586
Short name T370
Test name
Test status
Simulation time 108069954 ps
CPU time 1.23 seconds
Started Mar 12 01:50:45 PM PDT 24
Finished Mar 12 01:50:47 PM PDT 24
Peak memory 199716 kb
Host smart-05ecadd7-2d4f-4385-89ac-245c2383cb79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658339586 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2658339586
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3359590800
Short name T486
Test name
Test status
Simulation time 17943319976 ps
CPU time 443.4 seconds
Started Mar 12 01:50:49 PM PDT 24
Finished Mar 12 01:58:13 PM PDT 24
Peak memory 200016 kb
Host smart-fb9b5e15-5764-4424-9b7c-75f755b0b8e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359590800 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.3359590800
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.775442756
Short name T240
Test name
Test status
Simulation time 5820107232 ps
CPU time 24.54 seconds
Started Mar 12 01:50:45 PM PDT 24
Finished Mar 12 01:51:10 PM PDT 24
Peak memory 200056 kb
Host smart-b01279fa-4a31-4103-b6f6-5ea698541fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775442756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.775442756
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3986007377
Short name T300
Test name
Test status
Simulation time 11902936 ps
CPU time 0.55 seconds
Started Mar 12 01:50:59 PM PDT 24
Finished Mar 12 01:50:59 PM PDT 24
Peak memory 195264 kb
Host smart-66696f68-5e09-4fa7-afaa-31286d5770b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986007377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3986007377
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.606706550
Short name T503
Test name
Test status
Simulation time 2213660133 ps
CPU time 41.05 seconds
Started Mar 12 01:50:57 PM PDT 24
Finished Mar 12 01:51:38 PM PDT 24
Peak memory 208072 kb
Host smart-18772571-8e49-46e4-a096-fb57b5170ea0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=606706550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.606706550
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1239333223
Short name T208
Test name
Test status
Simulation time 1385259641 ps
CPU time 22.81 seconds
Started Mar 12 01:50:55 PM PDT 24
Finished Mar 12 01:51:18 PM PDT 24
Peak memory 199912 kb
Host smart-773f7bf2-8c9c-4067-a08f-b2dd6cc080fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239333223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1239333223
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.683821879
Short name T200
Test name
Test status
Simulation time 108637741 ps
CPU time 7.14 seconds
Started Mar 12 01:50:56 PM PDT 24
Finished Mar 12 01:51:03 PM PDT 24
Peak memory 199908 kb
Host smart-5241f3d6-73e9-4500-a6e0-0757b419b26f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683821879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.683821879
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1511420411
Short name T254
Test name
Test status
Simulation time 15002843066 ps
CPU time 97.6 seconds
Started Mar 12 01:50:55 PM PDT 24
Finished Mar 12 01:52:33 PM PDT 24
Peak memory 200024 kb
Host smart-aa65a930-acef-4522-ad02-dc5df8f93a30
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511420411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1511420411
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2465401210
Short name T564
Test name
Test status
Simulation time 6701904164 ps
CPU time 69.37 seconds
Started Mar 12 01:50:56 PM PDT 24
Finished Mar 12 01:52:05 PM PDT 24
Peak memory 200068 kb
Host smart-3566c73c-2720-4347-a3ad-bb5e586246ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465401210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2465401210
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3842913873
Short name T552
Test name
Test status
Simulation time 226496660 ps
CPU time 3.23 seconds
Started Mar 12 01:50:56 PM PDT 24
Finished Mar 12 01:50:59 PM PDT 24
Peak memory 199896 kb
Host smart-d4b0b25f-de75-4c84-87db-82dda03cd3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842913873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3842913873
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3088271174
Short name T64
Test name
Test status
Simulation time 1220314551998 ps
CPU time 805 seconds
Started Mar 12 01:50:57 PM PDT 24
Finished Mar 12 02:04:22 PM PDT 24
Peak memory 200004 kb
Host smart-54be4cb6-b883-49d0-9f6a-8e6562478c51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088271174 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3088271174
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2351955014
Short name T429
Test name
Test status
Simulation time 60559660 ps
CPU time 1.16 seconds
Started Mar 12 01:50:59 PM PDT 24
Finished Mar 12 01:51:00 PM PDT 24
Peak memory 199688 kb
Host smart-a25157a3-2fb6-4994-b0f7-235a4a6ac67d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351955014 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2351955014
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.4051412193
Short name T596
Test name
Test status
Simulation time 72310135253 ps
CPU time 546.73 seconds
Started Mar 12 01:50:55 PM PDT 24
Finished Mar 12 02:00:03 PM PDT 24
Peak memory 200044 kb
Host smart-a0613669-21de-4379-ad7f-505fb0928f21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051412193 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.4051412193
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.4144996389
Short name T298
Test name
Test status
Simulation time 2673351048 ps
CPU time 45.57 seconds
Started Mar 12 01:50:59 PM PDT 24
Finished Mar 12 01:51:45 PM PDT 24
Peak memory 199784 kb
Host smart-e04593d2-de07-47b5-a8fc-8029a77cec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144996389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.4144996389
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3065282991
Short name T535
Test name
Test status
Simulation time 41787316 ps
CPU time 0.57 seconds
Started Mar 12 01:51:06 PM PDT 24
Finished Mar 12 01:51:07 PM PDT 24
Peak memory 195328 kb
Host smart-a034561a-583d-485b-9049-131d4981eadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065282991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3065282991
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.4251935580
Short name T177
Test name
Test status
Simulation time 219045689 ps
CPU time 8.07 seconds
Started Mar 12 01:51:06 PM PDT 24
Finished Mar 12 01:51:14 PM PDT 24
Peak memory 215928 kb
Host smart-bece7ac3-d809-4223-9c32-ce0b143d452e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251935580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4251935580
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3269741718
Short name T561
Test name
Test status
Simulation time 4835952587 ps
CPU time 26.49 seconds
Started Mar 12 01:51:06 PM PDT 24
Finished Mar 12 01:51:32 PM PDT 24
Peak memory 200068 kb
Host smart-3d15d5cc-1de1-441d-b47c-f647ec5b6528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269741718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3269741718
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2780736863
Short name T39
Test name
Test status
Simulation time 890965401 ps
CPU time 29.97 seconds
Started Mar 12 01:51:07 PM PDT 24
Finished Mar 12 01:51:37 PM PDT 24
Peak memory 199860 kb
Host smart-28550ad0-c625-4c11-b689-7c9b4195a772
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2780736863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2780736863
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1248617122
Short name T297
Test name
Test status
Simulation time 19658163062 ps
CPU time 241.72 seconds
Started Mar 12 01:51:07 PM PDT 24
Finished Mar 12 01:55:08 PM PDT 24
Peak memory 200028 kb
Host smart-aee95c16-04c7-42bd-a914-c8f277e600fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248617122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1248617122
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1234753271
Short name T553
Test name
Test status
Simulation time 6483964550 ps
CPU time 123.51 seconds
Started Mar 12 01:51:05 PM PDT 24
Finished Mar 12 01:53:09 PM PDT 24
Peak memory 200028 kb
Host smart-84ee9a76-c135-4a7f-8cbf-6f81370eb31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234753271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1234753271
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1693967655
Short name T536
Test name
Test status
Simulation time 101037373 ps
CPU time 1.08 seconds
Started Mar 12 01:51:06 PM PDT 24
Finished Mar 12 01:51:07 PM PDT 24
Peak memory 199692 kb
Host smart-88a1f7d1-630e-4ec6-9fec-22672b0bb3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693967655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1693967655
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.254555959
Short name T474
Test name
Test status
Simulation time 28481857132 ps
CPU time 1577.64 seconds
Started Mar 12 01:51:05 PM PDT 24
Finished Mar 12 02:17:23 PM PDT 24
Peak memory 216432 kb
Host smart-3f3d6171-3b7d-4939-942a-078d1d63b6f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254555959 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.254555959
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.748984089
Short name T396
Test name
Test status
Simulation time 113694172 ps
CPU time 1.23 seconds
Started Mar 12 01:51:07 PM PDT 24
Finished Mar 12 01:51:08 PM PDT 24
Peak memory 199960 kb
Host smart-f7c779f5-939a-42a3-b180-a08cc8746201
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748984089 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.748984089
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3924995363
Short name T472
Test name
Test status
Simulation time 8573829966 ps
CPU time 486.09 seconds
Started Mar 12 01:51:05 PM PDT 24
Finished Mar 12 01:59:11 PM PDT 24
Peak memory 200076 kb
Host smart-e4fbba30-c39b-482b-86b1-53432298fe8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924995363 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.3924995363
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.4202235713
Short name T143
Test name
Test status
Simulation time 4390713148 ps
CPU time 62.61 seconds
Started Mar 12 01:51:07 PM PDT 24
Finished Mar 12 01:52:10 PM PDT 24
Peak memory 200024 kb
Host smart-c1ef10ec-b757-442b-89cd-46793c033314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202235713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.4202235713
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3952917676
Short name T88
Test name
Test status
Simulation time 12726514 ps
CPU time 0.59 seconds
Started Mar 12 01:51:06 PM PDT 24
Finished Mar 12 01:51:07 PM PDT 24
Peak memory 194852 kb
Host smart-04650931-378c-43d0-ac1a-5fc091096564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952917676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3952917676
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1536547100
Short name T51
Test name
Test status
Simulation time 701987857 ps
CPU time 25.89 seconds
Started Mar 12 01:51:07 PM PDT 24
Finished Mar 12 01:51:33 PM PDT 24
Peak memory 208012 kb
Host smart-484c81f2-445b-4632-944d-65d87daf16d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536547100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1536547100
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3128662863
Short name T591
Test name
Test status
Simulation time 1364194982 ps
CPU time 29.41 seconds
Started Mar 12 01:51:06 PM PDT 24
Finished Mar 12 01:51:36 PM PDT 24
Peak memory 199912 kb
Host smart-cd79db03-f63f-4e42-9342-97b3da353ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128662863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3128662863
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4063831899
Short name T542
Test name
Test status
Simulation time 9231723431 ps
CPU time 134.01 seconds
Started Mar 12 01:51:05 PM PDT 24
Finished Mar 12 01:53:19 PM PDT 24
Peak memory 200056 kb
Host smart-403e76d4-5cd7-4eaf-b0b1-5a5c215ec277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063831899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4063831899
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.385449097
Short name T144
Test name
Test status
Simulation time 5029867773 ps
CPU time 96.7 seconds
Started Mar 12 01:51:07 PM PDT 24
Finished Mar 12 01:52:44 PM PDT 24
Peak memory 200084 kb
Host smart-565939f0-7a16-44bc-9b7b-d4a0697998ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385449097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.385449097
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.4170001996
Short name T484
Test name
Test status
Simulation time 8881213457 ps
CPU time 47.62 seconds
Started Mar 12 01:51:07 PM PDT 24
Finished Mar 12 01:51:55 PM PDT 24
Peak memory 199900 kb
Host smart-349cd3f3-81dd-48f2-bec0-1d8d33e580ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170001996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.4170001996
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.938603465
Short name T235
Test name
Test status
Simulation time 1948446457 ps
CPU time 3.56 seconds
Started Mar 12 01:51:09 PM PDT 24
Finished Mar 12 01:51:12 PM PDT 24
Peak memory 199936 kb
Host smart-acc47d68-791f-4720-a4c7-bf2f94d05b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938603465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.938603465
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.4170066942
Short name T281
Test name
Test status
Simulation time 32785336883 ps
CPU time 472.84 seconds
Started Mar 12 01:51:05 PM PDT 24
Finished Mar 12 01:58:58 PM PDT 24
Peak memory 200044 kb
Host smart-faef639f-3228-4d12-934c-f33437c74c45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170066942 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.4170066942
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2786025809
Short name T287
Test name
Test status
Simulation time 32508081 ps
CPU time 1.25 seconds
Started Mar 12 01:51:06 PM PDT 24
Finished Mar 12 01:51:08 PM PDT 24
Peak memory 199688 kb
Host smart-7dd8be12-135c-4977-b82a-7fa18bac1fd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786025809 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2786025809
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3952517906
Short name T154
Test name
Test status
Simulation time 35585254563 ps
CPU time 511.64 seconds
Started Mar 12 01:51:06 PM PDT 24
Finished Mar 12 01:59:38 PM PDT 24
Peak memory 200044 kb
Host smart-f96666e4-c360-4129-ac01-26c9d03d18d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952517906 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3952517906
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2226768061
Short name T301
Test name
Test status
Simulation time 4309561770 ps
CPU time 64.62 seconds
Started Mar 12 01:51:05 PM PDT 24
Finished Mar 12 01:52:10 PM PDT 24
Peak memory 200044 kb
Host smart-80d7bd7b-e7c6-4232-b6bc-b979a844bd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226768061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2226768061
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1761792797
Short name T211
Test name
Test status
Simulation time 42113714 ps
CPU time 0.59 seconds
Started Mar 12 01:51:19 PM PDT 24
Finished Mar 12 01:51:20 PM PDT 24
Peak memory 194328 kb
Host smart-82008ce8-17b3-432a-86a8-4e199dfa8071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761792797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1761792797
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1031274053
Short name T242
Test name
Test status
Simulation time 473929124 ps
CPU time 16.92 seconds
Started Mar 12 01:51:16 PM PDT 24
Finished Mar 12 01:51:33 PM PDT 24
Peak memory 199884 kb
Host smart-20f0e6c0-20db-4fec-b081-cea5137e9a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031274053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1031274053
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3016435270
Short name T90
Test name
Test status
Simulation time 6155226783 ps
CPU time 14.8 seconds
Started Mar 12 01:51:16 PM PDT 24
Finished Mar 12 01:51:30 PM PDT 24
Peak memory 199940 kb
Host smart-e547fe40-ffa7-4740-afb6-9a925af76f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016435270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3016435270
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1657888255
Short name T129
Test name
Test status
Simulation time 1074026548 ps
CPU time 71.23 seconds
Started Mar 12 01:51:18 PM PDT 24
Finished Mar 12 01:52:30 PM PDT 24
Peak memory 199916 kb
Host smart-cd475b31-f90b-4291-80c4-f8c8178e77dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1657888255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1657888255
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1742549701
Short name T296
Test name
Test status
Simulation time 19373466616 ps
CPU time 256.95 seconds
Started Mar 12 01:51:15 PM PDT 24
Finished Mar 12 01:55:32 PM PDT 24
Peak memory 199876 kb
Host smart-401158c0-14bd-49d6-9f88-f2ce4e60ca8c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742549701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1742549701
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1715881065
Short name T87
Test name
Test status
Simulation time 1209780707 ps
CPU time 76.27 seconds
Started Mar 12 01:51:06 PM PDT 24
Finished Mar 12 01:52:22 PM PDT 24
Peak memory 199924 kb
Host smart-bd9eb83a-5a85-4d22-acaf-d54a45912990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715881065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1715881065
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3551952984
Short name T28
Test name
Test status
Simulation time 344631507 ps
CPU time 1.9 seconds
Started Mar 12 01:51:06 PM PDT 24
Finished Mar 12 01:51:08 PM PDT 24
Peak memory 199904 kb
Host smart-caf4de8f-2178-4b58-918c-6f991fd61408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551952984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3551952984
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3528706498
Short name T569
Test name
Test status
Simulation time 10576243456 ps
CPU time 210.37 seconds
Started Mar 12 01:51:16 PM PDT 24
Finished Mar 12 01:54:46 PM PDT 24
Peak memory 200044 kb
Host smart-32de8437-5c95-4538-8147-ffc380b51bff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528706498 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3528706498
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2655921409
Short name T502
Test name
Test status
Simulation time 221789937 ps
CPU time 1.33 seconds
Started Mar 12 01:51:18 PM PDT 24
Finished Mar 12 01:51:19 PM PDT 24
Peak memory 199836 kb
Host smart-0f9c6ad2-bdfc-4e2b-bfb1-e5caf9d7df6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655921409 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2655921409
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.29009739
Short name T245
Test name
Test status
Simulation time 51860666471 ps
CPU time 481.52 seconds
Started Mar 12 01:51:17 PM PDT 24
Finished Mar 12 01:59:19 PM PDT 24
Peak memory 199996 kb
Host smart-33590855-256f-431b-a886-0cf043779848
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29009739 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.29009739
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2249181771
Short name T563
Test name
Test status
Simulation time 3972963334 ps
CPU time 29.11 seconds
Started Mar 12 01:51:15 PM PDT 24
Finished Mar 12 01:51:44 PM PDT 24
Peak memory 200000 kb
Host smart-13c5959c-292f-4333-8284-c40127f76029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249181771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2249181771
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1773540168
Short name T218
Test name
Test status
Simulation time 30745445 ps
CPU time 0.64 seconds
Started Mar 12 01:44:44 PM PDT 24
Finished Mar 12 01:44:47 PM PDT 24
Peak memory 194344 kb
Host smart-1f3d5c71-3fab-4879-86d1-83ff41d4c84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773540168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1773540168
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3117942170
Short name T179
Test name
Test status
Simulation time 1344594704 ps
CPU time 17.59 seconds
Started Mar 12 01:44:48 PM PDT 24
Finished Mar 12 01:45:05 PM PDT 24
Peak memory 240840 kb
Host smart-e5784ddb-0323-4dc6-bdd7-f00fe78ff851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117942170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3117942170
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2249747052
Short name T22
Test name
Test status
Simulation time 2127951130 ps
CPU time 28.59 seconds
Started Mar 12 01:44:48 PM PDT 24
Finished Mar 12 01:45:17 PM PDT 24
Peak memory 199800 kb
Host smart-36fdd62d-aa4a-485f-90b2-4a98154bdfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249747052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2249747052
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1201951843
Short name T571
Test name
Test status
Simulation time 1327969466 ps
CPU time 80.5 seconds
Started Mar 12 01:44:47 PM PDT 24
Finished Mar 12 01:46:08 PM PDT 24
Peak memory 199880 kb
Host smart-c9371bc9-3c58-401a-a07a-49de96bad0a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201951843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1201951843
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.324203503
Short name T450
Test name
Test status
Simulation time 14670767578 ps
CPU time 50.16 seconds
Started Mar 12 01:44:47 PM PDT 24
Finished Mar 12 01:45:38 PM PDT 24
Peak memory 199984 kb
Host smart-06aed572-c894-4296-b3cb-99039fa20b26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324203503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.324203503
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1721713071
Short name T599
Test name
Test status
Simulation time 2702049291 ps
CPU time 42.3 seconds
Started Mar 12 01:44:47 PM PDT 24
Finished Mar 12 01:45:30 PM PDT 24
Peak memory 199976 kb
Host smart-0b5b1eca-6c41-48f1-ad8a-64f53c975c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721713071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1721713071
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3692956695
Short name T19
Test name
Test status
Simulation time 136243025 ps
CPU time 0.8 seconds
Started Mar 12 01:44:45 PM PDT 24
Finished Mar 12 01:44:47 PM PDT 24
Peak memory 218444 kb
Host smart-6134f3e9-06a9-489a-b78e-278efb633e45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692956695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3692956695
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.286676214
Short name T587
Test name
Test status
Simulation time 1556859906 ps
CPU time 3.53 seconds
Started Mar 12 01:44:44 PM PDT 24
Finished Mar 12 01:44:49 PM PDT 24
Peak memory 199784 kb
Host smart-8770e6e3-65a7-4106-84cc-bb4beff89232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286676214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.286676214
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.379678202
Short name T593
Test name
Test status
Simulation time 110104667687 ps
CPU time 974.81 seconds
Started Mar 12 01:44:49 PM PDT 24
Finished Mar 12 02:01:04 PM PDT 24
Peak memory 199968 kb
Host smart-2fd46296-a8dc-4639-88f5-4da47a6019f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379678202 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.379678202
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.126342697
Short name T422
Test name
Test status
Simulation time 75550478 ps
CPU time 1.47 seconds
Started Mar 12 01:44:45 PM PDT 24
Finished Mar 12 01:44:48 PM PDT 24
Peak memory 199380 kb
Host smart-4d5be15c-075e-4b48-9f67-09b1fea5520f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126342697 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.126342697
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3303200265
Short name T431
Test name
Test status
Simulation time 164817902670 ps
CPU time 566.36 seconds
Started Mar 12 01:44:44 PM PDT 24
Finished Mar 12 01:54:13 PM PDT 24
Peak memory 199968 kb
Host smart-ef980c41-c55f-45ce-80ee-b7c52d94ec5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303200265 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3303200265
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3621178147
Short name T580
Test name
Test status
Simulation time 6679526443 ps
CPU time 25.39 seconds
Started Mar 12 01:44:47 PM PDT 24
Finished Mar 12 01:45:13 PM PDT 24
Peak memory 199956 kb
Host smart-a6baf270-4d39-4971-8e47-966711e2dad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621178147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3621178147
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.867298694
Short name T420
Test name
Test status
Simulation time 48039681 ps
CPU time 0.57 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:51:32 PM PDT 24
Peak memory 194940 kb
Host smart-caa5242b-3a63-471f-88f4-d3f2cd935c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867298694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.867298694
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1012285125
Short name T455
Test name
Test status
Simulation time 1601694199 ps
CPU time 77.93 seconds
Started Mar 12 01:51:21 PM PDT 24
Finished Mar 12 01:52:39 PM PDT 24
Peak memory 240868 kb
Host smart-af45df48-c645-4960-9116-d42773790d10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012285125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1012285125
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1494879938
Short name T330
Test name
Test status
Simulation time 2333757589 ps
CPU time 13.46 seconds
Started Mar 12 01:51:16 PM PDT 24
Finished Mar 12 01:51:30 PM PDT 24
Peak memory 199940 kb
Host smart-f03d1c66-3f0b-41fa-83c2-884c9b8c0a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494879938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1494879938
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.70212904
Short name T576
Test name
Test status
Simulation time 2543769210 ps
CPU time 159.46 seconds
Started Mar 12 01:51:15 PM PDT 24
Finished Mar 12 01:53:55 PM PDT 24
Peak memory 199972 kb
Host smart-6aaadadc-01e8-4e08-8660-db3e627f510b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70212904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.70212904
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.594609737
Short name T223
Test name
Test status
Simulation time 541209260 ps
CPU time 18.68 seconds
Started Mar 12 01:51:19 PM PDT 24
Finished Mar 12 01:51:38 PM PDT 24
Peak memory 199796 kb
Host smart-51e62eda-795f-4b2e-bb88-90ed7bb77dfc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594609737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.594609737
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2403532498
Short name T430
Test name
Test status
Simulation time 23887941666 ps
CPU time 119.52 seconds
Started Mar 12 01:51:17 PM PDT 24
Finished Mar 12 01:53:16 PM PDT 24
Peak memory 199968 kb
Host smart-98949817-f0e9-4e73-ab83-5dcaf0340d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403532498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2403532498
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3825551908
Short name T470
Test name
Test status
Simulation time 451959966 ps
CPU time 6.35 seconds
Started Mar 12 01:51:15 PM PDT 24
Finished Mar 12 01:51:21 PM PDT 24
Peak memory 199860 kb
Host smart-e7a2dd47-48b9-4181-be83-eef28d38eac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825551908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3825551908
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2448724834
Short name T253
Test name
Test status
Simulation time 3604337793 ps
CPU time 65.89 seconds
Started Mar 12 01:51:18 PM PDT 24
Finished Mar 12 01:52:24 PM PDT 24
Peak memory 225556 kb
Host smart-58adc05f-b56a-4c0d-bec3-5cc4d4ea8a85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448724834 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2448724834
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3056368011
Short name T584
Test name
Test status
Simulation time 108694131 ps
CPU time 1.36 seconds
Started Mar 12 01:51:15 PM PDT 24
Finished Mar 12 01:51:17 PM PDT 24
Peak memory 199552 kb
Host smart-8f135720-458b-4dfb-bc00-b1edb32ced68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056368011 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3056368011
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3557775273
Short name T202
Test name
Test status
Simulation time 29698628174 ps
CPU time 420.84 seconds
Started Mar 12 01:51:18 PM PDT 24
Finished Mar 12 01:58:19 PM PDT 24
Peak memory 200040 kb
Host smart-036f7bcd-b295-4a0d-b77d-5a2db113c8c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557775273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3557775273
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1650663645
Short name T204
Test name
Test status
Simulation time 1297801684 ps
CPU time 57.45 seconds
Started Mar 12 01:51:19 PM PDT 24
Finished Mar 12 01:52:17 PM PDT 24
Peak memory 199892 kb
Host smart-36f2c6a6-0cc5-4a6f-81df-db8807023011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650663645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1650663645
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3019325400
Short name T326
Test name
Test status
Simulation time 10985595 ps
CPU time 0.55 seconds
Started Mar 12 01:51:32 PM PDT 24
Finished Mar 12 01:51:33 PM PDT 24
Peak memory 194880 kb
Host smart-7d831a7e-a97d-4ffe-8286-e09d6c7b948a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019325400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3019325400
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.454878640
Short name T554
Test name
Test status
Simulation time 489395911 ps
CPU time 25.04 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:51:56 PM PDT 24
Peak memory 225404 kb
Host smart-64b4b007-a1f0-4073-8d6e-dae710127ca2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454878640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.454878640
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2306692919
Short name T327
Test name
Test status
Simulation time 2839326039 ps
CPU time 46.82 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:52:18 PM PDT 24
Peak memory 199940 kb
Host smart-8cd17c62-8f8a-4117-a254-6068d8524c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306692919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2306692919
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3793138034
Short name T524
Test name
Test status
Simulation time 6452978052 ps
CPU time 77.24 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:52:48 PM PDT 24
Peak memory 200012 kb
Host smart-1bbfcb87-f0ef-467d-b444-90332bf5fbc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793138034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3793138034
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1833228109
Short name T217
Test name
Test status
Simulation time 6029624792 ps
CPU time 188.85 seconds
Started Mar 12 01:51:30 PM PDT 24
Finished Mar 12 01:54:39 PM PDT 24
Peak memory 200056 kb
Host smart-b4237655-a934-4560-a773-f2a1e0f0bea2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833228109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1833228109
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.866581518
Short name T162
Test name
Test status
Simulation time 19360494729 ps
CPU time 83.78 seconds
Started Mar 12 01:51:32 PM PDT 24
Finished Mar 12 01:52:56 PM PDT 24
Peak memory 200092 kb
Host smart-3c76c64f-a45c-48b8-8046-aeb78a63b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866581518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.866581518
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.230743547
Short name T309
Test name
Test status
Simulation time 25126195 ps
CPU time 0.86 seconds
Started Mar 12 01:51:30 PM PDT 24
Finished Mar 12 01:51:31 PM PDT 24
Peak memory 197752 kb
Host smart-e88f9cf3-cf78-491c-8405-640ec37e0369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230743547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.230743547
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3385819484
Short name T346
Test name
Test status
Simulation time 56532527034 ps
CPU time 1442.42 seconds
Started Mar 12 01:51:33 PM PDT 24
Finished Mar 12 02:15:36 PM PDT 24
Peak memory 200076 kb
Host smart-cd9f4130-a369-4da4-af65-0a0b4061d582
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385819484 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3385819484
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2922360262
Short name T320
Test name
Test status
Simulation time 55301654 ps
CPU time 1.3 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:51:32 PM PDT 24
Peak memory 198772 kb
Host smart-6168adf1-98eb-4509-b5b3-5adcebca05c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922360262 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2922360262
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.4116222720
Short name T138
Test name
Test status
Simulation time 26281704690 ps
CPU time 490.1 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:59:41 PM PDT 24
Peak memory 200064 kb
Host smart-d954780c-ed8c-41e8-a732-bea9cbf2546e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116222720 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.4116222720
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.678576713
Short name T172
Test name
Test status
Simulation time 2124739851 ps
CPU time 91.26 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:53:03 PM PDT 24
Peak memory 199908 kb
Host smart-70c974f8-a795-4e34-9804-aac9f0fbf78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678576713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.678576713
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2851457815
Short name T246
Test name
Test status
Simulation time 20659480 ps
CPU time 0.59 seconds
Started Mar 12 01:51:32 PM PDT 24
Finished Mar 12 01:51:33 PM PDT 24
Peak memory 195248 kb
Host smart-69e7a297-d2fe-4e56-a57b-4d4695fa4663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851457815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2851457815
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.150227364
Short name T457
Test name
Test status
Simulation time 2862899199 ps
CPU time 63.87 seconds
Started Mar 12 01:51:32 PM PDT 24
Finished Mar 12 01:52:36 PM PDT 24
Peak memory 218404 kb
Host smart-bac40fbd-dacf-4ac4-8ed5-2b9cebee03df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150227364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.150227364
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1710322061
Short name T347
Test name
Test status
Simulation time 1175976420 ps
CPU time 56.5 seconds
Started Mar 12 01:51:32 PM PDT 24
Finished Mar 12 01:52:29 PM PDT 24
Peak memory 199836 kb
Host smart-4ef96d5b-47aa-41e8-85b4-e9af2f46644d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710322061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1710322061
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2358300890
Short name T444
Test name
Test status
Simulation time 5365446662 ps
CPU time 165.64 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:54:17 PM PDT 24
Peak memory 199996 kb
Host smart-d515083c-b7e8-4c0d-9171-858ac2da86bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358300890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2358300890
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2534222458
Short name T49
Test name
Test status
Simulation time 6958898892 ps
CPU time 100.09 seconds
Started Mar 12 01:51:29 PM PDT 24
Finished Mar 12 01:53:10 PM PDT 24
Peak memory 200016 kb
Host smart-b97812ee-e2d3-4b5b-8054-1f95b836f0bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534222458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2534222458
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2903502290
Short name T166
Test name
Test status
Simulation time 22607210755 ps
CPU time 80.88 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:52:52 PM PDT 24
Peak memory 200028 kb
Host smart-9895b64d-1515-4c8f-aa0f-00dac32a3029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903502290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2903502290
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2006665118
Short name T314
Test name
Test status
Simulation time 697593826 ps
CPU time 6.39 seconds
Started Mar 12 01:51:33 PM PDT 24
Finished Mar 12 01:51:39 PM PDT 24
Peak memory 199952 kb
Host smart-f6e7d954-8b13-4804-9d15-721ebf0efd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006665118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2006665118
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2160474153
Short name T26
Test name
Test status
Simulation time 58746301907 ps
CPU time 764.14 seconds
Started Mar 12 01:51:32 PM PDT 24
Finished Mar 12 02:04:16 PM PDT 24
Peak memory 208280 kb
Host smart-b005e663-4788-457c-bab7-06526c487397
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160474153 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2160474153
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.128007525
Short name T394
Test name
Test status
Simulation time 106285464 ps
CPU time 1.09 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:51:32 PM PDT 24
Peak memory 198788 kb
Host smart-d3b99469-f0a2-4899-bc33-5a3077c64a5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128007525 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_hmac_vectors.128007525
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2317374614
Short name T602
Test name
Test status
Simulation time 7952501262 ps
CPU time 448.7 seconds
Started Mar 12 01:51:34 PM PDT 24
Finished Mar 12 01:59:03 PM PDT 24
Peak memory 200000 kb
Host smart-ce310b01-ad11-415d-a79f-a2d15e780144
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317374614 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2317374614
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3256415622
Short name T354
Test name
Test status
Simulation time 6300051155 ps
CPU time 86.95 seconds
Started Mar 12 01:51:31 PM PDT 24
Finished Mar 12 01:52:58 PM PDT 24
Peak memory 200064 kb
Host smart-4d11d15d-5fd0-4d60-9a1f-ed0e58be20f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256415622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3256415622
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.981322871
Short name T335
Test name
Test status
Simulation time 12176266 ps
CPU time 0.59 seconds
Started Mar 12 01:51:49 PM PDT 24
Finished Mar 12 01:51:49 PM PDT 24
Peak memory 194924 kb
Host smart-2c5b9a24-29c7-4d56-b192-941d9994bc4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981322871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.981322871
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.4257754792
Short name T443
Test name
Test status
Simulation time 3382022225 ps
CPU time 73.47 seconds
Started Mar 12 01:51:42 PM PDT 24
Finished Mar 12 01:52:55 PM PDT 24
Peak memory 248600 kb
Host smart-21b7778b-5aa8-43cb-aed4-964b10b4c43b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4257754792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.4257754792
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1057396432
Short name T506
Test name
Test status
Simulation time 9480386823 ps
CPU time 31.13 seconds
Started Mar 12 01:51:39 PM PDT 24
Finished Mar 12 01:52:10 PM PDT 24
Peak memory 199972 kb
Host smart-9485400a-7ba3-4aa7-a0f3-d593574e5f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057396432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1057396432
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.572078167
Short name T82
Test name
Test status
Simulation time 1023275134 ps
CPU time 21.32 seconds
Started Mar 12 01:51:39 PM PDT 24
Finished Mar 12 01:52:01 PM PDT 24
Peak memory 199892 kb
Host smart-443a0875-9d93-481c-9ba7-0e6e4c7e6b4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572078167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.572078167
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2044074412
Short name T585
Test name
Test status
Simulation time 1981598238 ps
CPU time 10.33 seconds
Started Mar 12 01:51:41 PM PDT 24
Finished Mar 12 01:51:52 PM PDT 24
Peak memory 199916 kb
Host smart-07b3eea6-f7f9-49ff-a782-2102707b2aad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044074412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2044074412
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2678079888
Short name T425
Test name
Test status
Simulation time 450230178 ps
CPU time 29.04 seconds
Started Mar 12 01:51:39 PM PDT 24
Finished Mar 12 01:52:08 PM PDT 24
Peak memory 199956 kb
Host smart-b116bc44-874d-4af9-83df-0c130d02237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678079888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2678079888
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3006792205
Short name T376
Test name
Test status
Simulation time 756459664 ps
CPU time 2.95 seconds
Started Mar 12 01:51:32 PM PDT 24
Finished Mar 12 01:51:35 PM PDT 24
Peak memory 199920 kb
Host smart-e7062482-e88c-441b-9db6-2eb7b9632d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006792205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3006792205
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3493455600
Short name T11
Test name
Test status
Simulation time 5754508093 ps
CPU time 287.98 seconds
Started Mar 12 01:51:45 PM PDT 24
Finished Mar 12 01:56:33 PM PDT 24
Peak memory 229232 kb
Host smart-9db4c9b1-1f68-47a2-85e4-eb5dd57c5f47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493455600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3493455600
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.52018639
Short name T509
Test name
Test status
Simulation time 317497355 ps
CPU time 1.4 seconds
Started Mar 12 01:51:45 PM PDT 24
Finished Mar 12 01:51:46 PM PDT 24
Peak memory 199644 kb
Host smart-4d11a78c-1b82-40e6-8464-ae0896f0ca35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52018639 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.hmac_test_hmac_vectors.52018639
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.212894306
Short name T271
Test name
Test status
Simulation time 8236312765 ps
CPU time 491.33 seconds
Started Mar 12 01:51:52 PM PDT 24
Finished Mar 12 02:00:03 PM PDT 24
Peak memory 200068 kb
Host smart-315d4561-052c-40ba-a3e5-196249e4ada6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212894306 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.212894306
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2429256213
Short name T146
Test name
Test status
Simulation time 5263599549 ps
CPU time 100 seconds
Started Mar 12 01:51:40 PM PDT 24
Finished Mar 12 01:53:21 PM PDT 24
Peak memory 199980 kb
Host smart-93c4cb12-edaa-44c7-89e5-40c3a84d7925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429256213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2429256213
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.17982936
Short name T241
Test name
Test status
Simulation time 14879953 ps
CPU time 0.6 seconds
Started Mar 12 01:51:41 PM PDT 24
Finished Mar 12 01:51:41 PM PDT 24
Peak memory 195324 kb
Host smart-7ca2650c-6974-42a7-9102-3ec8b303a9d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17982936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.17982936
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2897789200
Short name T304
Test name
Test status
Simulation time 4939471605 ps
CPU time 44.14 seconds
Started Mar 12 01:51:42 PM PDT 24
Finished Mar 12 01:52:26 PM PDT 24
Peak memory 208124 kb
Host smart-e90365cd-1ee3-48ef-938a-b4025ca4c722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897789200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2897789200
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1145437489
Short name T329
Test name
Test status
Simulation time 1840290467 ps
CPU time 39.82 seconds
Started Mar 12 01:51:42 PM PDT 24
Finished Mar 12 01:52:22 PM PDT 24
Peak memory 199848 kb
Host smart-eb54bb56-b6ab-44ab-b080-1588f2b5a725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145437489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1145437489
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1230607709
Short name T78
Test name
Test status
Simulation time 767091536 ps
CPU time 50.61 seconds
Started Mar 12 01:51:40 PM PDT 24
Finished Mar 12 01:52:30 PM PDT 24
Peak memory 199860 kb
Host smart-8899f8e2-a71e-4f19-8f1a-7734b07fc6fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230607709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1230607709
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1388618425
Short name T191
Test name
Test status
Simulation time 12385857686 ps
CPU time 165.44 seconds
Started Mar 12 01:51:52 PM PDT 24
Finished Mar 12 01:54:37 PM PDT 24
Peak memory 200052 kb
Host smart-ab2acf2e-8706-482e-9721-9437ff23e4a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388618425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1388618425
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1943103113
Short name T201
Test name
Test status
Simulation time 38716233050 ps
CPU time 94.59 seconds
Started Mar 12 01:51:42 PM PDT 24
Finished Mar 12 01:53:17 PM PDT 24
Peak memory 200068 kb
Host smart-85aec0ec-7991-4be0-8fe6-73bcb4ec9beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943103113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1943103113
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1497664866
Short name T313
Test name
Test status
Simulation time 161836729 ps
CPU time 5.18 seconds
Started Mar 12 01:51:42 PM PDT 24
Finished Mar 12 01:51:47 PM PDT 24
Peak memory 199936 kb
Host smart-7effad70-7b5a-4c57-b783-11ad7238a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497664866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1497664866
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3036992342
Short name T75
Test name
Test status
Simulation time 67676534504 ps
CPU time 248.11 seconds
Started Mar 12 01:51:39 PM PDT 24
Finished Mar 12 01:55:48 PM PDT 24
Peak memory 200000 kb
Host smart-910869f6-516a-4302-810c-0d1d6dc909b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036992342 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3036992342
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.742628379
Short name T264
Test name
Test status
Simulation time 69840987 ps
CPU time 1.29 seconds
Started Mar 12 01:51:42 PM PDT 24
Finished Mar 12 01:51:43 PM PDT 24
Peak memory 199888 kb
Host smart-1e413b40-cf8e-4506-aeba-69cf54171327
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742628379 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.742628379
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3720192331
Short name T523
Test name
Test status
Simulation time 14370231611 ps
CPU time 418.58 seconds
Started Mar 12 01:51:42 PM PDT 24
Finished Mar 12 01:58:41 PM PDT 24
Peak memory 199948 kb
Host smart-5d021074-31db-44bf-81ed-a6f185ab88e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720192331 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3720192331
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2909535253
Short name T307
Test name
Test status
Simulation time 543643066 ps
CPU time 12.55 seconds
Started Mar 12 01:51:49 PM PDT 24
Finished Mar 12 01:52:01 PM PDT 24
Peak memory 199904 kb
Host smart-09cb2c82-9f12-4adb-adcb-8642936f10a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909535253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2909535253
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.406899286
Short name T456
Test name
Test status
Simulation time 32602477 ps
CPU time 0.56 seconds
Started Mar 12 01:51:52 PM PDT 24
Finished Mar 12 01:51:52 PM PDT 24
Peak memory 194228 kb
Host smart-d836578a-8962-4b41-864c-8d3ddce63f51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406899286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.406899286
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.4253809992
Short name T543
Test name
Test status
Simulation time 307475062 ps
CPU time 12.72 seconds
Started Mar 12 01:52:04 PM PDT 24
Finished Mar 12 01:52:17 PM PDT 24
Peak memory 215648 kb
Host smart-a78d146a-f630-47cc-8e36-0e77fff55bd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253809992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.4253809992
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.497730790
Short name T491
Test name
Test status
Simulation time 2678999098 ps
CPU time 33.92 seconds
Started Mar 12 01:51:54 PM PDT 24
Finished Mar 12 01:52:28 PM PDT 24
Peak memory 199940 kb
Host smart-f1ce6516-f87c-4f82-8c11-8a7c2adc95e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497730790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.497730790
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1855817919
Short name T365
Test name
Test status
Simulation time 1204965868 ps
CPU time 77.33 seconds
Started Mar 12 01:51:52 PM PDT 24
Finished Mar 12 01:53:09 PM PDT 24
Peak memory 199932 kb
Host smart-84eaa7e0-a007-4c61-8f4b-27a89c40b21e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855817919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1855817919
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4126402932
Short name T43
Test name
Test status
Simulation time 17851986055 ps
CPU time 216.37 seconds
Started Mar 12 01:51:53 PM PDT 24
Finished Mar 12 01:55:29 PM PDT 24
Peak memory 200016 kb
Host smart-71ef1d7d-1d89-454d-86ad-e01f8ec6132c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126402932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4126402932
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2686545141
Short name T350
Test name
Test status
Simulation time 107768452033 ps
CPU time 159.24 seconds
Started Mar 12 01:51:53 PM PDT 24
Finished Mar 12 01:54:32 PM PDT 24
Peak memory 200004 kb
Host smart-28f1a0ec-22d2-4265-8ce4-f93dbe59dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686545141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2686545141
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.563123008
Short name T180
Test name
Test status
Simulation time 169711244 ps
CPU time 1.54 seconds
Started Mar 12 01:51:54 PM PDT 24
Finished Mar 12 01:51:55 PM PDT 24
Peak memory 199872 kb
Host smart-4f127d36-1756-4d49-9a1f-ef739dcef3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563123008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.563123008
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3720225909
Short name T421
Test name
Test status
Simulation time 280941112340 ps
CPU time 1347.85 seconds
Started Mar 12 01:51:54 PM PDT 24
Finished Mar 12 02:14:22 PM PDT 24
Peak memory 228700 kb
Host smart-0922a202-e744-4f13-affd-0cf1f496ede9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720225909 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3720225909
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3559687562
Short name T428
Test name
Test status
Simulation time 71449062 ps
CPU time 1.39 seconds
Started Mar 12 01:51:55 PM PDT 24
Finished Mar 12 01:51:56 PM PDT 24
Peak memory 199256 kb
Host smart-ec802d96-904e-4907-ad03-f0bc01d5943b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559687562 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3559687562
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.662606284
Short name T480
Test name
Test status
Simulation time 80566520204 ps
CPU time 523.56 seconds
Started Mar 12 01:51:53 PM PDT 24
Finished Mar 12 02:00:37 PM PDT 24
Peak memory 200096 kb
Host smart-9a1385db-ec32-4ccd-bc22-1501ce27ea6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662606284 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.662606284
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1151097077
Short name T488
Test name
Test status
Simulation time 6123348340 ps
CPU time 25.31 seconds
Started Mar 12 01:51:53 PM PDT 24
Finished Mar 12 01:52:18 PM PDT 24
Peak memory 200088 kb
Host smart-199bee6a-bdc2-4f10-8388-1d49a890560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151097077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1151097077
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.4149237498
Short name T238
Test name
Test status
Simulation time 49465796 ps
CPU time 0.6 seconds
Started Mar 12 01:51:54 PM PDT 24
Finished Mar 12 01:51:54 PM PDT 24
Peak memory 195336 kb
Host smart-cc6fa415-d9e8-480f-a735-deccf3b84c8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149237498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.4149237498
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.961838125
Short name T189
Test name
Test status
Simulation time 589898007 ps
CPU time 11.44 seconds
Started Mar 12 01:51:51 PM PDT 24
Finished Mar 12 01:52:03 PM PDT 24
Peak memory 224468 kb
Host smart-6af63642-c3a4-4b93-9282-e6ab0d6d00b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961838125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.961838125
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1768736724
Short name T321
Test name
Test status
Simulation time 523665852 ps
CPU time 4.83 seconds
Started Mar 12 01:51:52 PM PDT 24
Finished Mar 12 01:51:56 PM PDT 24
Peak memory 199748 kb
Host smart-1a69c59a-6938-4ca8-904a-a2f1a69f9cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768736724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1768736724
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.221528831
Short name T527
Test name
Test status
Simulation time 1278648452 ps
CPU time 73.28 seconds
Started Mar 12 01:51:52 PM PDT 24
Finished Mar 12 01:53:05 PM PDT 24
Peak memory 199940 kb
Host smart-29e612e6-c0f1-45e0-8a16-feebf4baf4f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221528831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.221528831
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3054166565
Short name T261
Test name
Test status
Simulation time 13103567262 ps
CPU time 179.91 seconds
Started Mar 12 01:51:53 PM PDT 24
Finished Mar 12 01:54:53 PM PDT 24
Peak memory 200000 kb
Host smart-6cd828ce-7708-4da9-a75f-7d073ec0e111
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054166565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3054166565
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1855416985
Short name T490
Test name
Test status
Simulation time 28816144185 ps
CPU time 111.29 seconds
Started Mar 12 01:51:53 PM PDT 24
Finished Mar 12 01:53:45 PM PDT 24
Peak memory 200028 kb
Host smart-1543ae79-eadd-474e-a6b9-cc91a88929ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855416985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1855416985
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.24815305
Short name T124
Test name
Test status
Simulation time 87913158 ps
CPU time 2.65 seconds
Started Mar 12 01:51:51 PM PDT 24
Finished Mar 12 01:51:54 PM PDT 24
Peak memory 199872 kb
Host smart-7363d1cf-813c-42c8-ae06-d86ea75149b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24815305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.24815305
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2166649277
Short name T63
Test name
Test status
Simulation time 2150038380 ps
CPU time 16.85 seconds
Started Mar 12 01:51:53 PM PDT 24
Finished Mar 12 01:52:10 PM PDT 24
Peak memory 199972 kb
Host smart-7811da2d-b2a6-4f7a-b278-08bd2f293228
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166649277 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2166649277
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.968816042
Short name T337
Test name
Test status
Simulation time 31405846 ps
CPU time 1.29 seconds
Started Mar 12 01:51:52 PM PDT 24
Finished Mar 12 01:51:53 PM PDT 24
Peak memory 199580 kb
Host smart-a9e9c280-eae8-4688-a15b-f70fea66f6fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968816042 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.968816042
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.3886317368
Short name T216
Test name
Test status
Simulation time 388327125508 ps
CPU time 520.21 seconds
Started Mar 12 01:51:53 PM PDT 24
Finished Mar 12 02:00:33 PM PDT 24
Peak memory 200052 kb
Host smart-3f25189f-28e7-4276-a083-d3c7819f7ddf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886317368 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.3886317368
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1060972770
Short name T517
Test name
Test status
Simulation time 343562078 ps
CPU time 7.69 seconds
Started Mar 12 01:51:51 PM PDT 24
Finished Mar 12 01:51:59 PM PDT 24
Peak memory 199956 kb
Host smart-7778a1ed-32fc-4005-a0cb-62de871da9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060972770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1060972770
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2102119031
Short name T227
Test name
Test status
Simulation time 27924427 ps
CPU time 0.63 seconds
Started Mar 12 01:52:01 PM PDT 24
Finished Mar 12 01:52:02 PM PDT 24
Peak memory 195316 kb
Host smart-1a637e85-8a3a-4125-90fe-48fc1bfa6c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102119031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2102119031
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1565092278
Short name T150
Test name
Test status
Simulation time 2316047748 ps
CPU time 25.35 seconds
Started Mar 12 01:52:01 PM PDT 24
Finished Mar 12 01:52:27 PM PDT 24
Peak memory 223180 kb
Host smart-7986bb86-6d98-4585-a7d1-8d24a92f6b0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565092278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1565092278
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3538973576
Short name T315
Test name
Test status
Simulation time 2986232933 ps
CPU time 22.93 seconds
Started Mar 12 01:52:03 PM PDT 24
Finished Mar 12 01:52:27 PM PDT 24
Peak memory 200008 kb
Host smart-1f896563-ca10-421c-b7d4-8590edf990ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538973576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3538973576
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.852387920
Short name T505
Test name
Test status
Simulation time 8208353086 ps
CPU time 149.95 seconds
Started Mar 12 01:52:03 PM PDT 24
Finished Mar 12 01:54:34 PM PDT 24
Peak memory 200020 kb
Host smart-950e0d1b-3765-422f-96d9-4b818c5f5c3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852387920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.852387920
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3454459176
Short name T448
Test name
Test status
Simulation time 26452926168 ps
CPU time 122.1 seconds
Started Mar 12 01:52:03 PM PDT 24
Finished Mar 12 01:54:06 PM PDT 24
Peak memory 200076 kb
Host smart-0a63a047-40c9-47d0-96a1-a9afa831604f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454459176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3454459176
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4294889862
Short name T342
Test name
Test status
Simulation time 3735154062 ps
CPU time 13.74 seconds
Started Mar 12 01:52:02 PM PDT 24
Finished Mar 12 01:52:18 PM PDT 24
Peak memory 199924 kb
Host smart-1316b664-8334-4776-abd8-ce9c5030be43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294889862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4294889862
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1295568199
Short name T125
Test name
Test status
Simulation time 291889972 ps
CPU time 0.87 seconds
Started Mar 12 01:51:54 PM PDT 24
Finished Mar 12 01:51:55 PM PDT 24
Peak memory 198040 kb
Host smart-7bf8aaf5-60d9-42a1-90a8-839882247cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295568199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1295568199
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2240646912
Short name T265
Test name
Test status
Simulation time 63021903 ps
CPU time 1.33 seconds
Started Mar 12 01:52:01 PM PDT 24
Finished Mar 12 01:52:03 PM PDT 24
Peak memory 198532 kb
Host smart-65eeacf8-1f53-4730-b7d2-82a34c4941cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240646912 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2240646912
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3827187840
Short name T415
Test name
Test status
Simulation time 8234751639 ps
CPU time 434.99 seconds
Started Mar 12 01:52:04 PM PDT 24
Finished Mar 12 01:59:20 PM PDT 24
Peak memory 200040 kb
Host smart-bf766d45-49dc-4934-92c9-af0d3cae20f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827187840 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.3827187840
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1719189643
Short name T120
Test name
Test status
Simulation time 7041783085 ps
CPU time 116.39 seconds
Started Mar 12 01:52:05 PM PDT 24
Finished Mar 12 01:54:01 PM PDT 24
Peak memory 200040 kb
Host smart-fd969a2d-3620-4f7d-b611-b8d1dcd61cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719189643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1719189643
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1154036389
Short name T279
Test name
Test status
Simulation time 34500734 ps
CPU time 0.59 seconds
Started Mar 12 01:52:01 PM PDT 24
Finished Mar 12 01:52:02 PM PDT 24
Peak memory 195316 kb
Host smart-b0556f9b-6814-451c-89ad-719021cd0ba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154036389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1154036389
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3851206919
Short name T601
Test name
Test status
Simulation time 1139834921 ps
CPU time 5.54 seconds
Started Mar 12 01:52:03 PM PDT 24
Finished Mar 12 01:52:10 PM PDT 24
Peak memory 208100 kb
Host smart-f22f8dcc-2c66-4fb3-a6f8-762b7eac94cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851206919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3851206919
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3050010505
Short name T403
Test name
Test status
Simulation time 2686554225 ps
CPU time 56.75 seconds
Started Mar 12 01:52:02 PM PDT 24
Finished Mar 12 01:53:00 PM PDT 24
Peak memory 199968 kb
Host smart-af94d5c5-4d88-42c0-b8c6-46866deb1e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050010505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3050010505
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.49135105
Short name T213
Test name
Test status
Simulation time 5498834353 ps
CPU time 84.83 seconds
Started Mar 12 01:52:01 PM PDT 24
Finished Mar 12 01:53:26 PM PDT 24
Peak memory 199976 kb
Host smart-0ccd0bd0-6da1-40c5-93b4-d2f7dbb5f8c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49135105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.49135105
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.659312736
Short name T590
Test name
Test status
Simulation time 5240005435 ps
CPU time 148.37 seconds
Started Mar 12 01:52:02 PM PDT 24
Finished Mar 12 01:54:32 PM PDT 24
Peak memory 200028 kb
Host smart-436b44aa-6309-496c-ae59-4ade54b3fb75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659312736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.659312736
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.912944202
Short name T483
Test name
Test status
Simulation time 10462949190 ps
CPU time 52.68 seconds
Started Mar 12 01:52:02 PM PDT 24
Finished Mar 12 01:52:56 PM PDT 24
Peak memory 200056 kb
Host smart-5af76dc0-a968-4204-b921-5bcae8eac7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912944202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.912944202
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.4145695005
Short name T436
Test name
Test status
Simulation time 539796748 ps
CPU time 3.32 seconds
Started Mar 12 01:52:00 PM PDT 24
Finished Mar 12 01:52:05 PM PDT 24
Peak memory 199916 kb
Host smart-9a786c55-5b3b-4fc9-887a-336818bb7fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145695005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4145695005
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2180775016
Short name T255
Test name
Test status
Simulation time 39756346659 ps
CPU time 843.45 seconds
Started Mar 12 01:52:04 PM PDT 24
Finished Mar 12 02:06:08 PM PDT 24
Peak memory 242196 kb
Host smart-79de1f18-57de-4965-9b69-4a5981d68958
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180775016 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2180775016
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2220142021
Short name T419
Test name
Test status
Simulation time 106443044 ps
CPU time 1.09 seconds
Started Mar 12 01:52:02 PM PDT 24
Finished Mar 12 01:52:04 PM PDT 24
Peak memory 198936 kb
Host smart-4f44354c-0335-4dc1-ac4f-a3cd3aa209b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220142021 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2220142021
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1234497819
Short name T273
Test name
Test status
Simulation time 87721474142 ps
CPU time 486.4 seconds
Started Mar 12 01:52:04 PM PDT 24
Finished Mar 12 02:00:11 PM PDT 24
Peak memory 200060 kb
Host smart-d7315eb2-c939-44df-b44d-9a553a0085d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234497819 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1234497819
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2640975187
Short name T424
Test name
Test status
Simulation time 12472953131 ps
CPU time 96.22 seconds
Started Mar 12 01:52:00 PM PDT 24
Finished Mar 12 01:53:38 PM PDT 24
Peak memory 200060 kb
Host smart-395a6a09-a4ba-411c-ab9e-addd4efcd526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640975187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2640975187
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3861825902
Short name T567
Test name
Test status
Simulation time 57644863 ps
CPU time 0.57 seconds
Started Mar 12 01:52:12 PM PDT 24
Finished Mar 12 01:52:13 PM PDT 24
Peak memory 195324 kb
Host smart-707c364b-369a-4682-ab25-40d92df07973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861825902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3861825902
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4139409718
Short name T188
Test name
Test status
Simulation time 1114402081 ps
CPU time 40.53 seconds
Started Mar 12 01:52:13 PM PDT 24
Finished Mar 12 01:52:54 PM PDT 24
Peak memory 224560 kb
Host smart-a3748450-d31d-4fcb-a313-047ee3374787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139409718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4139409718
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1321669181
Short name T174
Test name
Test status
Simulation time 8032068846 ps
CPU time 28.8 seconds
Started Mar 12 01:52:11 PM PDT 24
Finished Mar 12 01:52:40 PM PDT 24
Peak memory 200068 kb
Host smart-96f18ea4-1e40-42a3-b53a-54956ffaf63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321669181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1321669181
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3222060676
Short name T306
Test name
Test status
Simulation time 3245602490 ps
CPU time 47.14 seconds
Started Mar 12 01:52:13 PM PDT 24
Finished Mar 12 01:53:01 PM PDT 24
Peak memory 199952 kb
Host smart-bf06458d-6f7e-4bda-b92d-046c6be402af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222060676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3222060676
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3542783580
Short name T13
Test name
Test status
Simulation time 36412689475 ps
CPU time 143.56 seconds
Started Mar 12 01:52:12 PM PDT 24
Finished Mar 12 01:54:37 PM PDT 24
Peak memory 200008 kb
Host smart-3c6496d2-8d90-407c-b0b3-2a0564f99fe9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542783580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3542783580
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.4141977351
Short name T570
Test name
Test status
Simulation time 21525130891 ps
CPU time 93.39 seconds
Started Mar 12 01:52:02 PM PDT 24
Finished Mar 12 01:53:36 PM PDT 24
Peak memory 200100 kb
Host smart-9f6360e3-2bfb-43a9-b849-b7dda098678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141977351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.4141977351
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2690817379
Short name T406
Test name
Test status
Simulation time 136666256 ps
CPU time 0.84 seconds
Started Mar 12 01:52:06 PM PDT 24
Finished Mar 12 01:52:07 PM PDT 24
Peak memory 196756 kb
Host smart-b567098c-59f4-499c-b014-0fc3ad96a5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690817379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2690817379
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2934531013
Short name T237
Test name
Test status
Simulation time 58652078118 ps
CPU time 1600.29 seconds
Started Mar 12 01:52:12 PM PDT 24
Finished Mar 12 02:18:53 PM PDT 24
Peak memory 241008 kb
Host smart-04cdeb48-15ae-4ebc-85ce-61521e2011be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934531013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2934531013
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3502335660
Short name T459
Test name
Test status
Simulation time 31051247 ps
CPU time 1.05 seconds
Started Mar 12 01:52:12 PM PDT 24
Finished Mar 12 01:52:14 PM PDT 24
Peak memory 198736 kb
Host smart-1a6fd779-3a63-4cba-bcb9-ca4d9bf72852
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502335660 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3502335660
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1091776304
Short name T289
Test name
Test status
Simulation time 16046659609 ps
CPU time 455.51 seconds
Started Mar 12 01:52:10 PM PDT 24
Finished Mar 12 01:59:47 PM PDT 24
Peak memory 200040 kb
Host smart-3f5402f9-9360-4194-9e7c-6b2c72e0f288
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091776304 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1091776304
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1665219801
Short name T358
Test name
Test status
Simulation time 2927556609 ps
CPU time 38.9 seconds
Started Mar 12 01:52:13 PM PDT 24
Finished Mar 12 01:52:53 PM PDT 24
Peak memory 199968 kb
Host smart-c7ddd2f4-eb0f-4694-8ddb-e42ec6986d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665219801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1665219801
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3185884808
Short name T206
Test name
Test status
Simulation time 14617374 ps
CPU time 0.58 seconds
Started Mar 12 01:44:53 PM PDT 24
Finished Mar 12 01:44:53 PM PDT 24
Peak memory 194332 kb
Host smart-a77d7d65-09d5-4775-8074-dc114a3103bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185884808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3185884808
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1781971412
Short name T336
Test name
Test status
Simulation time 6980362457 ps
CPU time 70.67 seconds
Started Mar 12 01:44:44 PM PDT 24
Finished Mar 12 01:45:57 PM PDT 24
Peak memory 241016 kb
Host smart-2f7d5ce7-646f-4d70-ba8e-83774a06bbc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781971412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1781971412
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2559806625
Short name T222
Test name
Test status
Simulation time 347462912 ps
CPU time 19.33 seconds
Started Mar 12 01:44:51 PM PDT 24
Finished Mar 12 01:45:11 PM PDT 24
Peak memory 199764 kb
Host smart-8ce2b8a9-f950-45a7-aed2-d76f0cfc033c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559806625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2559806625
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2377818372
Short name T451
Test name
Test status
Simulation time 3229381239 ps
CPU time 48.59 seconds
Started Mar 12 01:44:48 PM PDT 24
Finished Mar 12 01:45:36 PM PDT 24
Peak memory 199944 kb
Host smart-b64e1bf0-83f8-4f11-8bce-6ce49d034172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377818372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2377818372
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3377639791
Short name T182
Test name
Test status
Simulation time 14082713575 ps
CPU time 184.59 seconds
Started Mar 12 01:44:50 PM PDT 24
Finished Mar 12 01:47:54 PM PDT 24
Peak memory 200056 kb
Host smart-336b4571-93c0-401e-a13c-03e7da6dd4cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377639791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3377639791
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.448006223
Short name T203
Test name
Test status
Simulation time 7641693627 ps
CPU time 98.04 seconds
Started Mar 12 01:44:46 PM PDT 24
Finished Mar 12 01:46:25 PM PDT 24
Peak memory 200008 kb
Host smart-fc901eb7-150c-47d8-8e98-4a4c3a0f5232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448006223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.448006223
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1913405708
Short name T181
Test name
Test status
Simulation time 150279669 ps
CPU time 1.33 seconds
Started Mar 12 01:44:46 PM PDT 24
Finished Mar 12 01:44:49 PM PDT 24
Peak memory 199892 kb
Host smart-90dad53b-4694-43d0-9cf5-5cdd807a25e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913405708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1913405708
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3217074664
Short name T282
Test name
Test status
Simulation time 49219037482 ps
CPU time 1511.4 seconds
Started Mar 12 01:44:51 PM PDT 24
Finished Mar 12 02:10:03 PM PDT 24
Peak memory 200036 kb
Host smart-db014377-b5e5-443a-84e4-e7022c1d87cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217074664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3217074664
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2184295317
Short name T61
Test name
Test status
Simulation time 62087949209 ps
CPU time 1952.07 seconds
Started Mar 12 01:44:51 PM PDT 24
Finished Mar 12 02:17:24 PM PDT 24
Peak memory 261488 kb
Host smart-418ef145-48b7-4835-8906-7fefdb96fbce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184295317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2184295317
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.426678862
Short name T123
Test name
Test status
Simulation time 65231043 ps
CPU time 1.31 seconds
Started Mar 12 01:44:51 PM PDT 24
Finished Mar 12 01:44:53 PM PDT 24
Peak memory 199296 kb
Host smart-c61ca8b5-b3c9-4271-a605-571d32cf8e4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426678862 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.426678862
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2892191188
Short name T446
Test name
Test status
Simulation time 33319967141 ps
CPU time 472.01 seconds
Started Mar 12 01:44:51 PM PDT 24
Finished Mar 12 01:52:43 PM PDT 24
Peak memory 200040 kb
Host smart-27bfbee5-5d3d-40fb-82d2-8abe2194e7a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892191188 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2892191188
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3529081868
Short name T263
Test name
Test status
Simulation time 2617977502 ps
CPU time 52.58 seconds
Started Mar 12 01:44:52 PM PDT 24
Finished Mar 12 01:45:45 PM PDT 24
Peak memory 200000 kb
Host smart-50c586fd-54b7-4833-b800-802069bbfef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529081868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3529081868
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.3125581647
Short name T541
Test name
Test status
Simulation time 52067843500 ps
CPU time 494.97 seconds
Started Mar 12 01:52:15 PM PDT 24
Finished Mar 12 02:00:30 PM PDT 24
Peak memory 208396 kb
Host smart-99203fab-4f8f-4364-81a3-5aed7629f9e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125581647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.3125581647
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3496879645
Short name T311
Test name
Test status
Simulation time 13942358 ps
CPU time 0.58 seconds
Started Mar 12 01:45:01 PM PDT 24
Finished Mar 12 01:45:01 PM PDT 24
Peak memory 194312 kb
Host smart-e2c582e0-26ed-4d0d-a551-62e1512eb7a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496879645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3496879645
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.584998739
Short name T50
Test name
Test status
Simulation time 2019185369 ps
CPU time 48.66 seconds
Started Mar 12 01:44:53 PM PDT 24
Finished Mar 12 01:45:41 PM PDT 24
Peak memory 208060 kb
Host smart-d0898ea1-57f1-48ec-90d5-008cf050006b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584998739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.584998739
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1806492181
Short name T392
Test name
Test status
Simulation time 335616486 ps
CPU time 8.67 seconds
Started Mar 12 01:45:00 PM PDT 24
Finished Mar 12 01:45:09 PM PDT 24
Peak memory 199920 kb
Host smart-d1b9b048-e567-480b-9d5f-529a10e6041e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806492181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1806492181
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.301059279
Short name T176
Test name
Test status
Simulation time 2611840572 ps
CPU time 147.33 seconds
Started Mar 12 01:44:51 PM PDT 24
Finished Mar 12 01:47:18 PM PDT 24
Peak memory 199988 kb
Host smart-fc22acfb-8064-46e5-b725-b07b42fb3173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301059279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.301059279
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.813184818
Short name T84
Test name
Test status
Simulation time 2908222669 ps
CPU time 165.26 seconds
Started Mar 12 01:45:01 PM PDT 24
Finished Mar 12 01:47:47 PM PDT 24
Peak memory 199992 kb
Host smart-090e396f-6ae6-4c06-ad4e-7d209b4fc697
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813184818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.813184818
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2179116089
Short name T290
Test name
Test status
Simulation time 7045697504 ps
CPU time 60.61 seconds
Started Mar 12 01:44:51 PM PDT 24
Finished Mar 12 01:45:52 PM PDT 24
Peak memory 199920 kb
Host smart-9bda6d76-6266-4e31-9b31-f922d70846e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179116089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2179116089
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3610537491
Short name T388
Test name
Test status
Simulation time 242221326 ps
CPU time 1.01 seconds
Started Mar 12 01:44:50 PM PDT 24
Finished Mar 12 01:44:51 PM PDT 24
Peak memory 199692 kb
Host smart-c7d73bef-2ee5-4eb8-bddd-451f3e69e5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610537491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3610537491
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.4270131053
Short name T400
Test name
Test status
Simulation time 6057666166 ps
CPU time 323.06 seconds
Started Mar 12 01:45:00 PM PDT 24
Finished Mar 12 01:50:23 PM PDT 24
Peak memory 219600 kb
Host smart-ebf0df94-35b3-41a3-825e-72d4185c31d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270131053 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4270131053
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.4055324568
Short name T266
Test name
Test status
Simulation time 100544335 ps
CPU time 0.88 seconds
Started Mar 12 01:45:00 PM PDT 24
Finished Mar 12 01:45:02 PM PDT 24
Peak memory 198400 kb
Host smart-52e4879f-c80f-4678-8358-fec637e67873
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055324568 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.4055324568
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.633828639
Short name T170
Test name
Test status
Simulation time 12211172733 ps
CPU time 407.68 seconds
Started Mar 12 01:45:00 PM PDT 24
Finished Mar 12 01:51:48 PM PDT 24
Peak memory 200004 kb
Host smart-a7265bed-9d3d-4135-811d-6c0bd23f1b09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633828639 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.633828639
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.274627055
Short name T516
Test name
Test status
Simulation time 6240877706 ps
CPU time 70.4 seconds
Started Mar 12 01:45:00 PM PDT 24
Finished Mar 12 01:46:11 PM PDT 24
Peak memory 200056 kb
Host smart-f2fcc236-b021-43a8-91ac-fe86f0ebb828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274627055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.274627055
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.29635069
Short name T322
Test name
Test status
Simulation time 35251236 ps
CPU time 0.62 seconds
Started Mar 12 01:45:01 PM PDT 24
Finished Mar 12 01:45:02 PM PDT 24
Peak memory 194252 kb
Host smart-57bbfb42-dff2-4293-a3e3-4f3b3ac8ee53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29635069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.29635069
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3095645302
Short name T545
Test name
Test status
Simulation time 18827372660 ps
CPU time 46.28 seconds
Started Mar 12 01:45:00 PM PDT 24
Finished Mar 12 01:45:46 PM PDT 24
Peak memory 234832 kb
Host smart-3958f245-4db2-4105-bba3-938e737e54e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095645302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3095645302
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3265441957
Short name T193
Test name
Test status
Simulation time 4239098619 ps
CPU time 58.31 seconds
Started Mar 12 01:44:59 PM PDT 24
Finished Mar 12 01:45:57 PM PDT 24
Peak memory 199924 kb
Host smart-dc793dcb-d8fb-4d03-874b-e255329441b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265441957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3265441957
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.671447198
Short name T121
Test name
Test status
Simulation time 187187792 ps
CPU time 11.77 seconds
Started Mar 12 01:44:59 PM PDT 24
Finished Mar 12 01:45:12 PM PDT 24
Peak memory 199892 kb
Host smart-b128cbb1-2f02-4ca6-8993-55e8817a0022
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671447198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.671447198
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3863260776
Short name T366
Test name
Test status
Simulation time 2400740533 ps
CPU time 44.7 seconds
Started Mar 12 01:45:01 PM PDT 24
Finished Mar 12 01:45:46 PM PDT 24
Peak memory 199968 kb
Host smart-c6fc2237-88fc-45d3-98ba-00263538fdfd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863260776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3863260776
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3048757810
Short name T288
Test name
Test status
Simulation time 29942636817 ps
CPU time 108.77 seconds
Started Mar 12 01:45:01 PM PDT 24
Finished Mar 12 01:46:50 PM PDT 24
Peak memory 200028 kb
Host smart-c45e897d-809a-49b1-8b97-3bbd9ea00154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048757810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3048757810
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2879223410
Short name T324
Test name
Test status
Simulation time 896851768 ps
CPU time 2.29 seconds
Started Mar 12 01:45:00 PM PDT 24
Finished Mar 12 01:45:02 PM PDT 24
Peak memory 199896 kb
Host smart-0848609e-e53b-478c-8bda-6276ca07216e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879223410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2879223410
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.30626525
Short name T364
Test name
Test status
Simulation time 110359547167 ps
CPU time 519.68 seconds
Started Mar 12 01:45:00 PM PDT 24
Finished Mar 12 01:53:40 PM PDT 24
Peak memory 208160 kb
Host smart-ed051beb-c44c-4a06-a917-b04ada53e72f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30626525 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.30626525
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1045683123
Short name T592
Test name
Test status
Simulation time 210023624 ps
CPU time 1.31 seconds
Started Mar 12 01:45:02 PM PDT 24
Finished Mar 12 01:45:03 PM PDT 24
Peak memory 199936 kb
Host smart-8026307c-13cb-49d5-ad24-eb2d00674bbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045683123 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1045683123
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2229222626
Short name T577
Test name
Test status
Simulation time 116459436298 ps
CPU time 527.21 seconds
Started Mar 12 01:45:01 PM PDT 24
Finished Mar 12 01:53:49 PM PDT 24
Peak memory 200040 kb
Host smart-c091aa8c-655f-49bb-b153-9f10a55f5706
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229222626 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2229222626
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3201567525
Short name T556
Test name
Test status
Simulation time 592541906 ps
CPU time 8.62 seconds
Started Mar 12 01:45:00 PM PDT 24
Finished Mar 12 01:45:09 PM PDT 24
Peak memory 199944 kb
Host smart-48b20492-cb79-49e2-b495-d6b067e3b7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201567525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3201567525
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.3009617521
Short name T6
Test name
Test status
Simulation time 98197620658 ps
CPU time 3247.1 seconds
Started Mar 12 01:52:25 PM PDT 24
Finished Mar 12 02:46:32 PM PDT 24
Peak memory 241992 kb
Host smart-bacbc88a-8953-4af1-bcf3-7bd1846d5a4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009617521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.3009617521
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2962291186
Short name T371
Test name
Test status
Simulation time 22353944 ps
CPU time 0.58 seconds
Started Mar 12 01:45:08 PM PDT 24
Finished Mar 12 01:45:09 PM PDT 24
Peak memory 195324 kb
Host smart-c631ecba-0880-45e2-abb8-af0c0d8a008a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962291186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2962291186
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1384251823
Short name T167
Test name
Test status
Simulation time 1734508872 ps
CPU time 15.06 seconds
Started Mar 12 01:44:59 PM PDT 24
Finished Mar 12 01:45:14 PM PDT 24
Peak memory 199900 kb
Host smart-d864161e-c85b-44ef-b386-c6e213015287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384251823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1384251823
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.4107601117
Short name T117
Test name
Test status
Simulation time 999765045 ps
CPU time 23.9 seconds
Started Mar 12 01:45:00 PM PDT 24
Finished Mar 12 01:45:24 PM PDT 24
Peak memory 199760 kb
Host smart-913fc8b7-1994-47bf-8656-1b9fc0e531d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107601117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.4107601117
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.100450812
Short name T199
Test name
Test status
Simulation time 11074199198 ps
CPU time 129.63 seconds
Started Mar 12 01:45:03 PM PDT 24
Finished Mar 12 01:47:12 PM PDT 24
Peak memory 199896 kb
Host smart-58a3c39f-6b9e-405d-863e-916f9d00b31e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100450812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.100450812
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.107951919
Short name T442
Test name
Test status
Simulation time 31071818431 ps
CPU time 196.2 seconds
Started Mar 12 01:45:09 PM PDT 24
Finished Mar 12 01:48:25 PM PDT 24
Peak memory 200024 kb
Host smart-86ef9770-85ed-4222-9451-1efaf2664d14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107951919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.107951919
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.291786304
Short name T186
Test name
Test status
Simulation time 1582733794 ps
CPU time 94.73 seconds
Started Mar 12 01:44:58 PM PDT 24
Finished Mar 12 01:46:33 PM PDT 24
Peak memory 199832 kb
Host smart-71dc39c5-6b8b-4df4-bef2-a0532ab6d7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291786304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.291786304
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2045147556
Short name T594
Test name
Test status
Simulation time 188983921 ps
CPU time 5.85 seconds
Started Mar 12 01:45:01 PM PDT 24
Finished Mar 12 01:45:07 PM PDT 24
Peak memory 199928 kb
Host smart-b9c63739-9968-4e98-95ec-050c129f82fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045147556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2045147556
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1843987366
Short name T134
Test name
Test status
Simulation time 15623395979 ps
CPU time 299.12 seconds
Started Mar 12 01:45:10 PM PDT 24
Finished Mar 12 01:50:09 PM PDT 24
Peak memory 215580 kb
Host smart-ce8a6dbf-89d2-4f5a-a4a7-0092a2c95331
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843987366 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1843987366
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2916178592
Short name T519
Test name
Test status
Simulation time 53438837 ps
CPU time 1.14 seconds
Started Mar 12 01:45:08 PM PDT 24
Finished Mar 12 01:45:10 PM PDT 24
Peak memory 199088 kb
Host smart-b34ac6f9-6f36-4d98-b48a-40403dfbdf07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916178592 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2916178592
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2405206185
Short name T550
Test name
Test status
Simulation time 85417274849 ps
CPU time 558.78 seconds
Started Mar 12 01:45:08 PM PDT 24
Finished Mar 12 01:54:28 PM PDT 24
Peak memory 200020 kb
Host smart-2d08329f-ff4b-40ac-a7bf-2e17fa385c0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405206185 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2405206185
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1545658562
Short name T440
Test name
Test status
Simulation time 1188290097 ps
CPU time 46.17 seconds
Started Mar 12 01:45:09 PM PDT 24
Finished Mar 12 01:45:55 PM PDT 24
Peak memory 199900 kb
Host smart-a70a146b-f06f-4bad-a9c2-194d198b31a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545658562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1545658562
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1079887426
Short name T195
Test name
Test status
Simulation time 34657273 ps
CPU time 0.6 seconds
Started Mar 12 01:45:07 PM PDT 24
Finished Mar 12 01:45:07 PM PDT 24
Peak memory 195316 kb
Host smart-2da96363-6c1f-41da-9b08-1c5f22b49701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079887426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1079887426
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2768530849
Short name T340
Test name
Test status
Simulation time 1104474976 ps
CPU time 32.05 seconds
Started Mar 12 01:45:11 PM PDT 24
Finished Mar 12 01:45:43 PM PDT 24
Peak memory 237744 kb
Host smart-e3e15333-6754-4a23-bbc3-74680d126d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768530849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2768530849
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4022845377
Short name T603
Test name
Test status
Simulation time 13559525451 ps
CPU time 49.96 seconds
Started Mar 12 01:45:08 PM PDT 24
Finished Mar 12 01:45:58 PM PDT 24
Peak memory 199928 kb
Host smart-75516dc1-ce57-474b-b64b-ec214d166c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022845377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4022845377
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1083131798
Short name T379
Test name
Test status
Simulation time 2369486749 ps
CPU time 71.01 seconds
Started Mar 12 01:45:09 PM PDT 24
Finished Mar 12 01:46:20 PM PDT 24
Peak memory 200008 kb
Host smart-02997bb6-71ba-4fae-af42-275a45381af4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083131798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1083131798
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.559682948
Short name T513
Test name
Test status
Simulation time 664626016 ps
CPU time 39.83 seconds
Started Mar 12 01:45:07 PM PDT 24
Finished Mar 12 01:45:47 PM PDT 24
Peak memory 199884 kb
Host smart-621d10d4-7ec6-4f3e-84a1-9387617d497e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559682948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.559682948
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3080896991
Short name T197
Test name
Test status
Simulation time 3970172060 ps
CPU time 123.11 seconds
Started Mar 12 01:45:09 PM PDT 24
Finished Mar 12 01:47:12 PM PDT 24
Peak memory 199932 kb
Host smart-324edc68-d02e-454b-a646-d7b9a6468482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080896991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3080896991
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1424518317
Short name T547
Test name
Test status
Simulation time 1616672610 ps
CPU time 6.07 seconds
Started Mar 12 01:45:07 PM PDT 24
Finished Mar 12 01:45:14 PM PDT 24
Peak memory 199900 kb
Host smart-2e0b3e4c-484c-4ae7-8038-896a7d216438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424518317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1424518317
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3046635331
Short name T389
Test name
Test status
Simulation time 38647876214 ps
CPU time 498.59 seconds
Started Mar 12 01:45:07 PM PDT 24
Finished Mar 12 01:53:26 PM PDT 24
Peak memory 216212 kb
Host smart-1fa03768-97a7-452f-8c76-e4d00faba4ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046635331 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3046635331
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2677539611
Short name T487
Test name
Test status
Simulation time 52141874 ps
CPU time 1 seconds
Started Mar 12 01:45:10 PM PDT 24
Finished Mar 12 01:45:11 PM PDT 24
Peak memory 198008 kb
Host smart-c4b5840c-b5f6-47f1-b27d-005299925d69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677539611 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2677539611
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.321184226
Short name T393
Test name
Test status
Simulation time 55039643671 ps
CPU time 513.81 seconds
Started Mar 12 01:45:08 PM PDT 24
Finished Mar 12 01:53:42 PM PDT 24
Peak memory 200028 kb
Host smart-3022609f-c54c-4bb1-90e1-3bdfdf02dabd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321184226 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.321184226
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.860661007
Short name T445
Test name
Test status
Simulation time 1055604058 ps
CPU time 33.29 seconds
Started Mar 12 01:45:08 PM PDT 24
Finished Mar 12 01:45:42 PM PDT 24
Peak memory 199884 kb
Host smart-2b32bce6-5269-471d-b55c-b2d185c644f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860661007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.860661007
Directory /workspace/9.hmac_wipe_secret/latest
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