Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15705595	1			T1	29		T2	8436		T3	18496
all_values[1]	15705595	1			T1	29		T2	8436		T3	18496
all_values[2]	15705595	1			T1	29		T2	8436		T3	18496

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94642

1

T2

167

T3

1678

T20

4

auto[1]

47022143

1

T1

87

T2

25141

T3

53810

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44341905

1

T1

83

T2

25267

T3

45036

auto[1]

2774880

1

T1

4

T2

41

T3

10452

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	36566	1			T3	1676		T6	504		T21	64
all_values[0]	auto[0]	auto[1]	503	1			T3	2		T6	12		T21	11
all_values[0]	auto[1]	auto[0]	15615779	1			T1	25		T2	8395		T3	16804
all_values[0]	auto[1]	auto[1]	52747	1			T1	4		T2	41		T3	14
all_values[1]	auto[0]	auto[0]	31757	1			T20	4		T6	780		T21	91
all_values[1]	auto[0]	auto[1]	224	1			T6	4		T21	8		T17	3
all_values[1]	auto[1]	auto[0]	15672883	1			T1	29		T2	8436		T3	18496
all_values[1]	auto[1]	auto[1]	731	1			T6	3		T21	1		T17	3
all_values[2]	auto[0]	auto[0]	22485	1			T2	167		T6	13		T58	2
all_values[2]	auto[0]	auto[1]	3107	1			T6	6		T21	1		T17	4
all_values[2]	auto[1]	auto[0]	12962435	1			T1	29		T2	8269		T3	8060
all_values[2]	auto[1]	auto[1]	2717568	1			T3	10436		T18	11		T19	8