Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7535194

1

T1

24

T2

4099

T3

5594

auto[1]

2928563

1

T2

4269

T3

1295

T4

83

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3016515

1

T2

3674

T3

1956

T4

72

auto[1]

7447242

1

T1

24

T2

4694

T3

4933

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6651339

1

T2

6058

T3

3263

T4

73

auto[1]

3812418

1

T1

24

T2

2310

T3

3626

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6714047	1			T1	15		T2	7713		T3	6723
fifo_depth[1]	491062	1			T1	1		T2	394		T3	124
fifo_depth[2]	405750	1			T1	5		T2	177		T3	28
fifo_depth[3]	331708	1			T1	1		T2	59		T3	12
fifo_depth[4]	287122	1			T1	1		T2	22		T3	1
fifo_depth[5]	256191	1			T1	1		T2	3		T3	1
fifo_depth[6]	242384	1			T4	4		T5	562		T8	4
fifo_depth[7]	212526	1			T4	3		T5	480		T8	1
fifo_depth[8]	193703	1			T4	3		T5	432		T7	243
fifo_depth[9]	133153	1			T4	2		T5	300		T7	163
fifo_depth[10]	102884	1			T4	4		T5	201		T7	91
fifo_depth[11]	64555	1			T5	121		T7	60		T21	537
fifo_depth[12]	66281	1			T5	60		T7	34		T21	338
fifo_depth[13]	34661	1			T4	2		T5	24		T7	16
fifo_depth[14]	46430	1			T4	3		T5	11		T7	3
fifo_depth[15]	30251	1			T5	5		T7	1		T21	153
fifo_depth[16]	107785	1			T5	3		T21	767		T114	3

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3916941

1

T1

9

T2

655

T3

166

auto[1]

6546816

1

T1

15

T2

7713

T3

6723

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10296526

1

T1

24

T2

8368

T3

6889

auto[1]

167231

1

T20

4

T21

1554

T51

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

263966

1

T2

85

T8

3

T20

7

auto[0]

auto[0]

auto[0]

auto[1]

286850

1

T2

152

T3

9

T8

78

auto[0]

auto[0]

auto[1]

auto[0]

1127488

1

T2

64

T3

16

T8

159

auto[0]

auto[0]

auto[1]

auto[1]

259765

1

T2

169

T8

1

T20

7

auto[0]

auto[1]

auto[0]

auto[0]

523505

1

T2

51

T3

24

T4

11

auto[0]

auto[1]

auto[0]

auto[1]

481042

1

T2

5

T3

57

T4

14

auto[0]

auto[1]

auto[1]

auto[0]

503993

1

T1

9

T2

116

T3

32

auto[0]

auto[1]

auto[1]

auto[1]

470332

1

T2

13

T3

28

T4

19

auto[1]

auto[0]

auto[0]

auto[0]

268425

1

T2

1051

T3

2

T4

17

auto[1]

auto[0]

auto[0]

auto[1]

269670

1

T2

1742

T3

191

T4

29

auto[1]

auto[0]

auto[1]

auto[0]

3908814

1

T2

769

T3

3043

T4

7

auto[1]

auto[0]

auto[1]

auto[1]

266361

1

T2

2026

T3

2

T4

20

auto[1]

auto[1]

auto[0]

auto[0]

462194

1

T2

569

T3

965

T4

1

auto[1]

auto[1]

auto[0]

auto[1]

460863

1

T2

19

T3

708

T5

442

auto[1]

auto[1]

auto[1]

auto[0]

476809

1

T1

15

T2

1394

T3

1512

auto[1]

auto[1]

auto[1]

auto[1]

433680

1

T2

143

T3

300

T4

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

512546

1

T2

1136

T3

2

T4

17

auto[0]

auto[0]

auto[0]

auto[1]

536790

1

T2

1894

T3

200

T4

29

auto[0]

auto[0]

auto[1]

auto[0]

5015439

1

T2

833

T3

3059

T4

7

auto[0]

auto[0]

auto[1]

auto[1]

504404

1

T2

2195

T3

2

T4

20

auto[0]

auto[1]

auto[0]

auto[0]

965336

1

T2

620

T3

989

T4

12

auto[0]

auto[1]

auto[0]

auto[1]

921895

1

T2

24

T3

765

T4

14

auto[0]

auto[1]

auto[1]

auto[0]

957906

1

T1

24

T2

1510

T3

1544

auto[0]

auto[1]

auto[1]

auto[1]

882210

1

T2

156

T3

328

T4

20

auto[1]

auto[0]

auto[0]

auto[0]

19845

1

T21

137

T116

54

T52

1385

auto[1]

auto[0]

auto[0]

auto[1]

19730

1

T20

1

T21

278

T51

1

auto[1]

auto[0]

auto[1]

auto[0]

20863

1

T21

8

T51

1

T116

355

auto[1]

auto[0]

auto[1]

auto[1]

21722

1

T21

15

T116

265

T9

124

auto[1]

auto[1]

auto[0]

auto[0]

20363

1

T21

598

T52

320

T128

1

auto[1]

auto[1]

auto[0]

auto[1]

20010

1

T20

1

T21

3

T116

7

auto[1]

auto[1]

auto[1]

auto[0]

22896

1

T20

1

T21

386

T116

131

auto[1]

auto[1]

auto[1]

auto[1]

21802

1

T20

1

T21

129

T116

91

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	288270	1			T2	1051		T3	2		T4	17
fifo_depth[0]	auto[0]	auto[0]	auto[1]	289400	1			T2	1742		T3	191		T4	29
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3929677	1			T2	769		T3	3043		T4	7
fifo_depth[0]	auto[0]	auto[1]	auto[1]	288083	1			T2	2026		T3	2		T4	20
fifo_depth[0]	auto[1]	auto[0]	auto[0]	482557	1			T2	569		T3	965		T4	1
fifo_depth[0]	auto[1]	auto[0]	auto[1]	480873	1			T2	19		T3	708		T5	442
fifo_depth[0]	auto[1]	auto[1]	auto[0]	499705	1			T1	15		T2	1394		T3	1512
fifo_depth[0]	auto[1]	auto[1]	auto[1]	455482	1			T2	143		T3	300		T4	1
fifo_depth[1]	auto[0]	auto[0]	auto[0]	19812	1			T2	45		T8	1		T6	332
fifo_depth[1]	auto[0]	auto[0]	auto[1]	20271	1			T2	83		T3	8		T8	40
fifo_depth[1]	auto[0]	auto[1]	auto[0]	234266	1			T2	41		T3	16		T8	77
fifo_depth[1]	auto[0]	auto[1]	auto[1]	20918	1			T2	97		T8	1		T6	246
fifo_depth[1]	auto[1]	auto[0]	auto[0]	49860	1			T2	35		T3	17		T4	1
fifo_depth[1]	auto[1]	auto[0]	auto[1]	48622	1			T2	2		T3	38		T4	4
fifo_depth[1]	auto[1]	auto[1]	auto[0]	51016	1			T1	1		T2	83		T3	27
fifo_depth[1]	auto[1]	auto[1]	auto[1]	46297	1			T2	8		T3	18		T4	3
fifo_depth[2]	auto[0]	auto[0]	auto[0]	16561	1			T2	26		T6	146		T58	9
fifo_depth[2]	auto[0]	auto[0]	auto[1]	16630	1			T2	49		T3	1		T8	21
fifo_depth[2]	auto[0]	auto[1]	auto[0]	179143	1			T2	15		T8	44		T57	182
fifo_depth[2]	auto[0]	auto[1]	auto[1]	17708	1			T2	55		T6	105		T7	41
fifo_depth[2]	auto[1]	auto[0]	auto[0]	44689	1			T2	9		T3	5		T4	1
fifo_depth[2]	auto[1]	auto[0]	auto[1]	43821	1			T2	2		T3	13		T4	2
fifo_depth[2]	auto[1]	auto[1]	auto[0]	45825	1			T1	5		T2	19		T3	5
fifo_depth[2]	auto[1]	auto[1]	auto[1]	41373	1			T2	2		T3	4		T4	4
fifo_depth[3]	auto[0]	auto[0]	auto[0]	13068	1			T2	9		T8	1		T6	45
fifo_depth[3]	auto[0]	auto[0]	auto[1]	13388	1			T2	12		T8	11		T6	43
fifo_depth[3]	auto[0]	auto[1]	auto[0]	136808	1			T2	7		T8	26		T57	37
fifo_depth[3]	auto[0]	auto[1]	auto[1]	14304	1			T2	11		T6	28		T7	27
fifo_depth[3]	auto[1]	auto[0]	auto[0]	39809	1			T2	6		T3	1		T4	2
fifo_depth[3]	auto[1]	auto[0]	auto[1]	38207	1			T3	5		T4	3		T5	86
fifo_depth[3]	auto[1]	auto[1]	auto[0]	39948	1			T1	1		T2	12		T5	201
fifo_depth[3]	auto[1]	auto[1]	auto[1]	36176	1			T2	2		T3	6		T4	1
fifo_depth[4]	auto[0]	auto[0]	auto[0]	12273	1			T2	5		T8	1		T6	12
fifo_depth[4]	auto[0]	auto[0]	auto[1]	12734	1			T2	7		T8	4		T6	6
fifo_depth[4]	auto[0]	auto[1]	auto[0]	100875	1			T2	1		T8	7		T57	4
fifo_depth[4]	auto[0]	auto[1]	auto[1]	13578	1			T2	5		T6	9		T7	36
fifo_depth[4]	auto[1]	auto[0]	auto[0]	38457	1			T2	1		T3	1		T4	1
fifo_depth[4]	auto[1]	auto[0]	auto[1]	36301	1			T2	1		T4	1		T5	94
fifo_depth[4]	auto[1]	auto[1]	auto[0]	38014	1			T1	1		T2	1		T5	195
fifo_depth[4]	auto[1]	auto[1]	auto[1]	34890	1			T2	1		T4	3		T5	215
fifo_depth[5]	auto[0]	auto[0]	auto[0]	10512	1			T6	3		T21	137		T83	1
fifo_depth[5]	auto[0]	auto[0]	auto[1]	10781	1			T2	1		T8	2		T6	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	83884	1			T8	4		T57	1		T6	3
fifo_depth[5]	auto[0]	auto[1]	auto[1]	12201	1			T2	1		T6	1		T7	38
fifo_depth[5]	auto[1]	auto[0]	auto[0]	35985	1			T5	36		T8	6		T7	25
fifo_depth[5]	auto[1]	auto[0]	auto[1]	34028	1			T3	1		T4	1		T5	96
fifo_depth[5]	auto[1]	auto[1]	auto[0]	36068	1			T1	1		T2	1		T5	205
fifo_depth[5]	auto[1]	auto[1]	auto[1]	32732	1			T5	206		T8	3		T6	3
fifo_depth[6]	auto[0]	auto[0]	auto[0]	10473	1			T21	131		T129	1		T130	11
fifo_depth[6]	auto[0]	auto[0]	auto[1]	11519	1			T7	90		T21	42		T46	39
fifo_depth[6]	auto[0]	auto[1]	auto[0]	72365	1			T8	1		T7	37		T21	1141
fifo_depth[6]	auto[0]	auto[1]	auto[1]	11990	1			T7	35		T21	43		T46	116
fifo_depth[6]	auto[1]	auto[0]	auto[0]	35365	1			T4	1		T5	37		T7	17
fifo_depth[6]	auto[1]	auto[0]	auto[1]	33089	1			T4	1		T5	80		T21	210
fifo_depth[6]	auto[1]	auto[1]	auto[0]	35352	1			T5	217		T8	2		T7	135
fifo_depth[6]	auto[1]	auto[1]	auto[1]	32231	1			T4	2		T5	228		T8	1
fifo_depth[7]	auto[0]	auto[0]	auto[0]	9329	1			T21	173		T130	12		T116	31
fifo_depth[7]	auto[0]	auto[0]	auto[1]	10184	1			T7	84		T21	42		T46	28
fifo_depth[7]	auto[0]	auto[1]	auto[0]	57881	1			T7	33		T21	852		T82	759
fifo_depth[7]	auto[0]	auto[1]	auto[1]	10674	1			T7	30		T21	26		T46	62
fifo_depth[7]	auto[1]	auto[0]	auto[0]	32459	1			T5	37		T30	1		T7	14
fifo_depth[7]	auto[1]	auto[0]	auto[1]	30150	1			T4	1		T5	95		T21	191
fifo_depth[7]	auto[1]	auto[1]	auto[0]	32663	1			T4	1		T5	184		T8	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	29186	1			T4	1		T5	164		T21	214
fifo_depth[8]	auto[0]	auto[0]	auto[0]	10070	1			T21	154		T130	4		T116	261
fifo_depth[8]	auto[0]	auto[0]	auto[1]	11385	1			T7	70		T21	40		T46	20
fifo_depth[8]	auto[0]	auto[1]	auto[0]	46057	1			T7	20		T21	638		T82	549
fifo_depth[8]	auto[0]	auto[1]	auto[1]	10937	1			T7	27		T21	22		T46	27
fifo_depth[8]	auto[1]	auto[0]	auto[0]	30111	1			T4	2		T5	28		T7	16
fifo_depth[8]	auto[1]	auto[0]	auto[1]	28131	1			T4	1		T5	74		T21	141
fifo_depth[8]	auto[1]	auto[1]	auto[0]	29596	1			T5	169		T7	110		T21	139
fifo_depth[8]	auto[1]	auto[1]	auto[1]	27416	1			T5	161		T21	164		T114	109
fifo_depth[9]	auto[0]	auto[0]	auto[0]	6342	1			T21	128		T130	4		T116	45
fifo_depth[9]	auto[0]	auto[0]	auto[1]	7539	1			T7	48		T21	21		T46	19
fifo_depth[9]	auto[0]	auto[1]	auto[0]	29875	1			T7	13		T21	430		T82	383
fifo_depth[9]	auto[0]	auto[1]	auto[1]	7699	1			T7	22		T21	19		T46	8
fifo_depth[9]	auto[1]	auto[0]	auto[0]	21210	1			T5	16		T7	11		T21	117
fifo_depth[9]	auto[1]	auto[0]	auto[1]	19660	1			T5	50		T21	114		T114	82
fifo_depth[9]	auto[1]	auto[1]	auto[0]	21335	1			T4	1		T5	132		T7	69
fifo_depth[9]	auto[1]	auto[1]	auto[1]	19493	1			T4	1		T5	102		T21	126
fifo_depth[10]	auto[0]	auto[0]	auto[0]	5924	1			T21	105		T130	1		T116	32
fifo_depth[10]	auto[0]	auto[0]	auto[1]	7473	1			T7	22		T21	21		T46	10
fifo_depth[10]	auto[0]	auto[1]	auto[0]	21034	1			T7	11		T21	275		T82	243
fifo_depth[10]	auto[0]	auto[1]	auto[1]	6392	1			T7	8		T21	8		T46	3
fifo_depth[10]	auto[1]	auto[0]	auto[0]	16367	1			T4	1		T5	11		T7	5
fifo_depth[10]	auto[1]	auto[0]	auto[1]	15026	1			T5	33		T21	72		T114	56
fifo_depth[10]	auto[1]	auto[1]	auto[0]	16114	1			T4	2		T5	90		T7	45
fifo_depth[10]	auto[1]	auto[1]	auto[1]	14554	1			T4	1		T5	67		T21	83
fifo_depth[11]	auto[0]	auto[0]	auto[0]	4012	1			T21	97		T130	2		T116	34
fifo_depth[11]	auto[0]	auto[0]	auto[1]	4994	1			T7	23		T21	16		T46	6
fifo_depth[11]	auto[0]	auto[1]	auto[0]	12716	1			T7	4		T21	211		T82	140
fifo_depth[11]	auto[0]	auto[1]	auto[1]	4558	1			T7	6		T21	11		T114	25
fifo_depth[11]	auto[1]	auto[0]	auto[0]	10199	1			T5	9		T7	5		T21	44
fifo_depth[11]	auto[1]	auto[0]	auto[1]	9082	1			T5	21		T21	55		T114	43
fifo_depth[11]	auto[1]	auto[1]	auto[0]	9792	1			T5	53		T7	22		T21	48
fifo_depth[11]	auto[1]	auto[1]	auto[1]	9202	1			T5	38		T21	55		T114	32
fifo_depth[12]	auto[0]	auto[0]	auto[0]	5343	1			T21	82		T130	3		T116	355
fifo_depth[12]	auto[0]	auto[0]	auto[1]	8582	1			T7	11		T21	8		T46	3
fifo_depth[12]	auto[0]	auto[1]	auto[0]	10924	1			T7	3		T21	123		T82	72
fifo_depth[12]	auto[0]	auto[1]	auto[1]	5627	1			T7	3		T21	9		T114	15
fifo_depth[12]	auto[1]	auto[0]	auto[0]	10116	1			T5	7		T7	2		T21	22
fifo_depth[12]	auto[1]	auto[0]	auto[1]	7816	1			T5	8		T21	25		T114	20
fifo_depth[12]	auto[1]	auto[1]	auto[0]	8426	1			T5	24		T7	15		T21	33
fifo_depth[12]	auto[1]	auto[1]	auto[1]	9447	1			T5	21		T21	36		T114	11
fifo_depth[13]	auto[0]	auto[0]	auto[0]	3156	1			T21	82		T130	1		T116	26
fifo_depth[13]	auto[0]	auto[0]	auto[1]	4727	1			T7	6		T21	4		T46	2
fifo_depth[13]	auto[0]	auto[1]	auto[0]	5381	1			T7	1		T21	70		T82	18
fifo_depth[13]	auto[0]	auto[1]	auto[1]	3225	1			T21	11		T114	5		T116	50
fifo_depth[13]	auto[1]	auto[0]	auto[0]	4993	1			T4	1		T7	2		T21	12
fifo_depth[13]	auto[1]	auto[0]	auto[1]	4019	1			T5	4		T21	8		T114	4
fifo_depth[13]	auto[1]	auto[1]	auto[0]	4499	1			T5	10		T7	7		T21	25
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4661	1			T4	1		T5	10		T21	28
fifo_depth[14]	auto[0]	auto[0]	auto[0]	4473	1			T21	77		T116	84		T131	2
fifo_depth[14]	auto[0]	auto[0]	auto[1]	7546	1			T7	1		T21	5		T114	1
fifo_depth[14]	auto[0]	auto[1]	auto[0]	6233	1			T7	1		T21	48		T82	15
fifo_depth[14]	auto[0]	auto[1]	auto[1]	5101	1			T7	1		T21	7		T116	87
fifo_depth[14]	auto[1]	auto[0]	auto[0]	6662	1			T4	1		T21	2		T116	44
fifo_depth[14]	auto[1]	auto[0]	auto[1]	4762	1			T5	6		T21	5		T114	2
fifo_depth[14]	auto[1]	auto[1]	auto[0]	5774	1			T5	3		T21	25		T114	2
fifo_depth[14]	auto[1]	auto[1]	auto[1]	5879	1			T4	2		T5	2		T21	22
fifo_depth[15]	auto[0]	auto[0]	auto[0]	3291	1			T21	51		T116	23		T131	2
fifo_depth[15]	auto[0]	auto[0]	auto[1]	4641	1			T7	1		T116	84		T131	1
fifo_depth[15]	auto[0]	auto[1]	auto[0]	4091	1			T21	47		T82	3		T116	60
fifo_depth[15]	auto[0]	auto[1]	auto[1]	3843	1			T21	3		T116	69		T9	24
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3829	1			T21	4		T114	1		T130	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	3047	1			T5	2		T114	1		T116	77
fifo_depth[15]	auto[1]	auto[1]	auto[0]	3717	1			T5	1		T21	14		T130	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	3792	1			T5	2		T21	34		T114	1
fifo_depth[16]	auto[0]	auto[0]	auto[0]	11972	1			T21	7		T116	279		T131	1
fifo_depth[16]	auto[0]	auto[0]	auto[1]	14699	1			T21	4		T116	37		T131	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	12613	1			T21	40		T116	251		T131	1
fifo_depth[16]	auto[0]	auto[1]	auto[1]	12136	1			T21	1		T116	123		T9	73
fifo_depth[16]	auto[1]	auto[0]	auto[0]	15174	1			T21	29		T114	1		T116	45
fifo_depth[16]	auto[1]	auto[0]	auto[1]	13895	1			T5	3		T21	1		T114	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	13897	1			T21	570		T114	1		T130	2
fifo_depth[16]	auto[1]	auto[1]	auto[1]	13399	1			T21	115		T116	2		T9	41