Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15705595	1			T1	29		T2	8436		T3	18496
all_pins[1]	15705595	1			T1	29		T2	8436		T3	18496
all_pins[2]	15705595	1			T1	29		T2	8436		T3	18496

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44344233	1			T1	83		T2	25267		T3	45037
values[0x1]	2772552	1			T1	4		T2	41		T3	10451
transitions[0x0=>0x1]	2772361	1			T1	4		T2	41		T3	10451
transitions[0x1=>0x0]	2772385	1			T1	4		T2	41		T3	10451

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15651369	1			T1	25		T2	8395		T3	18481
all_pins[0]	values[0x1]	54226	1			T1	4		T2	41		T3	15
all_pins[0]	transitions[0x0=>0x1]	54148	1			T1	4		T2	41		T3	15
all_pins[0]	transitions[0x1=>0x0]	2717514	1			T3	10436		T18	11		T19	8
all_pins[1]	values[0x0]	15704837	1			T1	29		T2	8436		T3	18496
all_pins[1]	values[0x1]	758	1			T6	3		T21	1		T17	3
all_pins[1]	transitions[0x0=>0x1]	704	1			T6	1		T21	1		T17	3
all_pins[1]	transitions[0x1=>0x0]	54172	1			T1	4		T2	41		T3	15
all_pins[2]	values[0x0]	12988027	1			T1	29		T2	8436		T3	8060
all_pins[2]	values[0x1]	2717568	1			T3	10436		T18	11		T19	8
all_pins[2]	transitions[0x0=>0x1]	2717509	1			T3	10436		T18	11		T19	8
all_pins[2]	transitions[0x1=>0x0]	699	1			T6	2		T21	1		T17	2