Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1081 1 T6 14 T21 18 T17 21
all_values[1] 1081 1 T6 14 T21 18 T17 21
all_values[2] 1081 1 T6 14 T21 18 T17 21


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1605 1 T6 14 T21 30 T17 34
auto[1] 1638 1 T6 28 T21 24 T17 29


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1172 1 T6 12 T21 20 T17 28
auto[1] 2071 1 T6 30 T21 34 T17 35


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1827 1 T6 23 T21 30 T17 42
auto[1] 1416 1 T6 19 T21 24 T17 21


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 209 1 T6 3 T21 3 T17 5
all_values[0] auto[0] auto[0] auto[1] 103 1 T21 3 T17 2 T117 2
all_values[0] auto[0] auto[1] auto[0] 218 1 T6 5 T21 3 T17 4
all_values[0] auto[0] auto[1] auto[1] 88 1 T6 1 T17 2 T9 1
all_values[0] auto[1] auto[0] auto[1] 239 1 T6 3 T21 8 T17 3
all_values[0] auto[1] auto[1] auto[1] 224 1 T6 2 T21 1 T17 5
all_values[1] auto[0] auto[0] auto[0] 172 1 T17 9 T9 4 T52 2
all_values[1] auto[0] auto[0] auto[1] 120 1 T6 2 T21 2 T17 2
all_values[1] auto[0] auto[1] auto[0] 177 1 T6 3 T21 5 T17 3
all_values[1] auto[0] auto[1] auto[1] 145 1 T6 2 T21 2 T17 1
all_values[1] auto[1] auto[0] auto[1] 213 1 T6 1 T21 7 T17 2
all_values[1] auto[1] auto[1] auto[1] 254 1 T6 6 T21 2 T17 4
all_values[2] auto[0] auto[0] auto[0] 208 1 T21 5 T17 4 T117 1
all_values[2] auto[0] auto[0] auto[1] 96 1 T6 3 T21 1 T17 2
all_values[2] auto[0] auto[1] auto[0] 188 1 T6 1 T21 4 T17 3
all_values[2] auto[0] auto[1] auto[1] 103 1 T6 3 T21 2 T17 5
all_values[2] auto[1] auto[0] auto[1] 245 1 T6 2 T21 1 T17 5
all_values[2] auto[1] auto[1] auto[1] 241 1 T6 5 T21 5 T17 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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