Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.39 92.80 85.92 100.00 76.32 88.15 99.49 69.08


Total test records in report: 741
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T533 /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.3846768690 Mar 14 12:43:26 PM PDT 24 Mar 14 12:49:36 PM PDT 24 24920169662 ps
T534 /workspace/coverage/default/39.hmac_test_sha_vectors.3969130077 Mar 14 12:42:35 PM PDT 24 Mar 14 12:49:25 PM PDT 24 42029820218 ps
T535 /workspace/coverage/default/35.hmac_test_sha_vectors.94955944 Mar 14 12:42:29 PM PDT 24 Mar 14 12:50:22 PM PDT 24 111517396543 ps
T536 /workspace/coverage/default/16.hmac_wipe_secret.777450904 Mar 14 12:41:12 PM PDT 24 Mar 14 12:42:18 PM PDT 24 2730661223 ps
T537 /workspace/coverage/default/17.hmac_wipe_secret.4082930380 Mar 14 12:41:10 PM PDT 24 Mar 14 12:41:28 PM PDT 24 4032140177 ps
T538 /workspace/coverage/default/38.hmac_test_hmac_vectors.4068624520 Mar 14 12:42:39 PM PDT 24 Mar 14 12:42:40 PM PDT 24 187172708 ps
T539 /workspace/coverage/default/45.hmac_smoke.2400059606 Mar 14 12:42:54 PM PDT 24 Mar 14 12:42:57 PM PDT 24 184840003 ps
T80 /workspace/coverage/default/18.hmac_stress_all.4200017749 Mar 14 12:41:18 PM PDT 24 Mar 14 12:55:18 PM PDT 24 57457164916 ps
T540 /workspace/coverage/default/20.hmac_alert_test.3291844071 Mar 14 12:41:28 PM PDT 24 Mar 14 12:41:29 PM PDT 24 12189910 ps
T541 /workspace/coverage/default/47.hmac_error.709644339 Mar 14 12:43:09 PM PDT 24 Mar 14 12:43:54 PM PDT 24 2470158019 ps
T542 /workspace/coverage/default/12.hmac_error.3268211787 Mar 14 12:40:50 PM PDT 24 Mar 14 12:43:37 PM PDT 24 11963227497 ps
T543 /workspace/coverage/default/35.hmac_alert_test.1759467747 Mar 14 12:42:26 PM PDT 24 Mar 14 12:42:27 PM PDT 24 36364066 ps
T544 /workspace/coverage/default/32.hmac_wipe_secret.3897238753 Mar 14 12:42:17 PM PDT 24 Mar 14 12:42:45 PM PDT 24 1495764808 ps
T545 /workspace/coverage/default/27.hmac_alert_test.1083634998 Mar 14 12:41:59 PM PDT 24 Mar 14 12:42:00 PM PDT 24 41252467 ps
T546 /workspace/coverage/default/26.hmac_alert_test.2306104896 Mar 14 12:41:58 PM PDT 24 Mar 14 12:41:58 PM PDT 24 61541745 ps
T547 /workspace/coverage/default/21.hmac_smoke.853658189 Mar 14 12:41:28 PM PDT 24 Mar 14 12:41:34 PM PDT 24 167369556 ps
T548 /workspace/coverage/default/26.hmac_back_pressure.2176259723 Mar 14 12:41:46 PM PDT 24 Mar 14 12:42:27 PM PDT 24 4519949080 ps
T549 /workspace/coverage/default/38.hmac_test_sha_vectors.3451569262 Mar 14 12:42:35 PM PDT 24 Mar 14 12:51:22 PM PDT 24 84454081576 ps
T550 /workspace/coverage/default/9.hmac_back_pressure.2546484284 Mar 14 12:40:25 PM PDT 24 Mar 14 12:41:27 PM PDT 24 1588252303 ps
T551 /workspace/coverage/default/49.hmac_burst_wr.3871119837 Mar 14 12:43:10 PM PDT 24 Mar 14 12:43:46 PM PDT 24 7642454878 ps
T552 /workspace/coverage/default/40.hmac_alert_test.445272999 Mar 14 12:42:47 PM PDT 24 Mar 14 12:42:48 PM PDT 24 87990363 ps
T34 /workspace/coverage/default/3.hmac_sec_cm.536627417 Mar 14 12:40:06 PM PDT 24 Mar 14 12:40:07 PM PDT 24 84233545 ps
T553 /workspace/coverage/default/32.hmac_long_msg.306952232 Mar 14 12:42:11 PM PDT 24 Mar 14 12:42:31 PM PDT 24 5445908115 ps
T554 /workspace/coverage/default/17.hmac_smoke.2226513596 Mar 14 12:41:10 PM PDT 24 Mar 14 12:41:11 PM PDT 24 81472529 ps
T555 /workspace/coverage/default/7.hmac_long_msg.4164123721 Mar 14 12:40:15 PM PDT 24 Mar 14 12:40:29 PM PDT 24 968117795 ps
T556 /workspace/coverage/default/1.hmac_datapath_stress.2054966317 Mar 14 12:39:29 PM PDT 24 Mar 14 12:40:21 PM PDT 24 2076684612 ps
T557 /workspace/coverage/default/5.hmac_smoke.2244952637 Mar 14 12:40:05 PM PDT 24 Mar 14 12:40:10 PM PDT 24 1491349554 ps
T558 /workspace/coverage/default/11.hmac_alert_test.942995260 Mar 14 12:40:40 PM PDT 24 Mar 14 12:40:41 PM PDT 24 17818385 ps
T559 /workspace/coverage/default/10.hmac_error.2501535624 Mar 14 12:40:32 PM PDT 24 Mar 14 12:40:51 PM PDT 24 562475099 ps
T560 /workspace/coverage/default/37.hmac_test_hmac_vectors.4179766360 Mar 14 12:42:29 PM PDT 24 Mar 14 12:42:32 PM PDT 24 219107537 ps
T561 /workspace/coverage/default/24.hmac_alert_test.446155115 Mar 14 12:41:51 PM PDT 24 Mar 14 12:41:52 PM PDT 24 14941224 ps
T562 /workspace/coverage/default/45.hmac_back_pressure.1334587368 Mar 14 12:43:01 PM PDT 24 Mar 14 12:43:21 PM PDT 24 2001753093 ps
T563 /workspace/coverage/default/26.hmac_wipe_secret.2427857481 Mar 14 12:41:54 PM PDT 24 Mar 14 12:41:58 PM PDT 24 217584844 ps
T564 /workspace/coverage/default/20.hmac_test_hmac_vectors.1805625089 Mar 14 12:41:26 PM PDT 24 Mar 14 12:41:27 PM PDT 24 49755961 ps
T565 /workspace/coverage/default/48.hmac_smoke.1836205736 Mar 14 12:43:11 PM PDT 24 Mar 14 12:43:12 PM PDT 24 210953003 ps
T566 /workspace/coverage/default/29.hmac_long_msg.2647455082 Mar 14 12:41:58 PM PDT 24 Mar 14 12:43:05 PM PDT 24 15276088694 ps
T567 /workspace/coverage/default/25.hmac_test_sha_vectors.2112952248 Mar 14 12:41:44 PM PDT 24 Mar 14 12:50:01 PM PDT 24 36521766144 ps
T568 /workspace/coverage/default/42.hmac_test_hmac_vectors.2904961218 Mar 14 12:42:47 PM PDT 24 Mar 14 12:42:49 PM PDT 24 197572734 ps
T569 /workspace/coverage/default/4.hmac_error.1472316261 Mar 14 12:40:05 PM PDT 24 Mar 14 12:41:15 PM PDT 24 1345248576 ps
T570 /workspace/coverage/default/38.hmac_smoke.1350840972 Mar 14 12:42:40 PM PDT 24 Mar 14 12:42:45 PM PDT 24 191532427 ps
T571 /workspace/coverage/default/0.hmac_wipe_secret.3780750342 Mar 14 12:39:23 PM PDT 24 Mar 14 12:40:19 PM PDT 24 4937215384 ps
T572 /workspace/coverage/default/19.hmac_wipe_secret.3174465752 Mar 14 12:41:19 PM PDT 24 Mar 14 12:41:41 PM PDT 24 19383221523 ps
T573 /workspace/coverage/default/4.hmac_stress_all.3800554342 Mar 14 12:40:07 PM PDT 24 Mar 14 12:41:50 PM PDT 24 35038231263 ps
T574 /workspace/coverage/default/3.hmac_stress_all.1428345471 Mar 14 12:40:04 PM PDT 24 Mar 14 12:59:30 PM PDT 24 58578916595 ps
T575 /workspace/coverage/default/49.hmac_long_msg.3586412927 Mar 14 12:43:11 PM PDT 24 Mar 14 12:44:48 PM PDT 24 4977373993 ps
T576 /workspace/coverage/default/24.hmac_datapath_stress.2601847065 Mar 14 12:41:38 PM PDT 24 Mar 14 12:43:26 PM PDT 24 1923305336 ps
T577 /workspace/coverage/default/16.hmac_smoke.3384961368 Mar 14 12:40:59 PM PDT 24 Mar 14 12:41:05 PM PDT 24 551339999 ps
T578 /workspace/coverage/default/48.hmac_back_pressure.2310708290 Mar 14 12:43:08 PM PDT 24 Mar 14 12:43:26 PM PDT 24 1059696342 ps
T579 /workspace/coverage/default/47.hmac_burst_wr.266703432 Mar 14 12:43:11 PM PDT 24 Mar 14 12:43:26 PM PDT 24 7926831698 ps
T580 /workspace/coverage/default/8.hmac_wipe_secret.1949382887 Mar 14 12:40:14 PM PDT 24 Mar 14 12:40:44 PM PDT 24 2878374381 ps
T581 /workspace/coverage/default/33.hmac_datapath_stress.2584877009 Mar 14 12:42:17 PM PDT 24 Mar 14 12:44:19 PM PDT 24 2096785140 ps
T582 /workspace/coverage/default/4.hmac_smoke.4006570604 Mar 14 12:40:07 PM PDT 24 Mar 14 12:40:14 PM PDT 24 498329153 ps
T583 /workspace/coverage/default/9.hmac_error.1656846676 Mar 14 12:40:24 PM PDT 24 Mar 14 12:41:23 PM PDT 24 4458782495 ps
T584 /workspace/coverage/default/16.hmac_test_sha_vectors.6147183 Mar 14 12:41:08 PM PDT 24 Mar 14 12:49:20 PM PDT 24 115398947131 ps
T81 /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.791779183 Mar 14 12:39:42 PM PDT 24 Mar 14 12:42:16 PM PDT 24 20453536071 ps
T585 /workspace/coverage/default/14.hmac_back_pressure.3188755063 Mar 14 12:40:54 PM PDT 24 Mar 14 12:41:53 PM PDT 24 1566975237 ps
T586 /workspace/coverage/default/8.hmac_long_msg.860874519 Mar 14 12:40:15 PM PDT 24 Mar 14 12:42:43 PM PDT 24 11000556795 ps
T587 /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.1268339852 Mar 14 12:43:29 PM PDT 24 Mar 14 12:51:34 PM PDT 24 13167749734 ps
T588 /workspace/coverage/default/18.hmac_alert_test.190360808 Mar 14 12:41:20 PM PDT 24 Mar 14 12:41:21 PM PDT 24 49332993 ps
T589 /workspace/coverage/default/38.hmac_error.3630809045 Mar 14 12:42:37 PM PDT 24 Mar 14 12:42:40 PM PDT 24 492662786 ps
T590 /workspace/coverage/default/6.hmac_back_pressure.3659630913 Mar 14 12:40:05 PM PDT 24 Mar 14 12:40:49 PM PDT 24 6302758796 ps
T591 /workspace/coverage/default/10.hmac_wipe_secret.1236862095 Mar 14 12:40:34 PM PDT 24 Mar 14 12:41:38 PM PDT 24 4799017501 ps
T592 /workspace/coverage/default/15.hmac_smoke.2362509236 Mar 14 12:40:59 PM PDT 24 Mar 14 12:41:06 PM PDT 24 4089683051 ps
T593 /workspace/coverage/default/28.hmac_error.3434712823 Mar 14 12:42:00 PM PDT 24 Mar 14 12:43:00 PM PDT 24 3408548075 ps
T594 /workspace/coverage/default/8.hmac_test_sha_vectors.3508288402 Mar 14 12:40:25 PM PDT 24 Mar 14 12:48:44 PM PDT 24 38108675703 ps
T595 /workspace/coverage/default/35.hmac_burst_wr.310570517 Mar 14 12:42:28 PM PDT 24 Mar 14 12:42:43 PM PDT 24 628366928 ps
T596 /workspace/coverage/default/41.hmac_datapath_stress.1912495159 Mar 14 12:42:43 PM PDT 24 Mar 14 12:42:44 PM PDT 24 77864540 ps
T597 /workspace/coverage/default/37.hmac_alert_test.3581253383 Mar 14 12:42:28 PM PDT 24 Mar 14 12:42:29 PM PDT 24 22925506 ps
T598 /workspace/coverage/default/25.hmac_test_hmac_vectors.3354354576 Mar 14 12:41:51 PM PDT 24 Mar 14 12:41:52 PM PDT 24 377575486 ps
T599 /workspace/coverage/default/0.hmac_back_pressure.1431524803 Mar 14 12:39:23 PM PDT 24 Mar 14 12:39:48 PM PDT 24 641354821 ps
T600 /workspace/coverage/default/33.hmac_smoke.2564259791 Mar 14 12:42:17 PM PDT 24 Mar 14 12:42:19 PM PDT 24 372260124 ps
T601 /workspace/coverage/default/28.hmac_stress_all.233882854 Mar 14 12:41:58 PM PDT 24 Mar 14 12:52:46 PM PDT 24 36893322053 ps
T602 /workspace/coverage/default/44.hmac_wipe_secret.2346451403 Mar 14 12:42:55 PM PDT 24 Mar 14 12:43:57 PM PDT 24 14762573767 ps
T35 /workspace/coverage/default/0.hmac_sec_cm.66734920 Mar 14 12:39:31 PM PDT 24 Mar 14 12:39:32 PM PDT 24 461539838 ps
T603 /workspace/coverage/default/35.hmac_long_msg.2035171117 Mar 14 12:42:28 PM PDT 24 Mar 14 12:43:22 PM PDT 24 11025619143 ps
T604 /workspace/coverage/default/44.hmac_smoke.1255565966 Mar 14 12:42:54 PM PDT 24 Mar 14 12:42:56 PM PDT 24 533240104 ps
T62 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4214716136 Mar 14 12:25:52 PM PDT 24 Mar 14 12:25:53 PM PDT 24 20983288 ps
T63 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1905563813 Mar 14 12:25:41 PM PDT 24 Mar 14 12:25:47 PM PDT 24 342593085 ps
T605 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3984626386 Mar 14 12:25:45 PM PDT 24 Mar 14 12:25:46 PM PDT 24 29748873 ps
T606 /workspace/coverage/cover_reg_top/6.hmac_intr_test.104979701 Mar 14 12:25:30 PM PDT 24 Mar 14 12:25:31 PM PDT 24 44812953 ps
T607 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2896861252 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:47 PM PDT 24 28211563 ps
T64 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2836275072 Mar 14 12:25:29 PM PDT 24 Mar 14 12:25:31 PM PDT 24 48886395 ps
T59 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2369214051 Mar 14 12:25:42 PM PDT 24 Mar 14 12:25:46 PM PDT 24 897823860 ps
T608 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.125974354 Mar 14 12:25:55 PM PDT 24 Mar 14 12:25:56 PM PDT 24 224941301 ps
T609 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2709266227 Mar 14 12:25:34 PM PDT 24 Mar 14 12:26:02 PM PDT 24 1862074038 ps
T610 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3655233540 Mar 14 12:25:50 PM PDT 24 Mar 14 12:25:52 PM PDT 24 28165856 ps
T611 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2054476747 Mar 14 12:25:40 PM PDT 24 Mar 14 12:25:55 PM PDT 24 7519373463 ps
T612 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2553503582 Mar 14 12:26:12 PM PDT 24 Mar 14 12:26:13 PM PDT 24 12298041 ps
T93 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1562041012 Mar 14 12:25:34 PM PDT 24 Mar 14 12:25:35 PM PDT 24 19747977 ps
T60 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3247763959 Mar 14 12:25:44 PM PDT 24 Mar 14 12:25:46 PM PDT 24 100730797 ps
T613 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2680049629 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:03 PM PDT 24 39100376 ps
T614 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3057786344 Mar 14 12:25:42 PM PDT 24 Mar 14 12:25:44 PM PDT 24 181322986 ps
T615 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2015353424 Mar 14 12:25:55 PM PDT 24 Mar 14 12:25:56 PM PDT 24 16626141 ps
T616 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1118868209 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:55 PM PDT 24 13967988 ps
T94 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2339043302 Mar 14 12:25:52 PM PDT 24 Mar 14 12:25:53 PM PDT 24 43747652 ps
T617 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1236187220 Mar 14 12:25:55 PM PDT 24 Mar 14 12:25:56 PM PDT 24 16909368 ps
T618 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.828080210 Mar 14 12:25:31 PM PDT 24 Mar 14 12:25:33 PM PDT 24 239479535 ps
T619 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2021187684 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:44 PM PDT 24 80106226 ps
T620 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2893208461 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:47 PM PDT 24 13396400 ps
T621 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1436694851 Mar 14 12:25:41 PM PDT 24 Mar 14 12:25:44 PM PDT 24 121261124 ps
T622 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3890541517 Mar 14 12:25:55 PM PDT 24 Mar 14 12:25:56 PM PDT 24 30304646 ps
T623 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.486306205 Mar 14 12:25:49 PM PDT 24 Mar 14 12:25:51 PM PDT 24 266425483 ps
T624 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3992973537 Mar 14 12:22:02 PM PDT 24 Mar 14 12:22:03 PM PDT 24 151535646 ps
T625 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3284766723 Mar 14 12:25:45 PM PDT 24 Mar 14 12:25:46 PM PDT 24 11971937 ps
T626 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3334689225 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:34 PM PDT 24 34641835 ps
T627 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3172631305 Mar 14 12:25:36 PM PDT 24 Mar 14 12:25:37 PM PDT 24 24159130 ps
T628 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2937632674 Mar 14 12:23:42 PM PDT 24 Mar 14 12:23:43 PM PDT 24 180213354 ps
T629 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2857026041 Mar 14 12:25:50 PM PDT 24 Mar 14 12:25:53 PM PDT 24 84794411 ps
T630 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1875711181 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:34 PM PDT 24 18245771 ps
T631 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2149347369 Mar 14 12:25:31 PM PDT 24 Mar 14 12:25:32 PM PDT 24 118782437 ps
T632 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2020442017 Mar 14 12:25:44 PM PDT 24 Mar 14 12:25:45 PM PDT 24 39527644 ps
T633 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.685706909 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:51 PM PDT 24 176611031 ps
T61 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.271422471 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:51 PM PDT 24 175301333 ps
T121 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3644240880 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:49 PM PDT 24 395654894 ps
T120 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3416313691 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:50 PM PDT 24 255768611 ps
T634 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1499703522 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:48 PM PDT 24 138398443 ps
T635 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1454906158 Mar 14 12:21:45 PM PDT 24 Mar 14 12:21:49 PM PDT 24 64567858 ps
T636 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2841846707 Mar 14 12:26:00 PM PDT 24 Mar 14 12:26:01 PM PDT 24 105614679 ps
T637 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.828477934 Mar 14 12:25:39 PM PDT 24 Mar 14 12:36:09 PM PDT 24 647104779101 ps
T638 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2212948284 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:47 PM PDT 24 66618833 ps
T639 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2403702993 Mar 14 12:25:45 PM PDT 24 Mar 14 12:25:45 PM PDT 24 28874721 ps
T640 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2986129416 Mar 14 12:25:57 PM PDT 24 Mar 14 12:32:38 PM PDT 24 142684401538 ps
T641 /workspace/coverage/cover_reg_top/22.hmac_intr_test.25581022 Mar 14 12:25:38 PM PDT 24 Mar 14 12:25:39 PM PDT 24 23298857 ps
T642 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.639337524 Mar 14 12:26:21 PM PDT 24 Mar 14 12:26:23 PM PDT 24 57903871 ps
T643 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1770634978 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:02 PM PDT 24 20496384 ps
T644 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1814877376 Mar 14 12:25:57 PM PDT 24 Mar 14 12:25:58 PM PDT 24 49514396 ps
T645 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2906366904 Mar 14 12:25:34 PM PDT 24 Mar 14 12:25:36 PM PDT 24 171871009 ps
T646 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4111119994 Mar 14 12:25:55 PM PDT 24 Mar 14 12:25:56 PM PDT 24 14901428 ps
T647 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.910034867 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:45 PM PDT 24 111907283 ps
T648 /workspace/coverage/cover_reg_top/1.hmac_intr_test.224368661 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:55 PM PDT 24 20116448 ps
T95 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1835515944 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:44 PM PDT 24 175830419 ps
T649 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2414674362 Mar 14 12:25:48 PM PDT 24 Mar 14 12:25:49 PM PDT 24 19707964 ps
T650 /workspace/coverage/cover_reg_top/36.hmac_intr_test.798741238 Mar 14 12:25:37 PM PDT 24 Mar 14 12:25:37 PM PDT 24 74337447 ps
T651 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2887306270 Mar 14 12:25:30 PM PDT 24 Mar 14 12:25:34 PM PDT 24 401960159 ps
T96 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1932226513 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:52 PM PDT 24 2106709585 ps
T652 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4286678434 Mar 14 12:25:52 PM PDT 24 Mar 14 12:26:01 PM PDT 24 443830076 ps
T653 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2773733562 Mar 14 12:25:49 PM PDT 24 Mar 14 12:25:51 PM PDT 24 196124187 ps
T654 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1881416242 Mar 14 12:25:49 PM PDT 24 Mar 14 12:25:52 PM PDT 24 651070008 ps
T655 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2038604568 Mar 14 12:25:40 PM PDT 24 Mar 14 12:25:41 PM PDT 24 14196200 ps
T125 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2449501568 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:05 PM PDT 24 151362944 ps
T97 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.771552944 Mar 14 12:20:28 PM PDT 24 Mar 14 12:20:34 PM PDT 24 211566933 ps
T656 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1301063309 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:02 PM PDT 24 49802942 ps
T657 /workspace/coverage/cover_reg_top/15.hmac_intr_test.363366236 Mar 14 12:25:35 PM PDT 24 Mar 14 12:25:36 PM PDT 24 14328715 ps
T658 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3210576275 Mar 14 12:25:39 PM PDT 24 Mar 14 12:25:40 PM PDT 24 23925760 ps
T659 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.886836656 Mar 14 12:25:27 PM PDT 24 Mar 14 12:25:28 PM PDT 24 67114626 ps
T660 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3052608376 Mar 14 12:25:32 PM PDT 24 Mar 14 12:25:35 PM PDT 24 585375158 ps
T661 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1786742173 Mar 14 12:25:35 PM PDT 24 Mar 14 12:25:35 PM PDT 24 16802688 ps
T662 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3058510255 Mar 14 12:22:42 PM PDT 24 Mar 14 12:22:45 PM PDT 24 935194617 ps
T663 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3078037498 Mar 14 12:25:40 PM PDT 24 Mar 14 12:25:41 PM PDT 24 14710751 ps
T664 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3593563777 Mar 14 12:25:56 PM PDT 24 Mar 14 12:26:00 PM PDT 24 68665033 ps
T665 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2017955818 Mar 14 12:25:50 PM PDT 24 Mar 14 12:25:51 PM PDT 24 36484519 ps
T118 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3966063863 Mar 14 12:25:39 PM PDT 24 Mar 14 12:25:48 PM PDT 24 893749111 ps
T666 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1576081030 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:58 PM PDT 24 178036793 ps
T667 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3455235966 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:45 PM PDT 24 147339928 ps
T119 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3162655700 Mar 14 12:25:48 PM PDT 24 Mar 14 12:25:51 PM PDT 24 90231373 ps
T668 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.563715381 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:46 PM PDT 24 143558755 ps
T669 /workspace/coverage/cover_reg_top/8.hmac_intr_test.783134791 Mar 14 12:25:42 PM PDT 24 Mar 14 12:25:43 PM PDT 24 18796612 ps
T670 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.26384414 Mar 14 12:25:28 PM PDT 24 Mar 14 12:30:50 PM PDT 24 83664369780 ps
T671 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2089412305 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:47 PM PDT 24 12336759 ps
T122 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2849922260 Mar 14 12:25:48 PM PDT 24 Mar 14 12:25:51 PM PDT 24 129347838 ps
T672 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1963884709 Mar 14 12:25:52 PM PDT 24 Mar 14 12:25:54 PM PDT 24 339366011 ps
T673 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2993276047 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:35 PM PDT 24 24070885 ps
T674 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3325208965 Mar 14 12:25:36 PM PDT 24 Mar 14 12:25:38 PM PDT 24 24036682 ps
T98 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3966196144 Mar 14 12:25:42 PM PDT 24 Mar 14 12:25:43 PM PDT 24 66022925 ps
T675 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3444360246 Mar 14 12:25:28 PM PDT 24 Mar 14 12:25:31 PM PDT 24 101622155 ps
T676 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.343370467 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:46 PM PDT 24 123803873 ps
T677 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2764018125 Mar 14 12:25:49 PM PDT 24 Mar 14 12:25:51 PM PDT 24 142116425 ps
T678 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2960918738 Mar 14 12:21:13 PM PDT 24 Mar 14 12:21:15 PM PDT 24 44229097 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.183759742 Mar 14 12:25:44 PM PDT 24 Mar 14 12:25:45 PM PDT 24 50609632 ps
T679 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3982375678 Mar 14 12:25:56 PM PDT 24 Mar 14 12:25:56 PM PDT 24 53612310 ps
T680 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1694044788 Mar 14 12:25:34 PM PDT 24 Mar 14 12:25:37 PM PDT 24 1366736116 ps
T100 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3465551672 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:51 PM PDT 24 975064128 ps
T681 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1362982710 Mar 14 12:25:52 PM PDT 24 Mar 14 12:25:55 PM PDT 24 46062938 ps
T101 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.702627984 Mar 14 12:25:28 PM PDT 24 Mar 14 12:25:29 PM PDT 24 112394114 ps
T682 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2291776611 Mar 14 12:25:45 PM PDT 24 Mar 14 12:25:47 PM PDT 24 218715525 ps
T683 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2512245602 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:43 PM PDT 24 61249566 ps
T684 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.7667595 Mar 14 12:25:51 PM PDT 24 Mar 14 12:25:52 PM PDT 24 139838557 ps
T685 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2294141805 Mar 14 12:25:50 PM PDT 24 Mar 14 12:25:52 PM PDT 24 69030136 ps
T686 /workspace/coverage/cover_reg_top/25.hmac_intr_test.446784044 Mar 14 12:25:50 PM PDT 24 Mar 14 12:25:50 PM PDT 24 18159190 ps
T124 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3201170786 Mar 14 12:25:38 PM PDT 24 Mar 14 12:25:43 PM PDT 24 247624229 ps
T687 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4251163546 Mar 14 12:25:35 PM PDT 24 Mar 14 12:25:37 PM PDT 24 77089965 ps
T111 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.4140909633 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:48 PM PDT 24 55282087 ps
T688 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3663305121 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:55 PM PDT 24 39144001 ps
T689 /workspace/coverage/cover_reg_top/19.hmac_intr_test.100915023 Mar 14 12:25:53 PM PDT 24 Mar 14 12:25:54 PM PDT 24 12784848 ps
T690 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.293546559 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:48 PM PDT 24 79826052 ps
T691 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.512155743 Mar 14 12:25:39 PM PDT 24 Mar 14 12:25:41 PM PDT 24 26645597 ps
T692 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.346551575 Mar 14 12:25:45 PM PDT 24 Mar 14 12:25:46 PM PDT 24 25906990 ps
T693 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2654409418 Mar 14 12:25:30 PM PDT 24 Mar 14 12:25:32 PM PDT 24 289618013 ps
T694 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1157448332 Mar 14 12:25:38 PM PDT 24 Mar 14 12:25:45 PM PDT 24 419622926 ps
T695 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2916326422 Mar 14 12:25:33 PM PDT 24 Mar 14 12:25:35 PM PDT 24 369396812 ps
T696 /workspace/coverage/cover_reg_top/27.hmac_intr_test.973254511 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:48 PM PDT 24 14760922 ps
T697 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2977562081 Mar 14 12:21:23 PM PDT 24 Mar 14 12:21:26 PM PDT 24 610901736 ps
T698 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1887216367 Mar 14 12:25:35 PM PDT 24 Mar 14 12:25:36 PM PDT 24 1051457894 ps
T699 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2182263909 Mar 14 12:25:44 PM PDT 24 Mar 14 12:26:00 PM PDT 24 8109287969 ps
T700 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2982865179 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:47 PM PDT 24 16208770 ps
T701 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3821256272 Mar 14 12:25:45 PM PDT 24 Mar 14 12:25:46 PM PDT 24 11922055 ps
T702 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1975332008 Mar 14 12:25:42 PM PDT 24 Mar 14 12:25:42 PM PDT 24 15613580 ps
T703 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2600450512 Mar 14 12:25:37 PM PDT 24 Mar 14 12:25:39 PM PDT 24 183792984 ps
T123 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3709186770 Mar 14 12:25:35 PM PDT 24 Mar 14 12:25:39 PM PDT 24 245470597 ps
T704 /workspace/coverage/cover_reg_top/0.hmac_intr_test.532275021 Mar 14 12:23:47 PM PDT 24 Mar 14 12:23:50 PM PDT 24 14504868 ps
T112 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1426199518 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:44 PM PDT 24 105028214 ps
T705 /workspace/coverage/cover_reg_top/31.hmac_intr_test.4286890455 Mar 14 12:25:57 PM PDT 24 Mar 14 12:25:58 PM PDT 24 33692104 ps
T706 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3708702490 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:43 PM PDT 24 34866049 ps
T707 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2227859972 Mar 14 12:25:34 PM PDT 24 Mar 14 12:25:36 PM PDT 24 101994522 ps
T708 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3922355336 Mar 14 12:25:52 PM PDT 24 Mar 14 12:25:59 PM PDT 24 596846303 ps
T126 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1739049375 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:52 PM PDT 24 228751714 ps
T709 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2878946824 Mar 14 12:25:41 PM PDT 24 Mar 14 12:25:44 PM PDT 24 1605895346 ps
T710 /workspace/coverage/cover_reg_top/46.hmac_intr_test.661685203 Mar 14 12:26:01 PM PDT 24 Mar 14 12:26:01 PM PDT 24 12863880 ps
T711 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3442269123 Mar 14 12:25:28 PM PDT 24 Mar 14 12:25:29 PM PDT 24 25596566 ps
T712 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.785710687 Mar 14 12:25:27 PM PDT 24 Mar 14 12:25:28 PM PDT 24 20975271 ps
T127 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3146209507 Mar 14 12:25:51 PM PDT 24 Mar 14 12:25:54 PM PDT 24 363390803 ps
T713 /workspace/coverage/cover_reg_top/7.hmac_intr_test.224226062 Mar 14 12:25:42 PM PDT 24 Mar 14 12:25:43 PM PDT 24 13571226 ps
T714 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.842169505 Mar 14 12:25:38 PM PDT 24 Mar 14 12:25:40 PM PDT 24 111653224 ps
T715 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.426445843 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:49 PM PDT 24 95607530 ps
T716 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.897638608 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:44 PM PDT 24 76658953 ps
T717 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1454042840 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:58 PM PDT 24 48507809 ps
T718 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.871454455 Mar 14 12:25:43 PM PDT 24 Mar 14 12:25:44 PM PDT 24 107319400 ps
T719 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4192464456 Mar 14 12:25:39 PM PDT 24 Mar 14 12:25:53 PM PDT 24 1028630337 ps
T720 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1298413798 Mar 14 12:25:52 PM PDT 24 Mar 14 12:25:53 PM PDT 24 18150113 ps
T721 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.681319436 Mar 14 12:25:27 PM PDT 24 Mar 14 12:25:29 PM PDT 24 103423174 ps
T722 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1797693026 Mar 14 12:25:41 PM PDT 24 Mar 14 12:25:42 PM PDT 24 25507408 ps
T723 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.213073752 Mar 14 12:25:55 PM PDT 24 Mar 14 12:25:58 PM PDT 24 155449952 ps
T724 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.682359558 Mar 14 12:25:34 PM PDT 24 Mar 14 12:25:35 PM PDT 24 132953556 ps
T725 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1920248924 Mar 14 12:25:55 PM PDT 24 Mar 14 12:25:55 PM PDT 24 35903069 ps
T726 /workspace/coverage/cover_reg_top/43.hmac_intr_test.548663642 Mar 14 12:25:50 PM PDT 24 Mar 14 12:25:51 PM PDT 24 179630439 ps
T727 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1899806370 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:48 PM PDT 24 41644755 ps
T728 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1353065135 Mar 14 12:25:57 PM PDT 24 Mar 14 12:25:58 PM PDT 24 94815929 ps
T729 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.871239784 Mar 14 12:22:02 PM PDT 24 Mar 14 12:22:08 PM PDT 24 4417745116 ps
T730 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4211036102 Mar 14 12:25:46 PM PDT 24 Mar 14 12:36:02 PM PDT 24 120830246296 ps
T731 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.584237097 Mar 14 12:26:27 PM PDT 24 Mar 14 12:26:29 PM PDT 24 52523559 ps
T732 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1895754549 Mar 14 12:25:40 PM PDT 24 Mar 14 12:25:40 PM PDT 24 17391010 ps
T733 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.421054534 Mar 14 12:25:56 PM PDT 24 Mar 14 12:25:59 PM PDT 24 223547497 ps
T734 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2347132187 Mar 14 12:25:50 PM PDT 24 Mar 14 12:25:50 PM PDT 24 17149567 ps
T735 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3725291316 Mar 14 12:25:41 PM PDT 24 Mar 14 12:25:42 PM PDT 24 14849648 ps
T736 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2282454720 Mar 14 12:25:37 PM PDT 24 Mar 14 12:25:39 PM PDT 24 40104113 ps
T737 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2841765503 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:36 PM PDT 24 84224792 ps
T738 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2440861318 Mar 14 12:25:59 PM PDT 24 Mar 14 12:26:01 PM PDT 24 289198399 ps
T739 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1705571331 Mar 14 12:26:00 PM PDT 24 Mar 14 12:26:00 PM PDT 24 31590913 ps
T740 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3946852986 Mar 14 12:25:39 PM PDT 24 Mar 14 12:25:41 PM PDT 24 168797635 ps
T741 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2390565563 Mar 14 12:25:52 PM PDT 24 Mar 14 12:25:55 PM PDT 24 364665074 ps
T113 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1821283099 Mar 14 12:25:44 PM PDT 24 Mar 14 12:25:45 PM PDT 24 48209234 ps

Test location /workspace/coverage/default/36.hmac_back_pressure.2247056032
Short name T20
Test name
Test status
Simulation time 10935380653 ps
CPU time 45.61 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:43:14 PM PDT 24
Peak memory 248432 kb
Host smart-e586f68a-38cb-4f24-b627-915a4c5f1867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247056032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2247056032
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.3927565312
Short name T9
Test name
Test status
Simulation time 71391221139 ps
CPU time 1811.36 seconds
Started Mar 14 12:44:09 PM PDT 24
Finished Mar 14 01:14:21 PM PDT 24
Peak memory 250288 kb
Host smart-1c6e55f5-34cd-434b-bdb9-f70eea6ea6d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927565312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.3927565312
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3664036841
Short name T21
Test name
Test status
Simulation time 14428112605 ps
CPU time 691.96 seconds
Started Mar 14 12:42:45 PM PDT 24
Finished Mar 14 12:54:17 PM PDT 24
Peak memory 241028 kb
Host smart-30396320-7246-44fe-a36f-9b1fb616e463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664036841 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3664036841
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.66734920
Short name T35
Test name
Test status
Simulation time 461539838 ps
CPU time 0.93 seconds
Started Mar 14 12:39:31 PM PDT 24
Finished Mar 14 12:39:32 PM PDT 24
Peak memory 219096 kb
Host smart-f1c7451b-c4c2-40fe-bea3-a4aa1ceb9757
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66734920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.66734920
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.11480704
Short name T12
Test name
Test status
Simulation time 137409266130 ps
CPU time 1795.49 seconds
Started Mar 14 12:41:37 PM PDT 24
Finished Mar 14 01:11:33 PM PDT 24
Peak memory 247584 kb
Host smart-59ff7963-4bfe-46f6-9265-16d84c821c41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11480704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.11480704
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2369214051
Short name T59
Test name
Test status
Simulation time 897823860 ps
CPU time 3.82 seconds
Started Mar 14 12:25:42 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 199376 kb
Host smart-7c1d84d5-6bf6-4619-bf9a-e1070aad8d78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369214051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2369214051
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1723810287
Short name T17
Test name
Test status
Simulation time 733224112734 ps
CPU time 1844.96 seconds
Started Mar 14 12:41:35 PM PDT 24
Finished Mar 14 01:12:20 PM PDT 24
Peak memory 230908 kb
Host smart-a635c883-2aaf-45ff-8c48-500930392c06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723810287 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1723810287
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1408618436
Short name T24
Test name
Test status
Simulation time 100052941 ps
CPU time 0.55 seconds
Started Mar 14 12:40:40 PM PDT 24
Finished Mar 14 12:40:41 PM PDT 24
Peak memory 195532 kb
Host smart-20a1dc52-d05a-4e89-93ea-e97fb1386e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408618436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1408618436
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1894744373
Short name T1
Test name
Test status
Simulation time 487320429 ps
CPU time 0.95 seconds
Started Mar 14 12:41:17 PM PDT 24
Finished Mar 14 12:41:18 PM PDT 24
Peak memory 198252 kb
Host smart-ee44c7df-a743-41da-873c-41b5dc1957d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894744373 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1894744373
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_error.43432121
Short name T48
Test name
Test status
Simulation time 2865452935 ps
CPU time 73.62 seconds
Started Mar 14 12:41:23 PM PDT 24
Finished Mar 14 12:42:37 PM PDT 24
Peak memory 198000 kb
Host smart-17ab9244-3150-46cf-b974-52d385b5f17f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43432121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.43432121
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3966063863
Short name T118
Test name
Test status
Simulation time 893749111 ps
CPU time 4.17 seconds
Started Mar 14 12:25:39 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 199396 kb
Host smart-2b9f1e76-3102-49ed-9c3f-7bfebb9c5c13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966063863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3966063863
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1695713875
Short name T240
Test name
Test status
Simulation time 162128664315 ps
CPU time 824.24 seconds
Started Mar 14 12:39:32 PM PDT 24
Finished Mar 14 12:53:17 PM PDT 24
Peak memory 227776 kb
Host smart-587166a9-78b5-44e2-9e6f-27bd19323783
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695713875 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1695713875
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.771552944
Short name T97
Test name
Test status
Simulation time 211566933 ps
CPU time 6.02 seconds
Started Mar 14 12:20:28 PM PDT 24
Finished Mar 14 12:20:34 PM PDT 24
Peak memory 198836 kb
Host smart-b6c66c6f-53f6-4133-b884-2dabfeea93aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771552944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.771552944
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1739049375
Short name T126
Test name
Test status
Simulation time 228751714 ps
CPU time 4.15 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:52 PM PDT 24
Peak memory 199340 kb
Host smart-15558ae6-c1c7-4644-b3f0-e61b31e8ddb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739049375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1739049375
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.871239784
Short name T729
Test name
Test status
Simulation time 4417745116 ps
CPU time 5.83 seconds
Started Mar 14 12:22:02 PM PDT 24
Finished Mar 14 12:22:08 PM PDT 24
Peak memory 198652 kb
Host smart-c157a518-c447-45d4-976c-6b51e6004e82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871239784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.871239784
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3992973537
Short name T624
Test name
Test status
Simulation time 151535646 ps
CPU time 0.89 seconds
Started Mar 14 12:22:02 PM PDT 24
Finished Mar 14 12:22:03 PM PDT 24
Peak memory 198568 kb
Host smart-f03ef194-1dca-4792-b520-1f92baa38583
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992973537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3992973537
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2960918738
Short name T678
Test name
Test status
Simulation time 44229097 ps
CPU time 1.31 seconds
Started Mar 14 12:21:13 PM PDT 24
Finished Mar 14 12:21:15 PM PDT 24
Peak memory 199372 kb
Host smart-d9eb6b32-b947-40a2-bb18-417d2657fc13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960918738 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2960918738
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2937632674
Short name T628
Test name
Test status
Simulation time 180213354 ps
CPU time 0.72 seconds
Started Mar 14 12:23:42 PM PDT 24
Finished Mar 14 12:23:43 PM PDT 24
Peak memory 195384 kb
Host smart-e4e965fe-02ab-4ef4-9c00-291a9174c9b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937632674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2937632674
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.532275021
Short name T704
Test name
Test status
Simulation time 14504868 ps
CPU time 0.56 seconds
Started Mar 14 12:23:47 PM PDT 24
Finished Mar 14 12:23:50 PM PDT 24
Peak memory 193868 kb
Host smart-9a3a97a2-34b6-4f64-a69d-306b4e782855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532275021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.532275021
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3058510255
Short name T662
Test name
Test status
Simulation time 935194617 ps
CPU time 2.63 seconds
Started Mar 14 12:22:42 PM PDT 24
Finished Mar 14 12:22:45 PM PDT 24
Peak memory 199048 kb
Host smart-5954393b-a1f0-441f-884c-4cc81dc07c00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058510255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3058510255
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1454906158
Short name T635
Test name
Test status
Simulation time 64567858 ps
CPU time 3.71 seconds
Started Mar 14 12:21:45 PM PDT 24
Finished Mar 14 12:21:49 PM PDT 24
Peak memory 199552 kb
Host smart-c3aadbee-2ce1-42d7-b714-8615a93edf62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454906158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1454906158
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2977562081
Short name T697
Test name
Test status
Simulation time 610901736 ps
CPU time 3.01 seconds
Started Mar 14 12:21:23 PM PDT 24
Finished Mar 14 12:21:26 PM PDT 24
Peak memory 199732 kb
Host smart-a21c5a2e-ddf2-4e2f-b5c6-f7415b0f06c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977562081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2977562081
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3922355336
Short name T708
Test name
Test status
Simulation time 596846303 ps
CPU time 5.89 seconds
Started Mar 14 12:25:52 PM PDT 24
Finished Mar 14 12:25:59 PM PDT 24
Peak memory 199312 kb
Host smart-d97e30fb-6953-4451-8c76-bb3facf5bfd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922355336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3922355336
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1932226513
Short name T96
Test name
Test status
Simulation time 2106709585 ps
CPU time 5.61 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:52 PM PDT 24
Peak memory 197748 kb
Host smart-ace61748-e5e5-434c-9824-b3fa40da740f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932226513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1932226513
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.125974354
Short name T608
Test name
Test status
Simulation time 224941301 ps
CPU time 0.84 seconds
Started Mar 14 12:25:55 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 198032 kb
Host smart-7bc26735-0445-4178-b5e3-f3ac64d41757
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125974354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.125974354
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2857026041
Short name T629
Test name
Test status
Simulation time 84794411 ps
CPU time 2.48 seconds
Started Mar 14 12:25:50 PM PDT 24
Finished Mar 14 12:25:53 PM PDT 24
Peak memory 199436 kb
Host smart-73b47586-b247-4060-a133-3143a7e763fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857026041 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2857026041
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.183759742
Short name T99
Test name
Test status
Simulation time 50609632 ps
CPU time 0.8 seconds
Started Mar 14 12:25:44 PM PDT 24
Finished Mar 14 12:25:45 PM PDT 24
Peak memory 198648 kb
Host smart-5ec66f04-e438-4157-a78c-ee900cab281d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183759742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.183759742
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.224368661
Short name T648
Test name
Test status
Simulation time 20116448 ps
CPU time 0.59 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:55 PM PDT 24
Peak memory 193884 kb
Host smart-0d10411a-0778-4485-8848-55f7c0218f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224368661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.224368661
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.213073752
Short name T723
Test name
Test status
Simulation time 155449952 ps
CPU time 2.34 seconds
Started Mar 14 12:25:55 PM PDT 24
Finished Mar 14 12:25:58 PM PDT 24
Peak memory 199336 kb
Host smart-d55f9027-50f4-444c-9e82-927cc4392127
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213073752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.213073752
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2841765503
Short name T737
Test name
Test status
Simulation time 84224792 ps
CPU time 1.25 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:36 PM PDT 24
Peak memory 199452 kb
Host smart-e3ae4a8e-bac7-4bc5-9bc3-4273f1a874da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841765503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2841765503
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3247763959
Short name T60
Test name
Test status
Simulation time 100730797 ps
CPU time 1.84 seconds
Started Mar 14 12:25:44 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 199356 kb
Host smart-435ab9ad-52f2-4752-a680-a6b67b37a549
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247763959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3247763959
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.639337524
Short name T642
Test name
Test status
Simulation time 57903871 ps
CPU time 1.59 seconds
Started Mar 14 12:26:21 PM PDT 24
Finished Mar 14 12:26:23 PM PDT 24
Peak memory 199440 kb
Host smart-e9ef2936-99a9-4f7a-b587-afe6d3f15412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639337524 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.639337524
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1426199518
Short name T112
Test name
Test status
Simulation time 105028214 ps
CPU time 0.9 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 198788 kb
Host smart-06b28cf0-63c2-462c-b3d0-dcd5621df4b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426199518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1426199518
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1920248924
Short name T725
Test name
Test status
Simulation time 35903069 ps
CPU time 0.54 seconds
Started Mar 14 12:25:55 PM PDT 24
Finished Mar 14 12:25:55 PM PDT 24
Peak memory 193916 kb
Host smart-f1719232-3b68-4af3-9b3f-4a3711150c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920248924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1920248924
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1887216367
Short name T698
Test name
Test status
Simulation time 1051457894 ps
CPU time 1.13 seconds
Started Mar 14 12:25:35 PM PDT 24
Finished Mar 14 12:25:36 PM PDT 24
Peak memory 198728 kb
Host smart-c9dc81a5-129d-491f-bece-089eff37943b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887216367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1887216367
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.343370467
Short name T676
Test name
Test status
Simulation time 123803873 ps
CPU time 2.77 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 199388 kb
Host smart-4190280a-5cd9-4251-ae43-18ad6860ddb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343370467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.343370467
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.271422471
Short name T61
Test name
Test status
Simulation time 175301333 ps
CPU time 2.91 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 199316 kb
Host smart-8ad3778b-3d83-421a-92a6-8d7a140ce0f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271422471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.271422471
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.842169505
Short name T714
Test name
Test status
Simulation time 111653224 ps
CPU time 1.5 seconds
Started Mar 14 12:25:38 PM PDT 24
Finished Mar 14 12:25:40 PM PDT 24
Peak memory 199372 kb
Host smart-ccaa8c80-3d6a-4ae7-a25f-b071e2365393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842169505 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.842169505
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1298413798
Short name T720
Test name
Test status
Simulation time 18150113 ps
CPU time 0.69 seconds
Started Mar 14 12:25:52 PM PDT 24
Finished Mar 14 12:25:53 PM PDT 24
Peak memory 196836 kb
Host smart-f79717bc-410f-449f-8000-64935d75f06c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298413798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1298413798
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1899806370
Short name T727
Test name
Test status
Simulation time 41644755 ps
CPU time 0.65 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 193964 kb
Host smart-1711d378-8c5d-4709-9471-dcd8a6233739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899806370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1899806370
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.897638608
Short name T716
Test name
Test status
Simulation time 76658953 ps
CPU time 1.03 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 199196 kb
Host smart-c5862b3e-aca2-42ff-8cd0-db1389fb69f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897638608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.897638608
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.685706909
Short name T633
Test name
Test status
Simulation time 176611031 ps
CPU time 3.03 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 199360 kb
Host smart-a1f701c0-98ea-4dd2-9c3e-8aaa04b786a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685706909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.685706909
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3644240880
Short name T121
Test name
Test status
Simulation time 395654894 ps
CPU time 1.79 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:49 PM PDT 24
Peak memory 199248 kb
Host smart-5d1a87c4-0e61-4637-97e0-979877a10430
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644240880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3644240880
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2986129416
Short name T640
Test name
Test status
Simulation time 142684401538 ps
CPU time 401.1 seconds
Started Mar 14 12:25:57 PM PDT 24
Finished Mar 14 12:32:38 PM PDT 24
Peak memory 215000 kb
Host smart-c4b90c84-a4ea-4755-8545-8c0f3947df1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986129416 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2986129416
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2339043302
Short name T94
Test name
Test status
Simulation time 43747652 ps
CPU time 0.71 seconds
Started Mar 14 12:25:52 PM PDT 24
Finished Mar 14 12:25:53 PM PDT 24
Peak memory 196716 kb
Host smart-6900c520-b489-4fd7-b95c-4a2981323ef9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339043302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2339043302
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1353065135
Short name T728
Test name
Test status
Simulation time 94815929 ps
CPU time 0.61 seconds
Started Mar 14 12:25:57 PM PDT 24
Finished Mar 14 12:25:58 PM PDT 24
Peak memory 193932 kb
Host smart-5514b755-5537-4020-a5b9-195a0a183c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353065135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1353065135
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2841846707
Short name T636
Test name
Test status
Simulation time 105614679 ps
CPU time 1.07 seconds
Started Mar 14 12:26:00 PM PDT 24
Finished Mar 14 12:26:01 PM PDT 24
Peak memory 199060 kb
Host smart-a56470ba-d61b-4ba0-a290-47ea19881c41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841846707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2841846707
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3455235966
Short name T667
Test name
Test status
Simulation time 147339928 ps
CPU time 2.33 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:45 PM PDT 24
Peak memory 199388 kb
Host smart-07cc3557-8a21-456c-87d0-cf5c30ae298c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455235966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3455235966
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3416313691
Short name T120
Test name
Test status
Simulation time 255768611 ps
CPU time 2.68 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:50 PM PDT 24
Peak memory 199368 kb
Host smart-bea61b6e-41f6-45e3-87e9-a2914ee857d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416313691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3416313691
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2916326422
Short name T695
Test name
Test status
Simulation time 369396812 ps
CPU time 2.02 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:35 PM PDT 24
Peak memory 199456 kb
Host smart-914b4b9f-6c32-46db-bd66-f0234c2fc414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916326422 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2916326422
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3210576275
Short name T658
Test name
Test status
Simulation time 23925760 ps
CPU time 0.79 seconds
Started Mar 14 12:25:39 PM PDT 24
Finished Mar 14 12:25:40 PM PDT 24
Peak memory 198564 kb
Host smart-b375584f-45aa-46be-9082-c94180391678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210576275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3210576275
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1975332008
Short name T702
Test name
Test status
Simulation time 15613580 ps
CPU time 0.58 seconds
Started Mar 14 12:25:42 PM PDT 24
Finished Mar 14 12:25:42 PM PDT 24
Peak memory 194188 kb
Host smart-094b3c1e-9ad6-4658-98e3-7aee4a9b3ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975332008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1975332008
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1436694851
Short name T621
Test name
Test status
Simulation time 121261124 ps
CPU time 2.26 seconds
Started Mar 14 12:25:41 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 199156 kb
Host smart-cfce31af-89c6-4989-be30-7ec3ef2b5023
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436694851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1436694851
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.584237097
Short name T731
Test name
Test status
Simulation time 52523559 ps
CPU time 1.31 seconds
Started Mar 14 12:26:27 PM PDT 24
Finished Mar 14 12:26:29 PM PDT 24
Peak memory 198616 kb
Host smart-0332a1f8-6a52-4591-8177-6c6c1623b211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584237097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.584237097
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2440861318
Short name T738
Test name
Test status
Simulation time 289198399 ps
CPU time 1.71 seconds
Started Mar 14 12:25:59 PM PDT 24
Finished Mar 14 12:26:01 PM PDT 24
Peak memory 199388 kb
Host smart-34e6d66b-0f9b-47d2-8105-6a4cba34311b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440861318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2440861318
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4251163546
Short name T687
Test name
Test status
Simulation time 77089965 ps
CPU time 1.76 seconds
Started Mar 14 12:25:35 PM PDT 24
Finished Mar 14 12:25:37 PM PDT 24
Peak memory 199492 kb
Host smart-babed990-da25-4afe-bdfb-227c95da9876
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251163546 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.4251163546
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3442269123
Short name T711
Test name
Test status
Simulation time 25596566 ps
CPU time 0.78 seconds
Started Mar 14 12:25:28 PM PDT 24
Finished Mar 14 12:25:29 PM PDT 24
Peak memory 198616 kb
Host smart-cc9b6116-cf4d-4c83-b1fd-a1c567004e25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442269123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3442269123
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2020442017
Short name T632
Test name
Test status
Simulation time 39527644 ps
CPU time 0.58 seconds
Started Mar 14 12:25:44 PM PDT 24
Finished Mar 14 12:25:45 PM PDT 24
Peak memory 194024 kb
Host smart-f28940c3-601b-490d-a9aa-676ad4d85d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020442017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2020442017
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1797693026
Short name T722
Test name
Test status
Simulation time 25507408 ps
CPU time 1.11 seconds
Started Mar 14 12:25:41 PM PDT 24
Finished Mar 14 12:25:42 PM PDT 24
Peak memory 198660 kb
Host smart-a6ac0e4e-b067-4d71-8f29-7e63319cd5ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797693026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1797693026
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.426445843
Short name T715
Test name
Test status
Simulation time 95607530 ps
CPU time 2.3 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:49 PM PDT 24
Peak memory 199468 kb
Host smart-79c17335-81b8-41e2-8a1c-dbd353a05479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426445843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.426445843
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.26384414
Short name T670
Test name
Test status
Simulation time 83664369780 ps
CPU time 321.45 seconds
Started Mar 14 12:25:28 PM PDT 24
Finished Mar 14 12:30:50 PM PDT 24
Peak memory 215892 kb
Host smart-235eafe0-3412-4838-9e7c-476008f805cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26384414 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.26384414
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2403702993
Short name T639
Test name
Test status
Simulation time 28874721 ps
CPU time 0.86 seconds
Started Mar 14 12:25:45 PM PDT 24
Finished Mar 14 12:25:45 PM PDT 24
Peak memory 198508 kb
Host smart-4ef0d0dd-ed4b-4e32-a1d2-ed5ae3fca1ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403702993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2403702993
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.363366236
Short name T657
Test name
Test status
Simulation time 14328715 ps
CPU time 0.56 seconds
Started Mar 14 12:25:35 PM PDT 24
Finished Mar 14 12:25:36 PM PDT 24
Peak memory 193888 kb
Host smart-b220a776-ee7d-4d63-b3a8-dff9786798c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363366236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.363366236
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.785710687
Short name T712
Test name
Test status
Simulation time 20975271 ps
CPU time 0.99 seconds
Started Mar 14 12:25:27 PM PDT 24
Finished Mar 14 12:25:28 PM PDT 24
Peak memory 198940 kb
Host smart-204f08e3-53a8-42a3-883b-5f36ce7e59f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785710687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.785710687
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2878946824
Short name T709
Test name
Test status
Simulation time 1605895346 ps
CPU time 3.4 seconds
Started Mar 14 12:25:41 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 199480 kb
Host smart-1d9e3b7e-b955-4ade-9243-11471d371888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878946824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2878946824
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3201170786
Short name T124
Test name
Test status
Simulation time 247624229 ps
CPU time 4.11 seconds
Started Mar 14 12:25:38 PM PDT 24
Finished Mar 14 12:25:43 PM PDT 24
Peak memory 199396 kb
Host smart-32dda6ed-d584-4d40-a515-07c18e2dbc74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201170786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3201170786
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.828080210
Short name T618
Test name
Test status
Simulation time 239479535 ps
CPU time 1.69 seconds
Started Mar 14 12:25:31 PM PDT 24
Finished Mar 14 12:25:33 PM PDT 24
Peak memory 199456 kb
Host smart-2dcfbc24-54bd-48b9-81fd-9942aecede65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828080210 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.828080210
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1821283099
Short name T113
Test name
Test status
Simulation time 48209234 ps
CPU time 0.81 seconds
Started Mar 14 12:25:44 PM PDT 24
Finished Mar 14 12:25:45 PM PDT 24
Peak memory 198548 kb
Host smart-3c7c285a-6887-40c4-928e-a8801ccd2f3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821283099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1821283099
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2212948284
Short name T638
Test name
Test status
Simulation time 66618833 ps
CPU time 0.55 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:47 PM PDT 24
Peak memory 194128 kb
Host smart-3ce48afe-2319-4af3-9b57-cbfc5e4b1be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212948284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2212948284
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1499703522
Short name T634
Test name
Test status
Simulation time 138398443 ps
CPU time 1.53 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 199368 kb
Host smart-3f875561-65d0-4968-b767-b1b151f1f0fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499703522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1499703522
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1576081030
Short name T666
Test name
Test status
Simulation time 178036793 ps
CPU time 3.89 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:58 PM PDT 24
Peak memory 199420 kb
Host smart-660a0ac5-ee04-4c78-a6d5-df4342b2bb41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576081030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1576081030
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2849922260
Short name T122
Test name
Test status
Simulation time 129347838 ps
CPU time 3.64 seconds
Started Mar 14 12:25:48 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 199400 kb
Host smart-fe6c5430-2eca-4d93-b6da-3120d3059270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849922260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2849922260
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2906366904
Short name T645
Test name
Test status
Simulation time 171871009 ps
CPU time 1.2 seconds
Started Mar 14 12:25:34 PM PDT 24
Finished Mar 14 12:25:36 PM PDT 24
Peak memory 199408 kb
Host smart-4faf4d15-9af5-4847-a3f1-f4328e3d7505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906366904 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2906366904
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1562041012
Short name T93
Test name
Test status
Simulation time 19747977 ps
CPU time 0.87 seconds
Started Mar 14 12:25:34 PM PDT 24
Finished Mar 14 12:25:35 PM PDT 24
Peak memory 198392 kb
Host smart-8da60b49-6b98-4427-a77d-c45954a614da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562041012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1562041012
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3821256272
Short name T701
Test name
Test status
Simulation time 11922055 ps
CPU time 0.62 seconds
Started Mar 14 12:25:45 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 194176 kb
Host smart-299b5b2f-eb07-473c-abbe-4b23da496a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821256272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3821256272
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.886836656
Short name T659
Test name
Test status
Simulation time 67114626 ps
CPU time 1.03 seconds
Started Mar 14 12:25:27 PM PDT 24
Finished Mar 14 12:25:28 PM PDT 24
Peak memory 197736 kb
Host smart-8fec277d-81bc-4d6a-8d42-e80e2b9ad9b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886836656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.886836656
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.293546559
Short name T690
Test name
Test status
Simulation time 79826052 ps
CPU time 1.24 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 199396 kb
Host smart-6a4fc0d1-83e3-418e-be87-b57557ddd1d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293546559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.293546559
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1454042840
Short name T717
Test name
Test status
Simulation time 48507809 ps
CPU time 1.65 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:58 PM PDT 24
Peak memory 199372 kb
Host smart-db9ff873-093f-4efb-9f89-d3b0e50362c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454042840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1454042840
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3655233540
Short name T610
Test name
Test status
Simulation time 28165856 ps
CPU time 1.67 seconds
Started Mar 14 12:25:50 PM PDT 24
Finished Mar 14 12:25:52 PM PDT 24
Peak memory 199336 kb
Host smart-525b8858-bc32-4171-9d54-bdb8c9a0f403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655233540 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3655233540
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2414674362
Short name T649
Test name
Test status
Simulation time 19707964 ps
CPU time 0.66 seconds
Started Mar 14 12:25:48 PM PDT 24
Finished Mar 14 12:25:49 PM PDT 24
Peak memory 196752 kb
Host smart-27096b61-0353-4617-83a4-ca19ff8ca8ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414674362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2414674362
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3334689225
Short name T626
Test name
Test status
Simulation time 34641835 ps
CPU time 0.56 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:34 PM PDT 24
Peak memory 194104 kb
Host smart-e9fd1484-e919-443e-899b-eb17ed710759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334689225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3334689225
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1963884709
Short name T672
Test name
Test status
Simulation time 339366011 ps
CPU time 1.63 seconds
Started Mar 14 12:25:52 PM PDT 24
Finished Mar 14 12:25:54 PM PDT 24
Peak memory 198976 kb
Host smart-dc2fe845-89b9-47af-9f51-24991a43ff49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963884709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1963884709
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2600450512
Short name T703
Test name
Test status
Simulation time 183792984 ps
CPU time 1.83 seconds
Started Mar 14 12:25:37 PM PDT 24
Finished Mar 14 12:25:39 PM PDT 24
Peak memory 199420 kb
Host smart-afbc2c96-1f34-46aa-8ffa-9ba76cae0135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600450512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2600450512
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3325208965
Short name T674
Test name
Test status
Simulation time 24036682 ps
CPU time 1.41 seconds
Started Mar 14 12:25:36 PM PDT 24
Finished Mar 14 12:25:38 PM PDT 24
Peak memory 199400 kb
Host smart-0c213821-82aa-4f0a-b203-8fd5b301fe41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325208965 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3325208965
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.346551575
Short name T692
Test name
Test status
Simulation time 25906990 ps
CPU time 0.66 seconds
Started Mar 14 12:25:45 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 197012 kb
Host smart-3f5dcbc5-b8bd-49e6-b61f-ef82b1af9229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346551575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.346551575
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.100915023
Short name T689
Test name
Test status
Simulation time 12784848 ps
CPU time 0.61 seconds
Started Mar 14 12:25:53 PM PDT 24
Finished Mar 14 12:25:54 PM PDT 24
Peak memory 193956 kb
Host smart-fdf1059c-e59d-4490-a4ce-7a76346fdc3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100915023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.100915023
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1157448332
Short name T694
Test name
Test status
Simulation time 419622926 ps
CPU time 1.66 seconds
Started Mar 14 12:25:38 PM PDT 24
Finished Mar 14 12:25:45 PM PDT 24
Peak memory 199140 kb
Host smart-2a45e4a5-693a-447e-9de9-35dcf21131fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157448332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1157448332
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2390565563
Short name T741
Test name
Test status
Simulation time 364665074 ps
CPU time 2.3 seconds
Started Mar 14 12:25:52 PM PDT 24
Finished Mar 14 12:25:55 PM PDT 24
Peak memory 199344 kb
Host smart-893fb9cf-7245-43f5-8713-ba059f89511e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390565563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2390565563
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.421054534
Short name T733
Test name
Test status
Simulation time 223547497 ps
CPU time 2.97 seconds
Started Mar 14 12:25:56 PM PDT 24
Finished Mar 14 12:25:59 PM PDT 24
Peak memory 199272 kb
Host smart-8cc4b03f-8274-4e3e-bfe1-8861355df011
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421054534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.421054534
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3465551672
Short name T100
Test name
Test status
Simulation time 975064128 ps
CPU time 7.98 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 198592 kb
Host smart-bdd41b95-c142-4929-b5e0-994cff7402b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465551672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3465551672
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2182263909
Short name T699
Test name
Test status
Simulation time 8109287969 ps
CPU time 16.05 seconds
Started Mar 14 12:25:44 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 198572 kb
Host smart-b30663f1-bb70-4ace-b6f9-e73e94567c48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182263909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2182263909
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2512245602
Short name T683
Test name
Test status
Simulation time 61249566 ps
CPU time 0.69 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:43 PM PDT 24
Peak memory 196832 kb
Host smart-224cad14-47c8-4d1e-b550-cc8243243bbd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512245602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2512245602
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2887306270
Short name T651
Test name
Test status
Simulation time 401960159 ps
CPU time 3.47 seconds
Started Mar 14 12:25:30 PM PDT 24
Finished Mar 14 12:25:34 PM PDT 24
Peak memory 199432 kb
Host smart-5f662317-2183-44ef-989b-680d9a923256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887306270 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2887306270
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.7667595
Short name T684
Test name
Test status
Simulation time 139838557 ps
CPU time 0.87 seconds
Started Mar 14 12:25:51 PM PDT 24
Finished Mar 14 12:25:52 PM PDT 24
Peak memory 199188 kb
Host smart-4a3d1e44-8499-470f-8d1f-7665bd9125a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7667595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.7667595
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3078037498
Short name T663
Test name
Test status
Simulation time 14710751 ps
CPU time 0.57 seconds
Started Mar 14 12:25:40 PM PDT 24
Finished Mar 14 12:25:41 PM PDT 24
Peak memory 194176 kb
Host smart-05f50fcc-3a2a-4e67-b7ee-a19cbc017782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078037498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3078037498
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2654409418
Short name T693
Test name
Test status
Simulation time 289618013 ps
CPU time 1.61 seconds
Started Mar 14 12:25:30 PM PDT 24
Finished Mar 14 12:25:32 PM PDT 24
Peak memory 199132 kb
Host smart-1d3e3244-55cc-49ad-a5f2-72817bb58b5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654409418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2654409418
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1881416242
Short name T654
Test name
Test status
Simulation time 651070008 ps
CPU time 3.02 seconds
Started Mar 14 12:25:49 PM PDT 24
Finished Mar 14 12:25:52 PM PDT 24
Peak memory 199424 kb
Host smart-4ef2d025-3bd1-49e9-9ca1-f0fc711761b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881416242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1881416242
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2893208461
Short name T620
Test name
Test status
Simulation time 13396400 ps
CPU time 0.55 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:47 PM PDT 24
Peak memory 193852 kb
Host smart-62413a9d-4e0e-434d-9b96-f72eca35dbdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893208461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2893208461
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1786742173
Short name T661
Test name
Test status
Simulation time 16802688 ps
CPU time 0.59 seconds
Started Mar 14 12:25:35 PM PDT 24
Finished Mar 14 12:25:35 PM PDT 24
Peak memory 194140 kb
Host smart-eb8a91eb-aa08-45ff-9160-ccd80c84dd94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786742173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1786742173
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.25581022
Short name T641
Test name
Test status
Simulation time 23298857 ps
CPU time 0.58 seconds
Started Mar 14 12:25:38 PM PDT 24
Finished Mar 14 12:25:39 PM PDT 24
Peak memory 194104 kb
Host smart-e28ba88c-22de-4425-826a-11220db75a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25581022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.25581022
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1770634978
Short name T643
Test name
Test status
Simulation time 20496384 ps
CPU time 0.59 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:02 PM PDT 24
Peak memory 193676 kb
Host smart-a4bad64c-fd35-480a-9a68-f0af5b7275f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770634978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1770634978
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2680049629
Short name T613
Test name
Test status
Simulation time 39100376 ps
CPU time 0.6 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:03 PM PDT 24
Peak memory 193992 kb
Host smart-409ca8d5-8b88-4311-9877-ece002bf4bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680049629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2680049629
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.446784044
Short name T686
Test name
Test status
Simulation time 18159190 ps
CPU time 0.59 seconds
Started Mar 14 12:25:50 PM PDT 24
Finished Mar 14 12:25:50 PM PDT 24
Peak memory 193856 kb
Host smart-b104fb23-c98d-4c7b-9861-5855e06b1923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446784044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.446784044
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3982375678
Short name T679
Test name
Test status
Simulation time 53612310 ps
CPU time 0.59 seconds
Started Mar 14 12:25:56 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 193996 kb
Host smart-ffc97fe9-8d13-46b2-9f87-2ee75ea5778d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982375678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3982375678
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.973254511
Short name T696
Test name
Test status
Simulation time 14760922 ps
CPU time 0.56 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 193856 kb
Host smart-c5d04fd1-ab37-4f25-a911-133240392732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973254511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.973254511
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1301063309
Short name T656
Test name
Test status
Simulation time 49802942 ps
CPU time 0.59 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:02 PM PDT 24
Peak memory 193656 kb
Host smart-49b9501a-484e-4aee-8dec-5bde99a947e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301063309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1301063309
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1705571331
Short name T739
Test name
Test status
Simulation time 31590913 ps
CPU time 0.56 seconds
Started Mar 14 12:26:00 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 194044 kb
Host smart-3d9dec74-2a41-4d01-a707-0b073666a99a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705571331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1705571331
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4286678434
Short name T652
Test name
Test status
Simulation time 443830076 ps
CPU time 8.19 seconds
Started Mar 14 12:25:52 PM PDT 24
Finished Mar 14 12:26:01 PM PDT 24
Peak memory 198664 kb
Host smart-10840450-d7a0-4775-a2ca-9c1cdc119e37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286678434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4286678434
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4192464456
Short name T719
Test name
Test status
Simulation time 1028630337 ps
CPU time 14.05 seconds
Started Mar 14 12:25:39 PM PDT 24
Finished Mar 14 12:25:53 PM PDT 24
Peak memory 199328 kb
Host smart-b0ec085a-cd4c-470b-bf2e-e48dc07e9aba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192464456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.4192464456
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3966196144
Short name T98
Test name
Test status
Simulation time 66022925 ps
CPU time 0.81 seconds
Started Mar 14 12:25:42 PM PDT 24
Finished Mar 14 12:25:43 PM PDT 24
Peak memory 198272 kb
Host smart-92acbc85-da11-4541-a8b2-f0eb0ad2201a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966196144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3966196144
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2294141805
Short name T685
Test name
Test status
Simulation time 69030136 ps
CPU time 1.87 seconds
Started Mar 14 12:25:50 PM PDT 24
Finished Mar 14 12:25:52 PM PDT 24
Peak memory 199348 kb
Host smart-4504b858-3da5-4106-8ddc-576c95b78bfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294141805 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2294141805
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.4140909633
Short name T111
Test name
Test status
Simulation time 55282087 ps
CPU time 0.78 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 198324 kb
Host smart-4d95acd6-18fe-414c-9ffd-7c211952a349
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140909633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.4140909633
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3984626386
Short name T605
Test name
Test status
Simulation time 29748873 ps
CPU time 0.58 seconds
Started Mar 14 12:25:45 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 193884 kb
Host smart-bad1fa72-e0e9-4a19-b878-3c2626884fed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984626386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3984626386
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2291776611
Short name T682
Test name
Test status
Simulation time 218715525 ps
CPU time 2.2 seconds
Started Mar 14 12:25:45 PM PDT 24
Finished Mar 14 12:25:47 PM PDT 24
Peak memory 198920 kb
Host smart-48c0b5d1-e412-4e1c-83ce-e8787d428efc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291776611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2291776611
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2764018125
Short name T677
Test name
Test status
Simulation time 142116425 ps
CPU time 1.42 seconds
Started Mar 14 12:25:49 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 199388 kb
Host smart-75316b3d-0186-4458-97ef-b6b81cda4276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764018125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2764018125
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1694044788
Short name T680
Test name
Test status
Simulation time 1366736116 ps
CPU time 3.04 seconds
Started Mar 14 12:25:34 PM PDT 24
Finished Mar 14 12:25:37 PM PDT 24
Peak memory 199308 kb
Host smart-f17dea5e-c2d1-40ea-b75c-daa44003e08c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694044788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1694044788
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1814877376
Short name T644
Test name
Test status
Simulation time 49514396 ps
CPU time 0.59 seconds
Started Mar 14 12:25:57 PM PDT 24
Finished Mar 14 12:25:58 PM PDT 24
Peak memory 193864 kb
Host smart-d36aea74-6a03-44f8-a22e-77c793e56931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814877376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1814877376
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.4286890455
Short name T705
Test name
Test status
Simulation time 33692104 ps
CPU time 0.57 seconds
Started Mar 14 12:25:57 PM PDT 24
Finished Mar 14 12:25:58 PM PDT 24
Peak memory 194164 kb
Host smart-7a117c88-bb5d-43e4-8078-f6c4be666d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286890455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.4286890455
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3890541517
Short name T622
Test name
Test status
Simulation time 30304646 ps
CPU time 0.63 seconds
Started Mar 14 12:25:55 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 194212 kb
Host smart-6435fde0-abfc-4ebf-b661-d56881af1bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890541517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3890541517
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2982865179
Short name T700
Test name
Test status
Simulation time 16208770 ps
CPU time 0.58 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:47 PM PDT 24
Peak memory 193892 kb
Host smart-fcc46244-3285-44a1-bf36-7ec65de5b040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982865179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2982865179
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2089412305
Short name T671
Test name
Test status
Simulation time 12336759 ps
CPU time 0.54 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:47 PM PDT 24
Peak memory 194172 kb
Host smart-f17a5f57-da86-4df6-b89e-172401f815ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089412305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2089412305
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3284766723
Short name T625
Test name
Test status
Simulation time 11971937 ps
CPU time 0.61 seconds
Started Mar 14 12:25:45 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 194216 kb
Host smart-ca5a0686-1a72-4dbd-bac9-75b705464c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284766723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3284766723
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.798741238
Short name T650
Test name
Test status
Simulation time 74337447 ps
CPU time 0.6 seconds
Started Mar 14 12:25:37 PM PDT 24
Finished Mar 14 12:25:37 PM PDT 24
Peak memory 193972 kb
Host smart-305e696c-1140-4ac0-8e68-399fd6c48bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798741238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.798741238
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2553503582
Short name T612
Test name
Test status
Simulation time 12298041 ps
CPU time 0.58 seconds
Started Mar 14 12:26:12 PM PDT 24
Finished Mar 14 12:26:13 PM PDT 24
Peak memory 194040 kb
Host smart-11b5fa02-8ec5-4fcd-99c2-f4bec410e979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553503582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2553503582
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3663305121
Short name T688
Test name
Test status
Simulation time 39144001 ps
CPU time 0.58 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:55 PM PDT 24
Peak memory 193884 kb
Host smart-1cdbe2d7-1755-4f7d-a15d-c65f0802c351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663305121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3663305121
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1118868209
Short name T616
Test name
Test status
Simulation time 13967988 ps
CPU time 0.57 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:55 PM PDT 24
Peak memory 194128 kb
Host smart-59a2cfdb-898d-4f99-8164-b2fc86a9eeb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118868209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1118868209
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1905563813
Short name T63
Test name
Test status
Simulation time 342593085 ps
CPU time 5.66 seconds
Started Mar 14 12:25:41 PM PDT 24
Finished Mar 14 12:25:47 PM PDT 24
Peak memory 198724 kb
Host smart-ad0c40a1-5bbf-4975-beea-c2753a18b5e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905563813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1905563813
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2054476747
Short name T611
Test name
Test status
Simulation time 7519373463 ps
CPU time 15.33 seconds
Started Mar 14 12:25:40 PM PDT 24
Finished Mar 14 12:25:55 PM PDT 24
Peak memory 198512 kb
Host smart-c960379c-c86b-4993-9c74-2004a936ba83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054476747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2054476747
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4214716136
Short name T62
Test name
Test status
Simulation time 20983288 ps
CPU time 0.74 seconds
Started Mar 14 12:25:52 PM PDT 24
Finished Mar 14 12:25:53 PM PDT 24
Peak memory 196920 kb
Host smart-04123898-bb8a-4347-a791-61419c21a17b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214716136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.4214716136
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3444360246
Short name T675
Test name
Test status
Simulation time 101622155 ps
CPU time 3.19 seconds
Started Mar 14 12:25:28 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 207696 kb
Host smart-1f8ee5b4-b01c-4774-8978-7f7b46d593f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444360246 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3444360246
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.4111119994
Short name T646
Test name
Test status
Simulation time 14901428 ps
CPU time 0.77 seconds
Started Mar 14 12:25:55 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 198640 kb
Host smart-c89ac7c2-5af1-48eb-bb90-d8611909a59f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111119994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.4111119994
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2347132187
Short name T734
Test name
Test status
Simulation time 17149567 ps
CPU time 0.61 seconds
Started Mar 14 12:25:50 PM PDT 24
Finished Mar 14 12:25:50 PM PDT 24
Peak memory 193900 kb
Host smart-77650ba5-fa09-42aa-abdc-4cf38f8d2b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347132187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2347132187
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.910034867
Short name T647
Test name
Test status
Simulation time 111907283 ps
CPU time 1.54 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:45 PM PDT 24
Peak memory 199320 kb
Host smart-b9ea93c6-ecd2-4a1f-b7ee-412f003006e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910034867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.910034867
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3172631305
Short name T627
Test name
Test status
Simulation time 24159130 ps
CPU time 1.09 seconds
Started Mar 14 12:25:36 PM PDT 24
Finished Mar 14 12:25:37 PM PDT 24
Peak memory 199308 kb
Host smart-858117d6-8530-4003-bd7b-1fd05a04f4fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172631305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3172631305
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3162655700
Short name T119
Test name
Test status
Simulation time 90231373 ps
CPU time 2.69 seconds
Started Mar 14 12:25:48 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 199328 kb
Host smart-cc9593fd-8c6c-4fec-af8a-cf0975167bce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162655700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3162655700
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1895754549
Short name T732
Test name
Test status
Simulation time 17391010 ps
CPU time 0.59 seconds
Started Mar 14 12:25:40 PM PDT 24
Finished Mar 14 12:25:40 PM PDT 24
Peak memory 193972 kb
Host smart-8e944a2b-8b9c-4c8d-8ad6-d2b7968348f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895754549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1895754549
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3725291316
Short name T735
Test name
Test status
Simulation time 14849648 ps
CPU time 0.59 seconds
Started Mar 14 12:25:41 PM PDT 24
Finished Mar 14 12:25:42 PM PDT 24
Peak memory 193992 kb
Host smart-6c681a71-7652-4c11-9ad1-6aa5ed2ae649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725291316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3725291316
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2038604568
Short name T655
Test name
Test status
Simulation time 14196200 ps
CPU time 0.62 seconds
Started Mar 14 12:25:40 PM PDT 24
Finished Mar 14 12:25:41 PM PDT 24
Peak memory 194020 kb
Host smart-6c7c3f12-188a-43ea-9bdc-cc17541ea1e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038604568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2038604568
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.548663642
Short name T726
Test name
Test status
Simulation time 179630439 ps
CPU time 0.63 seconds
Started Mar 14 12:25:50 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 194204 kb
Host smart-cd9e941d-6bda-406c-ba0a-486b151f89a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548663642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.548663642
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2015353424
Short name T615
Test name
Test status
Simulation time 16626141 ps
CPU time 0.58 seconds
Started Mar 14 12:25:55 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 194020 kb
Host smart-37b24c28-9a93-4f14-8eaa-a5efd1946b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015353424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2015353424
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2896861252
Short name T607
Test name
Test status
Simulation time 28211563 ps
CPU time 0.58 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:47 PM PDT 24
Peak memory 193908 kb
Host smart-edf32902-bf3c-49c7-b2b5-b151ffb8a574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896861252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2896861252
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.661685203
Short name T710
Test name
Test status
Simulation time 12863880 ps
CPU time 0.62 seconds
Started Mar 14 12:26:01 PM PDT 24
Finished Mar 14 12:26:01 PM PDT 24
Peak memory 194008 kb
Host smart-c6be4762-4045-42eb-a423-cc00c6a1bf03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661685203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.661685203
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2017955818
Short name T665
Test name
Test status
Simulation time 36484519 ps
CPU time 0.56 seconds
Started Mar 14 12:25:50 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 194016 kb
Host smart-8edb6752-d833-4fb6-8a1e-c4ce3f718dc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017955818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2017955818
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1236187220
Short name T617
Test name
Test status
Simulation time 16909368 ps
CPU time 0.62 seconds
Started Mar 14 12:25:55 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 194204 kb
Host smart-32984b36-adef-490d-b7b1-a7f226c36dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236187220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1236187220
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1875711181
Short name T630
Test name
Test status
Simulation time 18245771 ps
CPU time 0.59 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:34 PM PDT 24
Peak memory 193864 kb
Host smart-641a904e-39bb-4b9d-b635-4233f8982684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875711181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1875711181
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4211036102
Short name T730
Test name
Test status
Simulation time 120830246296 ps
CPU time 616.35 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:36:02 PM PDT 24
Peak memory 216964 kb
Host smart-f5719ccd-afb5-49d9-ae7f-1a8e38beb8ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211036102 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4211036102
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.702627984
Short name T101
Test name
Test status
Simulation time 112394114 ps
CPU time 0.9 seconds
Started Mar 14 12:25:28 PM PDT 24
Finished Mar 14 12:25:29 PM PDT 24
Peak memory 198884 kb
Host smart-aa9802f9-0dbb-4ccd-8719-55ec1237720b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702627984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.702627984
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3708702490
Short name T706
Test name
Test status
Simulation time 34866049 ps
CPU time 0.56 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:43 PM PDT 24
Peak memory 193860 kb
Host smart-2c5161b0-4c7a-4950-9526-e77a5b527761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708702490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3708702490
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.681319436
Short name T721
Test name
Test status
Simulation time 103423174 ps
CPU time 1.84 seconds
Started Mar 14 12:25:27 PM PDT 24
Finished Mar 14 12:25:29 PM PDT 24
Peak memory 199468 kb
Host smart-15316052-578d-4e08-830d-401e6ccae87c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681319436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.681319436
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.563715381
Short name T668
Test name
Test status
Simulation time 143558755 ps
CPU time 2.6 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:46 PM PDT 24
Peak memory 199340 kb
Host smart-f904d7c5-d6b2-4b76-8d02-6ad8d0b827f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563715381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.563715381
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2449501568
Short name T125
Test name
Test status
Simulation time 151362944 ps
CPU time 2.87 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:05 PM PDT 24
Peak memory 199360 kb
Host smart-07e5cc6b-5663-40cd-8ddc-deaa53866288
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449501568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2449501568
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.828477934
Short name T637
Test name
Test status
Simulation time 647104779101 ps
CPU time 629.45 seconds
Started Mar 14 12:25:39 PM PDT 24
Finished Mar 14 12:36:09 PM PDT 24
Peak memory 215888 kb
Host smart-4fbeff7e-ee4e-4bbf-b86d-705ced27c127
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828477934 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.828477934
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2149347369
Short name T631
Test name
Test status
Simulation time 118782437 ps
CPU time 0.92 seconds
Started Mar 14 12:25:31 PM PDT 24
Finished Mar 14 12:25:32 PM PDT 24
Peak memory 198900 kb
Host smart-9e293f1f-d3d7-4b0b-ad3a-9f0cf577fadb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149347369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2149347369
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.104979701
Short name T606
Test name
Test status
Simulation time 44812953 ps
CPU time 0.56 seconds
Started Mar 14 12:25:30 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 193924 kb
Host smart-c82c4c9e-430a-492b-aaf3-3a373f4ecfe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104979701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.104979701
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2993276047
Short name T673
Test name
Test status
Simulation time 24070885 ps
CPU time 1.06 seconds
Started Mar 14 12:25:33 PM PDT 24
Finished Mar 14 12:25:35 PM PDT 24
Peak memory 198852 kb
Host smart-f4375225-467b-4591-89f6-6f73e89ec856
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993276047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2993276047
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.486306205
Short name T623
Test name
Test status
Simulation time 266425483 ps
CPU time 1.52 seconds
Started Mar 14 12:25:49 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 199428 kb
Host smart-fe157c25-4215-4d76-b0db-087cf1a620ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486306205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.486306205
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3946852986
Short name T740
Test name
Test status
Simulation time 168797635 ps
CPU time 1.75 seconds
Started Mar 14 12:25:39 PM PDT 24
Finished Mar 14 12:25:41 PM PDT 24
Peak memory 199436 kb
Host smart-3db97fc6-e692-4d30-83bc-aa56db736d37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946852986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3946852986
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2227859972
Short name T707
Test name
Test status
Simulation time 101994522 ps
CPU time 1.63 seconds
Started Mar 14 12:25:34 PM PDT 24
Finished Mar 14 12:25:36 PM PDT 24
Peak memory 199472 kb
Host smart-53e47c70-8eb0-4ed2-8c1a-092bc1ee1653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227859972 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2227859972
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.682359558
Short name T724
Test name
Test status
Simulation time 132953556 ps
CPU time 0.92 seconds
Started Mar 14 12:25:34 PM PDT 24
Finished Mar 14 12:25:35 PM PDT 24
Peak memory 198668 kb
Host smart-ee75529c-2315-40c0-b029-136a817dce0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682359558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.682359558
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.224226062
Short name T713
Test name
Test status
Simulation time 13571226 ps
CPU time 0.56 seconds
Started Mar 14 12:25:42 PM PDT 24
Finished Mar 14 12:25:43 PM PDT 24
Peak memory 194188 kb
Host smart-3446c402-a19d-4e6f-a613-7a1ec1870b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224226062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.224226062
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2773733562
Short name T653
Test name
Test status
Simulation time 196124187 ps
CPU time 1.19 seconds
Started Mar 14 12:25:49 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 198428 kb
Host smart-ddc0c3fc-db51-4969-b067-eb77585d69dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773733562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2773733562
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2282454720
Short name T736
Test name
Test status
Simulation time 40104113 ps
CPU time 1.99 seconds
Started Mar 14 12:25:37 PM PDT 24
Finished Mar 14 12:25:39 PM PDT 24
Peak memory 199368 kb
Host smart-9ad29d65-b099-44cd-bbfb-6ff9c01ed39c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282454720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2282454720
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3709186770
Short name T123
Test name
Test status
Simulation time 245470597 ps
CPU time 3.79 seconds
Started Mar 14 12:25:35 PM PDT 24
Finished Mar 14 12:25:39 PM PDT 24
Peak memory 199328 kb
Host smart-b3376594-9608-4736-a116-66272f4daa1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709186770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3709186770
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2709266227
Short name T609
Test name
Test status
Simulation time 1862074038 ps
CPU time 27.42 seconds
Started Mar 14 12:25:34 PM PDT 24
Finished Mar 14 12:26:02 PM PDT 24
Peak memory 214824 kb
Host smart-0b654a10-4ef8-4ca8-931e-4cd8248a0fdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709266227 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2709266227
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.871454455
Short name T718
Test name
Test status
Simulation time 107319400 ps
CPU time 0.9 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 198352 kb
Host smart-b3f460cb-804a-473b-afa1-aad171906769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871454455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.871454455
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.783134791
Short name T669
Test name
Test status
Simulation time 18796612 ps
CPU time 0.65 seconds
Started Mar 14 12:25:42 PM PDT 24
Finished Mar 14 12:25:43 PM PDT 24
Peak memory 193960 kb
Host smart-e71c59dd-fef0-4cc3-b48c-2e178de3d85f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783134791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.783134791
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2836275072
Short name T64
Test name
Test status
Simulation time 48886395 ps
CPU time 2.01 seconds
Started Mar 14 12:25:29 PM PDT 24
Finished Mar 14 12:25:31 PM PDT 24
Peak memory 199072 kb
Host smart-33f452ed-c457-4f16-95d1-e00e902efaf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836275072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2836275072
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3593563777
Short name T664
Test name
Test status
Simulation time 68665033 ps
CPU time 3.82 seconds
Started Mar 14 12:25:56 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 199452 kb
Host smart-be0d8bc7-45b0-4f4d-a641-95baf326595b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593563777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3593563777
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3052608376
Short name T660
Test name
Test status
Simulation time 585375158 ps
CPU time 2.97 seconds
Started Mar 14 12:25:32 PM PDT 24
Finished Mar 14 12:25:35 PM PDT 24
Peak memory 199392 kb
Host smart-376732a0-857b-463f-8d4a-b120c8f229f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052608376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3052608376
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.512155743
Short name T691
Test name
Test status
Simulation time 26645597 ps
CPU time 1.43 seconds
Started Mar 14 12:25:39 PM PDT 24
Finished Mar 14 12:25:41 PM PDT 24
Peak memory 199424 kb
Host smart-4cd6c50f-c835-4fd0-a3d8-8fc143ebb97e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512155743 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.512155743
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1835515944
Short name T95
Test name
Test status
Simulation time 175830419 ps
CPU time 0.91 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 199096 kb
Host smart-44923c9c-5b31-499f-bf50-a52efb9880f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835515944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1835515944
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2021187684
Short name T619
Test name
Test status
Simulation time 80106226 ps
CPU time 0.6 seconds
Started Mar 14 12:25:43 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 193880 kb
Host smart-eea8ce7b-13d8-497f-befc-095be6348cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021187684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2021187684
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3057786344
Short name T614
Test name
Test status
Simulation time 181322986 ps
CPU time 2.12 seconds
Started Mar 14 12:25:42 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 198968 kb
Host smart-4978bd7c-fd49-4472-95e6-807b5248e93b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057786344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3057786344
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1362982710
Short name T681
Test name
Test status
Simulation time 46062938 ps
CPU time 2.48 seconds
Started Mar 14 12:25:52 PM PDT 24
Finished Mar 14 12:25:55 PM PDT 24
Peak memory 199412 kb
Host smart-7268974b-2b99-4e31-9495-61617e7a5d38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362982710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1362982710
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3146209507
Short name T127
Test name
Test status
Simulation time 363390803 ps
CPU time 2.84 seconds
Started Mar 14 12:25:51 PM PDT 24
Finished Mar 14 12:25:54 PM PDT 24
Peak memory 199400 kb
Host smart-b4b9c599-1d69-4e3e-b320-43ca97f22453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146209507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3146209507
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3962294184
Short name T187
Test name
Test status
Simulation time 13165602 ps
CPU time 0.54 seconds
Started Mar 14 12:39:31 PM PDT 24
Finished Mar 14 12:39:33 PM PDT 24
Peak memory 195624 kb
Host smart-c1aeb024-8126-4f31-b1ca-cbab117f194b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962294184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3962294184
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1431524803
Short name T599
Test name
Test status
Simulation time 641354821 ps
CPU time 23.99 seconds
Started Mar 14 12:39:23 PM PDT 24
Finished Mar 14 12:39:48 PM PDT 24
Peak memory 223708 kb
Host smart-ab7edd7c-0336-44af-afb6-d796fcd11060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1431524803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1431524803
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2154787096
Short name T186
Test name
Test status
Simulation time 1229740777 ps
CPU time 6.27 seconds
Started Mar 14 12:39:23 PM PDT 24
Finished Mar 14 12:39:30 PM PDT 24
Peak memory 200052 kb
Host smart-e96750e4-1912-4bef-beb7-86196fe42026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154787096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2154787096
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3242935918
Short name T447
Test name
Test status
Simulation time 234044769 ps
CPU time 13.28 seconds
Started Mar 14 12:39:19 PM PDT 24
Finished Mar 14 12:39:34 PM PDT 24
Peak memory 199976 kb
Host smart-ac940d69-c589-4d24-bad3-1d5cfab6babc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3242935918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3242935918
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.786551535
Short name T46
Test name
Test status
Simulation time 927277442 ps
CPU time 47.55 seconds
Started Mar 14 12:39:24 PM PDT 24
Finished Mar 14 12:40:11 PM PDT 24
Peak memory 199880 kb
Host smart-9b38cf1b-d2a0-4a7d-8fa1-eb2ab94ca545
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786551535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.786551535
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2262940114
Short name T138
Test name
Test status
Simulation time 3619642848 ps
CPU time 57.42 seconds
Started Mar 14 12:39:23 PM PDT 24
Finished Mar 14 12:40:20 PM PDT 24
Peak memory 199980 kb
Host smart-a7bbe760-6015-4cdf-b62f-ec4ccdb99c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262940114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2262940114
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1195170036
Short name T489
Test name
Test status
Simulation time 294382604 ps
CPU time 3.69 seconds
Started Mar 14 12:39:23 PM PDT 24
Finished Mar 14 12:39:27 PM PDT 24
Peak memory 200028 kb
Host smart-0f2c7bfc-9097-41ae-9f83-11fefd4d1a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195170036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1195170036
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.2933177149
Short name T369
Test name
Test status
Simulation time 512214145 ps
CPU time 1.2 seconds
Started Mar 14 12:39:33 PM PDT 24
Finished Mar 14 12:39:34 PM PDT 24
Peak memory 200032 kb
Host smart-5cbe5599-d4d7-42b2-9d88-2daff5a0b1ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933177149 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.2933177149
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.4004134176
Short name T460
Test name
Test status
Simulation time 36741077620 ps
CPU time 460.62 seconds
Started Mar 14 12:39:30 PM PDT 24
Finished Mar 14 12:47:11 PM PDT 24
Peak memory 200092 kb
Host smart-fab00954-627b-42d2-b22d-e0e454911dd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004134176 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.4004134176
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3780750342
Short name T571
Test name
Test status
Simulation time 4937215384 ps
CPU time 55.12 seconds
Started Mar 14 12:39:23 PM PDT 24
Finished Mar 14 12:40:19 PM PDT 24
Peak memory 200068 kb
Host smart-7b49052c-148c-485f-809c-cc60d19d545b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780750342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3780750342
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3998256313
Short name T453
Test name
Test status
Simulation time 19138266 ps
CPU time 0.56 seconds
Started Mar 14 12:39:43 PM PDT 24
Finished Mar 14 12:39:43 PM PDT 24
Peak memory 195628 kb
Host smart-67f812b1-5d53-4e28-9e34-7c4fda6243e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998256313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3998256313
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.411377505
Short name T51
Test name
Test status
Simulation time 4908400197 ps
CPU time 43.42 seconds
Started Mar 14 12:39:32 PM PDT 24
Finished Mar 14 12:40:16 PM PDT 24
Peak memory 222664 kb
Host smart-66d3ef70-4bb6-4cf2-acdf-e0dd67cfc100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411377505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.411377505
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2785366924
Short name T449
Test name
Test status
Simulation time 17865970218 ps
CPU time 52.78 seconds
Started Mar 14 12:39:30 PM PDT 24
Finished Mar 14 12:40:23 PM PDT 24
Peak memory 199996 kb
Host smart-3396595c-684b-43ec-89f5-e99c60cb8dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785366924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2785366924
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2054966317
Short name T556
Test name
Test status
Simulation time 2076684612 ps
CPU time 51.17 seconds
Started Mar 14 12:39:29 PM PDT 24
Finished Mar 14 12:40:21 PM PDT 24
Peak memory 200036 kb
Host smart-43511b19-1c4e-4239-a2b8-4f1f7c17fa4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054966317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2054966317
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3070830425
Short name T47
Test name
Test status
Simulation time 5955252380 ps
CPU time 160.47 seconds
Started Mar 14 12:39:30 PM PDT 24
Finished Mar 14 12:42:10 PM PDT 24
Peak memory 199960 kb
Host smart-d0c38a77-8366-42c4-98de-d765c4ff6098
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070830425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3070830425
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.4119466260
Short name T414
Test name
Test status
Simulation time 1741544195 ps
CPU time 6.21 seconds
Started Mar 14 12:39:31 PM PDT 24
Finished Mar 14 12:39:38 PM PDT 24
Peak memory 199864 kb
Host smart-86cc01ed-a6fb-4ac9-9677-de19529270b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119466260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4119466260
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3878308038
Short name T32
Test name
Test status
Simulation time 54780649 ps
CPU time 0.85 seconds
Started Mar 14 12:39:40 PM PDT 24
Finished Mar 14 12:39:41 PM PDT 24
Peak memory 218232 kb
Host smart-9d5da2fc-0a8d-4184-b7be-36dc843e5ba8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878308038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3878308038
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2422395775
Short name T178
Test name
Test status
Simulation time 148782687 ps
CPU time 4.33 seconds
Started Mar 14 12:39:31 PM PDT 24
Finished Mar 14 12:39:37 PM PDT 24
Peak memory 199872 kb
Host smart-b415c053-fa7f-49ed-b850-df58587c411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422395775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2422395775
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1345648633
Short name T507
Test name
Test status
Simulation time 91805946764 ps
CPU time 378.92 seconds
Started Mar 14 12:39:42 PM PDT 24
Finished Mar 14 12:46:01 PM PDT 24
Peak memory 199908 kb
Host smart-d73a84bd-d200-43a2-b17c-4665fcdf7555
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345648633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1345648633
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.791779183
Short name T81
Test name
Test status
Simulation time 20453536071 ps
CPU time 153.51 seconds
Started Mar 14 12:39:42 PM PDT 24
Finished Mar 14 12:42:16 PM PDT 24
Peak memory 213412 kb
Host smart-3a1a77fb-f983-4088-84ee-35c9141bb8f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791779183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.791779183
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1681077619
Short name T19
Test name
Test status
Simulation time 61567023 ps
CPU time 1.18 seconds
Started Mar 14 12:39:40 PM PDT 24
Finished Mar 14 12:39:41 PM PDT 24
Peak memory 200044 kb
Host smart-4570f131-4b41-426c-9084-93eac7ff7299
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681077619 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1681077619
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3312655273
Short name T525
Test name
Test status
Simulation time 8391905818 ps
CPU time 463.33 seconds
Started Mar 14 12:39:30 PM PDT 24
Finished Mar 14 12:47:14 PM PDT 24
Peak memory 200124 kb
Host smart-cdfe68bd-24cd-4963-8cbb-4ca638c3dedf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312655273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.3312655273
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.4165632310
Short name T42
Test name
Test status
Simulation time 11800766619 ps
CPU time 74.87 seconds
Started Mar 14 12:39:30 PM PDT 24
Finished Mar 14 12:40:45 PM PDT 24
Peak memory 200092 kb
Host smart-fefe88c4-1541-460f-9f26-04d48021b598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165632310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.4165632310
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.30920566
Short name T128
Test name
Test status
Simulation time 5340383302 ps
CPU time 31.59 seconds
Started Mar 14 12:40:33 PM PDT 24
Finished Mar 14 12:41:05 PM PDT 24
Peak memory 248572 kb
Host smart-743e6301-cbc0-41b6-ad85-5db3c70641cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30920566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.30920566
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3910271112
Short name T394
Test name
Test status
Simulation time 3117771026 ps
CPU time 25.57 seconds
Started Mar 14 12:40:33 PM PDT 24
Finished Mar 14 12:40:58 PM PDT 24
Peak memory 199996 kb
Host smart-4116328d-9980-42a8-a6de-b0b4560e8617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910271112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3910271112
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.559251484
Short name T401
Test name
Test status
Simulation time 1060536028 ps
CPU time 28.84 seconds
Started Mar 14 12:40:32 PM PDT 24
Finished Mar 14 12:41:01 PM PDT 24
Peak memory 199968 kb
Host smart-90a7b62a-781c-44f0-89fd-6de8bb9dff4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559251484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.559251484
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2501535624
Short name T559
Test name
Test status
Simulation time 562475099 ps
CPU time 19.29 seconds
Started Mar 14 12:40:32 PM PDT 24
Finished Mar 14 12:40:51 PM PDT 24
Peak memory 199968 kb
Host smart-13eb64c3-b4e9-4ded-9407-3593ec39f907
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501535624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2501535624
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.157409107
Short name T92
Test name
Test status
Simulation time 2988877089 ps
CPU time 75.62 seconds
Started Mar 14 12:40:30 PM PDT 24
Finished Mar 14 12:41:46 PM PDT 24
Peak memory 200012 kb
Host smart-75b0964c-8a59-4ee3-ac75-f3a5730a0f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157409107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.157409107
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1557193447
Short name T44
Test name
Test status
Simulation time 1768558386 ps
CPU time 6.5 seconds
Started Mar 14 12:40:34 PM PDT 24
Finished Mar 14 12:40:40 PM PDT 24
Peak memory 200052 kb
Host smart-4f936902-db99-48da-a369-03ffc8f4d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557193447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1557193447
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3121888139
Short name T512
Test name
Test status
Simulation time 18783576330 ps
CPU time 941.01 seconds
Started Mar 14 12:40:41 PM PDT 24
Finished Mar 14 12:56:23 PM PDT 24
Peak memory 229840 kb
Host smart-fb5428eb-ea78-4222-b555-bf573b3eb57f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121888139 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3121888139
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1687256018
Short name T139
Test name
Test status
Simulation time 1126681066 ps
CPU time 1.25 seconds
Started Mar 14 12:40:39 PM PDT 24
Finished Mar 14 12:40:41 PM PDT 24
Peak memory 199704 kb
Host smart-98d6ef8a-db0d-4ffa-b89b-64de1b341215
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687256018 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1687256018
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.796172139
Short name T209
Test name
Test status
Simulation time 24093453003 ps
CPU time 447.31 seconds
Started Mar 14 12:40:33 PM PDT 24
Finished Mar 14 12:48:00 PM PDT 24
Peak memory 200096 kb
Host smart-e3886407-457b-408a-acdd-c90a5eda138a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796172139 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.796172139
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1236862095
Short name T591
Test name
Test status
Simulation time 4799017501 ps
CPU time 63.81 seconds
Started Mar 14 12:40:34 PM PDT 24
Finished Mar 14 12:41:38 PM PDT 24
Peak memory 200052 kb
Host smart-447c07cc-b446-444a-962c-1c69f16da997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236862095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1236862095
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.3735066565
Short name T14
Test name
Test status
Simulation time 59858154548 ps
CPU time 1598.07 seconds
Started Mar 14 12:43:40 PM PDT 24
Finished Mar 14 01:10:18 PM PDT 24
Peak memory 232864 kb
Host smart-e70182b0-7eea-4b44-a69f-fe180a0d446f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735066565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.3735066565
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.942995260
Short name T558
Test name
Test status
Simulation time 17818385 ps
CPU time 0.56 seconds
Started Mar 14 12:40:40 PM PDT 24
Finished Mar 14 12:40:41 PM PDT 24
Peak memory 195672 kb
Host smart-0f0f0be1-125b-458e-a6e6-2600222e4b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942995260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.942995260
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3850278711
Short name T450
Test name
Test status
Simulation time 3649205941 ps
CPU time 42.45 seconds
Started Mar 14 12:40:40 PM PDT 24
Finished Mar 14 12:41:23 PM PDT 24
Peak memory 241060 kb
Host smart-d5b35e5d-de14-44ad-90d0-a8a0fd7b64f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850278711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3850278711
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2417494100
Short name T204
Test name
Test status
Simulation time 2716256803 ps
CPU time 40.74 seconds
Started Mar 14 12:40:41 PM PDT 24
Finished Mar 14 12:41:23 PM PDT 24
Peak memory 200060 kb
Host smart-cd4efbaf-824f-4c3c-9924-12f0596e6467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417494100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2417494100
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2537432877
Short name T233
Test name
Test status
Simulation time 742004869 ps
CPU time 41.01 seconds
Started Mar 14 12:40:39 PM PDT 24
Finished Mar 14 12:41:21 PM PDT 24
Peak memory 200040 kb
Host smart-0603aef2-c206-4543-81b9-7691d8847c20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2537432877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2537432877
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.4080174873
Short name T143
Test name
Test status
Simulation time 36690253643 ps
CPU time 40.23 seconds
Started Mar 14 12:40:42 PM PDT 24
Finished Mar 14 12:41:22 PM PDT 24
Peak memory 199832 kb
Host smart-f6647cac-7e55-41e8-9a2b-6f96e6caf156
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080174873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.4080174873
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3179036259
Short name T256
Test name
Test status
Simulation time 1079918835 ps
CPU time 61.68 seconds
Started Mar 14 12:40:43 PM PDT 24
Finished Mar 14 12:41:46 PM PDT 24
Peak memory 199808 kb
Host smart-d043087f-9c9c-451f-9830-5c7571e55b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179036259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3179036259
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.64697510
Short name T523
Test name
Test status
Simulation time 713528490 ps
CPU time 5.72 seconds
Started Mar 14 12:40:42 PM PDT 24
Finished Mar 14 12:40:48 PM PDT 24
Peak memory 199972 kb
Host smart-873722b8-8e1f-4c0b-bfe7-d09726c2cf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64697510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.64697510
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1868672343
Short name T313
Test name
Test status
Simulation time 24748268140 ps
CPU time 333.23 seconds
Started Mar 14 12:40:41 PM PDT 24
Finished Mar 14 12:46:15 PM PDT 24
Peak memory 200024 kb
Host smart-63cd9546-ec7c-4895-8fa8-3d7ec122cc28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868672343 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1868672343
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3227952802
Short name T323
Test name
Test status
Simulation time 65797424 ps
CPU time 1.19 seconds
Started Mar 14 12:40:42 PM PDT 24
Finished Mar 14 12:40:44 PM PDT 24
Peak memory 199576 kb
Host smart-f00822d0-2100-473a-9226-accf115902aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227952802 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3227952802
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3711978517
Short name T398
Test name
Test status
Simulation time 34668172231 ps
CPU time 466.86 seconds
Started Mar 14 12:40:42 PM PDT 24
Finished Mar 14 12:48:29 PM PDT 24
Peak memory 199996 kb
Host smart-4174c4d2-4fd6-4035-89f8-d76eb413dcbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711978517 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3711978517
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1575465871
Short name T446
Test name
Test status
Simulation time 964279287 ps
CPU time 46.76 seconds
Started Mar 14 12:40:41 PM PDT 24
Finished Mar 14 12:41:28 PM PDT 24
Peak memory 199948 kb
Host smart-85f41182-bca5-4d30-b53c-c25e1d80fe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575465871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1575465871
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.527040949
Short name T377
Test name
Test status
Simulation time 86175254770 ps
CPU time 4115.98 seconds
Started Mar 14 12:43:35 PM PDT 24
Finished Mar 14 01:52:11 PM PDT 24
Peak memory 259472 kb
Host smart-b10a1f17-5138-4b2c-9cfc-4967427057a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=527040949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.527040949
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1933025816
Short name T393
Test name
Test status
Simulation time 13315363 ps
CPU time 0.55 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:40:52 PM PDT 24
Peak memory 195536 kb
Host smart-40e25216-9e85-40a5-bfae-8030d0475488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933025816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1933025816
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.201556863
Short name T245
Test name
Test status
Simulation time 1318684577 ps
CPU time 11.84 seconds
Started Mar 14 12:40:52 PM PDT 24
Finished Mar 14 12:41:04 PM PDT 24
Peak memory 208108 kb
Host smart-57009904-b376-4673-8c7d-45b0e615a46e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201556863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.201556863
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.305081589
Short name T358
Test name
Test status
Simulation time 818440173 ps
CPU time 39.91 seconds
Started Mar 14 12:40:49 PM PDT 24
Finished Mar 14 12:41:29 PM PDT 24
Peak memory 199944 kb
Host smart-bbb89d3e-c255-4221-939c-30742bfa9721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305081589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.305081589
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2055666145
Short name T348
Test name
Test status
Simulation time 2313072329 ps
CPU time 121.31 seconds
Started Mar 14 12:40:50 PM PDT 24
Finished Mar 14 12:42:51 PM PDT 24
Peak memory 200004 kb
Host smart-a532988c-2f25-44e6-a4da-5b450783c1c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055666145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2055666145
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3268211787
Short name T542
Test name
Test status
Simulation time 11963227497 ps
CPU time 167.21 seconds
Started Mar 14 12:40:50 PM PDT 24
Finished Mar 14 12:43:37 PM PDT 24
Peak memory 200072 kb
Host smart-6a05a62d-e2a8-45ca-ab2b-7ce57ecb9836
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268211787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3268211787
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1749909846
Short name T426
Test name
Test status
Simulation time 197295882 ps
CPU time 4.17 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:40:55 PM PDT 24
Peak memory 200000 kb
Host smart-542acb8c-af77-4879-80e7-316ef8696000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749909846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1749909846
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1118650311
Short name T494
Test name
Test status
Simulation time 138048185 ps
CPU time 4.19 seconds
Started Mar 14 12:40:50 PM PDT 24
Finished Mar 14 12:40:54 PM PDT 24
Peak memory 199836 kb
Host smart-84b5439e-68a1-49e0-8027-c9da12939050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118650311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1118650311
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2729895472
Short name T459
Test name
Test status
Simulation time 67652841525 ps
CPU time 969.28 seconds
Started Mar 14 12:40:50 PM PDT 24
Finished Mar 14 12:57:00 PM PDT 24
Peak memory 248056 kb
Host smart-daa22e49-c057-40d8-b272-d5f5237edc4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729895472 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2729895472
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3285680086
Short name T429
Test name
Test status
Simulation time 26254762 ps
CPU time 0.93 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:40:52 PM PDT 24
Peak memory 198584 kb
Host smart-bb07f3c0-ec48-45b2-a129-e352afae28c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285680086 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.3285680086
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1571191692
Short name T335
Test name
Test status
Simulation time 26730499774 ps
CPU time 453.06 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:48:24 PM PDT 24
Peak memory 200092 kb
Host smart-5bf85f67-7ce2-48d3-b7f1-90a5ee7b1a25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571191692 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.1571191692
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3403761455
Short name T236
Test name
Test status
Simulation time 581982030 ps
CPU time 9.71 seconds
Started Mar 14 12:40:54 PM PDT 24
Finished Mar 14 12:41:04 PM PDT 24
Peak memory 200020 kb
Host smart-fd579bd6-3cbf-467d-ba8c-3c6317db996d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403761455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3403761455
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.1407850456
Short name T67
Test name
Test status
Simulation time 82084625151 ps
CPU time 653 seconds
Started Mar 14 12:43:38 PM PDT 24
Finished Mar 14 12:54:31 PM PDT 24
Peak memory 209288 kb
Host smart-afd58937-f5bf-4c08-9cfa-af420a1c809b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1407850456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.1407850456
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2873293107
Short name T307
Test name
Test status
Simulation time 12194952 ps
CPU time 0.56 seconds
Started Mar 14 12:40:50 PM PDT 24
Finished Mar 14 12:40:51 PM PDT 24
Peak memory 195644 kb
Host smart-58100f9a-70d6-46e8-b5e3-aea2c1b99ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873293107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2873293107
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.897173479
Short name T301
Test name
Test status
Simulation time 2592518465 ps
CPU time 45.15 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:41:37 PM PDT 24
Peak memory 215500 kb
Host smart-59d37935-d718-4fc0-aace-fcad5e2559db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=897173479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.897173479
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3701220823
Short name T217
Test name
Test status
Simulation time 1209047863 ps
CPU time 56.3 seconds
Started Mar 14 12:40:50 PM PDT 24
Finished Mar 14 12:41:47 PM PDT 24
Peak memory 200032 kb
Host smart-d21d4066-c6d7-48f0-b2ff-4d52f62fde18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701220823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3701220823
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.616171781
Short name T185
Test name
Test status
Simulation time 3963610657 ps
CPU time 68.16 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:42:00 PM PDT 24
Peak memory 199896 kb
Host smart-64b992b1-7c8e-412a-a208-32b80e2bbb8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616171781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.616171781
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3494342812
Short name T156
Test name
Test status
Simulation time 13123728389 ps
CPU time 56.63 seconds
Started Mar 14 12:40:50 PM PDT 24
Finished Mar 14 12:41:47 PM PDT 24
Peak memory 200116 kb
Host smart-fad3d178-e76f-44fa-b5b9-e381ff36728a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494342812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3494342812
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2728307876
Short name T268
Test name
Test status
Simulation time 3345428883 ps
CPU time 45.47 seconds
Started Mar 14 12:40:52 PM PDT 24
Finished Mar 14 12:41:38 PM PDT 24
Peak memory 200088 kb
Host smart-20a0df7c-f1ab-4836-97a1-8329f4ac8ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728307876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2728307876
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.4291626310
Short name T291
Test name
Test status
Simulation time 812745448 ps
CPU time 4.76 seconds
Started Mar 14 12:40:50 PM PDT 24
Finished Mar 14 12:40:55 PM PDT 24
Peak memory 200024 kb
Host smart-5a8465b0-44cf-405d-8f03-d86a7ed430a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291626310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.4291626310
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2869695340
Short name T356
Test name
Test status
Simulation time 27606303863 ps
CPU time 685.38 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:52:16 PM PDT 24
Peak memory 248692 kb
Host smart-8e519359-9d06-4675-8329-3e96cdeb0614
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869695340 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2869695340
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1695813330
Short name T181
Test name
Test status
Simulation time 98683160 ps
CPU time 0.93 seconds
Started Mar 14 12:40:49 PM PDT 24
Finished Mar 14 12:40:50 PM PDT 24
Peak memory 199388 kb
Host smart-92b5945d-cc24-4d1d-96fb-3e05d3677863
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695813330 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.1695813330
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.117412255
Short name T363
Test name
Test status
Simulation time 279798375510 ps
CPU time 446.29 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:48:17 PM PDT 24
Peak memory 199976 kb
Host smart-c6127a2a-e94e-4b45-8cdd-4ba4830c4930
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117412255 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.117412255
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1584168769
Short name T161
Test name
Test status
Simulation time 17927751785 ps
CPU time 13.6 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:41:04 PM PDT 24
Peak memory 200052 kb
Host smart-c2c7d669-7821-4655-8633-24031dd6c837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584168769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1584168769
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1339684724
Short name T487
Test name
Test status
Simulation time 43852993 ps
CPU time 0.57 seconds
Started Mar 14 12:41:00 PM PDT 24
Finished Mar 14 12:41:03 PM PDT 24
Peak memory 194380 kb
Host smart-041c9da9-a1b0-46a3-ad7e-86831811ea03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339684724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1339684724
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3188755063
Short name T585
Test name
Test status
Simulation time 1566975237 ps
CPU time 58.32 seconds
Started Mar 14 12:40:54 PM PDT 24
Finished Mar 14 12:41:53 PM PDT 24
Peak memory 228576 kb
Host smart-7332059b-b1d5-4609-a44a-20d510e83d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188755063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3188755063
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.162213382
Short name T257
Test name
Test status
Simulation time 1113631124 ps
CPU time 15.98 seconds
Started Mar 14 12:40:50 PM PDT 24
Finished Mar 14 12:41:06 PM PDT 24
Peak memory 199948 kb
Host smart-2f954547-ec55-4c44-8075-d342dc035a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162213382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.162213382
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.278411827
Short name T252
Test name
Test status
Simulation time 449645926 ps
CPU time 5.92 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:40:57 PM PDT 24
Peak memory 199928 kb
Host smart-a465f596-4da5-43dd-9800-bb85644c9445
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278411827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.278411827
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.4197070619
Short name T499
Test name
Test status
Simulation time 27047447322 ps
CPU time 115.1 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:42:46 PM PDT 24
Peak memory 200076 kb
Host smart-8684e47d-20da-4f77-96dd-882dd4c99d67
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197070619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.4197070619
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.261128183
Short name T164
Test name
Test status
Simulation time 8596270718 ps
CPU time 55.32 seconds
Started Mar 14 12:40:51 PM PDT 24
Finished Mar 14 12:41:46 PM PDT 24
Peak memory 199988 kb
Host smart-45ca95d2-6086-433c-b9b6-7a24b81bb569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261128183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.261128183
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3521716048
Short name T436
Test name
Test status
Simulation time 554277442 ps
CPU time 5.81 seconds
Started Mar 14 12:40:54 PM PDT 24
Finished Mar 14 12:40:59 PM PDT 24
Peak memory 199900 kb
Host smart-0858c594-b59c-434e-adac-bd2b808a3c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521716048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3521716048
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.113495843
Short name T506
Test name
Test status
Simulation time 2682809511 ps
CPU time 24.33 seconds
Started Mar 14 12:41:01 PM PDT 24
Finished Mar 14 12:41:26 PM PDT 24
Peak memory 208280 kb
Host smart-61a3caaa-c638-4868-a2d3-063d4f985f80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113495843 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.113495843
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.2160228445
Short name T66
Test name
Test status
Simulation time 146843753334 ps
CPU time 2021.93 seconds
Started Mar 14 12:41:03 PM PDT 24
Finished Mar 14 01:14:45 PM PDT 24
Peak memory 265008 kb
Host smart-5150cea6-a00b-401e-9a02-c2e540d62133
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2160228445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.2160228445
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.364720521
Short name T444
Test name
Test status
Simulation time 106784543 ps
CPU time 1.15 seconds
Started Mar 14 12:40:58 PM PDT 24
Finished Mar 14 12:41:00 PM PDT 24
Peak memory 199736 kb
Host smart-b872cf50-6c88-4cb6-8b58-99d7553ddb40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364720521 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.364720521
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1934797184
Short name T104
Test name
Test status
Simulation time 24323707409 ps
CPU time 408.23 seconds
Started Mar 14 12:41:02 PM PDT 24
Finished Mar 14 12:47:50 PM PDT 24
Peak memory 200048 kb
Host smart-48780859-6375-4dae-9d31-03a62a2aaaa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934797184 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1934797184
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4023184934
Short name T239
Test name
Test status
Simulation time 409412581 ps
CPU time 11.74 seconds
Started Mar 14 12:40:54 PM PDT 24
Finished Mar 14 12:41:06 PM PDT 24
Peak memory 199964 kb
Host smart-9420ebe2-e2c3-499b-b99f-fdcb0587a25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023184934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4023184934
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.257512160
Short name T331
Test name
Test status
Simulation time 34641173 ps
CPU time 0.58 seconds
Started Mar 14 12:41:00 PM PDT 24
Finished Mar 14 12:41:03 PM PDT 24
Peak memory 195644 kb
Host smart-430468ed-0d7e-450f-aefa-9642eda4b18d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257512160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.257512160
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.178626786
Short name T241
Test name
Test status
Simulation time 294171890 ps
CPU time 2.59 seconds
Started Mar 14 12:41:02 PM PDT 24
Finished Mar 14 12:41:05 PM PDT 24
Peak memory 199792 kb
Host smart-7cb8ad05-a9ff-49ba-abb5-786bee6740ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=178626786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.178626786
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.4065957867
Short name T350
Test name
Test status
Simulation time 1226189462 ps
CPU time 56.29 seconds
Started Mar 14 12:41:00 PM PDT 24
Finished Mar 14 12:41:58 PM PDT 24
Peak memory 200032 kb
Host smart-cebeeec6-2b3a-41ef-9b15-75d3291e3834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065957867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.4065957867
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3891839910
Short name T325
Test name
Test status
Simulation time 8795321384 ps
CPU time 106.22 seconds
Started Mar 14 12:40:58 PM PDT 24
Finished Mar 14 12:42:45 PM PDT 24
Peak memory 200104 kb
Host smart-620a29f4-e329-463c-a423-de09f7988ac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891839910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3891839910
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.4248368212
Short name T36
Test name
Test status
Simulation time 10449798449 ps
CPU time 93.08 seconds
Started Mar 14 12:41:00 PM PDT 24
Finished Mar 14 12:42:35 PM PDT 24
Peak memory 199968 kb
Host smart-28e9629b-3d0a-46a3-974e-d8fa7ba5d638
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248368212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.4248368212
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.562193675
Short name T197
Test name
Test status
Simulation time 2482498843 ps
CPU time 68.69 seconds
Started Mar 14 12:41:01 PM PDT 24
Finished Mar 14 12:42:11 PM PDT 24
Peak memory 199944 kb
Host smart-996bd2e1-1082-4dbc-81dc-e1093e983e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562193675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.562193675
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2362509236
Short name T592
Test name
Test status
Simulation time 4089683051 ps
CPU time 6.87 seconds
Started Mar 14 12:40:59 PM PDT 24
Finished Mar 14 12:41:06 PM PDT 24
Peak memory 200096 kb
Host smart-56a513d9-428f-4892-add3-fbc95227cc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362509236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2362509236
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3641029527
Short name T29
Test name
Test status
Simulation time 30229253372 ps
CPU time 174.22 seconds
Started Mar 14 12:40:58 PM PDT 24
Finished Mar 14 12:43:53 PM PDT 24
Peak memory 215816 kb
Host smart-0150aa23-ee33-43cb-8c68-c5d50a492528
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641029527 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3641029527
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.189097749
Short name T11
Test name
Test status
Simulation time 19272233570 ps
CPU time 536.61 seconds
Started Mar 14 12:41:01 PM PDT 24
Finished Mar 14 12:49:59 PM PDT 24
Peak memory 208292 kb
Host smart-5060a512-6b13-4dfd-a385-1bfd2565b12d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=189097749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.189097749
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2988135839
Short name T136
Test name
Test status
Simulation time 173490877 ps
CPU time 0.98 seconds
Started Mar 14 12:41:00 PM PDT 24
Finished Mar 14 12:41:03 PM PDT 24
Peak memory 199376 kb
Host smart-c811466a-df44-4342-b55d-110fa9a02f0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988135839 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.2988135839
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.486830529
Short name T190
Test name
Test status
Simulation time 107390066560 ps
CPU time 463.69 seconds
Started Mar 14 12:41:00 PM PDT 24
Finished Mar 14 12:48:46 PM PDT 24
Peak memory 199984 kb
Host smart-32cf5988-2e90-4e56-87f9-70727b7be4f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486830529 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.486830529
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3189042080
Short name T153
Test name
Test status
Simulation time 14630227435 ps
CPU time 65.54 seconds
Started Mar 14 12:40:58 PM PDT 24
Finished Mar 14 12:42:05 PM PDT 24
Peak memory 200052 kb
Host smart-d05bb338-5ebf-4fbf-aa01-5c023f0f3648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189042080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3189042080
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3050353379
Short name T87
Test name
Test status
Simulation time 14602819 ps
CPU time 0.55 seconds
Started Mar 14 12:41:12 PM PDT 24
Finished Mar 14 12:41:14 PM PDT 24
Peak memory 194488 kb
Host smart-5ab787ac-364a-40db-80bc-12b791eae958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050353379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3050353379
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1348337115
Short name T56
Test name
Test status
Simulation time 1223771333 ps
CPU time 46.19 seconds
Started Mar 14 12:40:58 PM PDT 24
Finished Mar 14 12:41:45 PM PDT 24
Peak memory 224576 kb
Host smart-8ebab4f4-fef1-4812-b6a3-68e5a2d5cba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1348337115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1348337115
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2489976309
Short name T167
Test name
Test status
Simulation time 2279104556 ps
CPU time 42.91 seconds
Started Mar 14 12:40:59 PM PDT 24
Finished Mar 14 12:41:42 PM PDT 24
Peak memory 199984 kb
Host smart-573b27b2-727c-4ab2-b04c-70f685be5653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489976309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2489976309
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1208054083
Short name T254
Test name
Test status
Simulation time 174616922 ps
CPU time 9.25 seconds
Started Mar 14 12:41:00 PM PDT 24
Finished Mar 14 12:41:11 PM PDT 24
Peak memory 200032 kb
Host smart-020c920e-e2e6-4069-9637-edd214f317f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208054083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1208054083
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.989542981
Short name T452
Test name
Test status
Simulation time 29833332092 ps
CPU time 119.79 seconds
Started Mar 14 12:41:10 PM PDT 24
Finished Mar 14 12:43:11 PM PDT 24
Peak memory 199892 kb
Host smart-e00dbf85-ce33-4812-9a03-9eb66fe4bceb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989542981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.989542981
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2310468913
Short name T488
Test name
Test status
Simulation time 1089100778 ps
CPU time 10.53 seconds
Started Mar 14 12:41:00 PM PDT 24
Finished Mar 14 12:41:13 PM PDT 24
Peak memory 199940 kb
Host smart-ad944c55-21b9-4b67-aab1-0edb393e8331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310468913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2310468913
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3384961368
Short name T577
Test name
Test status
Simulation time 551339999 ps
CPU time 6.2 seconds
Started Mar 14 12:40:59 PM PDT 24
Finished Mar 14 12:41:05 PM PDT 24
Peak memory 200072 kb
Host smart-52981976-4b47-42a3-87c3-836f9a2309a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384961368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3384961368
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2062804999
Short name T193
Test name
Test status
Simulation time 17309487180 ps
CPU time 63.17 seconds
Started Mar 14 12:41:08 PM PDT 24
Finished Mar 14 12:42:12 PM PDT 24
Peak memory 200076 kb
Host smart-c0cacb72-81e9-4025-8be3-bfd9224c73ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062804999 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2062804999
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.4022118091
Short name T135
Test name
Test status
Simulation time 26236315 ps
CPU time 1.01 seconds
Started Mar 14 12:41:12 PM PDT 24
Finished Mar 14 12:41:14 PM PDT 24
Peak memory 198376 kb
Host smart-fbff2469-14b8-4c02-96c4-5b21059c703f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022118091 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.4022118091
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.6147183
Short name T584
Test name
Test status
Simulation time 115398947131 ps
CPU time 491.26 seconds
Started Mar 14 12:41:08 PM PDT 24
Finished Mar 14 12:49:20 PM PDT 24
Peak memory 199864 kb
Host smart-1f3fcdbb-ad8d-488b-8517-7bb94d942d74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6147183 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.6147183
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.777450904
Short name T536
Test name
Test status
Simulation time 2730661223 ps
CPU time 64.89 seconds
Started Mar 14 12:41:12 PM PDT 24
Finished Mar 14 12:42:18 PM PDT 24
Peak memory 200024 kb
Host smart-6031271b-f9b0-44d7-a69d-94245314d324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777450904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.777450904
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.1508788315
Short name T65
Test name
Test status
Simulation time 136792077549 ps
CPU time 1877.32 seconds
Started Mar 14 12:43:44 PM PDT 24
Finished Mar 14 01:15:02 PM PDT 24
Peak memory 239640 kb
Host smart-47bda1bd-882c-49db-960c-8f2a9134520f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508788315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.1508788315
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3820940086
Short name T513
Test name
Test status
Simulation time 10963875 ps
CPU time 0.56 seconds
Started Mar 14 12:41:10 PM PDT 24
Finished Mar 14 12:41:11 PM PDT 24
Peak memory 195540 kb
Host smart-af2acc66-28fc-483d-bb76-1e7111b2a227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820940086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3820940086
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2564776734
Short name T54
Test name
Test status
Simulation time 957610559 ps
CPU time 36.47 seconds
Started Mar 14 12:41:10 PM PDT 24
Finished Mar 14 12:41:47 PM PDT 24
Peak memory 227332 kb
Host smart-cdd82d81-6bae-4468-a7b2-df5033e98790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564776734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2564776734
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2221878927
Short name T516
Test name
Test status
Simulation time 1128244331 ps
CPU time 55.29 seconds
Started Mar 14 12:41:12 PM PDT 24
Finished Mar 14 12:42:09 PM PDT 24
Peak memory 200000 kb
Host smart-4a45bd8d-fefc-4757-b857-05cafba9d519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221878927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2221878927
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.873544931
Short name T265
Test name
Test status
Simulation time 3117216985 ps
CPU time 43.73 seconds
Started Mar 14 12:41:10 PM PDT 24
Finished Mar 14 12:41:54 PM PDT 24
Peak memory 200040 kb
Host smart-8dc95c09-70cb-4289-9ef9-a9b50c8e73f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873544931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.873544931
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1491739015
Short name T493
Test name
Test status
Simulation time 8374034206 ps
CPU time 117.39 seconds
Started Mar 14 12:41:08 PM PDT 24
Finished Mar 14 12:43:05 PM PDT 24
Peak memory 200108 kb
Host smart-022fdbc2-dce5-49b9-8331-8377f1be5cb9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491739015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1491739015
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.321185127
Short name T445
Test name
Test status
Simulation time 120692949511 ps
CPU time 120.67 seconds
Started Mar 14 12:41:07 PM PDT 24
Finished Mar 14 12:43:08 PM PDT 24
Peak memory 200060 kb
Host smart-b2bfe438-09a5-4e37-9958-6e06369ebe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321185127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.321185127
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2226513596
Short name T554
Test name
Test status
Simulation time 81472529 ps
CPU time 1.2 seconds
Started Mar 14 12:41:10 PM PDT 24
Finished Mar 14 12:41:11 PM PDT 24
Peak memory 199808 kb
Host smart-74d74b13-812d-41a7-a041-43be1b7fbe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226513596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2226513596
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.4232330884
Short name T50
Test name
Test status
Simulation time 89640689414 ps
CPU time 273.13 seconds
Started Mar 14 12:41:13 PM PDT 24
Finished Mar 14 12:45:47 PM PDT 24
Peak memory 216468 kb
Host smart-f9f712ee-87f9-41a2-83d3-4f78c364a83e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232330884 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.4232330884
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2066391799
Short name T416
Test name
Test status
Simulation time 59203939 ps
CPU time 1.25 seconds
Started Mar 14 12:41:11 PM PDT 24
Finished Mar 14 12:41:14 PM PDT 24
Peak memory 199668 kb
Host smart-8091a69e-fe2c-477a-b5de-e73e1718c362
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066391799 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2066391799
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2648814938
Short name T333
Test name
Test status
Simulation time 15469574414 ps
CPU time 416.19 seconds
Started Mar 14 12:41:12 PM PDT 24
Finished Mar 14 12:48:10 PM PDT 24
Peak memory 200004 kb
Host smart-aed47a77-1acb-4da4-84fe-1fbf75349f5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648814938 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2648814938
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4082930380
Short name T537
Test name
Test status
Simulation time 4032140177 ps
CPU time 17.36 seconds
Started Mar 14 12:41:10 PM PDT 24
Finished Mar 14 12:41:28 PM PDT 24
Peak memory 199964 kb
Host smart-173870be-5492-4ff6-9e50-0e7ab6e00a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082930380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4082930380
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.190360808
Short name T588
Test name
Test status
Simulation time 49332993 ps
CPU time 0.57 seconds
Started Mar 14 12:41:20 PM PDT 24
Finished Mar 14 12:41:21 PM PDT 24
Peak memory 195664 kb
Host smart-1807e52d-f2f8-4bd0-aea4-193cad1f6546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190360808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.190360808
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2342637401
Short name T438
Test name
Test status
Simulation time 5266782497 ps
CPU time 46.99 seconds
Started Mar 14 12:41:08 PM PDT 24
Finished Mar 14 12:41:56 PM PDT 24
Peak memory 232024 kb
Host smart-7090ed43-e418-46a6-8a00-e53fedfebb3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342637401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2342637401
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2781686761
Short name T85
Test name
Test status
Simulation time 7887733063 ps
CPU time 26.28 seconds
Started Mar 14 12:41:09 PM PDT 24
Finished Mar 14 12:41:36 PM PDT 24
Peak memory 199864 kb
Host smart-d5bc8cdc-506e-449b-906a-a6617095111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781686761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2781686761
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.501412336
Short name T434
Test name
Test status
Simulation time 22629441828 ps
CPU time 112.83 seconds
Started Mar 14 12:41:10 PM PDT 24
Finished Mar 14 12:43:04 PM PDT 24
Peak memory 199880 kb
Host smart-42d83835-e2ca-4719-b102-4d72eb67d3ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501412336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.501412336
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3973059073
Short name T522
Test name
Test status
Simulation time 3491709549 ps
CPU time 194.76 seconds
Started Mar 14 12:41:23 PM PDT 24
Finished Mar 14 12:44:38 PM PDT 24
Peak memory 200068 kb
Host smart-38f68a4c-12d7-4368-8909-8be09366fe72
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973059073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3973059073
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1705025038
Short name T243
Test name
Test status
Simulation time 30574272698 ps
CPU time 101.14 seconds
Started Mar 14 12:41:10 PM PDT 24
Finished Mar 14 12:42:51 PM PDT 24
Peak memory 200052 kb
Host smart-af6b1822-3e39-47c0-a13d-e52d8c829781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705025038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1705025038
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.436562403
Short name T373
Test name
Test status
Simulation time 126347232 ps
CPU time 3.11 seconds
Started Mar 14 12:41:12 PM PDT 24
Finished Mar 14 12:41:16 PM PDT 24
Peak memory 199916 kb
Host smart-50a9cfff-b6b7-4964-8d74-bde1964c1b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436562403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.436562403
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.4200017749
Short name T80
Test name
Test status
Simulation time 57457164916 ps
CPU time 840.06 seconds
Started Mar 14 12:41:18 PM PDT 24
Finished Mar 14 12:55:18 PM PDT 24
Peak memory 241052 kb
Host smart-5a47eaf2-bf17-47d8-abb0-f82ab6a6fccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200017749 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.4200017749
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3504163099
Short name T226
Test name
Test status
Simulation time 43428473 ps
CPU time 0.97 seconds
Started Mar 14 12:41:20 PM PDT 24
Finished Mar 14 12:41:21 PM PDT 24
Peak memory 198108 kb
Host smart-2143c2b0-cdd3-4d2e-9667-2fa35d0bae83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504163099 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3504163099
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.691500400
Short name T378
Test name
Test status
Simulation time 65988691833 ps
CPU time 398 seconds
Started Mar 14 12:41:19 PM PDT 24
Finished Mar 14 12:47:57 PM PDT 24
Peak memory 200044 kb
Host smart-5824dbf4-eb46-4880-b6dd-bb593fd1592d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691500400 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.691500400
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2730325095
Short name T41
Test name
Test status
Simulation time 12225671323 ps
CPU time 59.85 seconds
Started Mar 14 12:41:18 PM PDT 24
Finished Mar 14 12:42:18 PM PDT 24
Peak memory 199980 kb
Host smart-2db62bab-3fde-4c31-a1d8-abf19fdbbb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730325095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2730325095
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2569103475
Short name T403
Test name
Test status
Simulation time 33078555 ps
CPU time 0.58 seconds
Started Mar 14 12:41:22 PM PDT 24
Finished Mar 14 12:41:22 PM PDT 24
Peak memory 195644 kb
Host smart-8cb0360d-b807-416a-9b36-f37a522d6d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569103475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2569103475
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1380915988
Short name T188
Test name
Test status
Simulation time 1157725468 ps
CPU time 20.03 seconds
Started Mar 14 12:41:22 PM PDT 24
Finished Mar 14 12:41:42 PM PDT 24
Peak memory 215964 kb
Host smart-50acd99f-4d2d-4f99-bbf5-047df20f0195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380915988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1380915988
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2043351158
Short name T116
Test name
Test status
Simulation time 2297296432 ps
CPU time 33.89 seconds
Started Mar 14 12:41:20 PM PDT 24
Finished Mar 14 12:41:54 PM PDT 24
Peak memory 199912 kb
Host smart-ebc0a41c-2622-4354-bba0-6d7018395d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043351158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2043351158
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1991019502
Short name T115
Test name
Test status
Simulation time 421945765 ps
CPU time 6.11 seconds
Started Mar 14 12:41:19 PM PDT 24
Finished Mar 14 12:41:25 PM PDT 24
Peak memory 200004 kb
Host smart-51bc9b7e-4b50-4f30-a276-c89e120731c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991019502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1991019502
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2498343327
Short name T501
Test name
Test status
Simulation time 24273104432 ps
CPU time 215.9 seconds
Started Mar 14 12:41:23 PM PDT 24
Finished Mar 14 12:44:59 PM PDT 24
Peak memory 200100 kb
Host smart-c3ce5ad1-a4a2-4418-a61c-c967f01194ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498343327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2498343327
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4191525763
Short name T395
Test name
Test status
Simulation time 65520295 ps
CPU time 0.61 seconds
Started Mar 14 12:41:20 PM PDT 24
Finished Mar 14 12:41:21 PM PDT 24
Peak memory 196472 kb
Host smart-009c27b9-04ea-46df-951b-edb99b89f1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191525763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4191525763
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1882266933
Short name T469
Test name
Test status
Simulation time 3639080336 ps
CPU time 5.14 seconds
Started Mar 14 12:41:21 PM PDT 24
Finished Mar 14 12:41:27 PM PDT 24
Peak memory 200084 kb
Host smart-5e245b8c-9a98-4981-9782-d6afd5180220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882266933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1882266933
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2192133470
Short name T270
Test name
Test status
Simulation time 90499142640 ps
CPU time 880.76 seconds
Started Mar 14 12:41:22 PM PDT 24
Finished Mar 14 12:56:03 PM PDT 24
Peak memory 232608 kb
Host smart-df7d4726-5ef6-468a-98a1-a8b708f587de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192133470 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2192133470
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3786110703
Short name T142
Test name
Test status
Simulation time 34517354672 ps
CPU time 435.63 seconds
Started Mar 14 12:41:18 PM PDT 24
Finished Mar 14 12:48:34 PM PDT 24
Peak memory 199900 kb
Host smart-da22f7b0-dc9d-404d-b7dd-23f124b6ba4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786110703 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.3786110703
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3174465752
Short name T572
Test name
Test status
Simulation time 19383221523 ps
CPU time 22.13 seconds
Started Mar 14 12:41:19 PM PDT 24
Finished Mar 14 12:41:41 PM PDT 24
Peak memory 200096 kb
Host smart-8a0685e9-00c5-4921-a2f4-0c9d264b318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174465752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3174465752
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.141655780
Short name T147
Test name
Test status
Simulation time 55895584 ps
CPU time 0.57 seconds
Started Mar 14 12:39:55 PM PDT 24
Finished Mar 14 12:39:56 PM PDT 24
Peak memory 195612 kb
Host smart-0280d9d4-ad29-4967-afb2-af3934e706b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141655780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.141655780
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2019149425
Short name T431
Test name
Test status
Simulation time 1846742197 ps
CPU time 7.67 seconds
Started Mar 14 12:39:42 PM PDT 24
Finished Mar 14 12:39:50 PM PDT 24
Peak memory 216204 kb
Host smart-21a8fb32-48f0-41b9-bce1-1705d97ea1f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019149425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2019149425
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.4257943761
Short name T302
Test name
Test status
Simulation time 101428241 ps
CPU time 2.11 seconds
Started Mar 14 12:39:40 PM PDT 24
Finished Mar 14 12:39:42 PM PDT 24
Peak memory 200056 kb
Host smart-8c2fb3a1-1eb9-4d79-bb12-dd83548f998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257943761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.4257943761
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.99486084
Short name T491
Test name
Test status
Simulation time 474659577 ps
CPU time 25.11 seconds
Started Mar 14 12:39:40 PM PDT 24
Finished Mar 14 12:40:05 PM PDT 24
Peak memory 200052 kb
Host smart-681b6854-d03c-4c31-aca9-ec91c0d52230
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99486084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.99486084
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.338403651
Short name T264
Test name
Test status
Simulation time 2938665911 ps
CPU time 36.97 seconds
Started Mar 14 12:39:54 PM PDT 24
Finished Mar 14 12:40:33 PM PDT 24
Peak memory 200024 kb
Host smart-5606f350-fa00-403b-b74b-0d8b64276627
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338403651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.338403651
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2782834629
Short name T155
Test name
Test status
Simulation time 2316391728 ps
CPU time 17.01 seconds
Started Mar 14 12:39:43 PM PDT 24
Finished Mar 14 12:40:01 PM PDT 24
Peak memory 200076 kb
Host smart-f826db55-9862-48a2-9f76-c8bf5c28197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782834629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2782834629
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2236894323
Short name T33
Test name
Test status
Simulation time 90181616 ps
CPU time 0.96 seconds
Started Mar 14 12:39:56 PM PDT 24
Finished Mar 14 12:39:57 PM PDT 24
Peak memory 219124 kb
Host smart-d9098d3b-bca9-46f3-a403-bd54f347ba9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236894323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2236894323
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2075926009
Short name T352
Test name
Test status
Simulation time 720329558 ps
CPU time 2.13 seconds
Started Mar 14 12:39:41 PM PDT 24
Finished Mar 14 12:39:43 PM PDT 24
Peak memory 200048 kb
Host smart-2f6c0864-77ee-4411-aa77-42795c275673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075926009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2075926009
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.435908774
Short name T227
Test name
Test status
Simulation time 4090416783 ps
CPU time 73.37 seconds
Started Mar 14 12:40:03 PM PDT 24
Finished Mar 14 12:41:17 PM PDT 24
Peak memory 200044 kb
Host smart-e06f96c4-c641-44eb-ab57-b24f2c57b153
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435908774 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.435908774
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3636192308
Short name T375
Test name
Test status
Simulation time 27051750821 ps
CPU time 1283.93 seconds
Started Mar 14 12:39:56 PM PDT 24
Finished Mar 14 01:01:21 PM PDT 24
Peak memory 225428 kb
Host smart-ce89abc9-8604-49ad-9981-c1612f2a4b35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636192308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3636192308
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3010135438
Short name T170
Test name
Test status
Simulation time 214913621 ps
CPU time 1.23 seconds
Started Mar 14 12:39:58 PM PDT 24
Finished Mar 14 12:40:00 PM PDT 24
Peak memory 199800 kb
Host smart-feb97d66-254c-4a46-89f5-c517bc855d96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010135438 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.3010135438
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3865100754
Short name T347
Test name
Test status
Simulation time 27767458730 ps
CPU time 494.26 seconds
Started Mar 14 12:39:57 PM PDT 24
Finished Mar 14 12:48:12 PM PDT 24
Peak memory 199924 kb
Host smart-096344fb-7028-4ce8-b074-596283a52720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865100754 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.3865100754
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2705698132
Short name T379
Test name
Test status
Simulation time 5569965418 ps
CPU time 54.5 seconds
Started Mar 14 12:39:55 PM PDT 24
Finished Mar 14 12:40:50 PM PDT 24
Peak memory 200128 kb
Host smart-4aadadbd-fa1b-4d9f-9106-3624e9634f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705698132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2705698132
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3291844071
Short name T540
Test name
Test status
Simulation time 12189910 ps
CPU time 0.57 seconds
Started Mar 14 12:41:28 PM PDT 24
Finished Mar 14 12:41:29 PM PDT 24
Peak memory 195616 kb
Host smart-ce544949-4210-4025-9039-f3afb6b17dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291844071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3291844071
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4034700919
Short name T524
Test name
Test status
Simulation time 12312637394 ps
CPU time 45.42 seconds
Started Mar 14 12:41:19 PM PDT 24
Finished Mar 14 12:42:04 PM PDT 24
Peak memory 232188 kb
Host smart-e79c7e41-f2bc-4323-bd9f-3c7874f75bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034700919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4034700919
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3484361323
Short name T390
Test name
Test status
Simulation time 1180478758 ps
CPU time 54.64 seconds
Started Mar 14 12:41:19 PM PDT 24
Finished Mar 14 12:42:14 PM PDT 24
Peak memory 199856 kb
Host smart-b6be985c-c3e7-49dd-a3b9-e24c1018f4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484361323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3484361323
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2030411844
Short name T284
Test name
Test status
Simulation time 1532200481 ps
CPU time 87.43 seconds
Started Mar 14 12:41:20 PM PDT 24
Finished Mar 14 12:42:47 PM PDT 24
Peak memory 199860 kb
Host smart-1ed965aa-d39b-4c4a-b6fd-b2cafe889256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030411844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2030411844
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.629010697
Short name T16
Test name
Test status
Simulation time 52631538132 ps
CPU time 160.55 seconds
Started Mar 14 12:41:19 PM PDT 24
Finished Mar 14 12:44:00 PM PDT 24
Peak memory 200012 kb
Host smart-058986c8-86c7-4f9a-b685-e1db9b90f44f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629010697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.629010697
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2723412710
Short name T451
Test name
Test status
Simulation time 1367656012 ps
CPU time 80.32 seconds
Started Mar 14 12:41:19 PM PDT 24
Finished Mar 14 12:42:39 PM PDT 24
Peak memory 200064 kb
Host smart-232b6477-e634-4db8-ba61-440c1556b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723412710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2723412710
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1646716218
Short name T455
Test name
Test status
Simulation time 250063694 ps
CPU time 3.8 seconds
Started Mar 14 12:41:17 PM PDT 24
Finished Mar 14 12:41:21 PM PDT 24
Peak memory 199964 kb
Host smart-6ff1d1f7-22fd-400c-beb9-50b31896f585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646716218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1646716218
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1731142248
Short name T338
Test name
Test status
Simulation time 18044487531 ps
CPU time 888.94 seconds
Started Mar 14 12:41:27 PM PDT 24
Finished Mar 14 12:56:17 PM PDT 24
Peak memory 240148 kb
Host smart-da4df84c-041f-4c7c-8c2b-ac074fbe7964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731142248 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1731142248
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1805625089
Short name T564
Test name
Test status
Simulation time 49755961 ps
CPU time 1.11 seconds
Started Mar 14 12:41:26 PM PDT 24
Finished Mar 14 12:41:27 PM PDT 24
Peak memory 199808 kb
Host smart-3337c2ae-2a26-41ac-a036-c7efd698b41d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805625089 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1805625089
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3821355944
Short name T376
Test name
Test status
Simulation time 16726893414 ps
CPU time 447.61 seconds
Started Mar 14 12:41:26 PM PDT 24
Finished Mar 14 12:48:54 PM PDT 24
Peak memory 199908 kb
Host smart-69526290-e09a-4039-94f5-541615d037e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821355944 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3821355944
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3883255429
Short name T505
Test name
Test status
Simulation time 9482335148 ps
CPU time 67.54 seconds
Started Mar 14 12:41:17 PM PDT 24
Finished Mar 14 12:42:25 PM PDT 24
Peak memory 200044 kb
Host smart-8f5106bf-4082-44d0-873d-3f4b4c3e3d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883255429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3883255429
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2937553587
Short name T225
Test name
Test status
Simulation time 115942567 ps
CPU time 0.64 seconds
Started Mar 14 12:41:29 PM PDT 24
Finished Mar 14 12:41:30 PM PDT 24
Peak memory 195600 kb
Host smart-87d6db74-8157-49f6-8292-de3f0848a60c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937553587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2937553587
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3334533415
Short name T344
Test name
Test status
Simulation time 410362139 ps
CPU time 8.16 seconds
Started Mar 14 12:41:28 PM PDT 24
Finished Mar 14 12:41:36 PM PDT 24
Peak memory 208220 kb
Host smart-b6a944cf-69a3-4f63-b9e8-80d5399d3c4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3334533415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3334533415
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1094751741
Short name T175
Test name
Test status
Simulation time 10178967298 ps
CPU time 38.62 seconds
Started Mar 14 12:41:28 PM PDT 24
Finished Mar 14 12:42:07 PM PDT 24
Peak memory 199900 kb
Host smart-557672c6-cde4-44cf-92f5-e09dae33d859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094751741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1094751741
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3644653585
Short name T288
Test name
Test status
Simulation time 4218511530 ps
CPU time 113.35 seconds
Started Mar 14 12:41:27 PM PDT 24
Finished Mar 14 12:43:21 PM PDT 24
Peak memory 200316 kb
Host smart-6e537fad-8f0f-46e6-b818-6983f01fb973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3644653585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3644653585
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.767158672
Short name T532
Test name
Test status
Simulation time 6975765063 ps
CPU time 128.56 seconds
Started Mar 14 12:41:32 PM PDT 24
Finished Mar 14 12:43:40 PM PDT 24
Peak memory 200036 kb
Host smart-baf163c2-7e43-4f57-a3ea-186eed1fe734
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767158672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.767158672
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3091855339
Short name T355
Test name
Test status
Simulation time 423631929 ps
CPU time 9.05 seconds
Started Mar 14 12:41:29 PM PDT 24
Finished Mar 14 12:41:39 PM PDT 24
Peak memory 200024 kb
Host smart-238b3df7-a103-4775-b97f-2d943968058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091855339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3091855339
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.853658189
Short name T547
Test name
Test status
Simulation time 167369556 ps
CPU time 5.21 seconds
Started Mar 14 12:41:28 PM PDT 24
Finished Mar 14 12:41:34 PM PDT 24
Peak memory 199972 kb
Host smart-00804fd3-904d-4a3e-801f-d59ca7f85cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853658189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.853658189
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.526395508
Short name T456
Test name
Test status
Simulation time 333621887477 ps
CPU time 1539.85 seconds
Started Mar 14 12:41:26 PM PDT 24
Finished Mar 14 01:07:07 PM PDT 24
Peak memory 208308 kb
Host smart-96f9d443-a9b4-4504-8480-290c3f4b75a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526395508 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.526395508
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3655473916
Short name T419
Test name
Test status
Simulation time 193371799 ps
CPU time 1.03 seconds
Started Mar 14 12:41:45 PM PDT 24
Finished Mar 14 12:41:46 PM PDT 24
Peak memory 199044 kb
Host smart-6d49f9c7-f2f7-4bfc-8a7c-4add0741ed74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655473916 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3655473916
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3166900609
Short name T37
Test name
Test status
Simulation time 12244417520 ps
CPU time 417.24 seconds
Started Mar 14 12:41:31 PM PDT 24
Finished Mar 14 12:48:29 PM PDT 24
Peak memory 199980 kb
Host smart-d0ba0c4c-b3dd-478b-aef6-2c81d2c00090
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166900609 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.3166900609
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.884190579
Short name T8
Test name
Test status
Simulation time 5020613350 ps
CPU time 46.86 seconds
Started Mar 14 12:41:28 PM PDT 24
Finished Mar 14 12:42:15 PM PDT 24
Peak memory 200352 kb
Host smart-800fe283-2236-4a28-a7bb-1a4fe5b74695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884190579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.884190579
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1318670165
Short name T411
Test name
Test status
Simulation time 34266231 ps
CPU time 0.56 seconds
Started Mar 14 12:41:36 PM PDT 24
Finished Mar 14 12:41:36 PM PDT 24
Peak memory 195560 kb
Host smart-8e467d89-f689-4c83-ae04-0220fa4aca6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318670165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1318670165
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2734807724
Short name T249
Test name
Test status
Simulation time 3635949121 ps
CPU time 35.15 seconds
Started Mar 14 12:41:27 PM PDT 24
Finished Mar 14 12:42:03 PM PDT 24
Peak memory 246092 kb
Host smart-a3d4679a-8eb6-4899-b1a6-175a0726b693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734807724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2734807724
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1433399845
Short name T396
Test name
Test status
Simulation time 4460458384 ps
CPU time 46.37 seconds
Started Mar 14 12:41:35 PM PDT 24
Finished Mar 14 12:42:22 PM PDT 24
Peak memory 200112 kb
Host smart-225057cd-9d12-483a-bd93-ceb8395e4e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433399845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1433399845
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.976090392
Short name T359
Test name
Test status
Simulation time 355622044 ps
CPU time 19.32 seconds
Started Mar 14 12:41:28 PM PDT 24
Finished Mar 14 12:41:47 PM PDT 24
Peak memory 199968 kb
Host smart-de730098-5035-4dc6-86a9-1f6a8115bc7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976090392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.976090392
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3286180886
Short name T218
Test name
Test status
Simulation time 461267222 ps
CPU time 4.45 seconds
Started Mar 14 12:41:36 PM PDT 24
Finished Mar 14 12:41:41 PM PDT 24
Peak memory 199896 kb
Host smart-e35f7fa1-1e1f-484b-b03c-038855fb6594
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286180886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3286180886
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3512345327
Short name T199
Test name
Test status
Simulation time 2655653490 ps
CPU time 32.87 seconds
Started Mar 14 12:41:29 PM PDT 24
Finished Mar 14 12:42:01 PM PDT 24
Peak memory 200008 kb
Host smart-87eec91f-fc7f-4233-9ed5-62a3213368dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512345327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3512345327
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2985314970
Short name T357
Test name
Test status
Simulation time 596935162 ps
CPU time 5.4 seconds
Started Mar 14 12:41:28 PM PDT 24
Finished Mar 14 12:41:33 PM PDT 24
Peak memory 200024 kb
Host smart-2578c7c8-6a56-417d-824c-4d1e147bc1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985314970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2985314970
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1871450148
Short name T422
Test name
Test status
Simulation time 320383052 ps
CPU time 1.03 seconds
Started Mar 14 12:41:37 PM PDT 24
Finished Mar 14 12:41:39 PM PDT 24
Peak memory 199852 kb
Host smart-bafb90ad-9a9b-4e15-b8a0-423fab93915a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871450148 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1871450148
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.705655055
Short name T176
Test name
Test status
Simulation time 37870390546 ps
CPU time 422.25 seconds
Started Mar 14 12:41:37 PM PDT 24
Finished Mar 14 12:48:39 PM PDT 24
Peak memory 200012 kb
Host smart-4ed9769e-4ec8-49c6-a4b5-908bfdd1bb7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705655055 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.705655055
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2910673604
Short name T229
Test name
Test status
Simulation time 17669734767 ps
CPU time 88.56 seconds
Started Mar 14 12:41:39 PM PDT 24
Finished Mar 14 12:43:09 PM PDT 24
Peak memory 200184 kb
Host smart-a8092ff0-bcea-40ac-a9d7-3f2e2ce24f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910673604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2910673604
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.809290769
Short name T346
Test name
Test status
Simulation time 30911928 ps
CPU time 0.56 seconds
Started Mar 14 12:41:36 PM PDT 24
Finished Mar 14 12:41:37 PM PDT 24
Peak memory 195716 kb
Host smart-af96538d-4945-48db-b4ab-f11d3d4f3dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809290769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.809290769
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1196879745
Short name T278
Test name
Test status
Simulation time 6857130563 ps
CPU time 68.25 seconds
Started Mar 14 12:41:35 PM PDT 24
Finished Mar 14 12:42:44 PM PDT 24
Peak memory 232696 kb
Host smart-3be6e27f-2b4b-44dc-83bc-472284a559a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1196879745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1196879745
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2180055420
Short name T192
Test name
Test status
Simulation time 12281258226 ps
CPU time 44.14 seconds
Started Mar 14 12:41:35 PM PDT 24
Finished Mar 14 12:42:19 PM PDT 24
Peak memory 200152 kb
Host smart-11050246-8711-4079-a022-fd833cab5d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180055420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2180055420
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.4067043737
Short name T5
Test name
Test status
Simulation time 4044309542 ps
CPU time 51.71 seconds
Started Mar 14 12:41:38 PM PDT 24
Finished Mar 14 12:42:30 PM PDT 24
Peak memory 200124 kb
Host smart-27ece36d-71e7-4d29-9d84-61468c556629
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067043737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.4067043737
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2921108384
Short name T311
Test name
Test status
Simulation time 13969400046 ps
CPU time 189.71 seconds
Started Mar 14 12:41:39 PM PDT 24
Finished Mar 14 12:44:49 PM PDT 24
Peak memory 200144 kb
Host smart-2f62514f-b83b-49f4-b2cd-88ebd8de11ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921108384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2921108384
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2664991873
Short name T402
Test name
Test status
Simulation time 17363159041 ps
CPU time 91.98 seconds
Started Mar 14 12:41:35 PM PDT 24
Finished Mar 14 12:43:08 PM PDT 24
Peak memory 200044 kb
Host smart-83398b84-d1fc-4b6c-8b99-770fa1baa359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664991873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2664991873
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3604995912
Short name T457
Test name
Test status
Simulation time 450837361 ps
CPU time 6.44 seconds
Started Mar 14 12:41:36 PM PDT 24
Finished Mar 14 12:41:43 PM PDT 24
Peak memory 199996 kb
Host smart-755637fb-3513-4f0c-8857-ee2e580958dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604995912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3604995912
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1380039919
Short name T78
Test name
Test status
Simulation time 1071449821886 ps
CPU time 2520.76 seconds
Started Mar 14 12:41:36 PM PDT 24
Finished Mar 14 01:23:38 PM PDT 24
Peak memory 200140 kb
Host smart-3e3607e9-b979-4bc7-8ece-dfac73020ca6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380039919 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1380039919
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2460745786
Short name T248
Test name
Test status
Simulation time 206672852 ps
CPU time 1.2 seconds
Started Mar 14 12:41:36 PM PDT 24
Finished Mar 14 12:41:38 PM PDT 24
Peak memory 199000 kb
Host smart-aa420600-aaed-4ad4-ad6e-cd46bebe1501
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460745786 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2460745786
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1676435006
Short name T251
Test name
Test status
Simulation time 51488971406 ps
CPU time 470.45 seconds
Started Mar 14 12:41:37 PM PDT 24
Finished Mar 14 12:49:27 PM PDT 24
Peak memory 200040 kb
Host smart-7636e4b2-1638-416e-b749-86ba87b778c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676435006 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1676435006
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2783311742
Short name T114
Test name
Test status
Simulation time 1508691199 ps
CPU time 65.63 seconds
Started Mar 14 12:41:37 PM PDT 24
Finished Mar 14 12:42:43 PM PDT 24
Peak memory 199944 kb
Host smart-37090725-d5c3-4ecc-90ff-df446be676b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783311742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2783311742
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.446155115
Short name T561
Test name
Test status
Simulation time 14941224 ps
CPU time 0.56 seconds
Started Mar 14 12:41:51 PM PDT 24
Finished Mar 14 12:41:52 PM PDT 24
Peak memory 194596 kb
Host smart-9b068588-936f-4fe7-9503-984ef85f4c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446155115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.446155115
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1376542526
Short name T201
Test name
Test status
Simulation time 3541413273 ps
CPU time 66.69 seconds
Started Mar 14 12:41:36 PM PDT 24
Finished Mar 14 12:42:43 PM PDT 24
Peak memory 224568 kb
Host smart-689ffd86-b50d-4257-9596-07570491909e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376542526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1376542526
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.8767970
Short name T427
Test name
Test status
Simulation time 947371222 ps
CPU time 24.4 seconds
Started Mar 14 12:41:41 PM PDT 24
Finished Mar 14 12:42:05 PM PDT 24
Peak memory 200044 kb
Host smart-449169c8-664b-4909-bb56-5a64a86a31c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8767970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.8767970
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2601847065
Short name T576
Test name
Test status
Simulation time 1923305336 ps
CPU time 107.9 seconds
Started Mar 14 12:41:38 PM PDT 24
Finished Mar 14 12:43:26 PM PDT 24
Peak memory 199984 kb
Host smart-32e7cdd9-afce-4d44-b674-bd626ee5fd04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601847065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2601847065
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3726336723
Short name T49
Test name
Test status
Simulation time 91763000598 ps
CPU time 188.85 seconds
Started Mar 14 12:41:43 PM PDT 24
Finished Mar 14 12:44:52 PM PDT 24
Peak memory 200148 kb
Host smart-e6b43e1d-81f9-4ae6-969b-4dd76abeb1ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726336723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3726336723
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.943453621
Short name T130
Test name
Test status
Simulation time 1297045375 ps
CPU time 17.65 seconds
Started Mar 14 12:41:35 PM PDT 24
Finished Mar 14 12:41:53 PM PDT 24
Peak memory 199924 kb
Host smart-072ec8a5-f119-43e7-b5de-a90fcc1c7e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943453621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.943453621
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.568655274
Short name T132
Test name
Test status
Simulation time 434456979 ps
CPU time 6.35 seconds
Started Mar 14 12:41:36 PM PDT 24
Finished Mar 14 12:41:43 PM PDT 24
Peak memory 199976 kb
Host smart-0f97e124-9e54-4124-a27e-178540dc24e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568655274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.568655274
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2741271756
Short name T247
Test name
Test status
Simulation time 6009320347 ps
CPU time 120.98 seconds
Started Mar 14 12:41:51 PM PDT 24
Finished Mar 14 12:43:52 PM PDT 24
Peak memory 236448 kb
Host smart-ed0e50b4-a642-4737-83b3-c8ee9fe9c957
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741271756 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2741271756
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1783449750
Short name T300
Test name
Test status
Simulation time 31017637 ps
CPU time 1.23 seconds
Started Mar 14 12:41:44 PM PDT 24
Finished Mar 14 12:41:46 PM PDT 24
Peak memory 199748 kb
Host smart-a1e3dba4-e854-4b14-bc68-c866945f6679
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783449750 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1783449750
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.199698739
Short name T74
Test name
Test status
Simulation time 42586493197 ps
CPU time 478.49 seconds
Started Mar 14 12:41:45 PM PDT 24
Finished Mar 14 12:49:44 PM PDT 24
Peak memory 200032 kb
Host smart-f40c7c8e-47be-41f8-b230-702feb8f7e46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199698739 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.199698739
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2776185092
Short name T39
Test name
Test status
Simulation time 20773291857 ps
CPU time 84.51 seconds
Started Mar 14 12:41:43 PM PDT 24
Finished Mar 14 12:43:08 PM PDT 24
Peak memory 200108 kb
Host smart-dec94b27-35cc-46f9-bb60-a77061fd2d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776185092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2776185092
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3026713703
Short name T424
Test name
Test status
Simulation time 26889430 ps
CPU time 0.57 seconds
Started Mar 14 12:41:45 PM PDT 24
Finished Mar 14 12:41:47 PM PDT 24
Peak memory 195456 kb
Host smart-410968c4-1287-470b-8e57-ce04c8c1a9ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026713703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3026713703
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2294789011
Short name T55
Test name
Test status
Simulation time 302818320 ps
CPU time 14.42 seconds
Started Mar 14 12:41:45 PM PDT 24
Finished Mar 14 12:41:59 PM PDT 24
Peak memory 241000 kb
Host smart-f9d95eba-5000-44d1-b9e9-f36ac5063f60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294789011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2294789011
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2432624770
Short name T231
Test name
Test status
Simulation time 8958531355 ps
CPU time 47.82 seconds
Started Mar 14 12:41:46 PM PDT 24
Finished Mar 14 12:42:34 PM PDT 24
Peak memory 200008 kb
Host smart-dad9fef2-e869-4125-b9b7-44d45bdd5860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432624770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2432624770
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2053178273
Short name T339
Test name
Test status
Simulation time 1448880228 ps
CPU time 67.46 seconds
Started Mar 14 12:41:46 PM PDT 24
Finished Mar 14 12:42:53 PM PDT 24
Peak memory 199848 kb
Host smart-eeb5fc5d-aa1a-48a3-8965-2cb02fc15be0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2053178273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2053178273
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1964383617
Short name T149
Test name
Test status
Simulation time 7620270687 ps
CPU time 111.5 seconds
Started Mar 14 12:41:54 PM PDT 24
Finished Mar 14 12:43:46 PM PDT 24
Peak memory 200068 kb
Host smart-52834281-d3c2-4502-91ad-e274e835c7bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964383617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1964383617
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1701657476
Short name T519
Test name
Test status
Simulation time 650105540 ps
CPU time 19.5 seconds
Started Mar 14 12:41:50 PM PDT 24
Finished Mar 14 12:42:09 PM PDT 24
Peak memory 200004 kb
Host smart-9a76a5a6-c1f5-4bd2-a353-76f4b0f21199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701657476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1701657476
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.656266320
Short name T198
Test name
Test status
Simulation time 41722714 ps
CPU time 0.72 seconds
Started Mar 14 12:41:51 PM PDT 24
Finished Mar 14 12:41:52 PM PDT 24
Peak memory 197160 kb
Host smart-9ee0a5a1-35bc-4094-a706-f8f8d722075a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656266320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.656266320
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.4217734570
Short name T76
Test name
Test status
Simulation time 339191349620 ps
CPU time 1064.88 seconds
Started Mar 14 12:41:49 PM PDT 24
Finished Mar 14 12:59:34 PM PDT 24
Peak memory 224624 kb
Host smart-b53c40f8-d2e8-4e21-a36b-0759cf1895c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217734570 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.4217734570
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3354354576
Short name T598
Test name
Test status
Simulation time 377575486 ps
CPU time 1.18 seconds
Started Mar 14 12:41:51 PM PDT 24
Finished Mar 14 12:41:52 PM PDT 24
Peak memory 199960 kb
Host smart-89577c9e-cef1-47bc-9d92-8489e731ac02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354354576 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3354354576
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2112952248
Short name T567
Test name
Test status
Simulation time 36521766144 ps
CPU time 496.72 seconds
Started Mar 14 12:41:44 PM PDT 24
Finished Mar 14 12:50:01 PM PDT 24
Peak memory 200000 kb
Host smart-d6e47483-0e27-4be9-894d-c810852617fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112952248 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2112952248
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.4197377066
Short name T365
Test name
Test status
Simulation time 362252325 ps
CPU time 7.06 seconds
Started Mar 14 12:41:45 PM PDT 24
Finished Mar 14 12:41:52 PM PDT 24
Peak memory 199912 kb
Host smart-45ce1c66-9353-4ed2-afb3-a183bc131bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197377066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.4197377066
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2306104896
Short name T546
Test name
Test status
Simulation time 61541745 ps
CPU time 0.56 seconds
Started Mar 14 12:41:58 PM PDT 24
Finished Mar 14 12:41:58 PM PDT 24
Peak memory 195300 kb
Host smart-7b5127bd-3096-4bad-aa76-f30c3ba70adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306104896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2306104896
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2176259723
Short name T548
Test name
Test status
Simulation time 4519949080 ps
CPU time 40.12 seconds
Started Mar 14 12:41:46 PM PDT 24
Finished Mar 14 12:42:27 PM PDT 24
Peak memory 224700 kb
Host smart-808617e2-5f46-40d9-a5a7-b61ee8d4426f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176259723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2176259723
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.271739199
Short name T205
Test name
Test status
Simulation time 1672338634 ps
CPU time 19.96 seconds
Started Mar 14 12:41:44 PM PDT 24
Finished Mar 14 12:42:04 PM PDT 24
Peak memory 199980 kb
Host smart-4b353b50-ede4-4b4d-8c8e-c3649346298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271739199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.271739199
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.818731770
Short name T477
Test name
Test status
Simulation time 26342426557 ps
CPU time 89.66 seconds
Started Mar 14 12:41:44 PM PDT 24
Finished Mar 14 12:43:14 PM PDT 24
Peak memory 200064 kb
Host smart-4b5ebc00-e924-4158-9498-29f0a9620867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818731770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.818731770
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2133235042
Short name T341
Test name
Test status
Simulation time 77213984149 ps
CPU time 67.6 seconds
Started Mar 14 12:41:45 PM PDT 24
Finished Mar 14 12:42:54 PM PDT 24
Peak memory 200064 kb
Host smart-a54c0085-fe19-4af3-9ac8-dbfc319daacb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133235042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2133235042
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2320515623
Short name T407
Test name
Test status
Simulation time 1669026480 ps
CPU time 22.42 seconds
Started Mar 14 12:41:44 PM PDT 24
Finished Mar 14 12:42:07 PM PDT 24
Peak memory 199900 kb
Host smart-fb169f48-1898-4296-98ff-80524d52715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320515623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2320515623
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3139494780
Short name T203
Test name
Test status
Simulation time 246215718 ps
CPU time 2.85 seconds
Started Mar 14 12:41:44 PM PDT 24
Finished Mar 14 12:41:47 PM PDT 24
Peak memory 199988 kb
Host smart-f1bdd505-722b-46a8-9911-5906df2af602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139494780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3139494780
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1232445879
Short name T327
Test name
Test status
Simulation time 18803571404 ps
CPU time 1014.68 seconds
Started Mar 14 12:41:45 PM PDT 24
Finished Mar 14 12:58:40 PM PDT 24
Peak memory 200040 kb
Host smart-148ca095-a0f4-46ab-8d37-942f8b798fcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232445879 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1232445879
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3752011530
Short name T315
Test name
Test status
Simulation time 46285442 ps
CPU time 0.99 seconds
Started Mar 14 12:41:44 PM PDT 24
Finished Mar 14 12:41:45 PM PDT 24
Peak memory 198120 kb
Host smart-c69e5341-144b-485c-adb2-955b67b1e28a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752011530 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.3752011530
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.514052495
Short name T340
Test name
Test status
Simulation time 75631145479 ps
CPU time 474.23 seconds
Started Mar 14 12:41:43 PM PDT 24
Finished Mar 14 12:49:37 PM PDT 24
Peak memory 200032 kb
Host smart-da624e9c-7bd2-495d-89de-2435b6c60f4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514052495 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.514052495
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2427857481
Short name T563
Test name
Test status
Simulation time 217584844 ps
CPU time 3.58 seconds
Started Mar 14 12:41:54 PM PDT 24
Finished Mar 14 12:41:58 PM PDT 24
Peak memory 199980 kb
Host smart-b339aa08-cb8c-4dc3-9b66-9afd7df9118e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427857481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2427857481
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1083634998
Short name T545
Test name
Test status
Simulation time 41252467 ps
CPU time 0.57 seconds
Started Mar 14 12:41:59 PM PDT 24
Finished Mar 14 12:42:00 PM PDT 24
Peak memory 195572 kb
Host smart-2db90fdb-16d6-4889-b183-2aa62f64a35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083634998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1083634998
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3110992863
Short name T294
Test name
Test status
Simulation time 717218375 ps
CPU time 12.63 seconds
Started Mar 14 12:41:59 PM PDT 24
Finished Mar 14 12:42:12 PM PDT 24
Peak memory 208208 kb
Host smart-77e8f92f-f5bd-4552-93b5-05d4feb0d997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110992863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3110992863
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3220523937
Short name T277
Test name
Test status
Simulation time 1321921366 ps
CPU time 27.09 seconds
Started Mar 14 12:42:02 PM PDT 24
Finished Mar 14 12:42:29 PM PDT 24
Peak memory 200120 kb
Host smart-aec6bf84-6bea-4062-9882-8a46e5e58b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220523937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3220523937
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.988327685
Short name T168
Test name
Test status
Simulation time 7633073023 ps
CPU time 105.56 seconds
Started Mar 14 12:41:59 PM PDT 24
Finished Mar 14 12:43:44 PM PDT 24
Peak memory 200100 kb
Host smart-947e9950-7bb7-42a1-985e-48981f069780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988327685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.988327685
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2023189605
Short name T38
Test name
Test status
Simulation time 11663176318 ps
CPU time 35.58 seconds
Started Mar 14 12:41:57 PM PDT 24
Finished Mar 14 12:42:33 PM PDT 24
Peak memory 200044 kb
Host smart-b3086efb-299a-4d71-8773-f7de98f000f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023189605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2023189605
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3788858217
Short name T129
Test name
Test status
Simulation time 24956713209 ps
CPU time 88.98 seconds
Started Mar 14 12:42:01 PM PDT 24
Finished Mar 14 12:43:30 PM PDT 24
Peak memory 200100 kb
Host smart-36123d29-0c3b-42e9-a8e8-2cbb8e40598b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788858217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3788858217
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.4019999882
Short name T399
Test name
Test status
Simulation time 2708770253 ps
CPU time 3.06 seconds
Started Mar 14 12:41:58 PM PDT 24
Finished Mar 14 12:42:02 PM PDT 24
Peak memory 200000 kb
Host smart-5f97ad46-a033-44cc-a6b9-d680df7f15c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019999882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4019999882
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1881748309
Short name T148
Test name
Test status
Simulation time 112112649974 ps
CPU time 1211.24 seconds
Started Mar 14 12:41:57 PM PDT 24
Finished Mar 14 01:02:09 PM PDT 24
Peak memory 200068 kb
Host smart-fb67c95a-8e05-459e-8323-acca99d980a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881748309 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1881748309
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3823378883
Short name T146
Test name
Test status
Simulation time 252584017 ps
CPU time 1.32 seconds
Started Mar 14 12:42:01 PM PDT 24
Finished Mar 14 12:42:02 PM PDT 24
Peak memory 199996 kb
Host smart-1ec4f378-7c67-40ba-b2c8-153846b356a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823378883 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3823378883
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1934127496
Short name T433
Test name
Test status
Simulation time 36568990178 ps
CPU time 472.45 seconds
Started Mar 14 12:41:58 PM PDT 24
Finished Mar 14 12:49:51 PM PDT 24
Peak memory 199952 kb
Host smart-44cac4ba-e7c4-41e8-bab3-3ba468bac6d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934127496 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.1934127496
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1052848878
Short name T242
Test name
Test status
Simulation time 31289347445 ps
CPU time 46.11 seconds
Started Mar 14 12:41:57 PM PDT 24
Finished Mar 14 12:42:43 PM PDT 24
Peak memory 200096 kb
Host smart-89c970f0-aac5-4659-ae9f-e043b648d9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052848878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1052848878
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1181518361
Short name T374
Test name
Test status
Simulation time 28091705 ps
CPU time 0.59 seconds
Started Mar 14 12:41:58 PM PDT 24
Finished Mar 14 12:41:59 PM PDT 24
Peak memory 195696 kb
Host smart-70a523fb-1c97-4b29-8ba3-690e1f8a3baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181518361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1181518361
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3432322925
Short name T177
Test name
Test status
Simulation time 5529088960 ps
CPU time 57.12 seconds
Started Mar 14 12:41:59 PM PDT 24
Finished Mar 14 12:42:56 PM PDT 24
Peak memory 216408 kb
Host smart-f446271b-8739-40f5-a987-01b518dd2c26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432322925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3432322925
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2108191799
Short name T520
Test name
Test status
Simulation time 5545707303 ps
CPU time 62.33 seconds
Started Mar 14 12:41:59 PM PDT 24
Finished Mar 14 12:43:02 PM PDT 24
Peak memory 200056 kb
Host smart-8bdb0492-e4bf-4cc0-ab3c-ee6dfd70793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108191799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2108191799
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.30945542
Short name T514
Test name
Test status
Simulation time 2574247204 ps
CPU time 121.24 seconds
Started Mar 14 12:41:57 PM PDT 24
Finished Mar 14 12:43:58 PM PDT 24
Peak memory 199940 kb
Host smart-467e523f-8bdd-442b-8922-4966e696c6e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30945542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.30945542
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3434712823
Short name T593
Test name
Test status
Simulation time 3408548075 ps
CPU time 59.56 seconds
Started Mar 14 12:42:00 PM PDT 24
Finished Mar 14 12:43:00 PM PDT 24
Peak memory 200068 kb
Host smart-e78ac280-8003-42c8-9c73-804a072f930f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434712823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3434712823
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3372775520
Short name T361
Test name
Test status
Simulation time 3385064341 ps
CPU time 46.59 seconds
Started Mar 14 12:41:59 PM PDT 24
Finished Mar 14 12:42:46 PM PDT 24
Peak memory 200060 kb
Host smart-3673bba2-0b6a-46c9-a85d-9401f78da48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372775520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3372775520
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2384253551
Short name T212
Test name
Test status
Simulation time 366088298 ps
CPU time 5.7 seconds
Started Mar 14 12:41:58 PM PDT 24
Finished Mar 14 12:42:04 PM PDT 24
Peak memory 200032 kb
Host smart-33fc8c94-d2a9-4d69-9dd3-22a0961c3580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384253551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2384253551
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.233882854
Short name T601
Test name
Test status
Simulation time 36893322053 ps
CPU time 646.92 seconds
Started Mar 14 12:41:58 PM PDT 24
Finished Mar 14 12:52:46 PM PDT 24
Peak memory 227540 kb
Host smart-5ac79e3d-e21b-4ee2-b1e0-93940b253fe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233882854 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.233882854
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.4099965103
Short name T364
Test name
Test status
Simulation time 70399865 ps
CPU time 1.23 seconds
Started Mar 14 12:41:59 PM PDT 24
Finished Mar 14 12:42:01 PM PDT 24
Peak memory 199816 kb
Host smart-c7790fa5-c458-4e2a-9130-3bd71a04a2ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099965103 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.4099965103
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2912786862
Short name T57
Test name
Test status
Simulation time 347226452296 ps
CPU time 512.02 seconds
Started Mar 14 12:41:58 PM PDT 24
Finished Mar 14 12:50:31 PM PDT 24
Peak memory 199916 kb
Host smart-dd55ccf5-e1e5-49d4-b845-a2b42aa982f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912786862 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.2912786862
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3641735303
Short name T318
Test name
Test status
Simulation time 306752235 ps
CPU time 6.14 seconds
Started Mar 14 12:42:01 PM PDT 24
Finished Mar 14 12:42:07 PM PDT 24
Peak memory 199968 kb
Host smart-f14c052f-15fe-4cb7-bbf7-944ce7113b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641735303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3641735303
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.502210058
Short name T194
Test name
Test status
Simulation time 31360272 ps
CPU time 0.59 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:42:11 PM PDT 24
Peak memory 195628 kb
Host smart-bda7ff03-afc6-45f2-912c-08b930da5d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502210058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.502210058
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.4029071587
Short name T53
Test name
Test status
Simulation time 4576304096 ps
CPU time 11.65 seconds
Started Mar 14 12:41:58 PM PDT 24
Finished Mar 14 12:42:10 PM PDT 24
Peak memory 208244 kb
Host smart-d27c54d9-4d8a-4a12-9d00-d0b6b7a640d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4029071587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.4029071587
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.740812320
Short name T381
Test name
Test status
Simulation time 3247192853 ps
CPU time 36.64 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:42:47 PM PDT 24
Peak memory 200144 kb
Host smart-1c37a250-d706-4c3f-9c97-1851d2eb1164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740812320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.740812320
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1746098911
Short name T389
Test name
Test status
Simulation time 1571545609 ps
CPU time 84.44 seconds
Started Mar 14 12:42:07 PM PDT 24
Finished Mar 14 12:43:32 PM PDT 24
Peak memory 200040 kb
Host smart-6b67c743-2eb2-4b95-af10-7a3587017679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746098911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1746098911
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2497853836
Short name T3
Test name
Test status
Simulation time 9419315021 ps
CPU time 117.23 seconds
Started Mar 14 12:42:11 PM PDT 24
Finished Mar 14 12:44:08 PM PDT 24
Peak memory 200040 kb
Host smart-6f27c962-ac2a-408e-b356-bdbfa0800dba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497853836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2497853836
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2647455082
Short name T566
Test name
Test status
Simulation time 15276088694 ps
CPU time 66.56 seconds
Started Mar 14 12:41:58 PM PDT 24
Finished Mar 14 12:43:05 PM PDT 24
Peak memory 199936 kb
Host smart-593c4c46-76d2-4d47-a68f-efb2b31065e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647455082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2647455082
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3807046787
Short name T508
Test name
Test status
Simulation time 140708532 ps
CPU time 4.21 seconds
Started Mar 14 12:41:59 PM PDT 24
Finished Mar 14 12:42:03 PM PDT 24
Peak memory 199920 kb
Host smart-a0cf76da-6945-4ebe-b7ac-4de974b2ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807046787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3807046787
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3644052034
Short name T415
Test name
Test status
Simulation time 218189283143 ps
CPU time 740.75 seconds
Started Mar 14 12:42:09 PM PDT 24
Finished Mar 14 12:54:30 PM PDT 24
Peak memory 200108 kb
Host smart-9cf04720-a482-4e83-9470-add26d3f45fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644052034 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3644052034
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.195480712
Short name T296
Test name
Test status
Simulation time 133997283 ps
CPU time 1.26 seconds
Started Mar 14 12:42:07 PM PDT 24
Finished Mar 14 12:42:08 PM PDT 24
Peak memory 200004 kb
Host smart-4c27b64c-397c-4274-ba90-6fc5231e0e5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195480712 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.195480712
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3428427614
Short name T210
Test name
Test status
Simulation time 65445357187 ps
CPU time 453.15 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:49:43 PM PDT 24
Peak memory 199956 kb
Host smart-4214bfb5-cb4c-4f6a-8cbb-e29d284d970e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428427614 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.3428427614
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2784264960
Short name T496
Test name
Test status
Simulation time 32696824134 ps
CPU time 70.64 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:43:21 PM PDT 24
Peak memory 199872 kb
Host smart-3f88db16-cd43-4bc7-84c8-71dab6901d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784264960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2784264960
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1013309186
Short name T484
Test name
Test status
Simulation time 24768288 ps
CPU time 0.56 seconds
Started Mar 14 12:40:06 PM PDT 24
Finished Mar 14 12:40:07 PM PDT 24
Peak memory 195328 kb
Host smart-8a7abc6a-2f2d-45c1-891b-6f7c99aaba4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013309186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1013309186
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.261782195
Short name T108
Test name
Test status
Simulation time 813384104 ps
CPU time 27.94 seconds
Started Mar 14 12:39:55 PM PDT 24
Finished Mar 14 12:40:24 PM PDT 24
Peak memory 225212 kb
Host smart-ab81b325-e3f1-481d-be79-9a824cf92ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261782195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.261782195
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3463972445
Short name T391
Test name
Test status
Simulation time 2039529352 ps
CPU time 41.14 seconds
Started Mar 14 12:39:56 PM PDT 24
Finished Mar 14 12:40:37 PM PDT 24
Peak memory 200024 kb
Host smart-3a14175c-f4ec-403b-915a-961642a9d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463972445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3463972445
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2191067897
Short name T528
Test name
Test status
Simulation time 169716551 ps
CPU time 8.79 seconds
Started Mar 14 12:39:56 PM PDT 24
Finished Mar 14 12:40:05 PM PDT 24
Peak memory 200044 kb
Host smart-cbfaa76b-213d-4670-a71c-489be5249368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191067897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2191067897
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2461783590
Short name T232
Test name
Test status
Simulation time 26143346664 ps
CPU time 107.52 seconds
Started Mar 14 12:39:57 PM PDT 24
Finished Mar 14 12:41:44 PM PDT 24
Peak memory 200028 kb
Host smart-0cd7ae49-661d-4103-9862-978b04a35df6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461783590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2461783590
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2503048293
Short name T220
Test name
Test status
Simulation time 2070583392 ps
CPU time 94.67 seconds
Started Mar 14 12:39:54 PM PDT 24
Finished Mar 14 12:41:30 PM PDT 24
Peak memory 199992 kb
Host smart-ee727535-bad8-42de-abed-1e4071f9deca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503048293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2503048293
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.536627417
Short name T34
Test name
Test status
Simulation time 84233545 ps
CPU time 0.93 seconds
Started Mar 14 12:40:06 PM PDT 24
Finished Mar 14 12:40:07 PM PDT 24
Peak memory 219140 kb
Host smart-08a9c63b-a95c-40d7-bc6c-f77a6f48a1d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536627417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.536627417
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3591914477
Short name T4
Test name
Test status
Simulation time 215454184 ps
CPU time 3.33 seconds
Started Mar 14 12:39:58 PM PDT 24
Finished Mar 14 12:40:02 PM PDT 24
Peak memory 199940 kb
Host smart-a825345a-e33e-478b-8345-20bfc72054df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591914477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3591914477
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1428345471
Short name T574
Test name
Test status
Simulation time 58578916595 ps
CPU time 1165.08 seconds
Started Mar 14 12:40:04 PM PDT 24
Finished Mar 14 12:59:30 PM PDT 24
Peak memory 241072 kb
Host smart-606aa9f6-3e25-4f2d-ad7c-3e311f31c2ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428345471 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1428345471
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3405117064
Short name T133
Test name
Test status
Simulation time 56996307 ps
CPU time 1.14 seconds
Started Mar 14 12:39:55 PM PDT 24
Finished Mar 14 12:39:57 PM PDT 24
Peak memory 199828 kb
Host smart-7b936688-db08-476a-9331-8545db848a58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405117064 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3405117064
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2348361665
Short name T482
Test name
Test status
Simulation time 32177880961 ps
CPU time 416.27 seconds
Started Mar 14 12:39:55 PM PDT 24
Finished Mar 14 12:46:52 PM PDT 24
Peak memory 200000 kb
Host smart-ff1d24c8-162f-441c-9cf1-85d754686737
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348361665 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2348361665
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3397629255
Short name T527
Test name
Test status
Simulation time 2238834828 ps
CPU time 38.42 seconds
Started Mar 14 12:39:56 PM PDT 24
Finished Mar 14 12:40:35 PM PDT 24
Peak memory 200000 kb
Host smart-b0d74a5c-3c13-4f88-ac58-3390a5e95bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397629255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3397629255
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.589716557
Short name T255
Test name
Test status
Simulation time 35390259 ps
CPU time 0.55 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:42:11 PM PDT 24
Peak memory 195696 kb
Host smart-f9a73809-574b-46e0-80c6-a6ba09f4b847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589716557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.589716557
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1125489584
Short name T468
Test name
Test status
Simulation time 1957463882 ps
CPU time 33.75 seconds
Started Mar 14 12:42:11 PM PDT 24
Finished Mar 14 12:42:45 PM PDT 24
Peak memory 222552 kb
Host smart-28c7201a-7bee-4801-be2c-176dc9468668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125489584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1125489584
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.907591805
Short name T305
Test name
Test status
Simulation time 12548223121 ps
CPU time 45.51 seconds
Started Mar 14 12:42:09 PM PDT 24
Finished Mar 14 12:42:54 PM PDT 24
Peak memory 200092 kb
Host smart-a9ff4521-4c11-497f-bc5d-56892bd0db83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907591805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.907591805
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.490880697
Short name T140
Test name
Test status
Simulation time 1887245797 ps
CPU time 35.52 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:42:46 PM PDT 24
Peak memory 200020 kb
Host smart-eac5b4c5-4996-44ff-8341-65d221570eb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=490880697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.490880697
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.915044108
Short name T480
Test name
Test status
Simulation time 63453755758 ps
CPU time 102.61 seconds
Started Mar 14 12:42:11 PM PDT 24
Finished Mar 14 12:43:54 PM PDT 24
Peak memory 200140 kb
Host smart-96170a7b-1713-490a-899d-8826f4466743
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915044108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.915044108
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1689218969
Short name T40
Test name
Test status
Simulation time 22729990854 ps
CPU time 71.73 seconds
Started Mar 14 12:42:13 PM PDT 24
Finished Mar 14 12:43:25 PM PDT 24
Peak memory 200028 kb
Host smart-d9845955-fb06-4db1-918d-2eb5540732ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689218969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1689218969
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2917508536
Short name T211
Test name
Test status
Simulation time 1043552088 ps
CPU time 6.05 seconds
Started Mar 14 12:42:11 PM PDT 24
Finished Mar 14 12:42:17 PM PDT 24
Peak memory 199992 kb
Host smart-bb37f2ff-bad8-478a-8696-aa70434c84d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917508536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2917508536
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.532060988
Short name T6
Test name
Test status
Simulation time 776818479606 ps
CPU time 2551.06 seconds
Started Mar 14 12:42:08 PM PDT 24
Finished Mar 14 01:24:40 PM PDT 24
Peak memory 216400 kb
Host smart-4f95baac-2dc5-4f1f-beac-2acc06ecc891
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532060988 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.532060988
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1592094034
Short name T405
Test name
Test status
Simulation time 296163404 ps
CPU time 1.18 seconds
Started Mar 14 12:42:11 PM PDT 24
Finished Mar 14 12:42:12 PM PDT 24
Peak memory 199968 kb
Host smart-d8e9583d-860a-41b9-960d-8af9c4f2e837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592094034 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1592094034
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2783894708
Short name T274
Test name
Test status
Simulation time 206846262113 ps
CPU time 485.98 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:50:16 PM PDT 24
Peak memory 200044 kb
Host smart-6e13cf71-865a-40b6-8b92-5b228578faaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783894708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2783894708
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3247671871
Short name T246
Test name
Test status
Simulation time 436172304 ps
CPU time 8.69 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:42:19 PM PDT 24
Peak memory 200048 kb
Host smart-99cc3678-5812-42e2-ac43-79ef050223a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247671871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3247671871
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.327699809
Short name T481
Test name
Test status
Simulation time 27417953 ps
CPU time 0.56 seconds
Started Mar 14 12:42:08 PM PDT 24
Finished Mar 14 12:42:09 PM PDT 24
Peak memory 195732 kb
Host smart-96230ae5-d027-441f-952e-a5a1cd9baa5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327699809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.327699809
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1435854623
Short name T330
Test name
Test status
Simulation time 5618182896 ps
CPU time 57.02 seconds
Started Mar 14 12:42:07 PM PDT 24
Finished Mar 14 12:43:05 PM PDT 24
Peak memory 227768 kb
Host smart-bb1b9a5b-c33d-4f2e-aa84-a3a557f82a93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435854623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1435854623
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1017212026
Short name T349
Test name
Test status
Simulation time 3724206741 ps
CPU time 17.38 seconds
Started Mar 14 12:42:11 PM PDT 24
Finished Mar 14 12:42:28 PM PDT 24
Peak memory 200064 kb
Host smart-a528b309-d963-4278-bdc7-309cd1e564ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017212026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1017212026
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2574119254
Short name T174
Test name
Test status
Simulation time 7984783092 ps
CPU time 109.48 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:43:59 PM PDT 24
Peak memory 200100 kb
Host smart-3fc389c4-c0db-4a40-8672-ac7fb62aca7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574119254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2574119254
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.217896879
Short name T105
Test name
Test status
Simulation time 7442434239 ps
CPU time 46.42 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:42:57 PM PDT 24
Peak memory 200100 kb
Host smart-5a4392ac-3248-4f37-b72d-c52c30dc97c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217896879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.217896879
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.687341226
Short name T474
Test name
Test status
Simulation time 4125923932 ps
CPU time 74.53 seconds
Started Mar 14 12:42:08 PM PDT 24
Finished Mar 14 12:43:23 PM PDT 24
Peak memory 200048 kb
Host smart-0b229500-d595-43a4-ba9e-eebadd4e5b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687341226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.687341226
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.33971692
Short name T286
Test name
Test status
Simulation time 72397973 ps
CPU time 2.55 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:42:12 PM PDT 24
Peak memory 200080 kb
Host smart-e03af826-473a-4783-9f20-08b6d5518d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33971692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.33971692
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1962462814
Short name T27
Test name
Test status
Simulation time 96622171621 ps
CPU time 1195.35 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 01:02:06 PM PDT 24
Peak memory 200080 kb
Host smart-6b77e74a-ea51-4790-8946-7a25bb92ea02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962462814 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1962462814
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1770267642
Short name T213
Test name
Test status
Simulation time 71712049 ps
CPU time 1.23 seconds
Started Mar 14 12:42:11 PM PDT 24
Finished Mar 14 12:42:12 PM PDT 24
Peak memory 200036 kb
Host smart-f8e8367b-93ed-451b-ba88-02e13b202809
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770267642 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1770267642
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.3666596555
Short name T531
Test name
Test status
Simulation time 551542513714 ps
CPU time 488.64 seconds
Started Mar 14 12:42:16 PM PDT 24
Finished Mar 14 12:50:24 PM PDT 24
Peak memory 200000 kb
Host smart-00e0af6d-1923-472e-bee7-6b08388732d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666596555 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.3666596555
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3888922622
Short name T223
Test name
Test status
Simulation time 6663266816 ps
CPU time 83.4 seconds
Started Mar 14 12:42:07 PM PDT 24
Finished Mar 14 12:43:31 PM PDT 24
Peak memory 200124 kb
Host smart-d636d902-9852-4726-86ad-b9de4b41997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888922622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3888922622
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1205189685
Short name T208
Test name
Test status
Simulation time 41410352 ps
CPU time 0.54 seconds
Started Mar 14 12:42:17 PM PDT 24
Finished Mar 14 12:42:18 PM PDT 24
Peak memory 195252 kb
Host smart-890b6a0c-d1e9-4d77-b6a6-aea18cdda360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205189685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1205189685
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2211571573
Short name T464
Test name
Test status
Simulation time 131807352 ps
CPU time 1.42 seconds
Started Mar 14 12:42:09 PM PDT 24
Finished Mar 14 12:42:10 PM PDT 24
Peak memory 199920 kb
Host smart-e958a879-800a-44e9-a91d-5114ccd97ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211571573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2211571573
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.345322375
Short name T282
Test name
Test status
Simulation time 30668011744 ps
CPU time 40.44 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:42:51 PM PDT 24
Peak memory 200104 kb
Host smart-419185e0-b7e2-452a-b216-83ee43d57e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345322375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.345322375
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1320757685
Short name T408
Test name
Test status
Simulation time 5693579707 ps
CPU time 152.74 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:44:44 PM PDT 24
Peak memory 200028 kb
Host smart-0994c8ef-4f12-47c9-becb-80bcc293c477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320757685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1320757685
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3653417046
Short name T43
Test name
Test status
Simulation time 37747161079 ps
CPU time 114.6 seconds
Started Mar 14 12:42:10 PM PDT 24
Finished Mar 14 12:44:05 PM PDT 24
Peak memory 199864 kb
Host smart-4e2e8ae2-81c8-425d-b880-265af9e0d812
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653417046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3653417046
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.306952232
Short name T553
Test name
Test status
Simulation time 5445908115 ps
CPU time 19.75 seconds
Started Mar 14 12:42:11 PM PDT 24
Finished Mar 14 12:42:31 PM PDT 24
Peak memory 200040 kb
Host smart-e1cb03bc-7a20-4811-8cde-750079a301a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306952232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.306952232
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1188491317
Short name T182
Test name
Test status
Simulation time 235757616 ps
CPU time 1.2 seconds
Started Mar 14 12:42:09 PM PDT 24
Finished Mar 14 12:42:11 PM PDT 24
Peak memory 199908 kb
Host smart-9b67ae9a-ab66-40c2-9023-07dd7abb5cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188491317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1188491317
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3270418995
Short name T52
Test name
Test status
Simulation time 33431898860 ps
CPU time 1725.28 seconds
Started Mar 14 12:42:18 PM PDT 24
Finished Mar 14 01:11:04 PM PDT 24
Peak memory 211784 kb
Host smart-277235af-26fa-4656-9134-e2d28fb98d89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270418995 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3270418995
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1843724884
Short name T137
Test name
Test status
Simulation time 81116318 ps
CPU time 0.93 seconds
Started Mar 14 12:42:19 PM PDT 24
Finished Mar 14 12:42:20 PM PDT 24
Peak memory 198276 kb
Host smart-a95f09e5-fa9b-4323-b4fb-035e299f5da2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843724884 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1843724884
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.95271445
Short name T230
Test name
Test status
Simulation time 29724564216 ps
CPU time 384.72 seconds
Started Mar 14 12:42:21 PM PDT 24
Finished Mar 14 12:48:46 PM PDT 24
Peak memory 200056 kb
Host smart-6c9cc70a-499c-44ce-84bd-fefe7af853c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95271445 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.95271445
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3897238753
Short name T544
Test name
Test status
Simulation time 1495764808 ps
CPU time 27.33 seconds
Started Mar 14 12:42:17 PM PDT 24
Finished Mar 14 12:42:45 PM PDT 24
Peak memory 199948 kb
Host smart-f9677270-f926-485c-8e6b-32411a119777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897238753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3897238753
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3212563063
Short name T23
Test name
Test status
Simulation time 38862257 ps
CPU time 0.55 seconds
Started Mar 14 12:42:20 PM PDT 24
Finished Mar 14 12:42:21 PM PDT 24
Peak memory 194416 kb
Host smart-d77905ca-9878-410a-b244-a1386515dad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212563063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3212563063
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.434629145
Short name T261
Test name
Test status
Simulation time 1806408304 ps
CPU time 9.14 seconds
Started Mar 14 12:42:18 PM PDT 24
Finished Mar 14 12:42:27 PM PDT 24
Peak memory 228096 kb
Host smart-a9576e0a-fb30-4960-8e0b-7997f51eb5da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434629145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.434629145
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.4016556386
Short name T400
Test name
Test status
Simulation time 5635141624 ps
CPU time 5.93 seconds
Started Mar 14 12:42:19 PM PDT 24
Finished Mar 14 12:42:25 PM PDT 24
Peak memory 200020 kb
Host smart-11177ee8-1940-4d94-8dd2-ae97e622a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016556386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4016556386
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2584877009
Short name T581
Test name
Test status
Simulation time 2096785140 ps
CPU time 122 seconds
Started Mar 14 12:42:17 PM PDT 24
Finished Mar 14 12:44:19 PM PDT 24
Peak memory 200020 kb
Host smart-26d2501d-462a-4070-b2b3-b3f1a6fa4ff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584877009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2584877009
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1342856879
Short name T169
Test name
Test status
Simulation time 43219837353 ps
CPU time 147.74 seconds
Started Mar 14 12:42:23 PM PDT 24
Finished Mar 14 12:44:51 PM PDT 24
Peak memory 200008 kb
Host smart-a53e2e91-a6b5-4bdc-bdec-b02be758605b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342856879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1342856879
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3413595875
Short name T435
Test name
Test status
Simulation time 2438837503 ps
CPU time 73 seconds
Started Mar 14 12:42:18 PM PDT 24
Finished Mar 14 12:43:32 PM PDT 24
Peak memory 200060 kb
Host smart-bf1e71e4-31a2-45b6-995a-0958ef1d66ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413595875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3413595875
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2564259791
Short name T600
Test name
Test status
Simulation time 372260124 ps
CPU time 1.67 seconds
Started Mar 14 12:42:17 PM PDT 24
Finished Mar 14 12:42:19 PM PDT 24
Peak memory 199860 kb
Host smart-cbf6204e-7d2b-491c-954f-75d87db13eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564259791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2564259791
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2794734768
Short name T509
Test name
Test status
Simulation time 1616604552930 ps
CPU time 1521.51 seconds
Started Mar 14 12:42:20 PM PDT 24
Finished Mar 14 01:07:42 PM PDT 24
Peak memory 227776 kb
Host smart-882d51d5-e29e-4c51-b5eb-8763cd054c7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794734768 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2794734768
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2784446477
Short name T448
Test name
Test status
Simulation time 266629116 ps
CPU time 1.31 seconds
Started Mar 14 12:42:19 PM PDT 24
Finished Mar 14 12:42:21 PM PDT 24
Peak memory 199796 kb
Host smart-288cd513-17da-4ae6-80a8-7a1c449c0aa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784446477 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2784446477
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3505193960
Short name T221
Test name
Test status
Simulation time 7605114895 ps
CPU time 416.4 seconds
Started Mar 14 12:42:19 PM PDT 24
Finished Mar 14 12:49:16 PM PDT 24
Peak memory 200000 kb
Host smart-2a64a7e9-4435-465f-aef3-be4457b3fb7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505193960 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3505193960
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1617024767
Short name T72
Test name
Test status
Simulation time 15279150802 ps
CPU time 76.56 seconds
Started Mar 14 12:42:18 PM PDT 24
Finished Mar 14 12:43:35 PM PDT 24
Peak memory 200072 kb
Host smart-bfb7cc2d-cd90-440c-b514-e3cb881478c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617024767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1617024767
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3647636774
Short name T26
Test name
Test status
Simulation time 17366076 ps
CPU time 0.55 seconds
Started Mar 14 12:42:29 PM PDT 24
Finished Mar 14 12:42:31 PM PDT 24
Peak memory 195344 kb
Host smart-631e4992-de50-4db6-8b18-70f9631a8caf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647636774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3647636774
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.592417060
Short name T437
Test name
Test status
Simulation time 2446070252 ps
CPU time 42.81 seconds
Started Mar 14 12:42:19 PM PDT 24
Finished Mar 14 12:43:02 PM PDT 24
Peak memory 215976 kb
Host smart-1b000ffb-61a0-4edd-9cbb-c5341dacc610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=592417060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.592417060
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2344079875
Short name T280
Test name
Test status
Simulation time 12156168512 ps
CPU time 51.56 seconds
Started Mar 14 12:42:23 PM PDT 24
Finished Mar 14 12:43:14 PM PDT 24
Peak memory 199960 kb
Host smart-8115cffa-c16e-4925-af8b-b620a366b993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344079875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2344079875
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3008914424
Short name T412
Test name
Test status
Simulation time 5688544986 ps
CPU time 78.19 seconds
Started Mar 14 12:42:21 PM PDT 24
Finished Mar 14 12:43:39 PM PDT 24
Peak memory 200080 kb
Host smart-d066f806-e60f-46d8-aee3-467635fe2f46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008914424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3008914424
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3224641966
Short name T439
Test name
Test status
Simulation time 4089009560 ps
CPU time 76.37 seconds
Started Mar 14 12:42:19 PM PDT 24
Finished Mar 14 12:43:36 PM PDT 24
Peak memory 200100 kb
Host smart-daa70d23-9bfe-49f6-8c16-c213ccccb031
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224641966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3224641966
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3565306883
Short name T183
Test name
Test status
Simulation time 446398223 ps
CPU time 6.39 seconds
Started Mar 14 12:42:20 PM PDT 24
Finished Mar 14 12:42:26 PM PDT 24
Peak memory 199968 kb
Host smart-5a345503-b695-48b3-ad5d-c8d4f02dcff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565306883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3565306883
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2646739689
Short name T372
Test name
Test status
Simulation time 1962115343 ps
CPU time 2.89 seconds
Started Mar 14 12:42:19 PM PDT 24
Finished Mar 14 12:42:22 PM PDT 24
Peak memory 200048 kb
Host smart-a30b80a7-96c3-43c0-b841-b7535b7aef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646739689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2646739689
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.603536141
Short name T180
Test name
Test status
Simulation time 21010638296 ps
CPU time 159.36 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:45:08 PM PDT 24
Peak memory 200064 kb
Host smart-2117c15c-4293-4957-8012-23d5456c0a7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603536141 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.603536141
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2108427884
Short name T476
Test name
Test status
Simulation time 74796117 ps
CPU time 1.26 seconds
Started Mar 14 12:42:29 PM PDT 24
Finished Mar 14 12:42:31 PM PDT 24
Peak memory 199864 kb
Host smart-e030a0c0-1b74-4294-a234-a4a208ebdcf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108427884 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2108427884
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1090818965
Short name T473
Test name
Test status
Simulation time 9559484854 ps
CPU time 441.4 seconds
Started Mar 14 12:42:20 PM PDT 24
Finished Mar 14 12:49:41 PM PDT 24
Peak memory 199928 kb
Host smart-119e8aaf-b1aa-444f-98ec-9d9d10f43ece
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090818965 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1090818965
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3126430656
Short name T392
Test name
Test status
Simulation time 3930413915 ps
CPU time 75.74 seconds
Started Mar 14 12:42:18 PM PDT 24
Finished Mar 14 12:43:34 PM PDT 24
Peak memory 200080 kb
Host smart-6643f5d6-08e8-4177-b272-6f3b2389ed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126430656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3126430656
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1759467747
Short name T543
Test name
Test status
Simulation time 36364066 ps
CPU time 0.54 seconds
Started Mar 14 12:42:26 PM PDT 24
Finished Mar 14 12:42:27 PM PDT 24
Peak memory 195136 kb
Host smart-e5b20c35-3479-448d-a4dd-fc8e1a5146e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759467747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1759467747
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1343796790
Short name T425
Test name
Test status
Simulation time 160878151 ps
CPU time 5.5 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:42:34 PM PDT 24
Peak memory 199964 kb
Host smart-969dfebd-d510-4d85-9637-712c6085ce6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1343796790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1343796790
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.310570517
Short name T595
Test name
Test status
Simulation time 628366928 ps
CPU time 14.59 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:42:43 PM PDT 24
Peak memory 200056 kb
Host smart-99f0bd14-5811-460a-b2c9-78c81b5c4f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310570517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.310570517
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1038918316
Short name T165
Test name
Test status
Simulation time 1894435407 ps
CPU time 104.56 seconds
Started Mar 14 12:42:25 PM PDT 24
Finished Mar 14 12:44:10 PM PDT 24
Peak memory 199948 kb
Host smart-1f08cbb0-0cda-481e-a38b-7b5b7ac92412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038918316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1038918316
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.332313902
Short name T317
Test name
Test status
Simulation time 8754793490 ps
CPU time 139.72 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:44:48 PM PDT 24
Peak memory 200012 kb
Host smart-1a6bc46d-2786-4a3e-883a-ea734d6efe4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332313902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.332313902
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2035171117
Short name T603
Test name
Test status
Simulation time 11025619143 ps
CPU time 52.29 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:43:22 PM PDT 24
Peak memory 200032 kb
Host smart-f54853ec-2e72-45f9-aea8-cfb82a223fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035171117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2035171117
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1140675919
Short name T260
Test name
Test status
Simulation time 2415633526 ps
CPU time 6.88 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:42:36 PM PDT 24
Peak memory 200052 kb
Host smart-975f7116-9952-4195-beee-50f77a818444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140675919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1140675919
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.117000648
Short name T79
Test name
Test status
Simulation time 40706362608 ps
CPU time 137.67 seconds
Started Mar 14 12:42:27 PM PDT 24
Finished Mar 14 12:44:45 PM PDT 24
Peak memory 200144 kb
Host smart-7ceaeee0-1794-473d-970c-d460b9ad5785
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117000648 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.117000648
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.303177162
Short name T86
Test name
Test status
Simulation time 282994610 ps
CPU time 1.28 seconds
Started Mar 14 12:42:30 PM PDT 24
Finished Mar 14 12:42:32 PM PDT 24
Peak memory 200008 kb
Host smart-d8a6842b-e4ea-47d6-8623-f0f9bf2bbc80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303177162 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.303177162
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.94955944
Short name T535
Test name
Test status
Simulation time 111517396543 ps
CPU time 471.38 seconds
Started Mar 14 12:42:29 PM PDT 24
Finished Mar 14 12:50:22 PM PDT 24
Peak memory 200004 kb
Host smart-546bebeb-ea86-46e3-8194-3e7a3aa527d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94955944 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.94955944
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.632998618
Short name T337
Test name
Test status
Simulation time 10312829833 ps
CPU time 24.05 seconds
Started Mar 14 12:42:31 PM PDT 24
Finished Mar 14 12:42:55 PM PDT 24
Peak memory 199968 kb
Host smart-b8c6b468-2556-4e33-ac47-1168b0b83fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632998618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.632998618
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4080955368
Short name T329
Test name
Test status
Simulation time 21996561 ps
CPU time 0.54 seconds
Started Mar 14 12:42:29 PM PDT 24
Finished Mar 14 12:42:31 PM PDT 24
Peak memory 195524 kb
Host smart-b89cf9e2-b1f0-4d09-91d8-6d8975fca8bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080955368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4080955368
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.327999128
Short name T500
Test name
Test status
Simulation time 1422648893 ps
CPU time 17.49 seconds
Started Mar 14 12:42:29 PM PDT 24
Finished Mar 14 12:42:48 PM PDT 24
Peak memory 200076 kb
Host smart-8fc9afe2-a6a0-4bbe-81eb-036699e532b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327999128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.327999128
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1069034339
Short name T84
Test name
Test status
Simulation time 2885228775 ps
CPU time 83.42 seconds
Started Mar 14 12:42:25 PM PDT 24
Finished Mar 14 12:43:48 PM PDT 24
Peak memory 200068 kb
Host smart-f585b972-1158-40b9-82f1-363f9bab92d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069034339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1069034339
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2912321668
Short name T530
Test name
Test status
Simulation time 2970966455 ps
CPU time 153.62 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:45:02 PM PDT 24
Peak memory 200108 kb
Host smart-281fecb1-3f4c-4df2-ab27-54eba8882cdf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912321668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2912321668
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.624009511
Short name T503
Test name
Test status
Simulation time 6984598082 ps
CPU time 90.41 seconds
Started Mar 14 12:42:30 PM PDT 24
Finished Mar 14 12:44:01 PM PDT 24
Peak memory 200144 kb
Host smart-95572f0c-7aad-4883-808f-6dd4d4aa6826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624009511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.624009511
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1204102473
Short name T388
Test name
Test status
Simulation time 136159278 ps
CPU time 1.43 seconds
Started Mar 14 12:42:29 PM PDT 24
Finished Mar 14 12:42:30 PM PDT 24
Peak memory 199940 kb
Host smart-a4b08aa2-b882-4b3a-8f36-6e9da87286ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204102473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1204102473
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1422979624
Short name T441
Test name
Test status
Simulation time 145518696514 ps
CPU time 541.5 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:51:31 PM PDT 24
Peak memory 208288 kb
Host smart-1cbfb77e-de33-4897-a771-ccbc17b9afea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422979624 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1422979624
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.2425024864
Short name T45
Test name
Test status
Simulation time 604254627008 ps
CPU time 3994.81 seconds
Started Mar 14 12:42:26 PM PDT 24
Finished Mar 14 01:49:02 PM PDT 24
Peak memory 262344 kb
Host smart-655b392d-0a56-4e15-b299-7320b716b12a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425024864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.2425024864
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3446260104
Short name T309
Test name
Test status
Simulation time 68772662 ps
CPU time 1.19 seconds
Started Mar 14 12:42:27 PM PDT 24
Finished Mar 14 12:42:29 PM PDT 24
Peak memory 200020 kb
Host smart-a48901b2-658d-4fe7-b6fc-d154b334bf55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446260104 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3446260104
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1280497729
Short name T110
Test name
Test status
Simulation time 42373316434 ps
CPU time 490.44 seconds
Started Mar 14 12:42:31 PM PDT 24
Finished Mar 14 12:50:42 PM PDT 24
Peak memory 199816 kb
Host smart-90c0cf3f-58b1-4933-ac93-7d75a86e16c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280497729 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1280497729
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2757269382
Short name T2
Test name
Test status
Simulation time 19297335727 ps
CPU time 66.24 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:43:34 PM PDT 24
Peak memory 200072 kb
Host smart-d0a9b24a-9414-47f8-a0fd-dbb1bf4ba9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757269382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2757269382
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3581253383
Short name T597
Test name
Test status
Simulation time 22925506 ps
CPU time 0.58 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:42:29 PM PDT 24
Peak memory 195604 kb
Host smart-13e1296a-024d-4ad2-9955-996931b219da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581253383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3581253383
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2517078550
Short name T207
Test name
Test status
Simulation time 1127830919 ps
CPU time 48.77 seconds
Started Mar 14 12:42:29 PM PDT 24
Finished Mar 14 12:43:18 PM PDT 24
Peak memory 232080 kb
Host smart-e2a6826d-5f29-438e-9bb2-98e0b1af9124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517078550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2517078550
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3156996226
Short name T275
Test name
Test status
Simulation time 4903746713 ps
CPU time 23.61 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:42:52 PM PDT 24
Peak memory 199984 kb
Host smart-d3702b7b-9ef4-4b68-ba39-1c25ac1fee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156996226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3156996226
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.468885257
Short name T511
Test name
Test status
Simulation time 2578351383 ps
CPU time 9.21 seconds
Started Mar 14 12:42:27 PM PDT 24
Finished Mar 14 12:42:36 PM PDT 24
Peak memory 199864 kb
Host smart-b28b258e-2be4-4daa-85d9-052fd746d2e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468885257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.468885257
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.959057022
Short name T152
Test name
Test status
Simulation time 1551946743 ps
CPU time 82.6 seconds
Started Mar 14 12:42:26 PM PDT 24
Finished Mar 14 12:43:49 PM PDT 24
Peak memory 200032 kb
Host smart-c1ae10a1-05a2-4383-b1bd-e79dce3ee512
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959057022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.959057022
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.655713503
Short name T166
Test name
Test status
Simulation time 17837591407 ps
CPU time 37.99 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:43:06 PM PDT 24
Peak memory 200084 kb
Host smart-94de9f89-7c7d-493e-b69f-63aa4929451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655713503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.655713503
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2167434804
Short name T224
Test name
Test status
Simulation time 21757550 ps
CPU time 0.97 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:42:31 PM PDT 24
Peak memory 198640 kb
Host smart-dab9ca15-7a7c-44ef-b6f6-ab3144fb2948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167434804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2167434804
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2621018001
Short name T326
Test name
Test status
Simulation time 13695346983 ps
CPU time 766.05 seconds
Started Mar 14 12:42:29 PM PDT 24
Finished Mar 14 12:55:16 PM PDT 24
Peak memory 208116 kb
Host smart-213e3564-0039-4246-846d-4f0e0774bb88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621018001 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2621018001
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.4179766360
Short name T560
Test name
Test status
Simulation time 219107537 ps
CPU time 1.25 seconds
Started Mar 14 12:42:29 PM PDT 24
Finished Mar 14 12:42:32 PM PDT 24
Peak memory 199756 kb
Host smart-43de3967-771f-478e-8292-bd8d4e085aaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179766360 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.4179766360
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.282318594
Short name T150
Test name
Test status
Simulation time 167937707339 ps
CPU time 518.87 seconds
Started Mar 14 12:42:29 PM PDT 24
Finished Mar 14 12:51:09 PM PDT 24
Peak memory 199860 kb
Host smart-acb2817d-75d8-44b6-9dfe-4c626efbc404
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282318594 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.282318594
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1219363600
Short name T292
Test name
Test status
Simulation time 2727535280 ps
CPU time 40.45 seconds
Started Mar 14 12:42:28 PM PDT 24
Finished Mar 14 12:43:09 PM PDT 24
Peak memory 199912 kb
Host smart-79e8e2a1-c27e-4fd6-a467-c1ca0f9a71db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219363600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1219363600
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2173309573
Short name T25
Test name
Test status
Simulation time 10282372 ps
CPU time 0.57 seconds
Started Mar 14 12:42:35 PM PDT 24
Finished Mar 14 12:42:36 PM PDT 24
Peak memory 194400 kb
Host smart-91a6da93-edd1-4334-b119-1fbd81c6a4fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173309573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2173309573
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3817060924
Short name T354
Test name
Test status
Simulation time 1172089131 ps
CPU time 50.82 seconds
Started Mar 14 12:42:38 PM PDT 24
Finished Mar 14 12:43:29 PM PDT 24
Peak memory 224852 kb
Host smart-4511dea7-e400-4887-8abc-aac70dab5da3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817060924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3817060924
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.481998953
Short name T461
Test name
Test status
Simulation time 36078155510 ps
CPU time 44.29 seconds
Started Mar 14 12:42:35 PM PDT 24
Finished Mar 14 12:43:20 PM PDT 24
Peak memory 200012 kb
Host smart-9a5a3a7e-331f-4790-91d3-5e820efd04d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481998953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.481998953
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1629769927
Short name T308
Test name
Test status
Simulation time 721354175 ps
CPU time 12.13 seconds
Started Mar 14 12:42:38 PM PDT 24
Finished Mar 14 12:42:50 PM PDT 24
Peak memory 200080 kb
Host smart-50ee69c4-6c6b-44ad-9db9-a44f17132c47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1629769927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1629769927
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3630809045
Short name T589
Test name
Test status
Simulation time 492662786 ps
CPU time 3.19 seconds
Started Mar 14 12:42:37 PM PDT 24
Finished Mar 14 12:42:40 PM PDT 24
Peak memory 199852 kb
Host smart-7eeab9ea-38c4-4722-8a6a-c2b251bebeb2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630809045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3630809045
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.298854676
Short name T216
Test name
Test status
Simulation time 239573491 ps
CPU time 3.95 seconds
Started Mar 14 12:42:35 PM PDT 24
Finished Mar 14 12:42:40 PM PDT 24
Peak memory 199920 kb
Host smart-1b54dda7-9fe8-4ca0-aa93-867de50e5cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298854676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.298854676
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1350840972
Short name T570
Test name
Test status
Simulation time 191532427 ps
CPU time 5.08 seconds
Started Mar 14 12:42:40 PM PDT 24
Finished Mar 14 12:42:45 PM PDT 24
Peak memory 199916 kb
Host smart-c187286d-d021-4b37-bfdc-a409a3d9ad40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350840972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1350840972
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1467626722
Short name T316
Test name
Test status
Simulation time 44651512976 ps
CPU time 774.47 seconds
Started Mar 14 12:42:37 PM PDT 24
Finished Mar 14 12:55:32 PM PDT 24
Peak memory 240024 kb
Host smart-6c223841-c1f3-4d01-8e29-0813c7a07661
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467626722 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1467626722
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.4068624520
Short name T538
Test name
Test status
Simulation time 187172708 ps
CPU time 1.23 seconds
Started Mar 14 12:42:39 PM PDT 24
Finished Mar 14 12:42:40 PM PDT 24
Peak memory 199004 kb
Host smart-4373b07a-36ae-4abf-a6ef-47ac2be0a599
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068624520 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.4068624520
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3451569262
Short name T549
Test name
Test status
Simulation time 84454081576 ps
CPU time 526.46 seconds
Started Mar 14 12:42:35 PM PDT 24
Finished Mar 14 12:51:22 PM PDT 24
Peak memory 199796 kb
Host smart-096a953f-f915-439e-9305-0cd41ff9c289
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451569262 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3451569262
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3303312490
Short name T287
Test name
Test status
Simulation time 5858805885 ps
CPU time 85.31 seconds
Started Mar 14 12:42:38 PM PDT 24
Finished Mar 14 12:44:04 PM PDT 24
Peak memory 200008 kb
Host smart-327469f1-aab4-42bb-acab-1df4fc02ca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303312490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3303312490
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.4267827834
Short name T195
Test name
Test status
Simulation time 54055427 ps
CPU time 0.53 seconds
Started Mar 14 12:42:38 PM PDT 24
Finished Mar 14 12:42:38 PM PDT 24
Peak memory 195432 kb
Host smart-fe87ad7c-1c4f-45d1-b9a8-473ea3076580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267827834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.4267827834
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.460765077
Short name T320
Test name
Test status
Simulation time 1088915310 ps
CPU time 43.67 seconds
Started Mar 14 12:42:37 PM PDT 24
Finished Mar 14 12:43:21 PM PDT 24
Peak memory 225864 kb
Host smart-d69e13a2-7c0d-42d7-9919-4dd54929e382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460765077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.460765077
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3167612162
Short name T83
Test name
Test status
Simulation time 3529705327 ps
CPU time 51.27 seconds
Started Mar 14 12:42:35 PM PDT 24
Finished Mar 14 12:43:27 PM PDT 24
Peak memory 200076 kb
Host smart-ce7cadae-f9ba-47ac-88dc-08237fc92fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167612162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3167612162
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2136821613
Short name T385
Test name
Test status
Simulation time 1965210548 ps
CPU time 105.32 seconds
Started Mar 14 12:42:37 PM PDT 24
Finished Mar 14 12:44:22 PM PDT 24
Peak memory 199996 kb
Host smart-80bc810a-6d1e-411a-8568-fbdb73aea242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136821613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2136821613
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1880954655
Short name T504
Test name
Test status
Simulation time 413572050 ps
CPU time 7.13 seconds
Started Mar 14 12:42:37 PM PDT 24
Finished Mar 14 12:42:44 PM PDT 24
Peak memory 200044 kb
Host smart-9d057c35-fcf5-4119-9da9-5ea641127340
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880954655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1880954655
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3211805928
Short name T383
Test name
Test status
Simulation time 6498655888 ps
CPU time 89.28 seconds
Started Mar 14 12:42:40 PM PDT 24
Finished Mar 14 12:44:09 PM PDT 24
Peak memory 199984 kb
Host smart-db32b4df-f51c-4107-adbf-bc10092e616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211805928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3211805928
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2252317199
Short name T345
Test name
Test status
Simulation time 102888427 ps
CPU time 1.84 seconds
Started Mar 14 12:42:38 PM PDT 24
Finished Mar 14 12:42:40 PM PDT 24
Peak memory 199932 kb
Host smart-666bda4e-9837-41fd-9b66-f9b90a81f600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252317199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2252317199
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1768288140
Short name T454
Test name
Test status
Simulation time 759547769728 ps
CPU time 1579.77 seconds
Started Mar 14 12:42:35 PM PDT 24
Finished Mar 14 01:08:56 PM PDT 24
Peak memory 235720 kb
Host smart-1ed3ff53-339f-4b26-afad-1666e4a27bcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768288140 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1768288140
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1996086871
Short name T145
Test name
Test status
Simulation time 58917418 ps
CPU time 1.18 seconds
Started Mar 14 12:42:40 PM PDT 24
Finished Mar 14 12:42:41 PM PDT 24
Peak memory 199608 kb
Host smart-edf105ef-5c93-46f1-ab71-f422d914992f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996086871 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1996086871
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3969130077
Short name T534
Test name
Test status
Simulation time 42029820218 ps
CPU time 409.8 seconds
Started Mar 14 12:42:35 PM PDT 24
Finished Mar 14 12:49:25 PM PDT 24
Peak memory 199984 kb
Host smart-df7a155f-1374-4de7-ab9b-338e6df196a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969130077 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.3969130077
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3656641461
Short name T409
Test name
Test status
Simulation time 4536830341 ps
CPU time 7.46 seconds
Started Mar 14 12:42:36 PM PDT 24
Finished Mar 14 12:42:43 PM PDT 24
Peak memory 200016 kb
Host smart-a394c6c6-66b5-44c4-bedb-0d359da46bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656641461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3656641461
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.908445010
Short name T443
Test name
Test status
Simulation time 17999245 ps
CPU time 0.57 seconds
Started Mar 14 12:40:04 PM PDT 24
Finished Mar 14 12:40:05 PM PDT 24
Peak memory 195620 kb
Host smart-67b927ca-2a4f-4761-881b-0c3b5222b78c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908445010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.908445010
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2185000296
Short name T196
Test name
Test status
Simulation time 8273274646 ps
CPU time 51.94 seconds
Started Mar 14 12:40:05 PM PDT 24
Finished Mar 14 12:40:57 PM PDT 24
Peak memory 221604 kb
Host smart-155952cd-fce6-4076-a8ef-5983b3826400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185000296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2185000296
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2189609447
Short name T322
Test name
Test status
Simulation time 661472365 ps
CPU time 10.65 seconds
Started Mar 14 12:40:05 PM PDT 24
Finished Mar 14 12:40:16 PM PDT 24
Peak memory 199848 kb
Host smart-3de51f63-8425-48ab-9520-e6836781cbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189609447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2189609447
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1855879937
Short name T285
Test name
Test status
Simulation time 1647979243 ps
CPU time 22.92 seconds
Started Mar 14 12:40:07 PM PDT 24
Finished Mar 14 12:40:31 PM PDT 24
Peak memory 200036 kb
Host smart-e5ccc5ae-c72e-44b9-9077-e0be8cc928f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855879937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1855879937
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1472316261
Short name T569
Test name
Test status
Simulation time 1345248576 ps
CPU time 69.79 seconds
Started Mar 14 12:40:05 PM PDT 24
Finished Mar 14 12:41:15 PM PDT 24
Peak memory 199964 kb
Host smart-4b620b32-20dc-400d-a916-e75c4d709094
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472316261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1472316261
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3673000513
Short name T58
Test name
Test status
Simulation time 3082106377 ps
CPU time 9.86 seconds
Started Mar 14 12:40:07 PM PDT 24
Finished Mar 14 12:40:17 PM PDT 24
Peak memory 199936 kb
Host smart-a2598d20-7f5d-442c-9766-9ff7cb35982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673000513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3673000513
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1631313381
Short name T31
Test name
Test status
Simulation time 255604302 ps
CPU time 0.85 seconds
Started Mar 14 12:40:05 PM PDT 24
Finished Mar 14 12:40:06 PM PDT 24
Peak memory 218184 kb
Host smart-3ea35519-49b0-4370-b3ad-39b315fbf31d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631313381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1631313381
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.4006570604
Short name T582
Test name
Test status
Simulation time 498329153 ps
CPU time 6.33 seconds
Started Mar 14 12:40:07 PM PDT 24
Finished Mar 14 12:40:14 PM PDT 24
Peak memory 199972 kb
Host smart-78f7ab5f-93d1-4c11-be82-936995c667ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006570604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.4006570604
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3800554342
Short name T573
Test name
Test status
Simulation time 35038231263 ps
CPU time 103 seconds
Started Mar 14 12:40:07 PM PDT 24
Finished Mar 14 12:41:50 PM PDT 24
Peak memory 200028 kb
Host smart-8f9bd754-e16a-46f5-be08-c6e53f7f7335
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800554342 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3800554342
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.408112090
Short name T160
Test name
Test status
Simulation time 60110546 ps
CPU time 1.24 seconds
Started Mar 14 12:40:04 PM PDT 24
Finished Mar 14 12:40:06 PM PDT 24
Peak memory 199928 kb
Host smart-411b7bec-c85f-4d78-850a-b952d4b3d740
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408112090 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.408112090
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.642311374
Short name T228
Test name
Test status
Simulation time 129599276639 ps
CPU time 436.1 seconds
Started Mar 14 12:40:05 PM PDT 24
Finished Mar 14 12:47:21 PM PDT 24
Peak memory 199904 kb
Host smart-31d737da-8cd2-404c-a8f8-3b89b3ea9856
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642311374 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.642311374
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3877490850
Short name T386
Test name
Test status
Simulation time 3849329053 ps
CPU time 68.5 seconds
Started Mar 14 12:40:05 PM PDT 24
Finished Mar 14 12:41:14 PM PDT 24
Peak memory 200100 kb
Host smart-20d7bede-fdd9-48ea-9efc-f4df23368845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877490850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3877490850
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.445272999
Short name T552
Test name
Test status
Simulation time 87990363 ps
CPU time 0.57 seconds
Started Mar 14 12:42:47 PM PDT 24
Finished Mar 14 12:42:48 PM PDT 24
Peak memory 195536 kb
Host smart-dec30b44-815f-410d-ba8e-6b5283bf27f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445272999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.445272999
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3038267538
Short name T486
Test name
Test status
Simulation time 1867985028 ps
CPU time 9.22 seconds
Started Mar 14 12:42:40 PM PDT 24
Finished Mar 14 12:42:49 PM PDT 24
Peak memory 208072 kb
Host smart-94e83b9b-c054-4193-b928-0c4c396916b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3038267538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3038267538
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2467558430
Short name T334
Test name
Test status
Simulation time 5659579217 ps
CPU time 30.46 seconds
Started Mar 14 12:42:48 PM PDT 24
Finished Mar 14 12:43:19 PM PDT 24
Peak memory 200032 kb
Host smart-c3e42531-986e-4128-bcdc-b7225429aa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467558430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2467558430
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2974299331
Short name T382
Test name
Test status
Simulation time 545457573 ps
CPU time 11.38 seconds
Started Mar 14 12:42:49 PM PDT 24
Finished Mar 14 12:43:00 PM PDT 24
Peak memory 199972 kb
Host smart-adcc0aa6-65b0-4d01-8ee4-889f5c3cdd35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974299331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2974299331
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.593652187
Short name T314
Test name
Test status
Simulation time 12460638886 ps
CPU time 115.85 seconds
Started Mar 14 12:42:42 PM PDT 24
Finished Mar 14 12:44:38 PM PDT 24
Peak memory 200108 kb
Host smart-4fcf369a-6511-42bc-a54a-2b94b399cc9e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593652187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.593652187
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.102139408
Short name T131
Test name
Test status
Simulation time 1156184006 ps
CPU time 63.48 seconds
Started Mar 14 12:42:37 PM PDT 24
Finished Mar 14 12:43:40 PM PDT 24
Peak memory 199800 kb
Host smart-d5076f47-8fce-482e-85b2-cfbcd7216ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102139408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.102139408
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.128045490
Short name T336
Test name
Test status
Simulation time 211535866 ps
CPU time 1.72 seconds
Started Mar 14 12:42:35 PM PDT 24
Finished Mar 14 12:42:38 PM PDT 24
Peak memory 200008 kb
Host smart-74343fc8-9e05-42dd-82ff-5aec8dc6d30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128045490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.128045490
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.4237614621
Short name T141
Test name
Test status
Simulation time 181401202 ps
CPU time 2.45 seconds
Started Mar 14 12:42:51 PM PDT 24
Finished Mar 14 12:42:54 PM PDT 24
Peak memory 199912 kb
Host smart-4afeb174-d430-4eb7-8f37-6aefb2b0194f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237614621 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.4237614621
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.253016643
Short name T362
Test name
Test status
Simulation time 104709065 ps
CPU time 1.19 seconds
Started Mar 14 12:42:45 PM PDT 24
Finished Mar 14 12:42:46 PM PDT 24
Peak memory 199660 kb
Host smart-a0480b8c-06c0-4641-ac98-33e7afb211db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253016643 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.253016643
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.511169228
Short name T370
Test name
Test status
Simulation time 61337810686 ps
CPU time 440.45 seconds
Started Mar 14 12:42:45 PM PDT 24
Finished Mar 14 12:50:06 PM PDT 24
Peak memory 199980 kb
Host smart-c058a7c6-f853-4035-b596-cd16ef8fbbb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511169228 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.511169228
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2844492578
Short name T380
Test name
Test status
Simulation time 463990075 ps
CPU time 6.77 seconds
Started Mar 14 12:42:52 PM PDT 24
Finished Mar 14 12:42:59 PM PDT 24
Peak memory 200024 kb
Host smart-7651c2bd-5d1c-49d6-a29d-697e4e520196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844492578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2844492578
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.75042226
Short name T107
Test name
Test status
Simulation time 50809997 ps
CPU time 0.58 seconds
Started Mar 14 12:42:44 PM PDT 24
Finished Mar 14 12:42:45 PM PDT 24
Peak memory 195592 kb
Host smart-3499a5d4-0173-4eb7-9d3e-36f437dd7752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75042226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.75042226
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3611430219
Short name T384
Test name
Test status
Simulation time 9029720705 ps
CPU time 24.32 seconds
Started Mar 14 12:42:46 PM PDT 24
Finished Mar 14 12:43:10 PM PDT 24
Peak memory 221868 kb
Host smart-fc7b9beb-77f3-4a28-8bff-7841f0546de7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611430219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3611430219
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1838787502
Short name T495
Test name
Test status
Simulation time 651198889 ps
CPU time 12.95 seconds
Started Mar 14 12:42:48 PM PDT 24
Finished Mar 14 12:43:01 PM PDT 24
Peak memory 199932 kb
Host smart-9bc2ee75-7644-4254-99c1-d9b061fb57b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838787502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1838787502
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1912495159
Short name T596
Test name
Test status
Simulation time 77864540 ps
CPU time 0.97 seconds
Started Mar 14 12:42:43 PM PDT 24
Finished Mar 14 12:42:44 PM PDT 24
Peak memory 199920 kb
Host smart-2c737b55-ab79-41c5-9dd2-b2567d0c7937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912495159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1912495159
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1968492692
Short name T219
Test name
Test status
Simulation time 2773866807 ps
CPU time 75.51 seconds
Started Mar 14 12:42:45 PM PDT 24
Finished Mar 14 12:44:01 PM PDT 24
Peak memory 200084 kb
Host smart-d353c0c9-a638-4809-b158-4b483606979e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968492692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1968492692
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.582324618
Short name T7
Test name
Test status
Simulation time 490791034 ps
CPU time 28.17 seconds
Started Mar 14 12:42:44 PM PDT 24
Finished Mar 14 12:43:12 PM PDT 24
Peak memory 199988 kb
Host smart-e75a6e8d-3533-408c-aab0-2a5083dd9945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582324618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.582324618
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1513827025
Short name T351
Test name
Test status
Simulation time 257782054 ps
CPU time 3.91 seconds
Started Mar 14 12:42:47 PM PDT 24
Finished Mar 14 12:42:51 PM PDT 24
Peak memory 199932 kb
Host smart-f4debefe-3b25-49ba-a9d2-e01db3be89af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513827025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1513827025
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.3618807225
Short name T404
Test name
Test status
Simulation time 40411019426 ps
CPU time 1448.84 seconds
Started Mar 14 12:42:46 PM PDT 24
Finished Mar 14 01:06:55 PM PDT 24
Peak memory 257484 kb
Host smart-1882c7ed-9287-433a-9ead-2223f1565821
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618807225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.3618807225
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3131846358
Short name T515
Test name
Test status
Simulation time 30504745 ps
CPU time 1.23 seconds
Started Mar 14 12:42:44 PM PDT 24
Finished Mar 14 12:42:45 PM PDT 24
Peak memory 199980 kb
Host smart-755a8fbb-724c-4369-8b02-c7cb3eac7c5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131846358 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3131846358
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3837969623
Short name T276
Test name
Test status
Simulation time 7936468890 ps
CPU time 429.5 seconds
Started Mar 14 12:42:44 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 200008 kb
Host smart-b6b34194-5b0c-4dcd-8377-a70f14dd3230
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837969623 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3837969623
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3499736156
Short name T478
Test name
Test status
Simulation time 22424485650 ps
CPU time 66.92 seconds
Started Mar 14 12:42:44 PM PDT 24
Finished Mar 14 12:43:51 PM PDT 24
Peak memory 200080 kb
Host smart-bfa45970-65c6-492e-86b6-5ae6ee6c35ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499736156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3499736156
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.964404548
Short name T266
Test name
Test status
Simulation time 12853768 ps
CPU time 0.55 seconds
Started Mar 14 12:42:53 PM PDT 24
Finished Mar 14 12:42:54 PM PDT 24
Peak memory 195016 kb
Host smart-f0c4a801-e02e-457c-acf2-c14377cb5cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964404548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.964404548
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2032957628
Short name T420
Test name
Test status
Simulation time 6380693818 ps
CPU time 34.81 seconds
Started Mar 14 12:42:44 PM PDT 24
Finished Mar 14 12:43:19 PM PDT 24
Peak memory 225708 kb
Host smart-6def343c-006a-46d6-b14e-73d4918e3d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032957628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2032957628
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2715991765
Short name T269
Test name
Test status
Simulation time 2766485465 ps
CPU time 35.25 seconds
Started Mar 14 12:42:52 PM PDT 24
Finished Mar 14 12:43:27 PM PDT 24
Peak memory 200068 kb
Host smart-30352a40-fb3d-4cd2-9fac-ed0a0bbe4ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715991765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2715991765
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2774178705
Short name T440
Test name
Test status
Simulation time 580262706 ps
CPU time 5.63 seconds
Started Mar 14 12:42:46 PM PDT 24
Finished Mar 14 12:42:51 PM PDT 24
Peak memory 199900 kb
Host smart-871094f6-5f6a-4692-b65c-ba2a605b49e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774178705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2774178705
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3749723840
Short name T387
Test name
Test status
Simulation time 674071280 ps
CPU time 3.3 seconds
Started Mar 14 12:42:46 PM PDT 24
Finished Mar 14 12:42:50 PM PDT 24
Peak memory 199892 kb
Host smart-7e0ce925-84bd-4060-b585-1c237ae4ac02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749723840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3749723840
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1713028963
Short name T293
Test name
Test status
Simulation time 13104167197 ps
CPU time 65.12 seconds
Started Mar 14 12:42:45 PM PDT 24
Finished Mar 14 12:43:50 PM PDT 24
Peak memory 200064 kb
Host smart-47aff88d-5e26-41b8-8f8c-e0f72feda479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713028963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1713028963
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1682235396
Short name T144
Test name
Test status
Simulation time 650802063 ps
CPU time 7.73 seconds
Started Mar 14 12:42:51 PM PDT 24
Finished Mar 14 12:42:59 PM PDT 24
Peak memory 199996 kb
Host smart-11161df4-5b51-4107-94d6-fb6d245e2848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682235396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1682235396
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2344066866
Short name T91
Test name
Test status
Simulation time 81768561705 ps
CPU time 1479.73 seconds
Started Mar 14 12:42:53 PM PDT 24
Finished Mar 14 01:07:33 PM PDT 24
Peak memory 241048 kb
Host smart-2880a9c6-d36a-4a5d-8782-43902fc9dee4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344066866 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2344066866
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2904961218
Short name T568
Test name
Test status
Simulation time 197572734 ps
CPU time 1.18 seconds
Started Mar 14 12:42:47 PM PDT 24
Finished Mar 14 12:42:49 PM PDT 24
Peak memory 199940 kb
Host smart-3c714d03-44b1-4b5a-bdfa-e83edcdc758b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904961218 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2904961218
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.368806485
Short name T462
Test name
Test status
Simulation time 44186591398 ps
CPU time 561.05 seconds
Started Mar 14 12:42:46 PM PDT 24
Finished Mar 14 12:52:08 PM PDT 24
Peak memory 200092 kb
Host smart-c5d3bedd-d748-46b7-b5bd-7df5fc25ab7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368806485 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.368806485
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2593530656
Short name T321
Test name
Test status
Simulation time 30406750015 ps
CPU time 93.24 seconds
Started Mar 14 12:42:44 PM PDT 24
Finished Mar 14 12:44:17 PM PDT 24
Peak memory 200028 kb
Host smart-5bcf81c9-699f-4302-abd3-c12e66b5b2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593530656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2593530656
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1820690665
Short name T368
Test name
Test status
Simulation time 18313582 ps
CPU time 0.56 seconds
Started Mar 14 12:42:56 PM PDT 24
Finished Mar 14 12:42:56 PM PDT 24
Peak memory 194604 kb
Host smart-226d097b-a621-41f8-b8b7-9b2c43aafe31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820690665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1820690665
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3178206027
Short name T299
Test name
Test status
Simulation time 19352834720 ps
CPU time 51.27 seconds
Started Mar 14 12:42:54 PM PDT 24
Finished Mar 14 12:43:45 PM PDT 24
Peak memory 215660 kb
Host smart-759ab7ec-0264-43b6-a669-e38967517056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178206027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3178206027
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3106792327
Short name T103
Test name
Test status
Simulation time 28204651 ps
CPU time 0.7 seconds
Started Mar 14 12:42:57 PM PDT 24
Finished Mar 14 12:42:58 PM PDT 24
Peak memory 197300 kb
Host smart-ece0cc42-0ee7-4c6a-add5-f9f0ee3319c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106792327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3106792327
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4224110323
Short name T517
Test name
Test status
Simulation time 2060762940 ps
CPU time 112.68 seconds
Started Mar 14 12:42:54 PM PDT 24
Finished Mar 14 12:44:47 PM PDT 24
Peak memory 200040 kb
Host smart-a732bb4c-7483-4570-be5a-eb9f7c494b7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4224110323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4224110323
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2925116730
Short name T290
Test name
Test status
Simulation time 12657238544 ps
CPU time 164.28 seconds
Started Mar 14 12:42:56 PM PDT 24
Finished Mar 14 12:45:41 PM PDT 24
Peak memory 200104 kb
Host smart-9963dd7e-bf5d-4f83-9a30-30f7db75ccc9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925116730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2925116730
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.639508885
Short name T289
Test name
Test status
Simulation time 5040615862 ps
CPU time 25.4 seconds
Started Mar 14 12:42:56 PM PDT 24
Finished Mar 14 12:43:22 PM PDT 24
Peak memory 200048 kb
Host smart-afec418d-f043-4c47-b9b4-231357b4865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639508885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.639508885
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2240556017
Short name T297
Test name
Test status
Simulation time 170621471 ps
CPU time 2.78 seconds
Started Mar 14 12:42:59 PM PDT 24
Finished Mar 14 12:43:02 PM PDT 24
Peak memory 199852 kb
Host smart-9765f995-14b7-4eb4-abb4-909bfeb54540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240556017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2240556017
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3725046763
Short name T88
Test name
Test status
Simulation time 4439922195 ps
CPU time 82.38 seconds
Started Mar 14 12:42:59 PM PDT 24
Finished Mar 14 12:44:22 PM PDT 24
Peak memory 199932 kb
Host smart-8ad2ee29-ecf9-48a3-a4df-f8233431bf34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725046763 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3725046763
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1287455941
Short name T430
Test name
Test status
Simulation time 30308964 ps
CPU time 1.18 seconds
Started Mar 14 12:42:54 PM PDT 24
Finished Mar 14 12:42:55 PM PDT 24
Peak memory 199792 kb
Host smart-f979c4c3-6806-4575-a356-fc45c9b1857e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287455941 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1287455941
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1330040969
Short name T244
Test name
Test status
Simulation time 38463184382 ps
CPU time 490.26 seconds
Started Mar 14 12:42:59 PM PDT 24
Finished Mar 14 12:51:09 PM PDT 24
Peak memory 200012 kb
Host smart-e883d040-e2bf-4b7e-8b00-7399e853f74a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330040969 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.1330040969
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1730740304
Short name T428
Test name
Test status
Simulation time 17689255401 ps
CPU time 85.33 seconds
Started Mar 14 12:42:54 PM PDT 24
Finished Mar 14 12:44:20 PM PDT 24
Peak memory 199912 kb
Host smart-c445f70b-3600-436f-9684-71a28d426c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730740304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1730740304
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1218579194
Short name T371
Test name
Test status
Simulation time 14435418 ps
CPU time 0.59 seconds
Started Mar 14 12:42:56 PM PDT 24
Finished Mar 14 12:42:56 PM PDT 24
Peak memory 195536 kb
Host smart-59da5e36-4bec-4aac-89a2-99953aca0588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218579194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1218579194
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3909702513
Short name T479
Test name
Test status
Simulation time 2564210122 ps
CPU time 55.47 seconds
Started Mar 14 12:42:52 PM PDT 24
Finished Mar 14 12:43:48 PM PDT 24
Peak memory 236532 kb
Host smart-7c5e3735-8990-419f-9b19-fe85e2fac5b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909702513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3909702513
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.880027335
Short name T312
Test name
Test status
Simulation time 5950818934 ps
CPU time 26.18 seconds
Started Mar 14 12:43:00 PM PDT 24
Finished Mar 14 12:43:26 PM PDT 24
Peak memory 200040 kb
Host smart-19bdfb1e-d0e7-4dfe-be90-529258e4f781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880027335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.880027335
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2617855327
Short name T234
Test name
Test status
Simulation time 1065566666 ps
CPU time 55.89 seconds
Started Mar 14 12:42:53 PM PDT 24
Finished Mar 14 12:43:49 PM PDT 24
Peak memory 199756 kb
Host smart-18fbc4a3-ed30-4114-9ad0-98681d5af158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617855327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2617855327
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2475790246
Short name T298
Test name
Test status
Simulation time 15482043945 ps
CPU time 183.65 seconds
Started Mar 14 12:42:52 PM PDT 24
Finished Mar 14 12:45:56 PM PDT 24
Peak memory 200356 kb
Host smart-34b760b2-8bc4-4702-b212-b37aaf330d36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475790246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2475790246
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2655730524
Short name T310
Test name
Test status
Simulation time 12243885915 ps
CPU time 119.81 seconds
Started Mar 14 12:42:54 PM PDT 24
Finished Mar 14 12:44:54 PM PDT 24
Peak memory 200076 kb
Host smart-c5284f57-6bc2-4245-ae9b-7219ec89ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655730524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2655730524
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1255565966
Short name T604
Test name
Test status
Simulation time 533240104 ps
CPU time 2.66 seconds
Started Mar 14 12:42:54 PM PDT 24
Finished Mar 14 12:42:56 PM PDT 24
Peak memory 199952 kb
Host smart-23bc7994-33e4-486e-937f-a5e5e5e69f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255565966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1255565966
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2233782471
Short name T75
Test name
Test status
Simulation time 92817989595 ps
CPU time 568.01 seconds
Started Mar 14 12:42:53 PM PDT 24
Finished Mar 14 12:52:21 PM PDT 24
Peak memory 247528 kb
Host smart-b0312de9-f6fe-493c-a00c-57ce2dfdeeaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233782471 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2233782471
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.370513762
Short name T306
Test name
Test status
Simulation time 8669530336 ps
CPU time 362.8 seconds
Started Mar 14 12:42:55 PM PDT 24
Finished Mar 14 12:48:58 PM PDT 24
Peak memory 208316 kb
Host smart-dfcadd00-b219-4c13-acea-5b431f4d97fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370513762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.370513762
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.813699193
Short name T332
Test name
Test status
Simulation time 232980796 ps
CPU time 1.29 seconds
Started Mar 14 12:43:00 PM PDT 24
Finished Mar 14 12:43:01 PM PDT 24
Peak memory 199900 kb
Host smart-da1be554-7fd2-4873-b2b5-c008df9b0eb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813699193 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.813699193
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.441399713
Short name T250
Test name
Test status
Simulation time 7725746534 ps
CPU time 412.84 seconds
Started Mar 14 12:42:57 PM PDT 24
Finished Mar 14 12:49:50 PM PDT 24
Peak memory 200032 kb
Host smart-352ee29f-1206-4165-b6ce-d129099826ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441399713 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.441399713
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2346451403
Short name T602
Test name
Test status
Simulation time 14762573767 ps
CPU time 61.81 seconds
Started Mar 14 12:42:55 PM PDT 24
Finished Mar 14 12:43:57 PM PDT 24
Peak memory 200036 kb
Host smart-208f47a1-c31d-4dc2-a60f-6396da8b7ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346451403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2346451403
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1034445317
Short name T202
Test name
Test status
Simulation time 35448930 ps
CPU time 0.6 seconds
Started Mar 14 12:43:05 PM PDT 24
Finished Mar 14 12:43:06 PM PDT 24
Peak memory 195572 kb
Host smart-421cce9b-0338-49e3-82f7-7632f972ff56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034445317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1034445317
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1334587368
Short name T562
Test name
Test status
Simulation time 2001753093 ps
CPU time 19.87 seconds
Started Mar 14 12:43:01 PM PDT 24
Finished Mar 14 12:43:21 PM PDT 24
Peak memory 235868 kb
Host smart-08643fc6-6aef-4297-b4c2-a7bb8e76298a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334587368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1334587368
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1806147543
Short name T458
Test name
Test status
Simulation time 3709496282 ps
CPU time 48.84 seconds
Started Mar 14 12:42:59 PM PDT 24
Finished Mar 14 12:43:48 PM PDT 24
Peak memory 200152 kb
Host smart-a2329734-f568-46e4-81f8-43f7ca0b10ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806147543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1806147543
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3963955742
Short name T319
Test name
Test status
Simulation time 7493518037 ps
CPU time 109.04 seconds
Started Mar 14 12:43:05 PM PDT 24
Finished Mar 14 12:44:54 PM PDT 24
Peak memory 200096 kb
Host smart-b39c432f-7948-4640-8685-b7d242a6d1af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3963955742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3963955742
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1688878324
Short name T492
Test name
Test status
Simulation time 8228453813 ps
CPU time 71.71 seconds
Started Mar 14 12:43:00 PM PDT 24
Finished Mar 14 12:44:12 PM PDT 24
Peak memory 200112 kb
Host smart-b46a54a3-22ca-4adb-b3f0-1a191b8e6684
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688878324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1688878324
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1976067273
Short name T303
Test name
Test status
Simulation time 4701067313 ps
CPU time 90.1 seconds
Started Mar 14 12:43:01 PM PDT 24
Finished Mar 14 12:44:31 PM PDT 24
Peak memory 200108 kb
Host smart-a0eb8f81-628a-4ce8-82b1-ef1a43432975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976067273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1976067273
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2400059606
Short name T539
Test name
Test status
Simulation time 184840003 ps
CPU time 2.53 seconds
Started Mar 14 12:42:54 PM PDT 24
Finished Mar 14 12:42:57 PM PDT 24
Peak memory 200008 kb
Host smart-f61f6562-e6f7-402d-98bf-8cbb38ac2f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400059606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2400059606
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.280447013
Short name T151
Test name
Test status
Simulation time 190966781481 ps
CPU time 699.03 seconds
Started Mar 14 12:43:07 PM PDT 24
Finished Mar 14 12:54:47 PM PDT 24
Peak memory 200060 kb
Host smart-fa3b1946-d457-4ac1-bd09-eb604180471e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280447013 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.280447013
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.19671643
Short name T262
Test name
Test status
Simulation time 54080408 ps
CPU time 1.08 seconds
Started Mar 14 12:42:59 PM PDT 24
Finished Mar 14 12:43:01 PM PDT 24
Peak memory 199304 kb
Host smart-8380521e-26dd-4ca2-90f5-d22ee6132d89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19671643 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.hmac_test_hmac_vectors.19671643
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1302085900
Short name T237
Test name
Test status
Simulation time 47759213825 ps
CPU time 407.76 seconds
Started Mar 14 12:43:00 PM PDT 24
Finished Mar 14 12:49:48 PM PDT 24
Peak memory 199972 kb
Host smart-19cb6052-b788-44d1-9899-9b558b8252fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302085900 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1302085900
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3335353306
Short name T463
Test name
Test status
Simulation time 18446641840 ps
CPU time 83.37 seconds
Started Mar 14 12:42:59 PM PDT 24
Finished Mar 14 12:44:23 PM PDT 24
Peak memory 200072 kb
Host smart-5d609ad6-9b11-405d-bb1b-30ec26fc171c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335353306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3335353306
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2564044452
Short name T475
Test name
Test status
Simulation time 18101389 ps
CPU time 0.53 seconds
Started Mar 14 12:43:00 PM PDT 24
Finished Mar 14 12:43:01 PM PDT 24
Peak memory 194556 kb
Host smart-b25a7e10-9d2a-40df-9bc5-a2b2af4a602f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564044452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2564044452
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2417859153
Short name T22
Test name
Test status
Simulation time 86385134 ps
CPU time 2.87 seconds
Started Mar 14 12:43:00 PM PDT 24
Finished Mar 14 12:43:03 PM PDT 24
Peak memory 199972 kb
Host smart-3b27a197-4dbf-47c0-afcc-6978c37eacea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2417859153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2417859153
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2969506878
Short name T497
Test name
Test status
Simulation time 981028238 ps
CPU time 11.94 seconds
Started Mar 14 12:43:00 PM PDT 24
Finished Mar 14 12:43:12 PM PDT 24
Peak memory 199800 kb
Host smart-9afe28b4-9359-4a8a-bebe-f9d3987f3a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969506878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2969506878
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.226222783
Short name T442
Test name
Test status
Simulation time 2525376932 ps
CPU time 26.05 seconds
Started Mar 14 12:43:00 PM PDT 24
Finished Mar 14 12:43:27 PM PDT 24
Peak memory 199984 kb
Host smart-c067dea8-29d9-4d62-b923-19dd6000e6b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=226222783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.226222783
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1992178183
Short name T521
Test name
Test status
Simulation time 3291255429 ps
CPU time 170.5 seconds
Started Mar 14 12:43:07 PM PDT 24
Finished Mar 14 12:45:58 PM PDT 24
Peak memory 200060 kb
Host smart-045163c3-4f4b-4466-bfa1-cf87e025c15c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992178183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1992178183
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1277401936
Short name T157
Test name
Test status
Simulation time 5727440236 ps
CPU time 77.33 seconds
Started Mar 14 12:43:00 PM PDT 24
Finished Mar 14 12:44:17 PM PDT 24
Peak memory 199980 kb
Host smart-1966a449-3240-4650-b9e7-997cc3c05c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277401936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1277401936
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.610983474
Short name T470
Test name
Test status
Simulation time 155478863 ps
CPU time 4.85 seconds
Started Mar 14 12:43:01 PM PDT 24
Finished Mar 14 12:43:06 PM PDT 24
Peak memory 200048 kb
Host smart-e54829ad-c806-4ba4-bf21-726295a8a399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610983474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.610983474
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2130563070
Short name T235
Test name
Test status
Simulation time 189237514498 ps
CPU time 485.95 seconds
Started Mar 14 12:43:02 PM PDT 24
Finished Mar 14 12:51:09 PM PDT 24
Peak memory 232836 kb
Host smart-0399b356-d362-433e-aab2-f36661abef05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130563070 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2130563070
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.693772685
Short name T184
Test name
Test status
Simulation time 149000439 ps
CPU time 1 seconds
Started Mar 14 12:43:02 PM PDT 24
Finished Mar 14 12:43:04 PM PDT 24
Peak memory 198920 kb
Host smart-dd284280-e8a0-45f0-a89f-21a987e69936
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693772685 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.693772685
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1236136125
Short name T466
Test name
Test status
Simulation time 7241874413 ps
CPU time 383.64 seconds
Started Mar 14 12:43:01 PM PDT 24
Finished Mar 14 12:49:25 PM PDT 24
Peak memory 199856 kb
Host smart-8e699f17-1dab-400c-bcf8-1dce1b3a6965
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236136125 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.1236136125
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3461298426
Short name T171
Test name
Test status
Simulation time 11012631281 ps
CPU time 78.02 seconds
Started Mar 14 12:43:00 PM PDT 24
Finished Mar 14 12:44:19 PM PDT 24
Peak memory 200012 kb
Host smart-6b385acb-cc1a-487b-afe6-715c208f165d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461298426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3461298426
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2186268780
Short name T173
Test name
Test status
Simulation time 169010880 ps
CPU time 0.54 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 12:43:12 PM PDT 24
Peak memory 194428 kb
Host smart-df42db4b-f789-437a-a108-48e2c71152d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186268780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2186268780
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2721832829
Short name T271
Test name
Test status
Simulation time 766066594 ps
CPU time 7.86 seconds
Started Mar 14 12:43:05 PM PDT 24
Finished Mar 14 12:43:13 PM PDT 24
Peak memory 215396 kb
Host smart-62cd0a28-0d36-4231-9746-f4ae402cde9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721832829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2721832829
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.266703432
Short name T579
Test name
Test status
Simulation time 7926831698 ps
CPU time 15.2 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 12:43:26 PM PDT 24
Peak memory 200040 kb
Host smart-5b26917d-385a-4c0f-8ec8-411f7ccfeedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266703432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.266703432
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.184106998
Short name T472
Test name
Test status
Simulation time 3320209119 ps
CPU time 44.56 seconds
Started Mar 14 12:43:10 PM PDT 24
Finished Mar 14 12:43:55 PM PDT 24
Peak memory 200024 kb
Host smart-c5b833c5-5e49-4be6-bb8b-f7a507e7c942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=184106998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.184106998
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.709644339
Short name T541
Test name
Test status
Simulation time 2470158019 ps
CPU time 44.59 seconds
Started Mar 14 12:43:09 PM PDT 24
Finished Mar 14 12:43:54 PM PDT 24
Peak memory 200044 kb
Host smart-9f02ed8b-8434-44af-812e-b1f0ce1139ec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709644339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.709644339
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3968127827
Short name T163
Test name
Test status
Simulation time 2170979325 ps
CPU time 7.03 seconds
Started Mar 14 12:42:59 PM PDT 24
Finished Mar 14 12:43:06 PM PDT 24
Peak memory 199932 kb
Host smart-c3beea0d-4844-4f65-9ec1-e99e5eab62d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968127827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3968127827
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1230554470
Short name T154
Test name
Test status
Simulation time 424921043 ps
CPU time 6.25 seconds
Started Mar 14 12:43:02 PM PDT 24
Finished Mar 14 12:43:09 PM PDT 24
Peak memory 200000 kb
Host smart-46889fb7-75b7-4ded-b039-7c0d730e277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230554470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1230554470
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3431039883
Short name T28
Test name
Test status
Simulation time 148665592784 ps
CPU time 320.47 seconds
Started Mar 14 12:43:12 PM PDT 24
Finished Mar 14 12:48:33 PM PDT 24
Peak memory 208336 kb
Host smart-126d01a8-4235-42c4-a55b-b01c4933cf07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431039883 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3431039883
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.3525241563
Short name T68
Test name
Test status
Simulation time 227625888964 ps
CPU time 648.63 seconds
Started Mar 14 12:43:12 PM PDT 24
Finished Mar 14 12:54:01 PM PDT 24
Peak memory 248544 kb
Host smart-e0e00c64-5dca-4579-995a-17aeb27ba37b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525241563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.3525241563
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2908197569
Short name T214
Test name
Test status
Simulation time 511443838 ps
CPU time 1.04 seconds
Started Mar 14 12:43:10 PM PDT 24
Finished Mar 14 12:43:11 PM PDT 24
Peak memory 199512 kb
Host smart-70357a53-fb37-4183-9272-8f06dfcdf042
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908197569 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2908197569
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2297801678
Short name T73
Test name
Test status
Simulation time 37680217093 ps
CPU time 485.63 seconds
Started Mar 14 12:43:09 PM PDT 24
Finished Mar 14 12:51:15 PM PDT 24
Peak memory 200092 kb
Host smart-b2c86402-a201-4684-8261-0e5094fadc7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297801678 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2297801678
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3356354616
Short name T342
Test name
Test status
Simulation time 2077782562 ps
CPU time 79.09 seconds
Started Mar 14 12:43:10 PM PDT 24
Finished Mar 14 12:44:29 PM PDT 24
Peak memory 200000 kb
Host smart-24ae511c-aa2f-43a1-8287-9ef91e93024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356354616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3356354616
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2350222328
Short name T406
Test name
Test status
Simulation time 49214563 ps
CPU time 0.55 seconds
Started Mar 14 12:43:09 PM PDT 24
Finished Mar 14 12:43:10 PM PDT 24
Peak memory 195560 kb
Host smart-c0bc16d2-f03c-4de9-a208-ff71bbaa887c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350222328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2350222328
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2310708290
Short name T578
Test name
Test status
Simulation time 1059696342 ps
CPU time 17.74 seconds
Started Mar 14 12:43:08 PM PDT 24
Finished Mar 14 12:43:26 PM PDT 24
Peak memory 216316 kb
Host smart-0ede81d7-13f5-42b1-a3f3-f49541fda267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310708290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2310708290
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3464410609
Short name T272
Test name
Test status
Simulation time 4195201914 ps
CPU time 53.13 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 12:44:04 PM PDT 24
Peak memory 199320 kb
Host smart-04472af9-a8c0-4226-9723-a752a7f8d548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464410609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3464410609
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.4011014733
Short name T206
Test name
Test status
Simulation time 2375430773 ps
CPU time 95.75 seconds
Started Mar 14 12:43:09 PM PDT 24
Finished Mar 14 12:44:44 PM PDT 24
Peak memory 200116 kb
Host smart-ec62e971-dabf-4542-9a66-f1847975b585
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4011014733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.4011014733
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.502078828
Short name T483
Test name
Test status
Simulation time 3791629721 ps
CPU time 46.89 seconds
Started Mar 14 12:43:10 PM PDT 24
Finished Mar 14 12:43:57 PM PDT 24
Peak memory 200096 kb
Host smart-89217972-4fb8-4c10-a2b8-1b3834a5d2c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502078828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.502078828
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.738936631
Short name T324
Test name
Test status
Simulation time 1400391734 ps
CPU time 78.39 seconds
Started Mar 14 12:43:09 PM PDT 24
Finished Mar 14 12:44:28 PM PDT 24
Peak memory 199980 kb
Host smart-690af28a-8689-4072-aaf8-b6095af69e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738936631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.738936631
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1836205736
Short name T565
Test name
Test status
Simulation time 210953003 ps
CPU time 0.72 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 12:43:12 PM PDT 24
Peak memory 197160 kb
Host smart-18845bd3-a6d3-4027-8bf7-bd0fa36f1275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836205736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1836205736
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3243301649
Short name T518
Test name
Test status
Simulation time 223175529358 ps
CPU time 1411.14 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 01:06:42 PM PDT 24
Peak memory 200092 kb
Host smart-84bcb919-15b8-491e-8b74-f578a1cec1c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243301649 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3243301649
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.952648918
Short name T510
Test name
Test status
Simulation time 116681241 ps
CPU time 1.23 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 12:43:13 PM PDT 24
Peak memory 199624 kb
Host smart-b2bcc811-4d10-464d-9e10-5fa2fd2c89b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952648918 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.952648918
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2671294078
Short name T200
Test name
Test status
Simulation time 30555817432 ps
CPU time 536.57 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 12:52:08 PM PDT 24
Peak memory 199952 kb
Host smart-3c2187e8-b94b-43b3-baf0-3f517efaa1bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671294078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.2671294078
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3496904666
Short name T222
Test name
Test status
Simulation time 19805757115 ps
CPU time 39.74 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 12:43:51 PM PDT 24
Peak memory 199228 kb
Host smart-bc63e9c2-76a0-405d-a9ae-3f97dc9b46a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496904666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3496904666
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1492189112
Short name T89
Test name
Test status
Simulation time 27027449 ps
CPU time 0.59 seconds
Started Mar 14 12:43:19 PM PDT 24
Finished Mar 14 12:43:20 PM PDT 24
Peak memory 195624 kb
Host smart-a60deffb-035e-4062-82b6-634e61c48ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492189112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1492189112
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1352726829
Short name T502
Test name
Test status
Simulation time 1627906678 ps
CPU time 62.92 seconds
Started Mar 14 12:43:10 PM PDT 24
Finished Mar 14 12:44:13 PM PDT 24
Peak memory 229784 kb
Host smart-1b3f5b18-f0db-49a6-996e-2b97a28b3b67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352726829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1352726829
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3871119837
Short name T551
Test name
Test status
Simulation time 7642454878 ps
CPU time 36.48 seconds
Started Mar 14 12:43:10 PM PDT 24
Finished Mar 14 12:43:46 PM PDT 24
Peak memory 199888 kb
Host smart-1926c3ce-c346-4776-b2fe-cf219f1c58eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871119837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3871119837
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3071737356
Short name T467
Test name
Test status
Simulation time 109634925 ps
CPU time 0.77 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 12:43:12 PM PDT 24
Peak memory 197860 kb
Host smart-9b5d0ecf-9968-4699-ae5e-98dcf91f0aa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3071737356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3071737356
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.4165465025
Short name T69
Test name
Test status
Simulation time 40467690316 ps
CPU time 115.35 seconds
Started Mar 14 12:43:10 PM PDT 24
Finished Mar 14 12:45:06 PM PDT 24
Peak memory 200072 kb
Host smart-ae4b037d-0786-44a7-9b76-92b8fd0bc1b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165465025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4165465025
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3586412927
Short name T575
Test name
Test status
Simulation time 4977373993 ps
CPU time 97.01 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 12:44:48 PM PDT 24
Peak memory 200080 kb
Host smart-c53e1371-f2ed-42cc-9370-92a960e24a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586412927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3586412927
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2583014393
Short name T418
Test name
Test status
Simulation time 262858356 ps
CPU time 4 seconds
Started Mar 14 12:43:12 PM PDT 24
Finished Mar 14 12:43:16 PM PDT 24
Peak memory 200000 kb
Host smart-062cf091-0c0f-44bd-82d7-4a819aed745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583014393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2583014393
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1399774332
Short name T191
Test name
Test status
Simulation time 55212994653 ps
CPU time 731.7 seconds
Started Mar 14 12:43:22 PM PDT 24
Finished Mar 14 12:55:33 PM PDT 24
Peak memory 200060 kb
Host smart-3f69b02c-e719-4947-aabd-a2c8a5352f32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399774332 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1399774332
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.2284376282
Short name T485
Test name
Test status
Simulation time 5950804761 ps
CPU time 158.4 seconds
Started Mar 14 12:43:22 PM PDT 24
Finished Mar 14 12:46:00 PM PDT 24
Peak memory 216012 kb
Host smart-6fc848c1-bcc1-4371-80c2-fbb35ea84b29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284376282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.2284376282
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3731262960
Short name T281
Test name
Test status
Simulation time 59843202 ps
CPU time 1.28 seconds
Started Mar 14 12:43:18 PM PDT 24
Finished Mar 14 12:43:19 PM PDT 24
Peak memory 199904 kb
Host smart-806a34e1-5bba-4145-88a9-eab3fb88517b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731262960 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3731262960
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2499340647
Short name T162
Test name
Test status
Simulation time 33523687902 ps
CPU time 469.18 seconds
Started Mar 14 12:43:11 PM PDT 24
Finished Mar 14 12:51:00 PM PDT 24
Peak memory 200060 kb
Host smart-c4672d58-eb1a-45c5-a0f7-99fdcafdfbb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499340647 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2499340647
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3303499200
Short name T366
Test name
Test status
Simulation time 11874838843 ps
CPU time 56.17 seconds
Started Mar 14 12:43:10 PM PDT 24
Finished Mar 14 12:44:06 PM PDT 24
Peak memory 200068 kb
Host smart-546a77b0-076d-430e-bc2b-20bf0332b0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303499200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3303499200
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3598455143
Short name T417
Test name
Test status
Simulation time 27008939 ps
CPU time 0.57 seconds
Started Mar 14 12:40:06 PM PDT 24
Finished Mar 14 12:40:07 PM PDT 24
Peak memory 195464 kb
Host smart-3ec0c728-abbb-4182-99ee-735ef49ef2f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598455143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3598455143
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1285255427
Short name T343
Test name
Test status
Simulation time 1221978316 ps
CPU time 6.07 seconds
Started Mar 14 12:40:06 PM PDT 24
Finished Mar 14 12:40:13 PM PDT 24
Peak memory 216464 kb
Host smart-91e57908-5561-429a-8e8f-c7304b164c84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285255427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1285255427
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2840523147
Short name T159
Test name
Test status
Simulation time 1638857990 ps
CPU time 6.14 seconds
Started Mar 14 12:40:05 PM PDT 24
Finished Mar 14 12:40:12 PM PDT 24
Peak memory 199992 kb
Host smart-1af829be-163b-4803-91c1-7d6150f3e69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840523147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2840523147
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2466089201
Short name T471
Test name
Test status
Simulation time 15116425606 ps
CPU time 111.88 seconds
Started Mar 14 12:40:07 PM PDT 24
Finished Mar 14 12:41:59 PM PDT 24
Peak memory 200008 kb
Host smart-15d79c1c-065e-4520-b22b-c44ecbcafaeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2466089201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2466089201
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2917977899
Short name T283
Test name
Test status
Simulation time 26587612166 ps
CPU time 99.8 seconds
Started Mar 14 12:40:08 PM PDT 24
Finished Mar 14 12:41:48 PM PDT 24
Peak memory 200056 kb
Host smart-2615a54f-42b4-4006-9d02-c223e9a78ef7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917977899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2917977899
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1914936633
Short name T90
Test name
Test status
Simulation time 31120819924 ps
CPU time 75.59 seconds
Started Mar 14 12:40:05 PM PDT 24
Finished Mar 14 12:41:21 PM PDT 24
Peak memory 199964 kb
Host smart-32222e62-02f1-4bdc-aa66-e76c00d21d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914936633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1914936633
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2244952637
Short name T557
Test name
Test status
Simulation time 1491349554 ps
CPU time 4.21 seconds
Started Mar 14 12:40:05 PM PDT 24
Finished Mar 14 12:40:10 PM PDT 24
Peak memory 199996 kb
Host smart-38ef0c5e-70a6-44b4-8bb0-9be939016c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244952637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2244952637
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4112879564
Short name T295
Test name
Test status
Simulation time 176915934141 ps
CPU time 374.3 seconds
Started Mar 14 12:40:07 PM PDT 24
Finished Mar 14 12:46:21 PM PDT 24
Peak memory 224296 kb
Host smart-734b6846-19e3-4fd8-b2d5-de0b8e3aecb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112879564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4112879564
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1650313561
Short name T70
Test name
Test status
Simulation time 32175616 ps
CPU time 1.12 seconds
Started Mar 14 12:40:07 PM PDT 24
Finished Mar 14 12:40:09 PM PDT 24
Peak memory 199784 kb
Host smart-73dee8ca-4cbf-4405-a08d-05444dc48671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650313561 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.1650313561
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1310445471
Short name T413
Test name
Test status
Simulation time 29533880376 ps
CPU time 495.01 seconds
Started Mar 14 12:40:06 PM PDT 24
Finished Mar 14 12:48:21 PM PDT 24
Peak memory 199984 kb
Host smart-bc786ca8-22af-417e-9462-06f4ec024038
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310445471 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1310445471
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4193358980
Short name T134
Test name
Test status
Simulation time 299529345 ps
CPU time 4.04 seconds
Started Mar 14 12:40:04 PM PDT 24
Finished Mar 14 12:40:08 PM PDT 24
Peak memory 199724 kb
Host smart-a2bb6c02-abd1-49e3-98eb-59f2bbc960ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193358980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4193358980
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2665764767
Short name T109
Test name
Test status
Simulation time 38141137 ps
CPU time 0.52 seconds
Started Mar 14 12:40:13 PM PDT 24
Finished Mar 14 12:40:14 PM PDT 24
Peak memory 195096 kb
Host smart-5892f461-9ede-4c0b-a180-95f64efa78cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665764767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2665764767
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3659630913
Short name T590
Test name
Test status
Simulation time 6302758796 ps
CPU time 43.53 seconds
Started Mar 14 12:40:05 PM PDT 24
Finished Mar 14 12:40:49 PM PDT 24
Peak memory 218568 kb
Host smart-1b8bcb5a-ad18-48b6-906e-2a3378962d69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659630913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3659630913
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.4286728762
Short name T529
Test name
Test status
Simulation time 72960229 ps
CPU time 1.7 seconds
Started Mar 14 12:40:14 PM PDT 24
Finished Mar 14 12:40:16 PM PDT 24
Peak memory 200012 kb
Host smart-9893c8be-e0c6-446d-a359-028cad9b539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286728762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4286728762
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3564938124
Short name T158
Test name
Test status
Simulation time 8582127960 ps
CPU time 52.2 seconds
Started Mar 14 12:40:19 PM PDT 24
Finished Mar 14 12:41:12 PM PDT 24
Peak memory 200064 kb
Host smart-031b9b3d-2805-414a-a3a5-55a987df019e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564938124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3564938124
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1466090304
Short name T263
Test name
Test status
Simulation time 5401868301 ps
CPU time 57.86 seconds
Started Mar 14 12:40:14 PM PDT 24
Finished Mar 14 12:41:12 PM PDT 24
Peak memory 200060 kb
Host smart-a73ce158-ec8d-41a2-9b38-3fa65feccef9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466090304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1466090304
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.190390767
Short name T259
Test name
Test status
Simulation time 1521646524 ps
CPU time 41.14 seconds
Started Mar 14 12:40:08 PM PDT 24
Finished Mar 14 12:40:49 PM PDT 24
Peak memory 200048 kb
Host smart-b12543ee-e2b6-4a72-8b54-062203a97e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190390767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.190390767
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2518453834
Short name T258
Test name
Test status
Simulation time 601244612 ps
CPU time 3.68 seconds
Started Mar 14 12:40:06 PM PDT 24
Finished Mar 14 12:40:10 PM PDT 24
Peak memory 199856 kb
Host smart-df01e9a3-82e3-4ed2-957e-6b898b955abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518453834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2518453834
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1469984942
Short name T238
Test name
Test status
Simulation time 21708857799 ps
CPU time 1079.32 seconds
Started Mar 14 12:40:13 PM PDT 24
Finished Mar 14 12:58:13 PM PDT 24
Peak memory 200112 kb
Host smart-88e5686c-058d-4f69-a874-f73478727858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469984942 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1469984942
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3169186320
Short name T172
Test name
Test status
Simulation time 207696604 ps
CPU time 0.96 seconds
Started Mar 14 12:40:15 PM PDT 24
Finished Mar 14 12:40:16 PM PDT 24
Peak memory 199104 kb
Host smart-74caf503-ea4e-450d-897e-4d877eba0d83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169186320 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3169186320
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.2618490201
Short name T71
Test name
Test status
Simulation time 48125299381 ps
CPU time 405.33 seconds
Started Mar 14 12:41:23 PM PDT 24
Finished Mar 14 12:48:09 PM PDT 24
Peak memory 198800 kb
Host smart-5dcb8344-5503-447a-bc80-9de1f75636cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618490201 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.2618490201
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1134271964
Short name T421
Test name
Test status
Simulation time 1052873559 ps
CPU time 31.88 seconds
Started Mar 14 12:41:23 PM PDT 24
Finished Mar 14 12:41:56 PM PDT 24
Peak memory 198000 kb
Host smart-e77a2bd2-0b53-4bb6-91f8-0e5f919b7a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134271964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1134271964
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2378118232
Short name T267
Test name
Test status
Simulation time 12104596 ps
CPU time 0.54 seconds
Started Mar 14 12:40:18 PM PDT 24
Finished Mar 14 12:40:19 PM PDT 24
Peak memory 194572 kb
Host smart-6809dc84-b8f2-4b40-a0d7-814ecbfee3b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378118232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2378118232
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3828020071
Short name T360
Test name
Test status
Simulation time 13914678942 ps
CPU time 56.45 seconds
Started Mar 14 12:40:14 PM PDT 24
Finished Mar 14 12:41:10 PM PDT 24
Peak memory 230764 kb
Host smart-bcced9e8-8c6c-433f-b50d-4e41e6426e66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828020071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3828020071
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2264159036
Short name T397
Test name
Test status
Simulation time 11341588650 ps
CPU time 37.45 seconds
Started Mar 14 12:40:15 PM PDT 24
Finished Mar 14 12:40:53 PM PDT 24
Peak memory 200044 kb
Host smart-e9e2a3dd-4208-4891-a834-290f2f75365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264159036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2264159036
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2599193473
Short name T279
Test name
Test status
Simulation time 1167703238 ps
CPU time 43.36 seconds
Started Mar 14 12:40:15 PM PDT 24
Finished Mar 14 12:40:59 PM PDT 24
Peak memory 199936 kb
Host smart-fca66d24-6573-4559-9c6c-4f3143b65d7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599193473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2599193473
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4164123721
Short name T555
Test name
Test status
Simulation time 968117795 ps
CPU time 13.24 seconds
Started Mar 14 12:40:15 PM PDT 24
Finished Mar 14 12:40:29 PM PDT 24
Peak memory 199968 kb
Host smart-14612f5e-e637-45e1-b859-42900ffdac59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164123721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4164123721
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2403070724
Short name T432
Test name
Test status
Simulation time 173385505 ps
CPU time 5.12 seconds
Started Mar 14 12:40:19 PM PDT 24
Finished Mar 14 12:40:24 PM PDT 24
Peak memory 199844 kb
Host smart-d3aa22b3-daf5-40dc-baa6-f2d2ee443f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403070724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2403070724
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.579666160
Short name T328
Test name
Test status
Simulation time 332651728905 ps
CPU time 1591.03 seconds
Started Mar 14 12:40:17 PM PDT 24
Finished Mar 14 01:06:48 PM PDT 24
Peak memory 232580 kb
Host smart-5542b3c8-829e-4252-9321-b1b9c26fa905
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579666160 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.579666160
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.310902231
Short name T189
Test name
Test status
Simulation time 108278987 ps
CPU time 1.06 seconds
Started Mar 14 12:40:13 PM PDT 24
Finished Mar 14 12:40:14 PM PDT 24
Peak memory 199092 kb
Host smart-48d10200-69f0-40e3-ac86-12ef5a5ce310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310902231 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_hmac_vectors.310902231
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1286541491
Short name T82
Test name
Test status
Simulation time 33094887503 ps
CPU time 443.56 seconds
Started Mar 14 12:40:13 PM PDT 24
Finished Mar 14 12:47:37 PM PDT 24
Peak memory 200040 kb
Host smart-770f92bc-482d-4a38-829d-3f194287f547
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286541491 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1286541491
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1090869773
Short name T526
Test name
Test status
Simulation time 4047730893 ps
CPU time 41.4 seconds
Started Mar 14 12:40:16 PM PDT 24
Finished Mar 14 12:40:58 PM PDT 24
Peak memory 200024 kb
Host smart-515869a4-7b3b-47aa-b9e3-bb8d36b10934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090869773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1090869773
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.1253807547
Short name T490
Test name
Test status
Simulation time 1240757785168 ps
CPU time 2846.63 seconds
Started Mar 14 12:43:20 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 250452 kb
Host smart-4be2a083-7871-4d62-b8fb-4b30cc68bb6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1253807547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.1253807547
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.3098089173
Short name T10
Test name
Test status
Simulation time 87027209816 ps
CPU time 4639.84 seconds
Started Mar 14 12:43:29 PM PDT 24
Finished Mar 14 02:00:50 PM PDT 24
Peak memory 247560 kb
Host smart-ac418ce8-63ea-4a89-8760-d8035427a95e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098089173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.3098089173
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.2628186471
Short name T13
Test name
Test status
Simulation time 82753016596 ps
CPU time 3885.1 seconds
Started Mar 14 12:43:26 PM PDT 24
Finished Mar 14 01:48:12 PM PDT 24
Peak memory 257480 kb
Host smart-21690cc4-98cc-492b-8a50-8442eec3759a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628186471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.2628186471
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.3846768690
Short name T533
Test name
Test status
Simulation time 24920169662 ps
CPU time 369.7 seconds
Started Mar 14 12:43:26 PM PDT 24
Finished Mar 14 12:49:36 PM PDT 24
Peak memory 224792 kb
Host smart-7007d8da-4645-484a-9d31-229f8db7bbae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846768690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.3846768690
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1480543959
Short name T498
Test name
Test status
Simulation time 17800592 ps
CPU time 0.55 seconds
Started Mar 14 12:40:23 PM PDT 24
Finished Mar 14 12:40:24 PM PDT 24
Peak memory 195544 kb
Host smart-0cff559f-8663-4d72-85ca-d65c6e1e41ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480543959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1480543959
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3874128108
Short name T273
Test name
Test status
Simulation time 3295192545 ps
CPU time 31.41 seconds
Started Mar 14 12:40:18 PM PDT 24
Finished Mar 14 12:40:50 PM PDT 24
Peak memory 232792 kb
Host smart-f059b497-1f6a-4b4f-a6b6-6d576397e55e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874128108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3874128108
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3006249873
Short name T106
Test name
Test status
Simulation time 1101255248 ps
CPU time 24.92 seconds
Started Mar 14 12:40:18 PM PDT 24
Finished Mar 14 12:40:43 PM PDT 24
Peak memory 199964 kb
Host smart-8f36ea99-af21-405c-b227-e32a329b067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006249873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3006249873
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.4109039760
Short name T353
Test name
Test status
Simulation time 1829442030 ps
CPU time 93.39 seconds
Started Mar 14 12:41:31 PM PDT 24
Finished Mar 14 12:43:05 PM PDT 24
Peak memory 199544 kb
Host smart-b72a4f43-ca7c-404e-bb00-483dff01fd41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4109039760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4109039760
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3750639117
Short name T410
Test name
Test status
Simulation time 48921842408 ps
CPU time 36.53 seconds
Started Mar 14 12:40:13 PM PDT 24
Finished Mar 14 12:40:50 PM PDT 24
Peak memory 200320 kb
Host smart-b9af8312-a4a9-408e-a42c-9b379a76262d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750639117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3750639117
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.860874519
Short name T586
Test name
Test status
Simulation time 11000556795 ps
CPU time 147.55 seconds
Started Mar 14 12:40:15 PM PDT 24
Finished Mar 14 12:42:43 PM PDT 24
Peak memory 200048 kb
Host smart-6c56ca09-2dce-48eb-9ea8-a87a507b46f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860874519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.860874519
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4054006906
Short name T465
Test name
Test status
Simulation time 404690503 ps
CPU time 5.78 seconds
Started Mar 14 12:40:19 PM PDT 24
Finished Mar 14 12:40:26 PM PDT 24
Peak memory 199788 kb
Host smart-7e430509-d1ad-4f59-8128-6c8037e7dfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054006906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4054006906
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1841458316
Short name T77
Test name
Test status
Simulation time 239802613804 ps
CPU time 1437.81 seconds
Started Mar 14 12:40:25 PM PDT 24
Finished Mar 14 01:04:23 PM PDT 24
Peak memory 216500 kb
Host smart-960f6960-abbf-49e7-89b5-a2d63079fbff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841458316 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1841458316
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2168423984
Short name T215
Test name
Test status
Simulation time 209979897 ps
CPU time 1.11 seconds
Started Mar 14 12:40:25 PM PDT 24
Finished Mar 14 12:40:27 PM PDT 24
Peak memory 200008 kb
Host smart-92c82527-3d60-4e9e-8bb4-8b10beae33a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168423984 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2168423984
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3508288402
Short name T594
Test name
Test status
Simulation time 38108675703 ps
CPU time 499.07 seconds
Started Mar 14 12:40:25 PM PDT 24
Finished Mar 14 12:48:44 PM PDT 24
Peak memory 200052 kb
Host smart-5b2fb9d0-2b22-4fad-abde-530c864f792b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508288402 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3508288402
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1949382887
Short name T580
Test name
Test status
Simulation time 2878374381 ps
CPU time 29.71 seconds
Started Mar 14 12:40:14 PM PDT 24
Finished Mar 14 12:40:44 PM PDT 24
Peak memory 199956 kb
Host smart-e60a02ff-6d92-45f5-b70e-149e4105ec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949382887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1949382887
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.1268339852
Short name T587
Test name
Test status
Simulation time 13167749734 ps
CPU time 485.2 seconds
Started Mar 14 12:43:29 PM PDT 24
Finished Mar 14 12:51:34 PM PDT 24
Peak memory 249172 kb
Host smart-40834670-4840-43ce-8028-f0a02a8d9bd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268339852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.1268339852
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3457231652
Short name T304
Test name
Test status
Simulation time 19967652 ps
CPU time 0.54 seconds
Started Mar 14 12:40:33 PM PDT 24
Finished Mar 14 12:40:33 PM PDT 24
Peak memory 194612 kb
Host smart-9b6ebbea-f45d-43fc-b5f9-a609dc20af03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457231652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3457231652
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2546484284
Short name T550
Test name
Test status
Simulation time 1588252303 ps
CPU time 62.5 seconds
Started Mar 14 12:40:25 PM PDT 24
Finished Mar 14 12:41:27 PM PDT 24
Peak memory 230792 kb
Host smart-c7fce59d-8162-497a-8cfe-8e8d01c5b52b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546484284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2546484284
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.900317312
Short name T102
Test name
Test status
Simulation time 276947864 ps
CPU time 1.53 seconds
Started Mar 14 12:40:22 PM PDT 24
Finished Mar 14 12:40:24 PM PDT 24
Peak memory 199940 kb
Host smart-4c3df361-e847-4136-b4c0-948dfe1287cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900317312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.900317312
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3419734348
Short name T253
Test name
Test status
Simulation time 14252047339 ps
CPU time 118.78 seconds
Started Mar 14 12:40:22 PM PDT 24
Finished Mar 14 12:42:21 PM PDT 24
Peak memory 200036 kb
Host smart-9548275a-4087-4ca1-be21-ef8e04304a18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419734348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3419734348
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1656846676
Short name T583
Test name
Test status
Simulation time 4458782495 ps
CPU time 59.21 seconds
Started Mar 14 12:40:24 PM PDT 24
Finished Mar 14 12:41:23 PM PDT 24
Peak memory 200112 kb
Host smart-caa5755b-59a8-450f-8038-c053a3daa037
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656846676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1656846676
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3477779264
Short name T423
Test name
Test status
Simulation time 2362743573 ps
CPU time 11.6 seconds
Started Mar 14 12:40:24 PM PDT 24
Finished Mar 14 12:40:36 PM PDT 24
Peak memory 199964 kb
Host smart-86e2c6ca-af55-496d-af7e-e5768eb1138c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477779264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3477779264
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.4116391813
Short name T30
Test name
Test status
Simulation time 350886852 ps
CPU time 3.24 seconds
Started Mar 14 12:40:24 PM PDT 24
Finished Mar 14 12:40:28 PM PDT 24
Peak memory 200064 kb
Host smart-0531eb44-2516-4fd6-8b0e-8f0dde703aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116391813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.4116391813
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1991044026
Short name T117
Test name
Test status
Simulation time 58019150049 ps
CPU time 61.21 seconds
Started Mar 14 12:40:22 PM PDT 24
Finished Mar 14 12:41:24 PM PDT 24
Peak memory 200096 kb
Host smart-88a6d07c-a2be-46f1-806f-5f0b77759fc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991044026 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1991044026
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1804004190
Short name T18
Test name
Test status
Simulation time 112056021 ps
CPU time 1.17 seconds
Started Mar 14 12:40:24 PM PDT 24
Finished Mar 14 12:40:25 PM PDT 24
Peak memory 199936 kb
Host smart-b491b7ff-14b4-4230-b1c9-8f84d1a527b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804004190 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1804004190
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.691217602
Short name T367
Test name
Test status
Simulation time 8237498257 ps
CPU time 440.92 seconds
Started Mar 14 12:40:23 PM PDT 24
Finished Mar 14 12:47:44 PM PDT 24
Peak memory 200060 kb
Host smart-d4d34962-0fe0-4023-90fc-2eee80da2a3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691217602 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.691217602
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.4217195904
Short name T179
Test name
Test status
Simulation time 5094970338 ps
CPU time 66.39 seconds
Started Mar 14 12:40:25 PM PDT 24
Finished Mar 14 12:41:32 PM PDT 24
Peak memory 200056 kb
Host smart-f34ed792-9857-4c22-8250-8f74eaca18f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217195904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.4217195904
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.2266097029
Short name T15
Test name
Test status
Simulation time 233742899678 ps
CPU time 2566.9 seconds
Started Mar 14 12:43:28 PM PDT 24
Finished Mar 14 01:26:15 PM PDT 24
Peak memory 216416 kb
Host smart-0ceb15f5-b196-4a46-b878-be2951f360cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266097029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.2266097029
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest
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