Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14646078	1			T1	5356		T2	71637		T3	12807
all_values[1]	14646078	1			T1	5356		T2	71637		T3	12807
all_values[2]	14646078	1			T1	5356		T2	71637		T3	12807

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97005

1

T3

1004

T4

9

T22

239

auto[1]

43841229

1

T1

16068

T2

214911

T3

37417

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41495267

1

T1

16044

T2

206074

T3

38380

auto[1]

2442967

1

T1

24

T2

8837

T3

41

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29059	1			T6	7		T18	366		T12	6
all_values[0]	auto[0]	auto[1]	379	1			T6	6		T23	2		T54	2
all_values[0]	auto[1]	auto[0]	14569193	1			T1	5332		T2	71443		T3	12766
all_values[0]	auto[1]	auto[1]	47447	1			T1	24		T2	194		T3	41
all_values[1]	auto[0]	auto[0]	32033	1			T22	239		T6	6		T24	293
all_values[1]	auto[0]	auto[1]	175	1			T6	3		T12	3		T13	3
all_values[1]	auto[1]	auto[0]	14613453	1			T1	5356		T2	71637		T3	12807
all_values[1]	auto[1]	auto[1]	417	1			T12	51		T23	1		T13	3
all_values[2]	auto[0]	auto[0]	30335	1			T3	1004		T4	9		T6	2
all_values[2]	auto[0]	auto[1]	5024	1			T6	6		T12	2		T36	1
all_values[2]	auto[1]	auto[0]	12221194	1			T1	5356		T2	62994		T3	11803
all_values[2]	auto[1]	auto[1]	2389525	1			T2	8643		T5	5151		T6	244