Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6861886

1

T1

3172

T2

36941

T3

5244

auto[1]

2446350

1

T1

2110

T3

7063

T4

16752

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2395645

1

T1

2754

T3

5517

T4

20823

auto[1]

6912591

1

T1

2528

T2

36941

T3

6790

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6170173

1

T1

4006

T2

36941

T4

9284

auto[1]

3138063

1

T1

1276

T3

12307

T4

20797

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6116085	1			T1	4578		T2	23931		T3	4274
fifo_depth[1]	463182	1			T1	312		T2	2450		T3	887
fifo_depth[2]	388367	1			T1	214		T2	2425		T3	902
fifo_depth[3]	316199	1			T1	118		T2	1868		T3	890
fifo_depth[4]	268198	1			T1	46		T2	1550		T3	916
fifo_depth[5]	238346	1			T1	11		T2	1284		T3	888
fifo_depth[6]	223766	1			T1	2		T2	1069		T3	892
fifo_depth[7]	195718	1			T1	1		T2	864		T3	810
fifo_depth[8]	172576	1			T2	600		T3	664		T4	457
fifo_depth[9]	119501	1			T2	390		T3	515		T4	195
fifo_depth[10]	87595	1			T2	241		T3	321		T4	446
fifo_depth[11]	53730	1			T2	138		T3	172		T4	168
fifo_depth[12]	49805	1			T2	75		T3	97		T4	508
fifo_depth[13]	24421	1			T2	35		T3	43		T4	232
fifo_depth[14]	29965	1			T2	9		T3	19		T4	646
fifo_depth[15]	19287	1			T2	7		T3	10		T4	367
fifo_depth[16]	67288	1			T2	5		T3	3		T4	1471

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3288735

1

T1

704

T2

13010

T3

8033

auto[1]

6019501

1

T1

4578

T2

23931

T3

4274

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9211652

1

T1

5282

T2

36941

T3

12307

auto[1]

96584

1

T4

5029

T17

6

T12

11286

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

201676

1

T1

134

T4

1401

T5

37

auto[0]

auto[0]

auto[0]

auto[1]

217693

1

T1

187

T4

4004

T5

76

auto[0]

auto[0]

auto[1]

auto[0]

1088347

1

T1

150

T2

13010

T4

1102

auto[0]

auto[0]

auto[1]

auto[1]

195105

1

T1

59

T4

2403

T5

76

auto[0]

auto[1]

auto[0]

auto[0]

389999

1

T3

1778

T4

9639

T5

235

auto[0]

auto[1]

auto[0]

auto[1]

394849

1

T1

33

T3

1850

T4

5412

auto[0]

auto[1]

auto[1]

auto[0]

399129

1

T1

141

T3

1650

T4

951

auto[0]

auto[1]

auto[1]

auto[1]

401937

1

T3

2755

T4

4760

T5

87

auto[1]

auto[0]

auto[0]

auto[0]

208517

1

T1

891

T4

186

T5

505

auto[1]

auto[0]

auto[0]

auto[1]

222542

1

T1

1295

T4

156

T5

1133

auto[1]

auto[0]

auto[1]

auto[0]

3810934

1

T1

970

T2

23931

T4

24

auto[1]

auto[0]

auto[1]

auto[1]

225359

1

T1

320

T4

8

T5

1527

auto[1]

auto[1]

auto[0]

auto[0]

368080

1

T3

937

T4

22

T5

2770

auto[1]

auto[1]

auto[0]

auto[1]

392289

1

T1

214

T3

952

T4

3

auto[1]

auto[1]

auto[1]

auto[0]

395204

1

T1

886

T3

879

T4

4

auto[1]

auto[1]

auto[1]

auto[1]

396576

1

T1

2

T3

1506

T4

6

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

397251

1

T1

1025

T4

1506

T5

542

auto[0]

auto[0]

auto[0]

auto[1]

431444

1

T1

1482

T4

3920

T5

1209

auto[0]

auto[0]

auto[1]

auto[0]

4887107

1

T1

1120

T2

36941

T4

1092

auto[0]

auto[0]

auto[1]

auto[1]

410230

1

T1

379

T4

1901

T5

1603

auto[0]

auto[1]

auto[0]

auto[0]

742894

1

T3

2715

T4

7086

T5

3005

auto[0]

auto[1]

auto[0]

auto[1]

776834

1

T1

247

T3

2802

T4

4971

auto[0]

auto[1]

auto[1]

auto[0]

781564

1

T1

1027

T3

2529

T4

908

auto[0]

auto[1]

auto[1]

auto[1]

784328

1

T1

2

T3

4261

T4

3668

auto[1]

auto[0]

auto[0]

auto[0]

12942

1

T4

81

T17

1

T12

2335

auto[1]

auto[0]

auto[0]

auto[1]

8791

1

T4

240

T17

1

T12

855

auto[1]

auto[0]

auto[1]

auto[0]

12174

1

T4

34

T12

974

T23

571

auto[1]

auto[0]

auto[1]

auto[1]

10234

1

T4

510

T17

1

T12

1666

auto[1]

auto[1]

auto[0]

auto[0]

15185

1

T4

2575

T17

1

T12

797

auto[1]

auto[1]

auto[0]

auto[1]

10304

1

T4

444

T17

1

T12

1415

auto[1]

auto[1]

auto[1]

auto[0]

12769

1

T4

47

T12

2347

T23

16

auto[1]

auto[1]

auto[1]

auto[1]

14185

1

T4

1098

T17

1

T12

897

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	221459	1			T1	891		T4	267		T5	505
fifo_depth[0]	auto[0]	auto[0]	auto[1]	231333	1			T1	1295		T4	396		T5	1133
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3823108	1			T1	970		T2	23931		T4	58
fifo_depth[0]	auto[0]	auto[1]	auto[1]	235593	1			T1	320		T4	518		T5	1527
fifo_depth[0]	auto[1]	auto[0]	auto[0]	383265	1			T3	937		T4	2597		T5	2770
fifo_depth[0]	auto[1]	auto[0]	auto[1]	402593	1			T1	214		T3	952		T4	447
fifo_depth[0]	auto[1]	auto[1]	auto[0]	407973	1			T1	886		T3	879		T4	51
fifo_depth[0]	auto[1]	auto[1]	auto[1]	410761	1			T1	2		T3	1506		T4	1104
fifo_depth[1]	auto[0]	auto[0]	auto[0]	17345	1			T1	59		T4	49		T5	19
fifo_depth[1]	auto[0]	auto[0]	auto[1]	18709	1			T1	79		T4	41		T5	42
fifo_depth[1]	auto[0]	auto[1]	auto[0]	239700	1			T1	69		T2	2450		T4	12
fifo_depth[1]	auto[0]	auto[1]	auto[1]	17726	1			T1	26		T5	43		T22	25
fifo_depth[1]	auto[1]	auto[0]	auto[0]	39674	1			T3	208		T4	7		T5	140
fifo_depth[1]	auto[1]	auto[0]	auto[1]	43170	1			T1	19		T3	201		T5	27
fifo_depth[1]	auto[1]	auto[1]	auto[0]	43084	1			T1	60		T3	184		T4	2
fifo_depth[1]	auto[1]	auto[1]	auto[1]	43774	1			T3	294		T5	27		T27	4
fifo_depth[2]	auto[0]	auto[0]	auto[0]	14737	1			T1	38		T4	52		T5	9
fifo_depth[2]	auto[0]	auto[0]	auto[1]	16252	1			T1	62		T4	42		T5	20
fifo_depth[2]	auto[0]	auto[1]	auto[0]	191205	1			T1	41		T2	2425		T4	2
fifo_depth[2]	auto[0]	auto[1]	auto[1]	14859	1			T1	20		T4	1		T5	19
fifo_depth[2]	auto[1]	auto[0]	auto[0]	35722	1			T3	193		T4	4		T5	78
fifo_depth[2]	auto[1]	auto[0]	auto[1]	38456	1			T1	8		T3	203		T5	25
fifo_depth[2]	auto[1]	auto[1]	auto[0]	38670	1			T1	45		T3	201		T4	1
fifo_depth[2]	auto[1]	auto[1]	auto[1]	38466	1			T3	305		T4	1		T5	24
fifo_depth[3]	auto[0]	auto[0]	auto[0]	12001	1			T1	20		T4	50		T5	4
fifo_depth[3]	auto[0]	auto[0]	auto[1]	13283	1			T1	29		T4	36		T5	10
fifo_depth[3]	auto[0]	auto[1]	auto[0]	144745	1			T1	27		T2	1868		T4	12
fifo_depth[3]	auto[0]	auto[1]	auto[1]	12101	1			T1	9		T4	1		T5	8
fifo_depth[3]	auto[1]	auto[0]	auto[0]	31673	1			T3	203		T4	5		T5	9
fifo_depth[3]	auto[1]	auto[0]	auto[1]	34167	1			T1	5		T3	212		T4	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	34300	1			T1	28		T3	184		T4	3
fifo_depth[3]	auto[1]	auto[1]	auto[1]	33929	1			T3	291		T4	1		T5	13
fifo_depth[4]	auto[0]	auto[0]	auto[0]	11028	1			T1	14		T4	46		T5	3
fifo_depth[4]	auto[0]	auto[0]	auto[1]	12761	1			T1	11		T4	42		T5	2
fifo_depth[4]	auto[0]	auto[1]	auto[0]	104836	1			T1	9		T2	1550		T4	1
fifo_depth[4]	auto[0]	auto[1]	auto[1]	11767	1			T1	4		T4	1		T5	2
fifo_depth[4]	auto[1]	auto[0]	auto[0]	29850	1			T3	190		T4	6		T5	5
fifo_depth[4]	auto[1]	auto[0]	auto[1]	32507	1			T1	1		T3	208		T4	1
fifo_depth[4]	auto[1]	auto[1]	auto[0]	32802	1			T1	7		T3	209		T5	1
fifo_depth[4]	auto[1]	auto[1]	auto[1]	32647	1			T3	309		T4	1		T5	17
fifo_depth[5]	auto[0]	auto[0]	auto[0]	9989	1			T1	1		T4	50		T5	2
fifo_depth[5]	auto[0]	auto[0]	auto[1]	11398	1			T1	6		T4	44		T5	2
fifo_depth[5]	auto[0]	auto[1]	auto[0]	84920	1			T1	3		T2	1284		T4	12
fifo_depth[5]	auto[0]	auto[1]	auto[1]	10330	1			T5	2		T22	37		T6	9
fifo_depth[5]	auto[1]	auto[0]	auto[0]	28982	1			T3	180		T4	68		T5	2
fifo_depth[5]	auto[1]	auto[0]	auto[1]	30937	1			T3	200		T5	6		T27	5
fifo_depth[5]	auto[1]	auto[1]	auto[0]	30799	1			T1	1		T3	185		T5	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	30991	1			T3	323		T4	2		T5	2
fifo_depth[6]	auto[0]	auto[0]	auto[0]	9845	1			T1	2		T4	52		T6	4
fifo_depth[6]	auto[0]	auto[0]	auto[1]	11313	1			T4	38		T6	1		T15	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	73124	1			T2	1069		T4	2		T5	1
fifo_depth[6]	auto[0]	auto[1]	auto[1]	10459	1			T4	2		T5	2		T22	23
fifo_depth[6]	auto[1]	auto[0]	auto[0]	28030	1			T3	199		T4	15		T5	1
fifo_depth[6]	auto[1]	auto[0]	auto[1]	30283	1			T3	203		T5	6		T27	6
fifo_depth[6]	auto[1]	auto[1]	auto[0]	30528	1			T3	177		T4	3		T22	41
fifo_depth[6]	auto[1]	auto[1]	auto[1]	30184	1			T3	313		T4	5		T5	2
fifo_depth[7]	auto[0]	auto[0]	auto[0]	8756	1			T4	51		T6	1		T15	13
fifo_depth[7]	auto[0]	auto[0]	auto[1]	10125	1			T4	38		T12	119		T13	13
fifo_depth[7]	auto[0]	auto[1]	auto[0]	58162	1			T1	1		T2	864		T4	13
fifo_depth[7]	auto[0]	auto[1]	auto[1]	9163	1			T4	1		T22	22		T6	4
fifo_depth[7]	auto[1]	auto[0]	auto[0]	25888	1			T3	172		T4	73		T27	1
fifo_depth[7]	auto[1]	auto[0]	auto[1]	27751	1			T3	194		T4	3		T5	1
fifo_depth[7]	auto[1]	auto[1]	auto[0]	28289	1			T3	174		T4	1		T5	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	27584	1			T3	270		T4	4		T22	41
fifo_depth[8]	auto[0]	auto[0]	auto[0]	9206	1			T4	89		T6	2		T15	2
fifo_depth[8]	auto[0]	auto[0]	auto[1]	10283	1			T4	43		T12	169		T13	42
fifo_depth[8]	auto[0]	auto[1]	auto[0]	44544	1			T2	600		T4	3		T22	20
fifo_depth[8]	auto[0]	auto[1]	auto[1]	10504	1			T4	3		T22	11		T6	5
fifo_depth[8]	auto[1]	auto[0]	auto[0]	23203	1			T3	159		T4	300		T27	2
fifo_depth[8]	auto[1]	auto[0]	auto[1]	24861	1			T3	149		T4	1		T5	1
fifo_depth[8]	auto[1]	auto[1]	auto[0]	25460	1			T3	115		T4	1		T27	1
fifo_depth[8]	auto[1]	auto[1]	auto[1]	24515	1			T3	241		T4	17		T5	2
fifo_depth[9]	auto[0]	auto[0]	auto[0]	5970	1			T4	67		T6	1		T15	1
fifo_depth[9]	auto[0]	auto[0]	auto[1]	7001	1			T4	37		T12	124		T23	1
fifo_depth[9]	auto[0]	auto[1]	auto[0]	29498	1			T2	390		T4	12		T22	15
fifo_depth[9]	auto[0]	auto[1]	auto[1]	6318	1			T22	15		T6	4		T12	236
fifo_depth[9]	auto[1]	auto[0]	auto[0]	16650	1			T3	116		T4	66		T27	1
fifo_depth[9]	auto[1]	auto[0]	auto[1]	18002	1			T3	113		T27	4		T15	2
fifo_depth[9]	auto[1]	auto[1]	auto[0]	18197	1			T3	105		T4	2		T22	18
fifo_depth[9]	auto[1]	auto[1]	auto[1]	17865	1			T3	181		T4	11		T22	29
fifo_depth[10]	auto[0]	auto[0]	auto[0]	4979	1			T4	71		T12	68		T13	2
fifo_depth[10]	auto[0]	auto[0]	auto[1]	5859	1			T4	29		T12	120		T13	3
fifo_depth[10]	auto[0]	auto[1]	auto[0]	19854	1			T2	241		T4	3		T22	9
fifo_depth[10]	auto[0]	auto[1]	auto[1]	5634	1			T22	10		T6	2		T12	356
fifo_depth[10]	auto[1]	auto[0]	auto[0]	12535	1			T3	75		T4	309		T27	2
fifo_depth[10]	auto[1]	auto[0]	auto[1]	13094	1			T3	79		T4	18		T27	2
fifo_depth[10]	auto[1]	auto[1]	auto[0]	12723	1			T3	61		T4	1		T27	3
fifo_depth[10]	auto[1]	auto[1]	auto[1]	12917	1			T3	106		T4	15		T22	23
fifo_depth[11]	auto[0]	auto[0]	auto[0]	3120	1			T4	57		T12	56		T13	1
fifo_depth[11]	auto[0]	auto[0]	auto[1]	3903	1			T4	12		T12	102		T13	2
fifo_depth[11]	auto[0]	auto[1]	auto[0]	11556	1			T2	138		T4	11		T22	6
fifo_depth[11]	auto[0]	auto[1]	auto[1]	3512	1			T22	8		T6	2		T12	211
fifo_depth[11]	auto[1]	auto[0]	auto[0]	7521	1			T3	46		T4	56		T27	1
fifo_depth[11]	auto[1]	auto[0]	auto[1]	8112	1			T3	44		T4	18		T27	1
fifo_depth[11]	auto[1]	auto[1]	auto[0]	8057	1			T3	25		T4	6		T27	1
fifo_depth[11]	auto[1]	auto[1]	auto[1]	7949	1			T3	57		T4	8		T22	15
fifo_depth[12]	auto[0]	auto[0]	auto[0]	5635	1			T4	13		T12	262		T7	66
fifo_depth[12]	auto[0]	auto[0]	auto[1]	4462	1			T4	7		T12	102		T13	1
fifo_depth[12]	auto[0]	auto[1]	auto[0]	8018	1			T2	75		T4	36		T22	3
fifo_depth[12]	auto[0]	auto[1]	auto[1]	5444	1			T4	12		T22	3		T12	335
fifo_depth[12]	auto[1]	auto[0]	auto[0]	6565	1			T3	23		T4	317		T27	1
fifo_depth[12]	auto[1]	auto[0]	auto[1]	6536	1			T3	26		T4	97		T12	918
fifo_depth[12]	auto[1]	auto[1]	auto[0]	7049	1			T3	10		T4	7		T27	1
fifo_depth[12]	auto[1]	auto[1]	auto[1]	6096	1			T3	38		T4	19		T22	7
fifo_depth[13]	auto[0]	auto[0]	auto[0]	2108	1			T4	39		T12	85		T7	21
fifo_depth[13]	auto[0]	auto[0]	auto[1]	2480	1			T4	3		T12	134		T23	1
fifo_depth[13]	auto[0]	auto[1]	auto[0]	3991	1			T2	35		T4	10		T22	2
fifo_depth[13]	auto[0]	auto[1]	auto[1]	2539	1			T4	14		T22	1		T12	189
fifo_depth[13]	auto[1]	auto[0]	auto[0]	3431	1			T3	8		T4	47		T27	1
fifo_depth[13]	auto[1]	auto[0]	auto[1]	3217	1			T3	7		T4	105		T12	341
fifo_depth[13]	auto[1]	auto[1]	auto[0]	3513	1			T3	11		T4	5		T22	2
fifo_depth[13]	auto[1]	auto[1]	auto[1]	3142	1			T3	17		T4	9		T22	2
fifo_depth[14]	auto[0]	auto[0]	auto[0]	4073	1			T4	4		T12	185		T7	19
fifo_depth[14]	auto[0]	auto[0]	auto[1]	3433	1			T4	3		T12	148		T23	1
fifo_depth[14]	auto[0]	auto[1]	auto[0]	3839	1			T2	9		T4	35		T22	1
fifo_depth[14]	auto[0]	auto[1]	auto[1]	3499	1			T4	78		T12	294		T23	39
fifo_depth[14]	auto[1]	auto[0]	auto[0]	4493	1			T3	5		T4	342		T15	4
fifo_depth[14]	auto[1]	auto[0]	auto[1]	3740	1			T3	6		T4	163		T12	455
fifo_depth[14]	auto[1]	auto[1]	auto[0]	3398	1			T3	1		T4	7		T22	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	3490	1			T3	7		T4	14		T22	2
fifo_depth[15]	auto[0]	auto[0]	auto[0]	1983	1			T4	40		T12	192		T7	6
fifo_depth[15]	auto[0]	auto[0]	auto[1]	2558	1			T4	2		T12	146		T7	90
fifo_depth[15]	auto[0]	auto[1]	auto[0]	2082	1			T2	7		T4	13		T12	536
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2517	1			T4	79		T12	182		T23	40
fifo_depth[15]	auto[1]	auto[0]	auto[0]	2847	1			T4	53		T15	1		T12	466
fifo_depth[15]	auto[1]	auto[0]	auto[1]	2270	1			T3	5		T4	167		T12	249
fifo_depth[15]	auto[1]	auto[1]	auto[0]	2693	1			T3	4		T4	4		T22	2
fifo_depth[15]	auto[1]	auto[1]	auto[1]	2337	1			T3	1		T4	9		T12	161
fifo_depth[16]	auto[0]	auto[0]	auto[0]	8551	1			T4	7		T12	651		T7	10
fifo_depth[16]	auto[0]	auto[0]	auto[1]	9407	1			T4	2		T12	319		T7	80
fifo_depth[16]	auto[0]	auto[1]	auto[0]	6561	1			T2	5		T4	315		T12	1172
fifo_depth[16]	auto[0]	auto[1]	auto[1]	7727	1			T4	77		T12	654		T23	5
fifo_depth[16]	auto[1]	auto[0]	auto[0]	9895	1			T3	1		T4	501		T12	1680
fifo_depth[16]	auto[1]	auto[0]	auto[1]	8132	1			T4	164		T12	1589		T23	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	8591	1			T3	2		T4	70		T12	2754
fifo_depth[16]	auto[1]	auto[1]	auto[1]	8424	1			T4	335		T12	745		T7	105