Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14646078	1			T1	5356		T2	71637		T3	12807
all_pins[1]	14646078	1			T1	5356		T2	71637		T3	12807
all_pins[2]	14646078	1			T1	5356		T2	71637		T3	12807

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	41499694	1			T1	16043		T2	206074		T3	38377
values[0x1]	2438540	1			T1	25		T2	8837		T3	44
transitions[0x0=>0x1]	2438393	1			T1	25		T2	8837		T3	44
transitions[0x1=>0x0]	2438409	1			T1	25		T2	8837		T3	44

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14597504	1			T1	5331		T2	71443		T3	12763
all_pins[0]	values[0x1]	48574	1			T1	25		T2	194		T3	44
all_pins[0]	transitions[0x0=>0x1]	48515	1			T1	25		T2	194		T3	44
all_pins[0]	transitions[0x1=>0x0]	2389482	1			T2	8643		T5	5151		T6	244
all_pins[1]	values[0x0]	14645637	1			T1	5356		T2	71637		T3	12807
all_pins[1]	values[0x1]	441	1			T12	54		T23	1		T13	3
all_pins[1]	transitions[0x0=>0x1]	402	1			T12	54		T23	1		T13	3
all_pins[1]	transitions[0x1=>0x0]	48535	1			T1	25		T2	194		T3	44
all_pins[2]	values[0x0]	12256553	1			T1	5356		T2	62994		T3	12807
all_pins[2]	values[0x1]	2389525	1			T2	8643		T5	5151		T6	244
all_pins[2]	transitions[0x0=>0x1]	2389476	1			T2	8643		T5	5151		T6	244
all_pins[2]	transitions[0x1=>0x0]	392	1			T12	54		T23	1		T13	1