Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	830	1			T6	7		T12	7		T13	10
all_values[1]	830	1			T6	7		T12	7		T13	10
all_values[2]	830	1			T6	7		T12	7		T13	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1264

1

T6

15

T12

10

T13

12

auto[1]

1226

1

T6

6

T12

11

T13

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

901

1

T6

2

T12

7

T13

8

auto[1]

1589

1

T6

19

T12

14

T13

22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1406

1

T6

9

T12

10

T13

16

auto[1]

1084

1

T6

12

T12

11

T13

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

174

1

T12

2

T13

3

T7

3

all_values[0]

auto[0]

auto[0]

auto[1]

70

1

T6

1

T7

2

T103

2

all_values[0]

auto[0]

auto[1]

auto[0]

154

1

T12

1

T13

1

T7

3

all_values[0]

auto[0]

auto[1]

auto[1]

80

1

T6

1

T13

1

T36

1

all_values[0]

auto[1]

auto[0]

auto[1]

175

1

T6

2

T12

1

T13

3

all_values[0]

auto[1]

auto[1]

auto[1]

177

1

T6

3

T12

3

T13

2

all_values[1]

auto[0]

auto[0]

auto[0]

138

1

T6

1

T12

1

T7

1

all_values[1]

auto[0]

auto[0]

auto[1]

107

1

T6

2

T12

2

T13

1

all_values[1]

auto[0]

auto[1]

auto[0]

114

1

T6

1

T12

1

T7

2

all_values[1]

auto[0]

auto[1]

auto[1]

108

1

T13

3

T7

3

T36

1

all_values[1]

auto[1]

auto[0]

auto[1]

179

1

T6

3

T12

2

T13

2

all_values[1]

auto[1]

auto[1]

auto[1]

184

1

T12

1

T13

4

T7

2

all_values[2]

auto[0]

auto[0]

auto[0]

177

1

T13

3

T7

4

T36

2

all_values[2]

auto[0]

auto[0]

auto[1]

64

1

T6

3

T12

1

T104

1

all_values[2]

auto[0]

auto[1]

auto[0]

144

1

T12

2

T13

1

T7

2

all_values[2]

auto[0]

auto[1]

auto[1]

76

1

T13

3

T7

1

T36

2

all_values[2]

auto[1]

auto[0]

auto[1]

180

1

T6

3

T12

1

T36

4

all_values[2]

auto[1]

auto[1]

auto[1]

189

1

T6

1

T12

3

T13

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal