Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.03 92.80 86.04 100.00 73.68 88.15 99.49 69.08


Total test records in report: 734
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T529 /workspace/coverage/default/28.hmac_long_msg.756898545 Mar 17 01:34:38 PM PDT 24 Mar 17 01:34:54 PM PDT 24 664705356 ps
T530 /workspace/coverage/default/17.hmac_test_hmac_vectors.3397264006 Mar 17 01:33:46 PM PDT 24 Mar 17 01:33:48 PM PDT 24 65898595 ps
T531 /workspace/coverage/default/33.hmac_long_msg.2719586865 Mar 17 01:35:08 PM PDT 24 Mar 17 01:36:38 PM PDT 24 18785774859 ps
T532 /workspace/coverage/default/2.hmac_wipe_secret.2823676095 Mar 17 01:32:59 PM PDT 24 Mar 17 01:34:04 PM PDT 24 1625338202 ps
T533 /workspace/coverage/default/42.hmac_wipe_secret.3537867392 Mar 17 01:35:54 PM PDT 24 Mar 17 01:37:13 PM PDT 24 2440973562 ps
T534 /workspace/coverage/default/23.hmac_back_pressure.1670747882 Mar 17 01:34:17 PM PDT 24 Mar 17 01:34:55 PM PDT 24 972120978 ps
T535 /workspace/coverage/default/14.hmac_stress_all.3812060091 Mar 17 01:33:34 PM PDT 24 Mar 17 01:49:04 PM PDT 24 321077125355 ps
T536 /workspace/coverage/default/7.hmac_burst_wr.1728118910 Mar 17 01:33:16 PM PDT 24 Mar 17 01:34:18 PM PDT 24 5998016231 ps
T537 /workspace/coverage/default/30.hmac_back_pressure.1873031115 Mar 17 01:34:51 PM PDT 24 Mar 17 01:35:39 PM PDT 24 5721773649 ps
T538 /workspace/coverage/default/34.hmac_test_sha_vectors.1599973295 Mar 17 01:35:13 PM PDT 24 Mar 17 01:42:04 PM PDT 24 30379592905 ps
T539 /workspace/coverage/default/41.hmac_test_hmac_vectors.532557636 Mar 17 01:35:48 PM PDT 24 Mar 17 01:35:50 PM PDT 24 71055863 ps
T540 /workspace/coverage/default/41.hmac_datapath_stress.2612909354 Mar 17 01:35:47 PM PDT 24 Mar 17 01:37:02 PM PDT 24 2523455798 ps
T541 /workspace/coverage/default/1.hmac_datapath_stress.1542821005 Mar 17 01:32:54 PM PDT 24 Mar 17 01:34:39 PM PDT 24 10292101715 ps
T542 /workspace/coverage/default/28.hmac_error.1018971332 Mar 17 01:34:42 PM PDT 24 Mar 17 01:34:50 PM PDT 24 131751319 ps
T543 /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.1740259588 Mar 17 01:36:47 PM PDT 24 Mar 17 01:46:44 PM PDT 24 110631992669 ps
T544 /workspace/coverage/default/20.hmac_back_pressure.1644807202 Mar 17 01:34:01 PM PDT 24 Mar 17 01:34:18 PM PDT 24 511972435 ps
T545 /workspace/coverage/default/43.hmac_test_sha_vectors.4024305595 Mar 17 01:35:59 PM PDT 24 Mar 17 01:44:17 PM PDT 24 27002844394 ps
T546 /workspace/coverage/default/25.hmac_back_pressure.465834558 Mar 17 01:34:26 PM PDT 24 Mar 17 01:34:37 PM PDT 24 344605634 ps
T547 /workspace/coverage/default/43.hmac_burst_wr.1363547830 Mar 17 01:35:58 PM PDT 24 Mar 17 01:36:03 PM PDT 24 2154001534 ps
T548 /workspace/coverage/default/15.hmac_smoke.2628310240 Mar 17 01:33:35 PM PDT 24 Mar 17 01:33:39 PM PDT 24 185305461 ps
T549 /workspace/coverage/default/24.hmac_error.378978344 Mar 17 01:34:19 PM PDT 24 Mar 17 01:38:02 PM PDT 24 52094759018 ps
T550 /workspace/coverage/default/39.hmac_error.3428246267 Mar 17 01:35:36 PM PDT 24 Mar 17 01:36:58 PM PDT 24 6281571547 ps
T551 /workspace/coverage/default/48.hmac_datapath_stress.2779845174 Mar 17 01:36:21 PM PDT 24 Mar 17 01:38:06 PM PDT 24 3148969609 ps
T552 /workspace/coverage/default/12.hmac_test_hmac_vectors.2267045326 Mar 17 01:33:31 PM PDT 24 Mar 17 01:33:33 PM PDT 24 27349172 ps
T553 /workspace/coverage/default/6.hmac_datapath_stress.1169611079 Mar 17 01:33:11 PM PDT 24 Mar 17 01:34:25 PM PDT 24 4205608097 ps
T554 /workspace/coverage/default/16.hmac_alert_test.2675995269 Mar 17 01:33:47 PM PDT 24 Mar 17 01:33:48 PM PDT 24 36514283 ps
T555 /workspace/coverage/default/0.hmac_back_pressure.3915758049 Mar 17 01:32:51 PM PDT 24 Mar 17 01:33:41 PM PDT 24 1350170090 ps
T556 /workspace/coverage/default/47.hmac_error.1399659866 Mar 17 01:36:18 PM PDT 24 Mar 17 01:36:42 PM PDT 24 423142917 ps
T557 /workspace/coverage/default/9.hmac_test_sha_vectors.3247571393 Mar 17 01:33:24 PM PDT 24 Mar 17 01:42:23 PM PDT 24 469627403025 ps
T558 /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.2550531782 Mar 17 01:36:45 PM PDT 24 Mar 17 01:39:41 PM PDT 24 168716509178 ps
T559 /workspace/coverage/default/41.hmac_test_sha_vectors.3597520659 Mar 17 01:35:48 PM PDT 24 Mar 17 01:43:26 PM PDT 24 101384740044 ps
T560 /workspace/coverage/default/8.hmac_error.1783579204 Mar 17 01:33:18 PM PDT 24 Mar 17 01:34:03 PM PDT 24 812223210 ps
T561 /workspace/coverage/default/3.hmac_long_msg.2106432647 Mar 17 01:33:01 PM PDT 24 Mar 17 01:34:13 PM PDT 24 5464846581 ps
T78 /workspace/coverage/default/28.hmac_stress_all.3172868554 Mar 17 01:34:41 PM PDT 24 Mar 17 02:00:14 PM PDT 24 199987322755 ps
T562 /workspace/coverage/default/43.hmac_wipe_secret.2635320444 Mar 17 01:36:01 PM PDT 24 Mar 17 01:36:48 PM PDT 24 2023327681 ps
T563 /workspace/coverage/default/26.hmac_wipe_secret.1874094513 Mar 17 01:34:28 PM PDT 24 Mar 17 01:34:37 PM PDT 24 910622909 ps
T564 /workspace/coverage/default/43.hmac_error.1256519546 Mar 17 01:35:59 PM PDT 24 Mar 17 01:36:11 PM PDT 24 1195783311 ps
T565 /workspace/coverage/default/27.hmac_stress_all.2188219326 Mar 17 01:34:34 PM PDT 24 Mar 17 01:36:36 PM PDT 24 3293763144 ps
T566 /workspace/coverage/default/38.hmac_burst_wr.3260036531 Mar 17 01:35:31 PM PDT 24 Mar 17 01:35:50 PM PDT 24 1500269607 ps
T567 /workspace/coverage/default/7.hmac_test_sha_vectors.2946858483 Mar 17 01:33:28 PM PDT 24 Mar 17 01:41:36 PM PDT 24 8331928059 ps
T568 /workspace/coverage/default/42.hmac_test_sha_vectors.2573070889 Mar 17 01:35:56 PM PDT 24 Mar 17 01:42:51 PM PDT 24 7355978357 ps
T569 /workspace/coverage/default/0.hmac_alert_test.2002952144 Mar 17 01:32:55 PM PDT 24 Mar 17 01:32:56 PM PDT 24 16798107 ps
T570 /workspace/coverage/default/35.hmac_back_pressure.3215486733 Mar 17 01:35:17 PM PDT 24 Mar 17 01:35:47 PM PDT 24 2972316543 ps
T571 /workspace/coverage/default/5.hmac_long_msg.2986079835 Mar 17 01:33:11 PM PDT 24 Mar 17 01:34:40 PM PDT 24 2959770423 ps
T572 /workspace/coverage/default/19.hmac_wipe_secret.2493495673 Mar 17 01:33:59 PM PDT 24 Mar 17 01:35:13 PM PDT 24 3579148480 ps
T573 /workspace/coverage/default/7.hmac_datapath_stress.2218386714 Mar 17 01:33:19 PM PDT 24 Mar 17 01:35:22 PM PDT 24 2708566756 ps
T574 /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.2858537266 Mar 17 01:37:13 PM PDT 24 Mar 17 01:42:20 PM PDT 24 15364245541 ps
T575 /workspace/coverage/default/42.hmac_test_hmac_vectors.1089210529 Mar 17 01:35:52 PM PDT 24 Mar 17 01:35:53 PM PDT 24 29931131 ps
T576 /workspace/coverage/default/27.hmac_test_sha_vectors.1899795604 Mar 17 01:34:42 PM PDT 24 Mar 17 01:43:06 PM PDT 24 28279854619 ps
T577 /workspace/coverage/default/15.hmac_datapath_stress.1957470783 Mar 17 01:33:42 PM PDT 24 Mar 17 01:34:08 PM PDT 24 2886995467 ps
T578 /workspace/coverage/default/24.hmac_smoke.2591162063 Mar 17 01:34:19 PM PDT 24 Mar 17 01:34:21 PM PDT 24 69913175 ps
T579 /workspace/coverage/default/37.hmac_smoke.2811586441 Mar 17 01:35:26 PM PDT 24 Mar 17 01:35:29 PM PDT 24 322347406 ps
T580 /workspace/coverage/default/48.hmac_test_sha_vectors.3419320333 Mar 17 01:36:20 PM PDT 24 Mar 17 01:43:54 PM PDT 24 31921215201 ps
T581 /workspace/coverage/default/13.hmac_burst_wr.3767993312 Mar 17 01:33:37 PM PDT 24 Mar 17 01:34:14 PM PDT 24 4298391200 ps
T582 /workspace/coverage/default/32.hmac_burst_wr.2031374185 Mar 17 01:35:03 PM PDT 24 Mar 17 01:35:16 PM PDT 24 1386917458 ps
T583 /workspace/coverage/default/13.hmac_test_hmac_vectors.419314079 Mar 17 01:33:33 PM PDT 24 Mar 17 01:33:34 PM PDT 24 54438836 ps
T584 /workspace/coverage/default/33.hmac_smoke.312723736 Mar 17 01:35:07 PM PDT 24 Mar 17 01:35:14 PM PDT 24 235867176 ps
T585 /workspace/coverage/default/30.hmac_burst_wr.442560671 Mar 17 01:34:57 PM PDT 24 Mar 17 01:35:23 PM PDT 24 1024318868 ps
T586 /workspace/coverage/default/48.hmac_long_msg.2621341854 Mar 17 01:36:20 PM PDT 24 Mar 17 01:36:35 PM PDT 24 972264609 ps
T587 /workspace/coverage/default/20.hmac_test_sha_vectors.1971248020 Mar 17 01:34:08 PM PDT 24 Mar 17 01:42:56 PM PDT 24 105501243435 ps
T588 /workspace/coverage/default/11.hmac_back_pressure.3170918975 Mar 17 01:33:32 PM PDT 24 Mar 17 01:33:53 PM PDT 24 10473599018 ps
T589 /workspace/coverage/default/6.hmac_burst_wr.3101581869 Mar 17 01:33:12 PM PDT 24 Mar 17 01:33:35 PM PDT 24 1886487416 ps
T590 /workspace/coverage/default/47.hmac_long_msg.1220064618 Mar 17 01:36:15 PM PDT 24 Mar 17 01:37:26 PM PDT 24 9677066546 ps
T591 /workspace/coverage/default/15.hmac_wipe_secret.3214752089 Mar 17 01:33:42 PM PDT 24 Mar 17 01:34:49 PM PDT 24 70226921937 ps
T592 /workspace/coverage/default/46.hmac_burst_wr.3091667253 Mar 17 01:36:11 PM PDT 24 Mar 17 01:36:49 PM PDT 24 16773727149 ps
T593 /workspace/coverage/default/40.hmac_stress_all.1391994571 Mar 17 01:35:42 PM PDT 24 Mar 17 01:39:17 PM PDT 24 4873228895 ps
T594 /workspace/coverage/default/45.hmac_long_msg.4290578112 Mar 17 01:36:04 PM PDT 24 Mar 17 01:36:27 PM PDT 24 5892319188 ps
T595 /workspace/coverage/default/35.hmac_alert_test.3941670292 Mar 17 01:35:18 PM PDT 24 Mar 17 01:35:19 PM PDT 24 12865977 ps
T596 /workspace/coverage/default/18.hmac_stress_all.2649324304 Mar 17 01:33:52 PM PDT 24 Mar 17 01:34:20 PM PDT 24 5499506076 ps
T62 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1159582904 Mar 17 01:14:57 PM PDT 24 Mar 17 01:14:58 PM PDT 24 60985765 ps
T58 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.457168210 Mar 17 01:14:51 PM PDT 24 Mar 17 01:14:55 PM PDT 24 3112126852 ps
T597 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1126824905 Mar 17 01:15:14 PM PDT 24 Mar 17 01:15:14 PM PDT 24 31779084 ps
T59 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.707552854 Mar 17 01:15:02 PM PDT 24 Mar 17 01:15:07 PM PDT 24 2197469865 ps
T60 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3668748757 Mar 17 01:14:50 PM PDT 24 Mar 17 01:14:54 PM PDT 24 224137131 ps
T598 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2419320729 Mar 17 01:15:04 PM PDT 24 Mar 17 01:15:06 PM PDT 24 1896016467 ps
T599 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2839679483 Mar 17 01:15:20 PM PDT 24 Mar 17 01:15:21 PM PDT 24 64014375 ps
T600 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.222876744 Mar 17 01:14:58 PM PDT 24 Mar 17 01:15:00 PM PDT 24 26732932 ps
T601 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1027713260 Mar 17 01:15:40 PM PDT 24 Mar 17 01:15:41 PM PDT 24 25546697 ps
T87 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2114072448 Mar 17 01:14:50 PM PDT 24 Mar 17 01:14:51 PM PDT 24 62969249 ps
T602 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3130560850 Mar 17 01:15:04 PM PDT 24 Mar 17 01:15:05 PM PDT 24 38959719 ps
T603 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.215742397 Mar 17 01:14:50 PM PDT 24 Mar 17 01:14:53 PM PDT 24 34293188 ps
T97 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2150488948 Mar 17 01:14:40 PM PDT 24 Mar 17 01:14:47 PM PDT 24 740239691 ps
T604 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1882793340 Mar 17 01:15:22 PM PDT 24 Mar 17 01:15:23 PM PDT 24 101350978 ps
T61 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1338096302 Mar 17 01:15:12 PM PDT 24 Mar 17 01:15:17 PM PDT 24 1586997359 ps
T88 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2132672902 Mar 17 01:14:38 PM PDT 24 Mar 17 01:14:41 PM PDT 24 42106916 ps
T605 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2200220834 Mar 17 01:15:11 PM PDT 24 Mar 17 01:15:14 PM PDT 24 1173457272 ps
T606 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1187253187 Mar 17 01:15:21 PM PDT 24 Mar 17 01:15:22 PM PDT 24 37139936 ps
T607 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.67466753 Mar 17 01:15:20 PM PDT 24 Mar 17 01:15:22 PM PDT 24 33779623 ps
T608 /workspace/coverage/cover_reg_top/1.hmac_intr_test.4194853748 Mar 17 01:14:45 PM PDT 24 Mar 17 01:14:46 PM PDT 24 31452793 ps
T609 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2543346969 Mar 17 01:15:15 PM PDT 24 Mar 17 01:15:16 PM PDT 24 18575902 ps
T610 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2240058027 Mar 17 01:15:10 PM PDT 24 Mar 17 01:15:11 PM PDT 24 18056645 ps
T108 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1933468542 Mar 17 01:15:11 PM PDT 24 Mar 17 01:15:15 PM PDT 24 999172962 ps
T611 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.975395480 Mar 17 01:14:56 PM PDT 24 Mar 17 01:14:58 PM PDT 24 42678721 ps
T612 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2331097311 Mar 17 01:15:13 PM PDT 24 Mar 17 01:15:15 PM PDT 24 31876053 ps
T613 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3487284886 Mar 17 01:15:14 PM PDT 24 Mar 17 01:15:14 PM PDT 24 39951898 ps
T614 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.199141889 Mar 17 01:14:44 PM PDT 24 Mar 17 01:14:47 PM PDT 24 300046340 ps
T615 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.525633706 Mar 17 01:14:54 PM PDT 24 Mar 17 01:14:57 PM PDT 24 69053065 ps
T616 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3552237870 Mar 17 01:15:26 PM PDT 24 Mar 17 01:15:26 PM PDT 24 20512774 ps
T617 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.909808475 Mar 17 01:15:20 PM PDT 24 Mar 17 01:15:21 PM PDT 24 238996374 ps
T618 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2948056182 Mar 17 01:14:51 PM PDT 24 Mar 17 01:14:55 PM PDT 24 207639917 ps
T619 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1294951307 Mar 17 01:15:14 PM PDT 24 Mar 17 01:15:15 PM PDT 24 56937936 ps
T620 /workspace/coverage/cover_reg_top/18.hmac_intr_test.4270504526 Mar 17 01:15:20 PM PDT 24 Mar 17 01:15:21 PM PDT 24 54249260 ps
T621 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3137466334 Mar 17 01:14:45 PM PDT 24 Mar 17 01:14:48 PM PDT 24 110848064 ps
T622 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2643534463 Mar 17 01:14:45 PM PDT 24 Mar 17 01:14:46 PM PDT 24 23230560 ps
T623 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2301740129 Mar 17 01:15:11 PM PDT 24 Mar 17 01:15:12 PM PDT 24 190275619 ps
T624 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3567009914 Mar 17 01:14:51 PM PDT 24 Mar 17 01:14:54 PM PDT 24 1303127402 ps
T625 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2384294776 Mar 17 01:15:03 PM PDT 24 Mar 17 01:15:05 PM PDT 24 108036024 ps
T626 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1329248779 Mar 17 01:14:50 PM PDT 24 Mar 17 01:14:54 PM PDT 24 808527594 ps
T89 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.503437052 Mar 17 01:14:52 PM PDT 24 Mar 17 01:14:53 PM PDT 24 29634524 ps
T63 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2850426305 Mar 17 01:14:57 PM PDT 24 Mar 17 01:15:00 PM PDT 24 452385011 ps
T627 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.562739114 Mar 17 01:14:57 PM PDT 24 Mar 17 01:15:00 PM PDT 24 379027157 ps
T628 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.506150317 Mar 17 01:14:45 PM PDT 24 Mar 17 01:14:46 PM PDT 24 21314780 ps
T629 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3234481336 Mar 17 01:15:15 PM PDT 24 Mar 17 01:15:16 PM PDT 24 88275043 ps
T630 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1423541502 Mar 17 01:14:58 PM PDT 24 Mar 17 01:15:02 PM PDT 24 362836517 ps
T106 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1177728521 Mar 17 01:15:07 PM PDT 24 Mar 17 01:15:10 PM PDT 24 879775578 ps
T631 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2248477325 Mar 17 01:15:23 PM PDT 24 Mar 17 01:15:26 PM PDT 24 186709336 ps
T632 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1818709765 Mar 17 01:14:45 PM PDT 24 Mar 17 01:14:46 PM PDT 24 14569290 ps
T633 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.793024551 Mar 17 01:15:05 PM PDT 24 Mar 17 01:15:07 PM PDT 24 88643994 ps
T105 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3448531542 Mar 17 01:15:07 PM PDT 24 Mar 17 01:15:11 PM PDT 24 493913000 ps
T634 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3122812717 Mar 17 01:14:50 PM PDT 24 Mar 17 01:15:01 PM PDT 24 2630956564 ps
T635 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1262782488 Mar 17 01:14:47 PM PDT 24 Mar 17 01:14:48 PM PDT 24 16801115 ps
T636 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3327829684 Mar 17 01:14:57 PM PDT 24 Mar 17 01:14:57 PM PDT 24 111541290 ps
T637 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1043013035 Mar 17 01:15:26 PM PDT 24 Mar 17 01:15:27 PM PDT 24 16806101 ps
T638 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1258931761 Mar 17 01:15:03 PM PDT 24 Mar 17 01:15:04 PM PDT 24 12447196 ps
T639 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3464129812 Mar 17 01:15:15 PM PDT 24 Mar 17 01:15:16 PM PDT 24 87596077 ps
T640 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3362806561 Mar 17 01:14:51 PM PDT 24 Mar 17 01:14:51 PM PDT 24 174362775 ps
T641 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2241975625 Mar 17 01:15:15 PM PDT 24 Mar 17 01:15:18 PM PDT 24 74179344 ps
T642 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3907624125 Mar 17 01:14:49 PM PDT 24 Mar 17 01:14:51 PM PDT 24 177051410 ps
T643 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.457127568 Mar 17 01:15:09 PM PDT 24 Mar 17 01:15:11 PM PDT 24 249230616 ps
T644 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1520032298 Mar 17 01:15:32 PM PDT 24 Mar 17 01:15:33 PM PDT 24 62622948 ps
T645 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3244527188 Mar 17 01:15:22 PM PDT 24 Mar 17 01:15:22 PM PDT 24 58525887 ps
T90 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1105049185 Mar 17 01:15:08 PM PDT 24 Mar 17 01:15:08 PM PDT 24 16298251 ps
T646 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1780981627 Mar 17 01:14:51 PM PDT 24 Mar 17 01:14:52 PM PDT 24 45870264 ps
T91 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2068364021 Mar 17 01:15:03 PM PDT 24 Mar 17 01:15:04 PM PDT 24 32544541 ps
T107 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1421829308 Mar 17 01:14:57 PM PDT 24 Mar 17 01:15:02 PM PDT 24 232762751 ps
T647 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3956011324 Mar 17 01:15:21 PM PDT 24 Mar 17 01:15:22 PM PDT 24 35096914 ps
T648 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2239397825 Mar 17 01:15:24 PM PDT 24 Mar 17 01:15:25 PM PDT 24 56276603 ps
T649 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1067574801 Mar 17 01:15:21 PM PDT 24 Mar 17 01:15:22 PM PDT 24 57957594 ps
T650 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1050204762 Mar 17 01:15:25 PM PDT 24 Mar 17 01:15:25 PM PDT 24 48857947 ps
T651 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1217855423 Mar 17 01:14:57 PM PDT 24 Mar 17 01:14:58 PM PDT 24 60307685 ps
T652 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1982692667 Mar 17 01:15:28 PM PDT 24 Mar 17 01:15:29 PM PDT 24 13456879 ps
T653 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2847167453 Mar 17 01:14:57 PM PDT 24 Mar 17 01:14:58 PM PDT 24 69948480 ps
T92 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.115217611 Mar 17 01:14:55 PM PDT 24 Mar 17 01:14:56 PM PDT 24 75428386 ps
T654 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2884265728 Mar 17 01:15:17 PM PDT 24 Mar 17 01:15:22 PM PDT 24 447506090 ps
T655 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3941109718 Mar 17 01:14:51 PM PDT 24 Mar 17 01:14:58 PM PDT 24 403728642 ps
T656 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1689194544 Mar 17 01:15:25 PM PDT 24 Mar 17 01:15:26 PM PDT 24 13600190 ps
T93 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1833213493 Mar 17 01:14:53 PM PDT 24 Mar 17 01:14:56 PM PDT 24 739300501 ps
T657 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2115627618 Mar 17 01:15:09 PM PDT 24 Mar 17 01:15:11 PM PDT 24 316478153 ps
T658 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2445690703 Mar 17 01:15:21 PM PDT 24 Mar 17 01:29:51 PM PDT 24 236238622064 ps
T659 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2059938015 Mar 17 01:15:21 PM PDT 24 Mar 17 01:15:22 PM PDT 24 14937434 ps
T660 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1108347072 Mar 17 01:15:25 PM PDT 24 Mar 17 01:15:26 PM PDT 24 37772167 ps
T661 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3356901057 Mar 17 01:15:22 PM PDT 24 Mar 17 01:15:23 PM PDT 24 55389829 ps
T662 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1942006395 Mar 17 01:15:14 PM PDT 24 Mar 17 01:15:17 PM PDT 24 1244646063 ps
T663 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1003894627 Mar 17 01:14:38 PM PDT 24 Mar 17 01:14:40 PM PDT 24 32108538 ps
T664 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.620419727 Mar 17 01:15:10 PM PDT 24 Mar 17 01:15:12 PM PDT 24 195857401 ps
T665 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2870380257 Mar 17 01:15:14 PM PDT 24 Mar 17 01:15:15 PM PDT 24 40931463 ps
T109 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4183829816 Mar 17 01:15:14 PM PDT 24 Mar 17 01:15:17 PM PDT 24 1119662675 ps
T666 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1600482690 Mar 17 01:15:13 PM PDT 24 Mar 17 01:15:18 PM PDT 24 450076442 ps
T667 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2377656251 Mar 17 01:15:25 PM PDT 24 Mar 17 01:15:26 PM PDT 24 35166028 ps
T668 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1867383647 Mar 17 01:15:32 PM PDT 24 Mar 17 01:15:33 PM PDT 24 13575468 ps
T669 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.28262161 Mar 17 01:15:10 PM PDT 24 Mar 17 01:15:13 PM PDT 24 83997182 ps
T670 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1670795166 Mar 17 01:15:12 PM PDT 24 Mar 17 01:15:13 PM PDT 24 32068534 ps
T671 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2946307659 Mar 17 01:15:25 PM PDT 24 Mar 17 01:15:25 PM PDT 24 80956532 ps
T672 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.415487193 Mar 17 01:14:47 PM PDT 24 Mar 17 01:15:03 PM PDT 24 2147365984 ps
T94 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.569230577 Mar 17 01:14:39 PM PDT 24 Mar 17 01:14:42 PM PDT 24 70829655 ps
T673 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3466477244 Mar 17 01:14:38 PM PDT 24 Mar 17 01:14:41 PM PDT 24 145022997 ps
T674 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1697537481 Mar 17 01:14:43 PM PDT 24 Mar 17 01:14:47 PM PDT 24 503802362 ps
T675 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2368430684 Mar 17 01:15:18 PM PDT 24 Mar 17 01:15:21 PM PDT 24 376628997 ps
T676 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.253410483 Mar 17 01:15:18 PM PDT 24 Mar 17 01:15:19 PM PDT 24 50279166 ps
T677 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3898636727 Mar 17 01:15:32 PM PDT 24 Mar 17 01:15:34 PM PDT 24 37044293 ps
T678 /workspace/coverage/cover_reg_top/48.hmac_intr_test.90603673 Mar 17 01:15:26 PM PDT 24 Mar 17 01:15:27 PM PDT 24 14484333 ps
T679 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2940620069 Mar 17 01:15:13 PM PDT 24 Mar 17 01:15:15 PM PDT 24 182551560 ps
T680 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.275581045 Mar 17 01:15:16 PM PDT 24 Mar 17 01:15:18 PM PDT 24 85261266 ps
T681 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3180777570 Mar 17 01:15:12 PM PDT 24 Mar 17 01:15:13 PM PDT 24 20455036 ps
T95 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1449634921 Mar 17 01:14:44 PM PDT 24 Mar 17 01:14:51 PM PDT 24 366964016 ps
T682 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.142980208 Mar 17 01:15:09 PM PDT 24 Mar 17 01:15:11 PM PDT 24 100201601 ps
T683 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3441976140 Mar 17 01:15:15 PM PDT 24 Mar 17 01:15:18 PM PDT 24 314062961 ps
T684 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.299117464 Mar 17 01:15:08 PM PDT 24 Mar 17 01:15:09 PM PDT 24 23811883 ps
T685 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2902139194 Mar 17 01:14:40 PM PDT 24 Mar 17 01:14:44 PM PDT 24 2158665137 ps
T686 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1660583286 Mar 17 01:15:24 PM PDT 24 Mar 17 01:15:25 PM PDT 24 23599466 ps
T687 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3633059632 Mar 17 01:15:12 PM PDT 24 Mar 17 01:15:14 PM PDT 24 118695394 ps
T688 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.132353677 Mar 17 01:14:48 PM PDT 24 Mar 17 01:14:49 PM PDT 24 167436733 ps
T689 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3777047206 Mar 17 01:15:08 PM PDT 24 Mar 17 01:15:10 PM PDT 24 29043705 ps
T96 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1094125758 Mar 17 01:15:32 PM PDT 24 Mar 17 01:15:33 PM PDT 24 20092486 ps
T690 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2544399677 Mar 17 01:14:58 PM PDT 24 Mar 17 01:14:59 PM PDT 24 55448105 ps
T691 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3889766325 Mar 17 01:14:58 PM PDT 24 Mar 17 01:14:59 PM PDT 24 14102871 ps
T692 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3241802185 Mar 17 01:15:03 PM PDT 24 Mar 17 01:15:08 PM PDT 24 577324904 ps
T693 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3803357185 Mar 17 01:14:51 PM PDT 24 Mar 17 01:14:53 PM PDT 24 48096069 ps
T694 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2905826882 Mar 17 01:15:32 PM PDT 24 Mar 17 01:15:33 PM PDT 24 36070111 ps
T695 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3697986114 Mar 17 01:14:56 PM PDT 24 Mar 17 01:14:58 PM PDT 24 77773178 ps
T98 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1505600083 Mar 17 01:15:11 PM PDT 24 Mar 17 01:15:12 PM PDT 24 45112976 ps
T696 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.497991919 Mar 17 01:15:22 PM PDT 24 Mar 17 01:15:24 PM PDT 24 250827434 ps
T697 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3947020303 Mar 17 01:15:09 PM PDT 24 Mar 17 01:15:11 PM PDT 24 183929208 ps
T698 /workspace/coverage/cover_reg_top/9.hmac_intr_test.54150720 Mar 17 01:15:05 PM PDT 24 Mar 17 01:15:06 PM PDT 24 29785183 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1461783221 Mar 17 01:14:49 PM PDT 24 Mar 17 01:14:50 PM PDT 24 19735280 ps
T699 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1971505301 Mar 17 01:14:53 PM PDT 24 Mar 17 01:14:55 PM PDT 24 436884253 ps
T700 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.182535844 Mar 17 01:14:55 PM PDT 24 Mar 17 01:15:06 PM PDT 24 5084492251 ps
T701 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3274203361 Mar 17 01:15:24 PM PDT 24 Mar 17 01:15:25 PM PDT 24 16251927 ps
T702 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3676586544 Mar 17 01:14:38 PM PDT 24 Mar 17 01:14:46 PM PDT 24 117205955 ps
T703 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4110243665 Mar 17 01:15:04 PM PDT 24 Mar 17 01:15:04 PM PDT 24 126885690 ps
T704 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2299159956 Mar 17 01:15:20 PM PDT 24 Mar 17 01:15:21 PM PDT 24 18253555 ps
T705 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4074743208 Mar 17 01:15:12 PM PDT 24 Mar 17 01:15:14 PM PDT 24 793381281 ps
T706 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1540058813 Mar 17 01:15:21 PM PDT 24 Mar 17 01:15:23 PM PDT 24 123196791 ps
T707 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4201619790 Mar 17 01:15:02 PM PDT 24 Mar 17 01:15:05 PM PDT 24 486186214 ps
T708 /workspace/coverage/cover_reg_top/42.hmac_intr_test.4135609708 Mar 17 01:15:20 PM PDT 24 Mar 17 01:15:21 PM PDT 24 53341706 ps
T100 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3312526163 Mar 17 01:15:16 PM PDT 24 Mar 17 01:15:17 PM PDT 24 23639090 ps
T709 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3258840699 Mar 17 01:15:02 PM PDT 24 Mar 17 01:15:03 PM PDT 24 52448404 ps
T710 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1754549988 Mar 17 01:15:08 PM PDT 24 Mar 17 01:15:12 PM PDT 24 327597118 ps
T711 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1258693089 Mar 17 01:14:57 PM PDT 24 Mar 17 01:14:58 PM PDT 24 154142076 ps
T712 /workspace/coverage/cover_reg_top/40.hmac_intr_test.785672428 Mar 17 01:15:21 PM PDT 24 Mar 17 01:15:22 PM PDT 24 11299267 ps
T713 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.394607338 Mar 17 01:14:51 PM PDT 24 Mar 17 01:14:57 PM PDT 24 1443208000 ps
T714 /workspace/coverage/cover_reg_top/24.hmac_intr_test.741240564 Mar 17 01:15:23 PM PDT 24 Mar 17 01:15:25 PM PDT 24 11692705 ps
T715 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2014590028 Mar 17 01:15:14 PM PDT 24 Mar 17 01:15:17 PM PDT 24 134594621 ps
T101 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2780231533 Mar 17 01:15:17 PM PDT 24 Mar 17 01:15:18 PM PDT 24 34931479 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.220825285 Mar 17 01:14:52 PM PDT 24 Mar 17 01:14:53 PM PDT 24 139578863 ps
T716 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3617585570 Mar 17 01:14:58 PM PDT 24 Mar 17 01:15:01 PM PDT 24 181894649 ps
T717 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3107565640 Mar 17 01:15:23 PM PDT 24 Mar 17 01:15:24 PM PDT 24 29013854 ps
T718 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.215941413 Mar 17 01:14:52 PM PDT 24 Mar 17 01:14:54 PM PDT 24 643009961 ps
T719 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1055732739 Mar 17 01:14:39 PM PDT 24 Mar 17 01:29:41 PM PDT 24 88883824165 ps
T720 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2407026528 Mar 17 01:15:25 PM PDT 24 Mar 17 01:15:26 PM PDT 24 86564602 ps
T721 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.321484952 Mar 17 01:14:57 PM PDT 24 Mar 17 01:14:59 PM PDT 24 2188470850 ps
T722 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3942312783 Mar 17 01:15:26 PM PDT 24 Mar 17 01:15:27 PM PDT 24 23094432 ps
T723 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2494438039 Mar 17 01:15:01 PM PDT 24 Mar 17 01:15:05 PM PDT 24 501482319 ps
T724 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2597654433 Mar 17 01:15:18 PM PDT 24 Mar 17 01:15:22 PM PDT 24 71597020 ps
T725 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.679922055 Mar 17 01:15:03 PM PDT 24 Mar 17 01:15:04 PM PDT 24 300168264 ps
T726 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2337675873 Mar 17 01:15:20 PM PDT 24 Mar 17 01:15:25 PM PDT 24 532078064 ps
T727 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3997116258 Mar 17 01:15:14 PM PDT 24 Mar 17 01:15:18 PM PDT 24 443840921 ps
T728 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2495013340 Mar 17 01:15:23 PM PDT 24 Mar 17 01:15:23 PM PDT 24 63243626 ps
T729 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3602094073 Mar 17 01:15:20 PM PDT 24 Mar 17 01:15:22 PM PDT 24 210779829 ps
T730 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2765275427 Mar 17 01:14:51 PM PDT 24 Mar 17 01:14:51 PM PDT 24 25646935 ps
T731 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2452223097 Mar 17 01:15:03 PM PDT 24 Mar 17 01:15:05 PM PDT 24 243613035 ps
T732 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.60051284 Mar 17 01:15:09 PM PDT 24 Mar 17 01:15:12 PM PDT 24 52815696 ps
T733 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.826528884 Mar 17 01:14:46 PM PDT 24 Mar 17 01:14:47 PM PDT 24 16104633 ps
T734 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1861339430 Mar 17 01:15:07 PM PDT 24 Mar 17 01:15:08 PM PDT 24 105859403 ps

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.4064050643
Short name T6
Test name
Test status
Simulation time 22537610568 ps
CPU time 480.94 seconds
Started Mar 17 01:37:29 PM PDT 24
Finished Mar 17 01:45:30 PM PDT 24
Peak memory 241564 kb
Host smart-d3a9340d-af5c-4407-9661-c3da4233d4d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064050643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.4064050643
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.1776653530
Short name T9
Test name
Test status
Simulation time 81610827291 ps
CPU time 2906.58 seconds
Started Mar 17 01:37:30 PM PDT 24
Finished Mar 17 02:25:57 PM PDT 24
Peak memory 233336 kb
Host smart-faed4a2b-ab14-4eb4-b352-eb0e42070064
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776653530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.1776653530
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.10701899
Short name T28
Test name
Test status
Simulation time 53547397 ps
CPU time 0.88 seconds
Started Mar 17 01:32:55 PM PDT 24
Finished Mar 17 01:32:56 PM PDT 24
Peak memory 218860 kb
Host smart-1f094729-3f20-42af-9da2-dd8845336b16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10701899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.10701899
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.4103957118
Short name T4
Test name
Test status
Simulation time 4636469704 ps
CPU time 64.97 seconds
Started Mar 17 01:32:55 PM PDT 24
Finished Mar 17 01:34:00 PM PDT 24
Peak memory 200480 kb
Host smart-341e153b-1609-4469-bb9a-95ea3a455377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103957118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.4103957118
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.707552854
Short name T59
Test name
Test status
Simulation time 2197469865 ps
CPU time 4.39 seconds
Started Mar 17 01:15:02 PM PDT 24
Finished Mar 17 01:15:07 PM PDT 24
Peak memory 200128 kb
Host smart-2a479d49-8d2d-4e62-a0ea-ea31e8a20c76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707552854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.707552854
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.569230577
Short name T94
Test name
Test status
Simulation time 70829655 ps
CPU time 0.7 seconds
Started Mar 17 01:14:39 PM PDT 24
Finished Mar 17 01:14:42 PM PDT 24
Peak memory 198076 kb
Host smart-c38e60cf-1db8-49bc-b1af-19ee47d0b65b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569230577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.569230577
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/5.hmac_error.1486939708
Short name T15
Test name
Test status
Simulation time 3389915430 ps
CPU time 88.54 seconds
Started Mar 17 01:33:10 PM PDT 24
Finished Mar 17 01:34:39 PM PDT 24
Peak memory 200536 kb
Host smart-80f79996-5563-4c9d-975f-44be9e254819
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486939708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1486939708
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3667770708
Short name T19
Test name
Test status
Simulation time 33537286 ps
CPU time 0.64 seconds
Started Mar 17 01:34:09 PM PDT 24
Finished Mar 17 01:34:10 PM PDT 24
Peak memory 195912 kb
Host smart-eb4ccb01-4ef4-4f26-9436-a90ac2fac619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667770708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3667770708
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3668748757
Short name T60
Test name
Test status
Simulation time 224137131 ps
CPU time 4.03 seconds
Started Mar 17 01:14:50 PM PDT 24
Finished Mar 17 01:14:54 PM PDT 24
Peak memory 200040 kb
Host smart-bdb6677b-f210-4d97-b352-6adf8a1ff26f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668748757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3668748757
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all.4043531277
Short name T48
Test name
Test status
Simulation time 83789530507 ps
CPU time 464.39 seconds
Started Mar 17 01:32:53 PM PDT 24
Finished Mar 17 01:40:38 PM PDT 24
Peak memory 240964 kb
Host smart-8c62073d-e182-4eec-aa5d-9d2e3145da7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043531277 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.4043531277
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1933468542
Short name T108
Test name
Test status
Simulation time 999172962 ps
CPU time 4.54 seconds
Started Mar 17 01:15:11 PM PDT 24
Finished Mar 17 01:15:15 PM PDT 24
Peak memory 200028 kb
Host smart-753b6ea1-3a77-43bd-9867-a21dac7cef46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933468542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1933468542
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3159233402
Short name T43
Test name
Test status
Simulation time 7472176626 ps
CPU time 345.2 seconds
Started Mar 17 01:34:58 PM PDT 24
Finished Mar 17 01:40:44 PM PDT 24
Peak memory 200456 kb
Host smart-0bed7bec-0b59-4d03-8e43-c222f2aeddfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159233402 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3159233402
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1338096302
Short name T61
Test name
Test status
Simulation time 1586997359 ps
CPU time 4.21 seconds
Started Mar 17 01:15:12 PM PDT 24
Finished Mar 17 01:15:17 PM PDT 24
Peak memory 200032 kb
Host smart-cfe51578-704b-44ba-90e4-c07e8e7d9706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338096302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1338096302
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2850426305
Short name T63
Test name
Test status
Simulation time 452385011 ps
CPU time 2.8 seconds
Started Mar 17 01:14:57 PM PDT 24
Finished Mar 17 01:15:00 PM PDT 24
Peak memory 200012 kb
Host smart-07669be7-79a4-443d-acf5-3aa9a74f39dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850426305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2850426305
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3676586544
Short name T702
Test name
Test status
Simulation time 117205955 ps
CPU time 5.63 seconds
Started Mar 17 01:14:38 PM PDT 24
Finished Mar 17 01:14:46 PM PDT 24
Peak memory 198852 kb
Host smart-4a6f1155-2b96-463e-b1ec-b5f288bc4100
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676586544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3676586544
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2150488948
Short name T97
Test name
Test status
Simulation time 740239691 ps
CPU time 5.97 seconds
Started Mar 17 01:14:40 PM PDT 24
Finished Mar 17 01:14:47 PM PDT 24
Peak memory 199916 kb
Host smart-f4a11beb-be00-4441-9d8b-dc64bdebd805
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150488948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2150488948
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1055732739
Short name T719
Test name
Test status
Simulation time 88883824165 ps
CPU time 899.84 seconds
Started Mar 17 01:14:39 PM PDT 24
Finished Mar 17 01:29:41 PM PDT 24
Peak memory 216608 kb
Host smart-575c1d12-387e-453d-a799-c08c854c44f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055732739 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1055732739
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2132672902
Short name T88
Test name
Test status
Simulation time 42106916 ps
CPU time 0.67 seconds
Started Mar 17 01:14:38 PM PDT 24
Finished Mar 17 01:14:41 PM PDT 24
Peak memory 197796 kb
Host smart-080c5488-3daa-478a-a402-5d4bd24e64ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132672902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2132672902
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1003894627
Short name T663
Test name
Test status
Simulation time 32108538 ps
CPU time 0.57 seconds
Started Mar 17 01:14:38 PM PDT 24
Finished Mar 17 01:14:40 PM PDT 24
Peak memory 194820 kb
Host smart-33c24152-59dd-4114-b41b-65871ed676ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003894627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1003894627
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3466477244
Short name T673
Test name
Test status
Simulation time 145022997 ps
CPU time 1.05 seconds
Started Mar 17 01:14:38 PM PDT 24
Finished Mar 17 01:14:41 PM PDT 24
Peak memory 198216 kb
Host smart-7969d3d3-b10c-48d7-8cfb-3b46cd5f2cca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466477244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3466477244
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1697537481
Short name T674
Test name
Test status
Simulation time 503802362 ps
CPU time 3.5 seconds
Started Mar 17 01:14:43 PM PDT 24
Finished Mar 17 01:14:47 PM PDT 24
Peak memory 199992 kb
Host smart-380a3019-3d26-4bdf-8666-04acb4a735d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697537481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1697537481
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2902139194
Short name T685
Test name
Test status
Simulation time 2158665137 ps
CPU time 3.04 seconds
Started Mar 17 01:14:40 PM PDT 24
Finished Mar 17 01:14:44 PM PDT 24
Peak memory 200124 kb
Host smart-fd04e0ba-e211-4023-98fa-a9e94a891ede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902139194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2902139194
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1449634921
Short name T95
Test name
Test status
Simulation time 366964016 ps
CPU time 6.26 seconds
Started Mar 17 01:14:44 PM PDT 24
Finished Mar 17 01:14:51 PM PDT 24
Peak memory 199488 kb
Host smart-279ba4d1-4eda-4a5f-993f-11ee941d35bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449634921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1449634921
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.415487193
Short name T672
Test name
Test status
Simulation time 2147365984 ps
CPU time 15.27 seconds
Started Mar 17 01:14:47 PM PDT 24
Finished Mar 17 01:15:03 PM PDT 24
Peak memory 198852 kb
Host smart-4dea4011-3622-4678-bacc-9b25489acd00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415487193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.415487193
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.506150317
Short name T628
Test name
Test status
Simulation time 21314780 ps
CPU time 0.74 seconds
Started Mar 17 01:14:45 PM PDT 24
Finished Mar 17 01:14:46 PM PDT 24
Peak memory 197568 kb
Host smart-bc7e8aee-8763-4f29-9d44-c2f06c10fd56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506150317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.506150317
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.132353677
Short name T688
Test name
Test status
Simulation time 167436733 ps
CPU time 1.21 seconds
Started Mar 17 01:14:48 PM PDT 24
Finished Mar 17 01:14:49 PM PDT 24
Peak memory 199856 kb
Host smart-2155db08-c5c3-474e-80ee-6252aab0af6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132353677 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.132353677
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1461783221
Short name T99
Test name
Test status
Simulation time 19735280 ps
CPU time 0.93 seconds
Started Mar 17 01:14:49 PM PDT 24
Finished Mar 17 01:14:50 PM PDT 24
Peak memory 199408 kb
Host smart-3410727e-090c-4166-ac75-e847957e2758
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461783221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1461783221
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4194853748
Short name T608
Test name
Test status
Simulation time 31452793 ps
CPU time 0.61 seconds
Started Mar 17 01:14:45 PM PDT 24
Finished Mar 17 01:14:46 PM PDT 24
Peak memory 194604 kb
Host smart-121ec544-c602-4027-9986-9797beffa158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194853748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4194853748
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2643534463
Short name T622
Test name
Test status
Simulation time 23230560 ps
CPU time 1.12 seconds
Started Mar 17 01:14:45 PM PDT 24
Finished Mar 17 01:14:46 PM PDT 24
Peak memory 199448 kb
Host smart-6fed2ede-514d-48c8-aad0-18ce0c2d8343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643534463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2643534463
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.199141889
Short name T614
Test name
Test status
Simulation time 300046340 ps
CPU time 2.87 seconds
Started Mar 17 01:14:44 PM PDT 24
Finished Mar 17 01:14:47 PM PDT 24
Peak memory 200076 kb
Host smart-c6fc3b9d-db36-4fe2-bd20-9aa7783e759f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199141889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.199141889
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3633059632
Short name T687
Test name
Test status
Simulation time 118695394 ps
CPU time 2.12 seconds
Started Mar 17 01:15:12 PM PDT 24
Finished Mar 17 01:15:14 PM PDT 24
Peak memory 200120 kb
Host smart-5d494fb5-c2bf-4eef-ab5a-b6ba1aaffadf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633059632 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3633059632
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2068364021
Short name T91
Test name
Test status
Simulation time 32544541 ps
CPU time 1 seconds
Started Mar 17 01:15:03 PM PDT 24
Finished Mar 17 01:15:04 PM PDT 24
Peak memory 199572 kb
Host smart-0e95854c-a7d8-4015-8857-cc0ca1d3fc61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068364021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2068364021
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1258931761
Short name T638
Test name
Test status
Simulation time 12447196 ps
CPU time 0.59 seconds
Started Mar 17 01:15:03 PM PDT 24
Finished Mar 17 01:15:04 PM PDT 24
Peak memory 194864 kb
Host smart-dff232f2-c80d-4192-b871-d19b4ca19091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258931761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1258931761
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.620419727
Short name T664
Test name
Test status
Simulation time 195857401 ps
CPU time 2.17 seconds
Started Mar 17 01:15:10 PM PDT 24
Finished Mar 17 01:15:12 PM PDT 24
Peak memory 199868 kb
Host smart-069b71c8-45e8-4b2e-8905-597144461a43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620419727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.620419727
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2494438039
Short name T723
Test name
Test status
Simulation time 501482319 ps
CPU time 3.25 seconds
Started Mar 17 01:15:01 PM PDT 24
Finished Mar 17 01:15:05 PM PDT 24
Peak memory 200080 kb
Host smart-e577e18a-ef3c-4184-bc47-7d8086d85024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494438039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2494438039
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3448531542
Short name T105
Test name
Test status
Simulation time 493913000 ps
CPU time 3.88 seconds
Started Mar 17 01:15:07 PM PDT 24
Finished Mar 17 01:15:11 PM PDT 24
Peak memory 200024 kb
Host smart-93cd005e-02d0-447c-9833-7e0f8d9ed146
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448531542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3448531542
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.60051284
Short name T732
Test name
Test status
Simulation time 52815696 ps
CPU time 3.24 seconds
Started Mar 17 01:15:09 PM PDT 24
Finished Mar 17 01:15:12 PM PDT 24
Peak memory 208316 kb
Host smart-8f43bcfa-7440-44d6-94b0-3c6ed8508cf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60051284 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.60051284
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2301740129
Short name T623
Test name
Test status
Simulation time 190275619 ps
CPU time 0.82 seconds
Started Mar 17 01:15:11 PM PDT 24
Finished Mar 17 01:15:12 PM PDT 24
Peak memory 199160 kb
Host smart-0910144f-6186-4948-9139-6d25ee06f7e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301740129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2301740129
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1670795166
Short name T670
Test name
Test status
Simulation time 32068534 ps
CPU time 0.6 seconds
Started Mar 17 01:15:12 PM PDT 24
Finished Mar 17 01:15:13 PM PDT 24
Peak memory 194640 kb
Host smart-95addd9f-af62-4605-a20f-d006bf656221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670795166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1670795166
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.299117464
Short name T684
Test name
Test status
Simulation time 23811883 ps
CPU time 1.15 seconds
Started Mar 17 01:15:08 PM PDT 24
Finished Mar 17 01:15:09 PM PDT 24
Peak memory 199692 kb
Host smart-b727ed06-4b72-46c5-b87a-ac06c1793d10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299117464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.299117464
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2200220834
Short name T605
Test name
Test status
Simulation time 1173457272 ps
CPU time 2.33 seconds
Started Mar 17 01:15:11 PM PDT 24
Finished Mar 17 01:15:14 PM PDT 24
Peak memory 200028 kb
Host smart-c93ec646-d877-4c73-8af0-79faaa7de76e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200220834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2200220834
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2884265728
Short name T654
Test name
Test status
Simulation time 447506090 ps
CPU time 4.28 seconds
Started Mar 17 01:15:17 PM PDT 24
Finished Mar 17 01:15:22 PM PDT 24
Peak memory 200076 kb
Host smart-1fa128b3-01f7-4c39-b5dd-654f26962928
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884265728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2884265728
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3777047206
Short name T689
Test name
Test status
Simulation time 29043705 ps
CPU time 1.87 seconds
Started Mar 17 01:15:08 PM PDT 24
Finished Mar 17 01:15:10 PM PDT 24
Peak memory 200076 kb
Host smart-c275afc9-866d-4f0d-84c4-a3ad18673cdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777047206 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3777047206
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1294951307
Short name T619
Test name
Test status
Simulation time 56937936 ps
CPU time 0.69 seconds
Started Mar 17 01:15:14 PM PDT 24
Finished Mar 17 01:15:15 PM PDT 24
Peak memory 197576 kb
Host smart-bb2ba575-e805-4b71-b82c-f135353b7e49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294951307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1294951307
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3180777570
Short name T681
Test name
Test status
Simulation time 20455036 ps
CPU time 0.58 seconds
Started Mar 17 01:15:12 PM PDT 24
Finished Mar 17 01:15:13 PM PDT 24
Peak memory 194748 kb
Host smart-158d9a66-b9d3-4701-b5bf-5d8392807294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180777570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3180777570
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.457127568
Short name T643
Test name
Test status
Simulation time 249230616 ps
CPU time 1.81 seconds
Started Mar 17 01:15:09 PM PDT 24
Finished Mar 17 01:15:11 PM PDT 24
Peak memory 199832 kb
Host smart-ece2bdeb-8b98-43d5-b4f6-0bd9e7c9c487
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457127568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.457127568
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3947020303
Short name T697
Test name
Test status
Simulation time 183929208 ps
CPU time 1.35 seconds
Started Mar 17 01:15:09 PM PDT 24
Finished Mar 17 01:15:11 PM PDT 24
Peak memory 200064 kb
Host smart-163dd532-36a9-46b4-952f-9247a38ce277
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947020303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3947020303
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.28262161
Short name T669
Test name
Test status
Simulation time 83997182 ps
CPU time 2.52 seconds
Started Mar 17 01:15:10 PM PDT 24
Finished Mar 17 01:15:13 PM PDT 24
Peak memory 200056 kb
Host smart-d9574a64-f1f9-4caa-bcdd-8d7b8e810f4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28262161 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.28262161
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1505600083
Short name T98
Test name
Test status
Simulation time 45112976 ps
CPU time 0.99 seconds
Started Mar 17 01:15:11 PM PDT 24
Finished Mar 17 01:15:12 PM PDT 24
Peak memory 199448 kb
Host smart-22eabf8c-ba3e-4cd3-80c4-5fabe5cf3045
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505600083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1505600083
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2240058027
Short name T610
Test name
Test status
Simulation time 18056645 ps
CPU time 0.61 seconds
Started Mar 17 01:15:10 PM PDT 24
Finished Mar 17 01:15:11 PM PDT 24
Peak memory 194648 kb
Host smart-65a7d8e4-d86f-4cc6-b164-a44402931f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240058027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2240058027
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.142980208
Short name T682
Test name
Test status
Simulation time 100201601 ps
CPU time 1.69 seconds
Started Mar 17 01:15:09 PM PDT 24
Finished Mar 17 01:15:11 PM PDT 24
Peak memory 199636 kb
Host smart-a6e0cbf6-7a0b-4863-b4f0-f560170f52da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142980208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.142980208
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1754549988
Short name T710
Test name
Test status
Simulation time 327597118 ps
CPU time 4.09 seconds
Started Mar 17 01:15:08 PM PDT 24
Finished Mar 17 01:15:12 PM PDT 24
Peak memory 200084 kb
Host smart-2eb24df6-763b-4f46-9e5e-f8a8e9031680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754549988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1754549988
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1600482690
Short name T666
Test name
Test status
Simulation time 450076442 ps
CPU time 4.19 seconds
Started Mar 17 01:15:13 PM PDT 24
Finished Mar 17 01:15:18 PM PDT 24
Peak memory 200032 kb
Host smart-f067fea1-2714-4e32-83ac-509da9be70a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600482690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1600482690
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2331097311
Short name T612
Test name
Test status
Simulation time 31876053 ps
CPU time 1.24 seconds
Started Mar 17 01:15:13 PM PDT 24
Finished Mar 17 01:15:15 PM PDT 24
Peak memory 199804 kb
Host smart-27aaf21f-9b9b-4bd6-a483-1c1e3adb0161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331097311 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2331097311
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3234481336
Short name T629
Test name
Test status
Simulation time 88275043 ps
CPU time 0.84 seconds
Started Mar 17 01:15:15 PM PDT 24
Finished Mar 17 01:15:16 PM PDT 24
Peak memory 199760 kb
Host smart-5ae99c44-ef15-40ad-823f-60ea18bdd6f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234481336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3234481336
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1126824905
Short name T597
Test name
Test status
Simulation time 31779084 ps
CPU time 0.58 seconds
Started Mar 17 01:15:14 PM PDT 24
Finished Mar 17 01:15:14 PM PDT 24
Peak memory 194640 kb
Host smart-bc8eb6dd-f798-4682-bbb1-4eb30e87c21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126824905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1126824905
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4074743208
Short name T705
Test name
Test status
Simulation time 793381281 ps
CPU time 1.76 seconds
Started Mar 17 01:15:12 PM PDT 24
Finished Mar 17 01:15:14 PM PDT 24
Peak memory 199740 kb
Host smart-75a6b71b-6730-4bac-aa06-d7fb57115016
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074743208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.4074743208
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2115627618
Short name T657
Test name
Test status
Simulation time 316478153 ps
CPU time 2.02 seconds
Started Mar 17 01:15:09 PM PDT 24
Finished Mar 17 01:15:11 PM PDT 24
Peak memory 200000 kb
Host smart-86c34fae-68d3-4d8c-8dd2-259cc820521e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115627618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2115627618
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3602094073
Short name T729
Test name
Test status
Simulation time 210779829 ps
CPU time 2.32 seconds
Started Mar 17 01:15:20 PM PDT 24
Finished Mar 17 01:15:22 PM PDT 24
Peak memory 200140 kb
Host smart-803dbc43-7a89-4865-81df-1df1c27c51c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602094073 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3602094073
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3312526163
Short name T100
Test name
Test status
Simulation time 23639090 ps
CPU time 0.78 seconds
Started Mar 17 01:15:16 PM PDT 24
Finished Mar 17 01:15:17 PM PDT 24
Peak memory 198912 kb
Host smart-0c47dac7-365c-4c21-88c2-70dcdef4e47a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312526163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3312526163
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3487284886
Short name T613
Test name
Test status
Simulation time 39951898 ps
CPU time 0.59 seconds
Started Mar 17 01:15:14 PM PDT 24
Finished Mar 17 01:15:14 PM PDT 24
Peak memory 194632 kb
Host smart-29c0a91d-37be-4900-bbdc-2ad2c30264b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487284886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3487284886
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.253410483
Short name T676
Test name
Test status
Simulation time 50279166 ps
CPU time 1.25 seconds
Started Mar 17 01:15:18 PM PDT 24
Finished Mar 17 01:15:19 PM PDT 24
Peak memory 198040 kb
Host smart-b5ca6dd5-c714-4bc7-912c-1b672e8ab773
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253410483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.253410483
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2597654433
Short name T724
Test name
Test status
Simulation time 71597020 ps
CPU time 3.85 seconds
Started Mar 17 01:15:18 PM PDT 24
Finished Mar 17 01:15:22 PM PDT 24
Peak memory 200016 kb
Host smart-3701b6ff-93be-4f36-a331-a5f449df8281
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597654433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2597654433
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4183829816
Short name T109
Test name
Test status
Simulation time 1119662675 ps
CPU time 3.1 seconds
Started Mar 17 01:15:14 PM PDT 24
Finished Mar 17 01:15:17 PM PDT 24
Peak memory 200092 kb
Host smart-35b07aa0-d6b9-4994-ae07-94e4dc4a234d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183829816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4183829816
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2241975625
Short name T641
Test name
Test status
Simulation time 74179344 ps
CPU time 2.51 seconds
Started Mar 17 01:15:15 PM PDT 24
Finished Mar 17 01:15:18 PM PDT 24
Peak memory 200084 kb
Host smart-312b0dc9-78af-4142-aaae-fade70559efe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241975625 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2241975625
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2543346969
Short name T609
Test name
Test status
Simulation time 18575902 ps
CPU time 0.68 seconds
Started Mar 17 01:15:15 PM PDT 24
Finished Mar 17 01:15:16 PM PDT 24
Peak memory 197636 kb
Host smart-6916500f-a832-479c-ad3d-054c0dcac41e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543346969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2543346969
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3464129812
Short name T639
Test name
Test status
Simulation time 87596077 ps
CPU time 0.59 seconds
Started Mar 17 01:15:15 PM PDT 24
Finished Mar 17 01:15:16 PM PDT 24
Peak memory 194784 kb
Host smart-bcea1063-acde-4df2-ad58-4ad9fc596df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464129812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3464129812
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.67466753
Short name T607
Test name
Test status
Simulation time 33779623 ps
CPU time 1.55 seconds
Started Mar 17 01:15:20 PM PDT 24
Finished Mar 17 01:15:22 PM PDT 24
Peak memory 198944 kb
Host smart-f0a3359b-a043-4597-8ae1-8c0b9ec78dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67466753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_
outstanding.67466753
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2368430684
Short name T675
Test name
Test status
Simulation time 376628997 ps
CPU time 2.7 seconds
Started Mar 17 01:15:18 PM PDT 24
Finished Mar 17 01:15:21 PM PDT 24
Peak memory 200016 kb
Host smart-ae9b4b88-8eaf-4d3d-9bd0-acf6de69cca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368430684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2368430684
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3997116258
Short name T727
Test name
Test status
Simulation time 443840921 ps
CPU time 3.9 seconds
Started Mar 17 01:15:14 PM PDT 24
Finished Mar 17 01:15:18 PM PDT 24
Peak memory 200056 kb
Host smart-6752b0c2-dd8e-457e-b85c-e5cd3efdd8ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997116258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3997116258
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2014590028
Short name T715
Test name
Test status
Simulation time 134594621 ps
CPU time 2.46 seconds
Started Mar 17 01:15:14 PM PDT 24
Finished Mar 17 01:15:17 PM PDT 24
Peak memory 200100 kb
Host smart-0f53a613-7055-4877-9219-2387b8e43376
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014590028 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2014590028
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2780231533
Short name T101
Test name
Test status
Simulation time 34931479 ps
CPU time 0.9 seconds
Started Mar 17 01:15:17 PM PDT 24
Finished Mar 17 01:15:18 PM PDT 24
Peak memory 199820 kb
Host smart-231bdd36-c69b-4042-b329-d162b2498246
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780231533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2780231533
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2870380257
Short name T665
Test name
Test status
Simulation time 40931463 ps
CPU time 0.58 seconds
Started Mar 17 01:15:14 PM PDT 24
Finished Mar 17 01:15:15 PM PDT 24
Peak memory 194604 kb
Host smart-af5fe2fe-4b10-438f-aa8c-6185af189b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870380257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2870380257
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.909808475
Short name T617
Test name
Test status
Simulation time 238996374 ps
CPU time 1.05 seconds
Started Mar 17 01:15:20 PM PDT 24
Finished Mar 17 01:15:21 PM PDT 24
Peak memory 199860 kb
Host smart-44d6e579-fae1-463e-aba7-299497081175
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909808475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.909808475
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2940620069
Short name T679
Test name
Test status
Simulation time 182551560 ps
CPU time 2.07 seconds
Started Mar 17 01:15:13 PM PDT 24
Finished Mar 17 01:15:15 PM PDT 24
Peak memory 200092 kb
Host smart-561db1f4-0018-4524-91c6-68b3e375e3bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940620069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2940620069
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1942006395
Short name T662
Test name
Test status
Simulation time 1244646063 ps
CPU time 3.23 seconds
Started Mar 17 01:15:14 PM PDT 24
Finished Mar 17 01:15:17 PM PDT 24
Peak memory 200028 kb
Host smart-7ac5113c-5f68-4916-b896-900955cafacf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942006395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1942006395
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2445690703
Short name T658
Test name
Test status
Simulation time 236238622064 ps
CPU time 870.6 seconds
Started Mar 17 01:15:21 PM PDT 24
Finished Mar 17 01:29:51 PM PDT 24
Peak memory 224804 kb
Host smart-1ee254f1-2358-4326-820b-396a4657ec33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445690703 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2445690703
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1882793340
Short name T604
Test name
Test status
Simulation time 101350978 ps
CPU time 0.97 seconds
Started Mar 17 01:15:22 PM PDT 24
Finished Mar 17 01:15:23 PM PDT 24
Peak memory 199792 kb
Host smart-945aeb4b-1abd-448c-98dd-925266748413
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882793340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1882793340
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.4270504526
Short name T620
Test name
Test status
Simulation time 54249260 ps
CPU time 0.56 seconds
Started Mar 17 01:15:20 PM PDT 24
Finished Mar 17 01:15:21 PM PDT 24
Peak memory 194536 kb
Host smart-e60d58d1-24e3-448e-8079-eed62e815472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270504526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.4270504526
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2248477325
Short name T631
Test name
Test status
Simulation time 186709336 ps
CPU time 2.57 seconds
Started Mar 17 01:15:23 PM PDT 24
Finished Mar 17 01:15:26 PM PDT 24
Peak memory 199788 kb
Host smart-308513f4-baac-40a5-887c-28b7b6ca2d63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248477325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2248477325
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.275581045
Short name T680
Test name
Test status
Simulation time 85261266 ps
CPU time 1.55 seconds
Started Mar 17 01:15:16 PM PDT 24
Finished Mar 17 01:15:18 PM PDT 24
Peak memory 200148 kb
Host smart-0ccddcc4-467a-4a03-bd82-d5e16f264fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275581045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.275581045
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3441976140
Short name T683
Test name
Test status
Simulation time 314062961 ps
CPU time 3.02 seconds
Started Mar 17 01:15:15 PM PDT 24
Finished Mar 17 01:15:18 PM PDT 24
Peak memory 199996 kb
Host smart-46e1e096-4ca9-4dd5-824c-92c3b8c712dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441976140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3441976140
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1540058813
Short name T706
Test name
Test status
Simulation time 123196791 ps
CPU time 2 seconds
Started Mar 17 01:15:21 PM PDT 24
Finished Mar 17 01:15:23 PM PDT 24
Peak memory 200064 kb
Host smart-77055394-1602-4477-905c-db7bc7034413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540058813 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1540058813
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1094125758
Short name T96
Test name
Test status
Simulation time 20092486 ps
CPU time 0.87 seconds
Started Mar 17 01:15:32 PM PDT 24
Finished Mar 17 01:15:33 PM PDT 24
Peak memory 199288 kb
Host smart-57998733-44f0-4107-8150-a7d3ba468eb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094125758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1094125758
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1187253187
Short name T606
Test name
Test status
Simulation time 37139936 ps
CPU time 0.57 seconds
Started Mar 17 01:15:21 PM PDT 24
Finished Mar 17 01:15:22 PM PDT 24
Peak memory 194572 kb
Host smart-35e911b1-7371-4f88-85ef-6ad26fbea654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187253187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1187253187
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3898636727
Short name T677
Test name
Test status
Simulation time 37044293 ps
CPU time 1.6 seconds
Started Mar 17 01:15:32 PM PDT 24
Finished Mar 17 01:15:34 PM PDT 24
Peak memory 199960 kb
Host smart-2e7101c7-b619-44fe-978d-3eafb0eeda1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898636727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3898636727
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.497991919
Short name T696
Test name
Test status
Simulation time 250827434 ps
CPU time 1.82 seconds
Started Mar 17 01:15:22 PM PDT 24
Finished Mar 17 01:15:24 PM PDT 24
Peak memory 200108 kb
Host smart-3a2159e5-5a95-4d50-b9ec-00ad88d4c9c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497991919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.497991919
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2337675873
Short name T726
Test name
Test status
Simulation time 532078064 ps
CPU time 4.52 seconds
Started Mar 17 01:15:20 PM PDT 24
Finished Mar 17 01:15:25 PM PDT 24
Peak memory 200060 kb
Host smart-356e7768-5699-41cc-a987-aeaeb1c1a8c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337675873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2337675873
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1329248779
Short name T626
Test name
Test status
Simulation time 808527594 ps
CPU time 3.41 seconds
Started Mar 17 01:14:50 PM PDT 24
Finished Mar 17 01:14:54 PM PDT 24
Peak memory 198812 kb
Host smart-1be105d0-79ac-4e27-bc06-34fc951cfb30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329248779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1329248779
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.394607338
Short name T713
Test name
Test status
Simulation time 1443208000 ps
CPU time 5.89 seconds
Started Mar 17 01:14:51 PM PDT 24
Finished Mar 17 01:14:57 PM PDT 24
Peak memory 198776 kb
Host smart-5cd668e5-9d9f-4569-b28d-67748ddbb757
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394607338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.394607338
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1262782488
Short name T635
Test name
Test status
Simulation time 16801115 ps
CPU time 0.83 seconds
Started Mar 17 01:14:47 PM PDT 24
Finished Mar 17 01:14:48 PM PDT 24
Peak memory 198912 kb
Host smart-2af17af3-80f8-4780-8469-96e125c70d5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262782488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1262782488
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.215742397
Short name T603
Test name
Test status
Simulation time 34293188 ps
CPU time 2.17 seconds
Started Mar 17 01:14:50 PM PDT 24
Finished Mar 17 01:14:53 PM PDT 24
Peak memory 200196 kb
Host smart-165a9733-0dd8-451e-98f7-e4a463ac6e89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215742397 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.215742397
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.826528884
Short name T733
Test name
Test status
Simulation time 16104633 ps
CPU time 0.84 seconds
Started Mar 17 01:14:46 PM PDT 24
Finished Mar 17 01:14:47 PM PDT 24
Peak memory 199060 kb
Host smart-773f1b57-5983-496d-827d-8d92ffe67c40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826528884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.826528884
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1818709765
Short name T632
Test name
Test status
Simulation time 14569290 ps
CPU time 0.6 seconds
Started Mar 17 01:14:45 PM PDT 24
Finished Mar 17 01:14:46 PM PDT 24
Peak memory 194648 kb
Host smart-a893baa1-2780-4f25-80c7-130a5a4a2f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818709765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1818709765
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1780981627
Short name T646
Test name
Test status
Simulation time 45870264 ps
CPU time 1.12 seconds
Started Mar 17 01:14:51 PM PDT 24
Finished Mar 17 01:14:52 PM PDT 24
Peak memory 199532 kb
Host smart-6a154401-344f-4d71-afa6-68452d9af234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780981627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1780981627
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3137466334
Short name T621
Test name
Test status
Simulation time 110848064 ps
CPU time 2.76 seconds
Started Mar 17 01:14:45 PM PDT 24
Finished Mar 17 01:14:48 PM PDT 24
Peak memory 200124 kb
Host smart-093987e8-5e91-4c55-ab77-bdcbb5c44011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137466334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3137466334
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.457168210
Short name T58
Test name
Test status
Simulation time 3112126852 ps
CPU time 4.38 seconds
Started Mar 17 01:14:51 PM PDT 24
Finished Mar 17 01:14:55 PM PDT 24
Peak memory 200132 kb
Host smart-6bba53cb-5a99-4118-a630-9cca5241c2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457168210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.457168210
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2839679483
Short name T599
Test name
Test status
Simulation time 64014375 ps
CPU time 0.61 seconds
Started Mar 17 01:15:20 PM PDT 24
Finished Mar 17 01:15:21 PM PDT 24
Peak memory 194912 kb
Host smart-4bbb0cb8-7539-4108-913e-2f3c4854698a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839679483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2839679483
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1867383647
Short name T668
Test name
Test status
Simulation time 13575468 ps
CPU time 0.61 seconds
Started Mar 17 01:15:32 PM PDT 24
Finished Mar 17 01:15:33 PM PDT 24
Peak memory 194596 kb
Host smart-43cc0caf-3b72-4f11-aaa8-b03730730fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867383647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1867383647
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1108347072
Short name T660
Test name
Test status
Simulation time 37772167 ps
CPU time 0.62 seconds
Started Mar 17 01:15:25 PM PDT 24
Finished Mar 17 01:15:26 PM PDT 24
Peak memory 194000 kb
Host smart-dfd6b28c-3fd7-43f4-a670-b7cd11fac311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108347072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1108347072
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3274203361
Short name T701
Test name
Test status
Simulation time 16251927 ps
CPU time 0.65 seconds
Started Mar 17 01:15:24 PM PDT 24
Finished Mar 17 01:15:25 PM PDT 24
Peak memory 194784 kb
Host smart-a9aadae8-bb9f-428d-84a2-2b6da86a2db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274203361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3274203361
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.741240564
Short name T714
Test name
Test status
Simulation time 11692705 ps
CPU time 0.63 seconds
Started Mar 17 01:15:23 PM PDT 24
Finished Mar 17 01:15:25 PM PDT 24
Peak memory 194652 kb
Host smart-8113915e-f122-4dac-89e4-1a136a2f1ee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741240564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.741240564
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2299159956
Short name T704
Test name
Test status
Simulation time 18253555 ps
CPU time 0.6 seconds
Started Mar 17 01:15:20 PM PDT 24
Finished Mar 17 01:15:21 PM PDT 24
Peak memory 194596 kb
Host smart-77d8fe69-c656-4db9-88a6-706f7b19b908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299159956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2299159956
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1689194544
Short name T656
Test name
Test status
Simulation time 13600190 ps
CPU time 0.6 seconds
Started Mar 17 01:15:25 PM PDT 24
Finished Mar 17 01:15:26 PM PDT 24
Peak memory 194184 kb
Host smart-f88e733b-8af6-4c9c-a8c5-8eabaa16fce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689194544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1689194544
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2059938015
Short name T659
Test name
Test status
Simulation time 14937434 ps
CPU time 0.57 seconds
Started Mar 17 01:15:21 PM PDT 24
Finished Mar 17 01:15:22 PM PDT 24
Peak memory 194812 kb
Host smart-fa4fe993-c12b-412d-9719-fb11a8230b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059938015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2059938015
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3356901057
Short name T661
Test name
Test status
Simulation time 55389829 ps
CPU time 0.63 seconds
Started Mar 17 01:15:22 PM PDT 24
Finished Mar 17 01:15:23 PM PDT 24
Peak memory 194648 kb
Host smart-58669ccf-1754-42d7-9cba-2bd89f433740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356901057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3356901057
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3956011324
Short name T647
Test name
Test status
Simulation time 35096914 ps
CPU time 0.58 seconds
Started Mar 17 01:15:21 PM PDT 24
Finished Mar 17 01:15:22 PM PDT 24
Peak memory 194532 kb
Host smart-63dbbff8-1b03-443a-bbcd-6a5bd8d1f7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956011324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3956011324
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1833213493
Short name T93
Test name
Test status
Simulation time 739300501 ps
CPU time 3.08 seconds
Started Mar 17 01:14:53 PM PDT 24
Finished Mar 17 01:14:56 PM PDT 24
Peak memory 199008 kb
Host smart-71861535-38c0-4c79-8270-6b6a42ad32e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833213493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1833213493
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3122812717
Short name T634
Test name
Test status
Simulation time 2630956564 ps
CPU time 10.31 seconds
Started Mar 17 01:14:50 PM PDT 24
Finished Mar 17 01:15:01 PM PDT 24
Peak memory 199136 kb
Host smart-8ae35733-d895-4cdd-aaf9-8eb206d7cbed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122812717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3122812717
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.503437052
Short name T89
Test name
Test status
Simulation time 29634524 ps
CPU time 0.92 seconds
Started Mar 17 01:14:52 PM PDT 24
Finished Mar 17 01:14:53 PM PDT 24
Peak memory 198832 kb
Host smart-0272ac3c-3184-4490-9f58-77be462db844
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503437052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.503437052
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.525633706
Short name T615
Test name
Test status
Simulation time 69053065 ps
CPU time 2.21 seconds
Started Mar 17 01:14:54 PM PDT 24
Finished Mar 17 01:14:57 PM PDT 24
Peak memory 200044 kb
Host smart-28e079f7-ec74-4d9d-a092-b87223c56cc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525633706 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.525633706
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.220825285
Short name T102
Test name
Test status
Simulation time 139578863 ps
CPU time 0.92 seconds
Started Mar 17 01:14:52 PM PDT 24
Finished Mar 17 01:14:53 PM PDT 24
Peak memory 199248 kb
Host smart-31c11d55-0ef1-449e-9e6d-75429f07d81c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220825285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.220825285
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2765275427
Short name T730
Test name
Test status
Simulation time 25646935 ps
CPU time 0.57 seconds
Started Mar 17 01:14:51 PM PDT 24
Finished Mar 17 01:14:51 PM PDT 24
Peak memory 194776 kb
Host smart-7ed7c2b2-73dc-42a3-b385-99c54fb9c835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765275427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2765275427
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3907624125
Short name T642
Test name
Test status
Simulation time 177051410 ps
CPU time 1.95 seconds
Started Mar 17 01:14:49 PM PDT 24
Finished Mar 17 01:14:51 PM PDT 24
Peak memory 200036 kb
Host smart-bf8b1db7-ce22-4a42-bc44-dd0f5e3bbebe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907624125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3907624125
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2948056182
Short name T618
Test name
Test status
Simulation time 207639917 ps
CPU time 3.94 seconds
Started Mar 17 01:14:51 PM PDT 24
Finished Mar 17 01:14:55 PM PDT 24
Peak memory 200128 kb
Host smart-a9bc5dbc-16c4-451f-b7b3-da5d63cb68f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948056182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2948056182
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.215941413
Short name T718
Test name
Test status
Simulation time 643009961 ps
CPU time 1.92 seconds
Started Mar 17 01:14:52 PM PDT 24
Finished Mar 17 01:14:54 PM PDT 24
Peak memory 199980 kb
Host smart-e47b45e0-bb93-4fde-b30b-17c700e98960
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215941413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.215941413
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1043013035
Short name T637
Test name
Test status
Simulation time 16806101 ps
CPU time 0.65 seconds
Started Mar 17 01:15:26 PM PDT 24
Finished Mar 17 01:15:27 PM PDT 24
Peak memory 194832 kb
Host smart-f2ce9cc2-2506-4a8d-a843-f2ea4212ac97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043013035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1043013035
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2239397825
Short name T648
Test name
Test status
Simulation time 56276603 ps
CPU time 0.61 seconds
Started Mar 17 01:15:24 PM PDT 24
Finished Mar 17 01:15:25 PM PDT 24
Peak memory 194832 kb
Host smart-aa8d8261-9f34-465e-9bc6-d5c224e0391b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239397825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2239397825
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1067574801
Short name T649
Test name
Test status
Simulation time 57957594 ps
CPU time 0.63 seconds
Started Mar 17 01:15:21 PM PDT 24
Finished Mar 17 01:15:22 PM PDT 24
Peak memory 194672 kb
Host smart-f646b053-3fc6-47e4-b22f-57958c6aa020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067574801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1067574801
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2905826882
Short name T694
Test name
Test status
Simulation time 36070111 ps
CPU time 0.55 seconds
Started Mar 17 01:15:32 PM PDT 24
Finished Mar 17 01:15:33 PM PDT 24
Peak memory 194776 kb
Host smart-a0503158-690e-4a61-b722-fcc0b81bab09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905826882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2905826882
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3107565640
Short name T717
Test name
Test status
Simulation time 29013854 ps
CPU time 0.59 seconds
Started Mar 17 01:15:23 PM PDT 24
Finished Mar 17 01:15:24 PM PDT 24
Peak memory 194556 kb
Host smart-40638763-4a65-44d7-ad5c-5446a3f0a515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107565640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3107565640
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1520032298
Short name T644
Test name
Test status
Simulation time 62622948 ps
CPU time 0.67 seconds
Started Mar 17 01:15:32 PM PDT 24
Finished Mar 17 01:15:33 PM PDT 24
Peak memory 194776 kb
Host smart-c244641a-5028-4482-902d-21a5b8a604d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520032298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1520032298
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2407026528
Short name T720
Test name
Test status
Simulation time 86564602 ps
CPU time 0.6 seconds
Started Mar 17 01:15:25 PM PDT 24
Finished Mar 17 01:15:26 PM PDT 24
Peak memory 194596 kb
Host smart-1311854a-e872-4664-a5d2-0a161aad395d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407026528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2407026528
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1050204762
Short name T650
Test name
Test status
Simulation time 48857947 ps
CPU time 0.6 seconds
Started Mar 17 01:15:25 PM PDT 24
Finished Mar 17 01:15:25 PM PDT 24
Peak memory 194560 kb
Host smart-565bdb1a-fabe-494e-8713-ab69a1289f41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050204762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1050204762
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1027713260
Short name T601
Test name
Test status
Simulation time 25546697 ps
CPU time 0.6 seconds
Started Mar 17 01:15:40 PM PDT 24
Finished Mar 17 01:15:41 PM PDT 24
Peak memory 194532 kb
Host smart-6d634797-5e79-4516-aa1f-5bdc0f162825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027713260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1027713260
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3244527188
Short name T645
Test name
Test status
Simulation time 58525887 ps
CPU time 0.64 seconds
Started Mar 17 01:15:22 PM PDT 24
Finished Mar 17 01:15:22 PM PDT 24
Peak memory 194592 kb
Host smart-0fe6c1c5-30bb-41d2-8770-1828878b619c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244527188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3244527188
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3941109718
Short name T655
Test name
Test status
Simulation time 403728642 ps
CPU time 6.38 seconds
Started Mar 17 01:14:51 PM PDT 24
Finished Mar 17 01:14:58 PM PDT 24
Peak memory 200036 kb
Host smart-0fc523d6-d728-4f56-81ae-b9ac574f5011
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941109718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3941109718
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.182535844
Short name T700
Test name
Test status
Simulation time 5084492251 ps
CPU time 10.73 seconds
Started Mar 17 01:14:55 PM PDT 24
Finished Mar 17 01:15:06 PM PDT 24
Peak memory 200080 kb
Host smart-71caae62-4feb-4dfa-96cf-02afcf1bd4c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182535844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.182535844
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2114072448
Short name T87
Test name
Test status
Simulation time 62969249 ps
CPU time 0.74 seconds
Started Mar 17 01:14:50 PM PDT 24
Finished Mar 17 01:14:51 PM PDT 24
Peak memory 197696 kb
Host smart-8ea129c3-1ccf-4d34-9050-486cf8f41396
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114072448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2114072448
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.222876744
Short name T600
Test name
Test status
Simulation time 26732932 ps
CPU time 1.44 seconds
Started Mar 17 01:14:58 PM PDT 24
Finished Mar 17 01:15:00 PM PDT 24
Peak memory 200028 kb
Host smart-d6a09015-01bd-4cda-8bdf-28b96d9dc5b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222876744 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.222876744
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.115217611
Short name T92
Test name
Test status
Simulation time 75428386 ps
CPU time 0.79 seconds
Started Mar 17 01:14:55 PM PDT 24
Finished Mar 17 01:14:56 PM PDT 24
Peak memory 199204 kb
Host smart-053c46c1-069f-4847-9084-4ef4cc3530bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115217611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.115217611
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3362806561
Short name T640
Test name
Test status
Simulation time 174362775 ps
CPU time 0.59 seconds
Started Mar 17 01:14:51 PM PDT 24
Finished Mar 17 01:14:51 PM PDT 24
Peak memory 194636 kb
Host smart-4984f731-3615-4c6d-8ab3-ebc0105ae050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362806561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3362806561
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1971505301
Short name T699
Test name
Test status
Simulation time 436884253 ps
CPU time 2.42 seconds
Started Mar 17 01:14:53 PM PDT 24
Finished Mar 17 01:14:55 PM PDT 24
Peak memory 199988 kb
Host smart-6454afc2-1ec9-4c2b-8acd-16c6ca25be62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971505301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1971505301
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3567009914
Short name T624
Test name
Test status
Simulation time 1303127402 ps
CPU time 3.36 seconds
Started Mar 17 01:14:51 PM PDT 24
Finished Mar 17 01:14:54 PM PDT 24
Peak memory 200048 kb
Host smart-ba66cec0-83f7-4785-83c6-d6bd5063e579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567009914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3567009914
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3803357185
Short name T693
Test name
Test status
Simulation time 48096069 ps
CPU time 1.69 seconds
Started Mar 17 01:14:51 PM PDT 24
Finished Mar 17 01:14:53 PM PDT 24
Peak memory 199904 kb
Host smart-8a2c8f42-9a90-45bc-8dcd-8eb2088eafb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803357185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3803357185
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.785672428
Short name T712
Test name
Test status
Simulation time 11299267 ps
CPU time 0.62 seconds
Started Mar 17 01:15:21 PM PDT 24
Finished Mar 17 01:15:22 PM PDT 24
Peak memory 194948 kb
Host smart-351bfa7f-1fd2-4fd6-bfee-41af7ed385de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785672428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.785672428
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2377656251
Short name T667
Test name
Test status
Simulation time 35166028 ps
CPU time 0.58 seconds
Started Mar 17 01:15:25 PM PDT 24
Finished Mar 17 01:15:26 PM PDT 24
Peak memory 194828 kb
Host smart-39fd9ad2-587c-4f65-8c43-99e73faf6e51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377656251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2377656251
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.4135609708
Short name T708
Test name
Test status
Simulation time 53341706 ps
CPU time 0.63 seconds
Started Mar 17 01:15:20 PM PDT 24
Finished Mar 17 01:15:21 PM PDT 24
Peak memory 194724 kb
Host smart-9dfbdef6-54aa-4080-a4f1-665c84f4fd8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135609708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.4135609708
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2495013340
Short name T728
Test name
Test status
Simulation time 63243626 ps
CPU time 0.63 seconds
Started Mar 17 01:15:23 PM PDT 24
Finished Mar 17 01:15:23 PM PDT 24
Peak memory 194604 kb
Host smart-efc2bd41-3b97-407d-a7a7-f1fedbbd5751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495013340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2495013340
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1660583286
Short name T686
Test name
Test status
Simulation time 23599466 ps
CPU time 0.62 seconds
Started Mar 17 01:15:24 PM PDT 24
Finished Mar 17 01:15:25 PM PDT 24
Peak memory 194632 kb
Host smart-f37a657d-2e49-42f3-98f4-ee8d8933eb90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660583286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1660583286
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3942312783
Short name T722
Test name
Test status
Simulation time 23094432 ps
CPU time 0.56 seconds
Started Mar 17 01:15:26 PM PDT 24
Finished Mar 17 01:15:27 PM PDT 24
Peak memory 194808 kb
Host smart-4ab73917-5d44-4775-bb2b-72aed7e12ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942312783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3942312783
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2946307659
Short name T671
Test name
Test status
Simulation time 80956532 ps
CPU time 0.55 seconds
Started Mar 17 01:15:25 PM PDT 24
Finished Mar 17 01:15:25 PM PDT 24
Peak memory 194608 kb
Host smart-363f4a5a-5c06-4357-99bd-39856100111f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946307659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2946307659
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1982692667
Short name T652
Test name
Test status
Simulation time 13456879 ps
CPU time 0.59 seconds
Started Mar 17 01:15:28 PM PDT 24
Finished Mar 17 01:15:29 PM PDT 24
Peak memory 194848 kb
Host smart-63f6cdad-8b70-492d-9abd-63aedb4a06f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982692667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1982692667
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.90603673
Short name T678
Test name
Test status
Simulation time 14484333 ps
CPU time 0.63 seconds
Started Mar 17 01:15:26 PM PDT 24
Finished Mar 17 01:15:27 PM PDT 24
Peak memory 194564 kb
Host smart-4c0eb2cf-7e5d-4c8f-adf3-cae1ca239010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90603673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.90603673
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3552237870
Short name T616
Test name
Test status
Simulation time 20512774 ps
CPU time 0.6 seconds
Started Mar 17 01:15:26 PM PDT 24
Finished Mar 17 01:15:26 PM PDT 24
Peak memory 194732 kb
Host smart-2b96ad95-98d8-4ff6-8b5e-fb9ab75ecd89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552237870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3552237870
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2847167453
Short name T653
Test name
Test status
Simulation time 69948480 ps
CPU time 1.28 seconds
Started Mar 17 01:14:57 PM PDT 24
Finished Mar 17 01:14:58 PM PDT 24
Peak memory 199892 kb
Host smart-3a3897c9-901e-430a-bd53-8bcce74d34c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847167453 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2847167453
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1159582904
Short name T62
Test name
Test status
Simulation time 60985765 ps
CPU time 0.97 seconds
Started Mar 17 01:14:57 PM PDT 24
Finished Mar 17 01:14:58 PM PDT 24
Peak memory 199320 kb
Host smart-dbe1e9e7-b071-479f-9d03-644d86c68595
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159582904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1159582904
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3327829684
Short name T636
Test name
Test status
Simulation time 111541290 ps
CPU time 0.58 seconds
Started Mar 17 01:14:57 PM PDT 24
Finished Mar 17 01:14:57 PM PDT 24
Peak memory 194608 kb
Host smart-72cea2f8-82b1-4ca2-8428-19fb770f4235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327829684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3327829684
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3697986114
Short name T695
Test name
Test status
Simulation time 77773178 ps
CPU time 1.67 seconds
Started Mar 17 01:14:56 PM PDT 24
Finished Mar 17 01:14:58 PM PDT 24
Peak memory 199928 kb
Host smart-4a896150-0985-4439-8893-f32a9ff6fae0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697986114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3697986114
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1258693089
Short name T711
Test name
Test status
Simulation time 154142076 ps
CPU time 1.17 seconds
Started Mar 17 01:14:57 PM PDT 24
Finished Mar 17 01:14:58 PM PDT 24
Peak memory 199872 kb
Host smart-3bd1ce11-3fd7-4518-a4c1-1469b30667ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258693089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1258693089
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3617585570
Short name T716
Test name
Test status
Simulation time 181894649 ps
CPU time 3.12 seconds
Started Mar 17 01:14:58 PM PDT 24
Finished Mar 17 01:15:01 PM PDT 24
Peak memory 199976 kb
Host smart-668c1dc2-51c3-47b5-87a4-d72f7b4e1f70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617585570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3617585570
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.975395480
Short name T611
Test name
Test status
Simulation time 42678721 ps
CPU time 1.12 seconds
Started Mar 17 01:14:56 PM PDT 24
Finished Mar 17 01:14:58 PM PDT 24
Peak memory 199816 kb
Host smart-e3a1671b-6d69-49f2-92a9-248981f650ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975395480 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.975395480
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1217855423
Short name T651
Test name
Test status
Simulation time 60307685 ps
CPU time 0.68 seconds
Started Mar 17 01:14:57 PM PDT 24
Finished Mar 17 01:14:58 PM PDT 24
Peak memory 197584 kb
Host smart-2ce76145-c433-4639-9b0a-d76093167a6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217855423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1217855423
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3889766325
Short name T691
Test name
Test status
Simulation time 14102871 ps
CPU time 0.61 seconds
Started Mar 17 01:14:58 PM PDT 24
Finished Mar 17 01:14:59 PM PDT 24
Peak memory 194616 kb
Host smart-edf08efb-3274-4662-ba56-a132260e6fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889766325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3889766325
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.321484952
Short name T721
Test name
Test status
Simulation time 2188470850 ps
CPU time 2.21 seconds
Started Mar 17 01:14:57 PM PDT 24
Finished Mar 17 01:14:59 PM PDT 24
Peak memory 199972 kb
Host smart-636ae312-a23b-4443-8b68-51594e482507
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321484952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.321484952
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1423541502
Short name T630
Test name
Test status
Simulation time 362836517 ps
CPU time 3.71 seconds
Started Mar 17 01:14:58 PM PDT 24
Finished Mar 17 01:15:02 PM PDT 24
Peak memory 200044 kb
Host smart-4837e277-bd46-4150-a8d5-98cf8fc79151
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423541502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1423541502
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1421829308
Short name T107
Test name
Test status
Simulation time 232762751 ps
CPU time 4.49 seconds
Started Mar 17 01:14:57 PM PDT 24
Finished Mar 17 01:15:02 PM PDT 24
Peak memory 200076 kb
Host smart-e63cc84b-30ff-4825-95c9-0fdcb75a5815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421829308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1421829308
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3241802185
Short name T692
Test name
Test status
Simulation time 577324904 ps
CPU time 4.05 seconds
Started Mar 17 01:15:03 PM PDT 24
Finished Mar 17 01:15:08 PM PDT 24
Peak memory 208380 kb
Host smart-5c9a73aa-a07f-43ff-b867-54c76ff3a8d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241802185 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3241802185
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4110243665
Short name T703
Test name
Test status
Simulation time 126885690 ps
CPU time 0.8 seconds
Started Mar 17 01:15:04 PM PDT 24
Finished Mar 17 01:15:04 PM PDT 24
Peak memory 198924 kb
Host smart-123397cf-abb4-4c3e-9b58-2aace3f2cab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110243665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.4110243665
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2544399677
Short name T690
Test name
Test status
Simulation time 55448105 ps
CPU time 0.57 seconds
Started Mar 17 01:14:58 PM PDT 24
Finished Mar 17 01:14:59 PM PDT 24
Peak memory 194744 kb
Host smart-87c89a56-21df-4eb6-afdb-3dae236dc98d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544399677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2544399677
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2419320729
Short name T598
Test name
Test status
Simulation time 1896016467 ps
CPU time 2.05 seconds
Started Mar 17 01:15:04 PM PDT 24
Finished Mar 17 01:15:06 PM PDT 24
Peak memory 199784 kb
Host smart-6ae3eda9-892e-4c97-86d9-f816660911dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419320729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2419320729
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.562739114
Short name T627
Test name
Test status
Simulation time 379027157 ps
CPU time 2.88 seconds
Started Mar 17 01:14:57 PM PDT 24
Finished Mar 17 01:15:00 PM PDT 24
Peak memory 200052 kb
Host smart-61b3228b-2e0b-4fe6-89e4-e6f9bcfeb3ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562739114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.562739114
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3258840699
Short name T709
Test name
Test status
Simulation time 52448404 ps
CPU time 1.41 seconds
Started Mar 17 01:15:02 PM PDT 24
Finished Mar 17 01:15:03 PM PDT 24
Peak memory 200048 kb
Host smart-192b6aae-ce49-42cb-8530-35fdf7777c7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258840699 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3258840699
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1105049185
Short name T90
Test name
Test status
Simulation time 16298251 ps
CPU time 0.8 seconds
Started Mar 17 01:15:08 PM PDT 24
Finished Mar 17 01:15:08 PM PDT 24
Peak memory 198732 kb
Host smart-5772b570-493f-4998-b940-52fa1ef3bd14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105049185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1105049185
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3130560850
Short name T602
Test name
Test status
Simulation time 38959719 ps
CPU time 0.63 seconds
Started Mar 17 01:15:04 PM PDT 24
Finished Mar 17 01:15:05 PM PDT 24
Peak memory 194764 kb
Host smart-1cd75bd6-4327-454e-af06-20af3386b909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130560850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3130560850
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.679922055
Short name T725
Test name
Test status
Simulation time 300168264 ps
CPU time 1.58 seconds
Started Mar 17 01:15:03 PM PDT 24
Finished Mar 17 01:15:04 PM PDT 24
Peak memory 200080 kb
Host smart-4bc4c5ce-fc8b-4d9d-af24-416edbb05939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679922055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.679922055
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4201619790
Short name T707
Test name
Test status
Simulation time 486186214 ps
CPU time 2.53 seconds
Started Mar 17 01:15:02 PM PDT 24
Finished Mar 17 01:15:05 PM PDT 24
Peak memory 200096 kb
Host smart-9ef337dd-6e72-4e78-8fa3-1251b02524a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201619790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4201619790
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1177728521
Short name T106
Test name
Test status
Simulation time 879775578 ps
CPU time 3.09 seconds
Started Mar 17 01:15:07 PM PDT 24
Finished Mar 17 01:15:10 PM PDT 24
Peak memory 199988 kb
Host smart-d9435dec-54fe-4bac-8450-ce3ca96c634e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177728521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1177728521
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2452223097
Short name T731
Test name
Test status
Simulation time 243613035 ps
CPU time 2 seconds
Started Mar 17 01:15:03 PM PDT 24
Finished Mar 17 01:15:05 PM PDT 24
Peak memory 200100 kb
Host smart-df938eb1-488f-42ee-bd56-33ddeaf1d508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452223097 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2452223097
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1861339430
Short name T734
Test name
Test status
Simulation time 105859403 ps
CPU time 1.04 seconds
Started Mar 17 01:15:07 PM PDT 24
Finished Mar 17 01:15:08 PM PDT 24
Peak memory 199392 kb
Host smart-d222176e-e303-48d8-8954-2da0abda3c44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861339430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1861339430
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.54150720
Short name T698
Test name
Test status
Simulation time 29785183 ps
CPU time 0.62 seconds
Started Mar 17 01:15:05 PM PDT 24
Finished Mar 17 01:15:06 PM PDT 24
Peak memory 194616 kb
Host smart-11451f71-2f2b-4638-b75d-29c1f4fd4c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54150720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.54150720
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.793024551
Short name T633
Test name
Test status
Simulation time 88643994 ps
CPU time 2.24 seconds
Started Mar 17 01:15:05 PM PDT 24
Finished Mar 17 01:15:07 PM PDT 24
Peak memory 199592 kb
Host smart-ba0adc9c-de4b-4f5a-aa62-015f4d995693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793024551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.793024551
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2384294776
Short name T625
Test name
Test status
Simulation time 108036024 ps
CPU time 2.67 seconds
Started Mar 17 01:15:03 PM PDT 24
Finished Mar 17 01:15:05 PM PDT 24
Peak memory 200120 kb
Host smart-0d337c1f-0a47-47cb-8bb0-db7d41a09441
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384294776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2384294776
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2002952144
Short name T569
Test name
Test status
Simulation time 16798107 ps
CPU time 0.57 seconds
Started Mar 17 01:32:55 PM PDT 24
Finished Mar 17 01:32:56 PM PDT 24
Peak memory 194684 kb
Host smart-7ec3de39-a7b3-4da2-b6f8-55a9da4de957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002952144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2002952144
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3915758049
Short name T555
Test name
Test status
Simulation time 1350170090 ps
CPU time 49.43 seconds
Started Mar 17 01:32:51 PM PDT 24
Finished Mar 17 01:33:41 PM PDT 24
Peak memory 214324 kb
Host smart-b67ab278-344b-421e-b636-2e9027a305cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915758049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3915758049
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1180094830
Short name T274
Test name
Test status
Simulation time 931793340 ps
CPU time 46.19 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:33:34 PM PDT 24
Peak memory 200376 kb
Host smart-4b978b17-5ee4-4632-9266-09c704e1871b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180094830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1180094830
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2716172606
Short name T196
Test name
Test status
Simulation time 1760525854 ps
CPU time 100.05 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:34:28 PM PDT 24
Peak memory 200392 kb
Host smart-14f5cab0-574c-48f4-a613-e1129264e0cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716172606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2716172606
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2302080119
Short name T364
Test name
Test status
Simulation time 1984666659 ps
CPU time 37.1 seconds
Started Mar 17 01:32:53 PM PDT 24
Finished Mar 17 01:33:31 PM PDT 24
Peak memory 200440 kb
Host smart-2d5be48c-eb85-4469-80b8-c9226781629a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302080119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2302080119
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.766464822
Short name T329
Test name
Test status
Simulation time 4312007745 ps
CPU time 22.88 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:33:11 PM PDT 24
Peak memory 200488 kb
Host smart-69ae5839-b483-491e-9ab1-60b09d8f31a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766464822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.766464822
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.339674880
Short name T57
Test name
Test status
Simulation time 149344269 ps
CPU time 4.54 seconds
Started Mar 17 01:32:51 PM PDT 24
Finished Mar 17 01:32:56 PM PDT 24
Peak memory 200428 kb
Host smart-61f3e6ba-6b06-4052-a337-7d0c0e68c8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339674880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.339674880
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.2461191828
Short name T159
Test name
Test status
Simulation time 139583055 ps
CPU time 1.04 seconds
Started Mar 17 01:32:49 PM PDT 24
Finished Mar 17 01:32:50 PM PDT 24
Peak memory 199796 kb
Host smart-a16e7488-5882-48f6-8c48-28267efbbadd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461191828 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.2461191828
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.4205283972
Short name T145
Test name
Test status
Simulation time 16020140291 ps
CPU time 434.93 seconds
Started Mar 17 01:32:50 PM PDT 24
Finished Mar 17 01:40:05 PM PDT 24
Peak memory 200404 kb
Host smart-9af81182-de8d-43d6-b738-959407fa6a3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205283972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.4205283972
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.907768318
Short name T327
Test name
Test status
Simulation time 1210671502 ps
CPU time 60.11 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:33:48 PM PDT 24
Peak memory 200408 kb
Host smart-9eaaa042-a2c9-484a-870d-f1008169243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907768318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.907768318
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3182561890
Short name T466
Test name
Test status
Simulation time 63287093 ps
CPU time 0.59 seconds
Started Mar 17 01:32:59 PM PDT 24
Finished Mar 17 01:33:01 PM PDT 24
Peak memory 195804 kb
Host smart-7d511956-15d9-450c-8d82-3ab69123617e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182561890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3182561890
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3866336272
Short name T215
Test name
Test status
Simulation time 571429241 ps
CPU time 18.51 seconds
Started Mar 17 01:32:56 PM PDT 24
Finished Mar 17 01:33:15 PM PDT 24
Peak memory 208684 kb
Host smart-8a4587e2-74d4-432d-9d85-ca0b0c6188f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866336272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3866336272
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1542821005
Short name T541
Test name
Test status
Simulation time 10292101715 ps
CPU time 104.77 seconds
Started Mar 17 01:32:54 PM PDT 24
Finished Mar 17 01:34:39 PM PDT 24
Peak memory 200444 kb
Host smart-d804e85a-de01-42d3-bd3e-c83ebaa19090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1542821005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1542821005
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.435454221
Short name T47
Test name
Test status
Simulation time 2371098709 ps
CPU time 44.04 seconds
Started Mar 17 01:32:56 PM PDT 24
Finished Mar 17 01:33:40 PM PDT 24
Peak memory 200456 kb
Host smart-8d851b89-7131-4a98-8c36-5635810e5c65
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435454221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.435454221
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3733357884
Short name T123
Test name
Test status
Simulation time 9531902133 ps
CPU time 104.55 seconds
Started Mar 17 01:32:55 PM PDT 24
Finished Mar 17 01:34:40 PM PDT 24
Peak memory 200436 kb
Host smart-4a7fccdc-a439-462f-a0c3-a118efada51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733357884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3733357884
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1088880365
Short name T32
Test name
Test status
Simulation time 56778826 ps
CPU time 0.95 seconds
Started Mar 17 01:32:55 PM PDT 24
Finished Mar 17 01:32:56 PM PDT 24
Peak memory 218824 kb
Host smart-8e818c41-7e23-4baf-97c7-69619e5787d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088880365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1088880365
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3922304431
Short name T528
Test name
Test status
Simulation time 134123963 ps
CPU time 1.9 seconds
Started Mar 17 01:32:55 PM PDT 24
Finished Mar 17 01:32:57 PM PDT 24
Peak memory 200436 kb
Host smart-07f00c34-d0cd-41e9-a44a-8c4873619b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922304431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3922304431
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3840482326
Short name T352
Test name
Test status
Simulation time 13967505715 ps
CPU time 172.44 seconds
Started Mar 17 01:32:56 PM PDT 24
Finished Mar 17 01:35:48 PM PDT 24
Peak memory 200528 kb
Host smart-5eadfd25-43d3-480b-9c79-bddc71fe263c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840482326 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3840482326
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3662017056
Short name T126
Test name
Test status
Simulation time 87707445 ps
CPU time 1.04 seconds
Started Mar 17 01:32:56 PM PDT 24
Finished Mar 17 01:32:57 PM PDT 24
Peak memory 199536 kb
Host smart-48c30e08-78d8-46d7-bc30-858f3de4e2a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662017056 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.3662017056
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.935272087
Short name T397
Test name
Test status
Simulation time 66319978351 ps
CPU time 491.3 seconds
Started Mar 17 01:32:56 PM PDT 24
Finished Mar 17 01:41:08 PM PDT 24
Peak memory 200448 kb
Host smart-52871e75-47b8-45f2-bfb1-f7ffe49c8837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935272087 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.935272087
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3815213292
Short name T270
Test name
Test status
Simulation time 493792133 ps
CPU time 29.51 seconds
Started Mar 17 01:32:55 PM PDT 24
Finished Mar 17 01:33:24 PM PDT 24
Peak memory 200376 kb
Host smart-fc570d46-1dac-419c-bebf-3b31b8bef86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815213292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3815213292
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1762859413
Short name T464
Test name
Test status
Simulation time 16421672 ps
CPU time 0.59 seconds
Started Mar 17 01:33:32 PM PDT 24
Finished Mar 17 01:33:33 PM PDT 24
Peak memory 195684 kb
Host smart-10a24374-7549-40a7-b646-d378dcafd999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762859413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1762859413
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2278150472
Short name T213
Test name
Test status
Simulation time 965472295 ps
CPU time 30.69 seconds
Started Mar 17 01:33:26 PM PDT 24
Finished Mar 17 01:33:59 PM PDT 24
Peak memory 216036 kb
Host smart-18c21110-b5b2-4b3c-92f2-4091b93ae1fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2278150472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2278150472
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4240817481
Short name T116
Test name
Test status
Simulation time 9661074698 ps
CPU time 33.06 seconds
Started Mar 17 01:33:27 PM PDT 24
Finished Mar 17 01:34:02 PM PDT 24
Peak memory 200516 kb
Host smart-44c0db38-c6be-4727-bb0b-cc8f3305a86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240817481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4240817481
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.687574115
Short name T3
Test name
Test status
Simulation time 1421709753 ps
CPU time 79.02 seconds
Started Mar 17 01:33:24 PM PDT 24
Finished Mar 17 01:34:43 PM PDT 24
Peak memory 200360 kb
Host smart-fd270612-8e51-40a1-b293-d188fe861443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687574115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.687574115
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2058958534
Short name T80
Test name
Test status
Simulation time 3560682088 ps
CPU time 183.05 seconds
Started Mar 17 01:33:27 PM PDT 24
Finished Mar 17 01:36:32 PM PDT 24
Peak memory 200508 kb
Host smart-849cca44-2d59-44ec-bb77-2da23cf382a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058958534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2058958534
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.834126807
Short name T366
Test name
Test status
Simulation time 5749272351 ps
CPU time 22.21 seconds
Started Mar 17 01:33:26 PM PDT 24
Finished Mar 17 01:33:51 PM PDT 24
Peak memory 200504 kb
Host smart-2d5cfad4-8f82-4fbd-8bbd-df3e829a1577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834126807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.834126807
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1257691032
Short name T433
Test name
Test status
Simulation time 44569898 ps
CPU time 1.1 seconds
Started Mar 17 01:33:27 PM PDT 24
Finished Mar 17 01:33:30 PM PDT 24
Peak memory 200224 kb
Host smart-bd6ae385-432b-4b14-aeca-768f320c45ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257691032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1257691032
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2520362132
Short name T74
Test name
Test status
Simulation time 329876378564 ps
CPU time 2176.17 seconds
Started Mar 17 01:33:31 PM PDT 24
Finished Mar 17 02:09:48 PM PDT 24
Peak memory 225168 kb
Host smart-eb013e21-cee5-42ea-9dbf-c9a4868ac43a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520362132 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2520362132
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1735868542
Short name T331
Test name
Test status
Simulation time 149978382 ps
CPU time 1.31 seconds
Started Mar 17 01:33:31 PM PDT 24
Finished Mar 17 01:33:33 PM PDT 24
Peak memory 200348 kb
Host smart-df4970cb-acbe-40c2-a334-5e5f9a698f29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735868542 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1735868542
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1802853634
Short name T263
Test name
Test status
Simulation time 8677004177 ps
CPU time 465.6 seconds
Started Mar 17 01:33:24 PM PDT 24
Finished Mar 17 01:41:10 PM PDT 24
Peak memory 200420 kb
Host smart-5c6e794d-6772-489f-ab44-206c95dcd8f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802853634 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.1802853634
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.455643880
Short name T481
Test name
Test status
Simulation time 321593443 ps
CPU time 6.78 seconds
Started Mar 17 01:33:25 PM PDT 24
Finished Mar 17 01:33:35 PM PDT 24
Peak memory 200472 kb
Host smart-1d1437c6-679b-44ba-bad8-0f2e0b6bd0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455643880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.455643880
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.3098070183
Short name T66
Test name
Test status
Simulation time 20357986803 ps
CPU time 307.05 seconds
Started Mar 17 01:36:54 PM PDT 24
Finished Mar 17 01:42:02 PM PDT 24
Peak memory 229856 kb
Host smart-ac2e0e1a-67eb-4e42-9732-ea7ccdca1cb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098070183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.3098070183
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.878028332
Short name T309
Test name
Test status
Simulation time 26548480 ps
CPU time 0.56 seconds
Started Mar 17 01:33:33 PM PDT 24
Finished Mar 17 01:33:34 PM PDT 24
Peak memory 195544 kb
Host smart-aa4bef5d-ea89-42ae-96dc-5b62a353ebd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878028332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.878028332
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3170918975
Short name T588
Test name
Test status
Simulation time 10473599018 ps
CPU time 21.1 seconds
Started Mar 17 01:33:32 PM PDT 24
Finished Mar 17 01:33:53 PM PDT 24
Peak memory 244540 kb
Host smart-9971f613-baa7-4430-b779-fe2b205de8b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170918975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3170918975
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3958606514
Short name T208
Test name
Test status
Simulation time 1382980547 ps
CPU time 28.23 seconds
Started Mar 17 01:33:30 PM PDT 24
Finished Mar 17 01:33:59 PM PDT 24
Peak memory 200428 kb
Host smart-e710cbff-8f92-47a6-9650-3a7ed3b5f957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958606514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3958606514
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3750157524
Short name T278
Test name
Test status
Simulation time 3214030690 ps
CPU time 191.6 seconds
Started Mar 17 01:33:31 PM PDT 24
Finished Mar 17 01:36:43 PM PDT 24
Peak memory 200500 kb
Host smart-52679dd0-1527-41de-8a7e-796e955a42b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750157524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3750157524
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.4083588184
Short name T480
Test name
Test status
Simulation time 7899092954 ps
CPU time 214.31 seconds
Started Mar 17 01:33:30 PM PDT 24
Finished Mar 17 01:37:05 PM PDT 24
Peak memory 200488 kb
Host smart-ac1daa92-83cc-4429-a84f-423b5d6d1f39
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083588184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.4083588184
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2781225510
Short name T344
Test name
Test status
Simulation time 27719217890 ps
CPU time 90.92 seconds
Started Mar 17 01:33:32 PM PDT 24
Finished Mar 17 01:35:03 PM PDT 24
Peak memory 200588 kb
Host smart-100e3609-2af0-4556-b234-de26ec38d74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781225510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2781225510
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3751238319
Short name T34
Test name
Test status
Simulation time 377918031 ps
CPU time 4.73 seconds
Started Mar 17 01:33:33 PM PDT 24
Finished Mar 17 01:33:39 PM PDT 24
Peak memory 200440 kb
Host smart-18a0889b-61fd-41db-84ee-7c0cbee28298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751238319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3751238319
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2312009367
Short name T250
Test name
Test status
Simulation time 88928932758 ps
CPU time 1013.88 seconds
Started Mar 17 01:33:30 PM PDT 24
Finished Mar 17 01:50:25 PM PDT 24
Peak memory 228236 kb
Host smart-d52961e0-53dd-4984-9884-3e2b57e31f1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312009367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2312009367
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.831944934
Short name T518
Test name
Test status
Simulation time 352073265 ps
CPU time 1.22 seconds
Started Mar 17 01:33:33 PM PDT 24
Finished Mar 17 01:33:35 PM PDT 24
Peak memory 200484 kb
Host smart-e152dfb3-954c-432f-9abc-93ff6466461d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831944934 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.831944934
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2705568970
Short name T419
Test name
Test status
Simulation time 139631374963 ps
CPU time 481.47 seconds
Started Mar 17 01:33:33 PM PDT 24
Finished Mar 17 01:41:35 PM PDT 24
Peak memory 200420 kb
Host smart-922b00dd-1564-4dc7-a80d-94365515612b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705568970 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.2705568970
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.601433904
Short name T237
Test name
Test status
Simulation time 14496219277 ps
CPU time 72.8 seconds
Started Mar 17 01:33:37 PM PDT 24
Finished Mar 17 01:34:50 PM PDT 24
Peak memory 200440 kb
Host smart-4e9a5c8a-33f6-44c0-bc9c-7b6434d090d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601433904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.601433904
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.352970398
Short name T8
Test name
Test status
Simulation time 21897293991 ps
CPU time 1098.55 seconds
Started Mar 17 01:36:57 PM PDT 24
Finished Mar 17 01:55:16 PM PDT 24
Peak memory 217032 kb
Host smart-9ee55097-0b02-4ae6-a9b4-cd00ddef9a95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352970398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.352970398
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4065718187
Short name T214
Test name
Test status
Simulation time 46493192 ps
CPU time 0.59 seconds
Started Mar 17 01:33:34 PM PDT 24
Finished Mar 17 01:33:36 PM PDT 24
Peak memory 195508 kb
Host smart-457fddaf-de93-4386-b6b1-75d3004f2ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065718187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4065718187
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2625665668
Short name T224
Test name
Test status
Simulation time 1932565003 ps
CPU time 17.46 seconds
Started Mar 17 01:33:37 PM PDT 24
Finished Mar 17 01:33:56 PM PDT 24
Peak memory 208552 kb
Host smart-89bf6df4-3d49-4847-8606-d64f253e7260
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625665668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2625665668
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2368899152
Short name T219
Test name
Test status
Simulation time 3717028583 ps
CPU time 77.56 seconds
Started Mar 17 01:33:33 PM PDT 24
Finished Mar 17 01:34:52 PM PDT 24
Peak memory 200424 kb
Host smart-9cc54f78-2024-427e-8a10-8a96fd1f82f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368899152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2368899152
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2912581090
Short name T353
Test name
Test status
Simulation time 1877845024 ps
CPU time 116.34 seconds
Started Mar 17 01:33:37 PM PDT 24
Finished Mar 17 01:35:33 PM PDT 24
Peak memory 200372 kb
Host smart-a58717a3-4a9e-4d19-8aca-0f1b9198d717
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912581090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2912581090
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1338555877
Short name T372
Test name
Test status
Simulation time 17344072426 ps
CPU time 82.5 seconds
Started Mar 17 01:33:34 PM PDT 24
Finished Mar 17 01:34:58 PM PDT 24
Peak memory 200452 kb
Host smart-3f17b66e-ba04-419b-9c98-893cf76fe991
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338555877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1338555877
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1685802350
Short name T114
Test name
Test status
Simulation time 4749066783 ps
CPU time 69.85 seconds
Started Mar 17 01:33:33 PM PDT 24
Finished Mar 17 01:34:45 PM PDT 24
Peak memory 200504 kb
Host smart-fe5c92c8-3539-4509-9e40-1a25e3b7c32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685802350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1685802350
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.593858605
Short name T35
Test name
Test status
Simulation time 423390286 ps
CPU time 5.07 seconds
Started Mar 17 01:33:32 PM PDT 24
Finished Mar 17 01:33:37 PM PDT 24
Peak memory 200584 kb
Host smart-50aaee8d-0362-4f52-86ca-eeab7a7859a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593858605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.593858605
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2107532733
Short name T441
Test name
Test status
Simulation time 103352792387 ps
CPU time 640.39 seconds
Started Mar 17 01:33:31 PM PDT 24
Finished Mar 17 01:44:12 PM PDT 24
Peak memory 216212 kb
Host smart-a5680368-5e15-464c-af77-92192f37cb33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107532733 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2107532733
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2267045326
Short name T552
Test name
Test status
Simulation time 27349172 ps
CPU time 0.98 seconds
Started Mar 17 01:33:31 PM PDT 24
Finished Mar 17 01:33:33 PM PDT 24
Peak memory 199264 kb
Host smart-0310a1cb-5d94-40ca-a8f4-dbbbb8419e29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267045326 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2267045326
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2784156850
Short name T38
Test name
Test status
Simulation time 32607653015 ps
CPU time 460.58 seconds
Started Mar 17 01:33:33 PM PDT 24
Finished Mar 17 01:41:15 PM PDT 24
Peak memory 200468 kb
Host smart-5b1467c5-7ecd-4eda-8d04-fdbd94e0c623
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784156850 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2784156850
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.663595855
Short name T304
Test name
Test status
Simulation time 7792508658 ps
CPU time 77.71 seconds
Started Mar 17 01:33:31 PM PDT 24
Finished Mar 17 01:34:49 PM PDT 24
Peak memory 200576 kb
Host smart-9368c79d-ab11-4f8b-b761-56cdceb68724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663595855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.663595855
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.3905135594
Short name T10
Test name
Test status
Simulation time 214624247733 ps
CPU time 3098.43 seconds
Started Mar 17 01:36:58 PM PDT 24
Finished Mar 17 02:28:37 PM PDT 24
Peak memory 263288 kb
Host smart-55a0e37b-47de-48ef-883d-40351f481f40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905135594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.3905135594
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.703010851
Short name T177
Test name
Test status
Simulation time 163158319 ps
CPU time 0.57 seconds
Started Mar 17 01:33:32 PM PDT 24
Finished Mar 17 01:33:33 PM PDT 24
Peak memory 195916 kb
Host smart-fbd66ca6-a6b6-4d48-b967-69844a819352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703010851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.703010851
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2299162815
Short name T447
Test name
Test status
Simulation time 3273937515 ps
CPU time 45.86 seconds
Started Mar 17 01:33:33 PM PDT 24
Finished Mar 17 01:34:19 PM PDT 24
Peak memory 233172 kb
Host smart-f22f7d36-1bed-4b48-8c9f-01c4ade10dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299162815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2299162815
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3767993312
Short name T581
Test name
Test status
Simulation time 4298391200 ps
CPU time 36.04 seconds
Started Mar 17 01:33:37 PM PDT 24
Finished Mar 17 01:34:14 PM PDT 24
Peak memory 200436 kb
Host smart-797cca20-27e3-4f08-9f6e-6592b201647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767993312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3767993312
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.4153823031
Short name T131
Test name
Test status
Simulation time 9964886479 ps
CPU time 153.28 seconds
Started Mar 17 01:33:33 PM PDT 24
Finished Mar 17 01:36:07 PM PDT 24
Peak memory 200528 kb
Host smart-74e753a9-11f0-4600-8370-34307994b8be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4153823031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4153823031
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.618923981
Short name T448
Test name
Test status
Simulation time 16337382097 ps
CPU time 154.09 seconds
Started Mar 17 01:33:31 PM PDT 24
Finished Mar 17 01:36:06 PM PDT 24
Peak memory 200512 kb
Host smart-b4f495f3-173b-45f6-93b0-08e55ec55518
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618923981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.618923981
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.506600283
Short name T386
Test name
Test status
Simulation time 4969904747 ps
CPU time 48.65 seconds
Started Mar 17 01:33:38 PM PDT 24
Finished Mar 17 01:34:26 PM PDT 24
Peak memory 200460 kb
Host smart-24fd98a9-65aa-426b-9478-9cce95e7a3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506600283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.506600283
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.860038511
Short name T297
Test name
Test status
Simulation time 207308308 ps
CPU time 3.54 seconds
Started Mar 17 01:33:32 PM PDT 24
Finished Mar 17 01:33:36 PM PDT 24
Peak memory 200272 kb
Host smart-b3fb1a7e-8aaa-43bd-a098-2dd5185f192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860038511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.860038511
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2822389313
Short name T279
Test name
Test status
Simulation time 32012563001 ps
CPU time 1734.37 seconds
Started Mar 17 01:33:31 PM PDT 24
Finished Mar 17 02:02:26 PM PDT 24
Peak memory 224808 kb
Host smart-038c26a8-5811-4dd0-b348-d69ed8275aea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822389313 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2822389313
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.419314079
Short name T583
Test name
Test status
Simulation time 54438836 ps
CPU time 1.03 seconds
Started Mar 17 01:33:33 PM PDT 24
Finished Mar 17 01:33:34 PM PDT 24
Peak memory 199788 kb
Host smart-41cf1b96-9b55-4a51-9b9f-c0f7b849477c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419314079 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.419314079
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.881686308
Short name T236
Test name
Test status
Simulation time 50910323119 ps
CPU time 474.31 seconds
Started Mar 17 01:33:30 PM PDT 24
Finished Mar 17 01:41:25 PM PDT 24
Peak memory 200420 kb
Host smart-8c6c3bee-f7e9-45e2-81cd-c79fdc43bfee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881686308 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.881686308
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2868781496
Short name T239
Test name
Test status
Simulation time 53973579743 ps
CPU time 81.58 seconds
Started Mar 17 01:33:34 PM PDT 24
Finished Mar 17 01:34:57 PM PDT 24
Peak memory 200476 kb
Host smart-be0d1e76-a178-4ee4-83f0-a3768027ee6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868781496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2868781496
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.2144298800
Short name T11
Test name
Test status
Simulation time 130650212320 ps
CPU time 2683.25 seconds
Started Mar 17 01:37:03 PM PDT 24
Finished Mar 17 02:21:46 PM PDT 24
Peak memory 249592 kb
Host smart-da6c3123-018e-425a-8fff-ef7cd4ded282
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144298800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.2144298800
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.2858537266
Short name T574
Test name
Test status
Simulation time 15364245541 ps
CPU time 306.37 seconds
Started Mar 17 01:37:13 PM PDT 24
Finished Mar 17 01:42:20 PM PDT 24
Peak memory 241576 kb
Host smart-d325474a-ac61-4b91-b94a-de7316e1981e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858537266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.2858537266
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3333386246
Short name T55
Test name
Test status
Simulation time 52145998 ps
CPU time 0.59 seconds
Started Mar 17 01:33:37 PM PDT 24
Finished Mar 17 01:33:38 PM PDT 24
Peak memory 195936 kb
Host smart-461c518b-f423-43a3-9f8e-79ac77360dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333386246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3333386246
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3309137018
Short name T409
Test name
Test status
Simulation time 5559983868 ps
CPU time 54.82 seconds
Started Mar 17 01:33:35 PM PDT 24
Finished Mar 17 01:34:30 PM PDT 24
Peak memory 234364 kb
Host smart-8d4ca59d-5ea7-4bce-86de-045fcfe40137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309137018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3309137018
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3177897332
Short name T119
Test name
Test status
Simulation time 33783444397 ps
CPU time 37.32 seconds
Started Mar 17 01:33:36 PM PDT 24
Finished Mar 17 01:34:14 PM PDT 24
Peak memory 200512 kb
Host smart-2c594461-73dc-4a8b-b35d-1e2db9a85945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177897332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3177897332
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.677781490
Short name T357
Test name
Test status
Simulation time 1806474356 ps
CPU time 100.86 seconds
Started Mar 17 01:33:36 PM PDT 24
Finished Mar 17 01:35:17 PM PDT 24
Peak memory 200428 kb
Host smart-021e7512-f7e9-47d4-b076-194bb25d1e5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677781490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.677781490
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3353331047
Short name T520
Test name
Test status
Simulation time 8035908587 ps
CPU time 142.4 seconds
Started Mar 17 01:33:35 PM PDT 24
Finished Mar 17 01:35:58 PM PDT 24
Peak memory 200512 kb
Host smart-dbc8ce74-08be-4754-b62b-aa355ba5e956
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353331047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3353331047
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2684568176
Short name T462
Test name
Test status
Simulation time 40492330296 ps
CPU time 95.62 seconds
Started Mar 17 01:33:34 PM PDT 24
Finished Mar 17 01:35:11 PM PDT 24
Peak memory 200444 kb
Host smart-a3aef9ab-c115-447d-b79e-f8f935a1cbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684568176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2684568176
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.154133936
Short name T206
Test name
Test status
Simulation time 389796921 ps
CPU time 4.25 seconds
Started Mar 17 01:33:31 PM PDT 24
Finished Mar 17 01:33:36 PM PDT 24
Peak memory 200436 kb
Host smart-67ca60d8-22d4-41c9-a75f-b85a4d48c7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154133936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.154133936
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3812060091
Short name T535
Test name
Test status
Simulation time 321077125355 ps
CPU time 928.57 seconds
Started Mar 17 01:33:34 PM PDT 24
Finished Mar 17 01:49:04 PM PDT 24
Peak memory 200528 kb
Host smart-268e67a1-2b04-443b-99cf-0c81053affad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812060091 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3812060091
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.1442059269
Short name T7
Test name
Test status
Simulation time 387227813780 ps
CPU time 2219.31 seconds
Started Mar 17 01:33:36 PM PDT 24
Finished Mar 17 02:10:36 PM PDT 24
Peak memory 255752 kb
Host smart-2a614d0f-550f-4cfe-a980-673a908e07aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442059269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.1442059269
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2584306354
Short name T314
Test name
Test status
Simulation time 112113065 ps
CPU time 1.18 seconds
Started Mar 17 01:33:35 PM PDT 24
Finished Mar 17 01:33:37 PM PDT 24
Peak memory 200456 kb
Host smart-9f040337-54f1-4834-ae23-af926baff27a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584306354 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2584306354
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2772670310
Short name T381
Test name
Test status
Simulation time 107706127174 ps
CPU time 505.39 seconds
Started Mar 17 01:33:37 PM PDT 24
Finished Mar 17 01:42:02 PM PDT 24
Peak memory 200452 kb
Host smart-b2b694a9-e5e2-4b01-8427-62145ca8360f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772670310 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2772670310
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.131198295
Short name T269
Test name
Test status
Simulation time 1781724143 ps
CPU time 23.16 seconds
Started Mar 17 01:33:36 PM PDT 24
Finished Mar 17 01:33:59 PM PDT 24
Peak memory 200460 kb
Host smart-76fc5c5c-0d5e-4c94-aae9-b228c1dc56ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131198295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.131198295
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2040923269
Short name T311
Test name
Test status
Simulation time 31961303 ps
CPU time 0.58 seconds
Started Mar 17 01:33:43 PM PDT 24
Finished Mar 17 01:33:43 PM PDT 24
Peak memory 195876 kb
Host smart-ae4ec74c-687b-4e85-b634-a4be66313be3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040923269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2040923269
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3744543217
Short name T271
Test name
Test status
Simulation time 2064833100 ps
CPU time 19.33 seconds
Started Mar 17 01:33:42 PM PDT 24
Finished Mar 17 01:34:02 PM PDT 24
Peak memory 216236 kb
Host smart-64dcb7c5-b3f6-4003-af46-292a20437397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3744543217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3744543217
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1765223111
Short name T485
Test name
Test status
Simulation time 2165094808 ps
CPU time 56.42 seconds
Started Mar 17 01:33:41 PM PDT 24
Finished Mar 17 01:34:37 PM PDT 24
Peak memory 200428 kb
Host smart-1b646978-9d2f-41dc-a205-f8400f1b4fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765223111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1765223111
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1957470783
Short name T577
Test name
Test status
Simulation time 2886995467 ps
CPU time 25.3 seconds
Started Mar 17 01:33:42 PM PDT 24
Finished Mar 17 01:34:08 PM PDT 24
Peak memory 200528 kb
Host smart-05c19920-a88a-433b-86df-7e1f60d5b7cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957470783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1957470783
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2421509568
Short name T268
Test name
Test status
Simulation time 47577462136 ps
CPU time 220.28 seconds
Started Mar 17 01:33:40 PM PDT 24
Finished Mar 17 01:37:21 PM PDT 24
Peak memory 200516 kb
Host smart-5ba59d71-7a97-46d8-b8d0-0a1a0b82459d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421509568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2421509568
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3462941529
Short name T165
Test name
Test status
Simulation time 24107946439 ps
CPU time 125.01 seconds
Started Mar 17 01:33:40 PM PDT 24
Finished Mar 17 01:35:45 PM PDT 24
Peak memory 200532 kb
Host smart-267baeba-e68c-463f-9967-cfc0bee7c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462941529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3462941529
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2628310240
Short name T548
Test name
Test status
Simulation time 185305461 ps
CPU time 2.56 seconds
Started Mar 17 01:33:35 PM PDT 24
Finished Mar 17 01:33:39 PM PDT 24
Peak memory 200428 kb
Host smart-81b78d7d-7d35-4577-9b3e-de456af9f10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628310240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2628310240
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1886516881
Short name T500
Test name
Test status
Simulation time 4356733040 ps
CPU time 87.28 seconds
Started Mar 17 01:33:43 PM PDT 24
Finished Mar 17 01:35:10 PM PDT 24
Peak memory 200476 kb
Host smart-1edb4d89-bf53-4107-8a4a-8a5c1dfcdaf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886516881 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1886516881
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.89739705
Short name T261
Test name
Test status
Simulation time 97190421 ps
CPU time 1.12 seconds
Started Mar 17 01:33:42 PM PDT 24
Finished Mar 17 01:33:44 PM PDT 24
Peak memory 199816 kb
Host smart-b3d0354d-9c23-4689-b81f-ec3b171df35e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89739705 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.hmac_test_hmac_vectors.89739705
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1552682610
Short name T2
Test name
Test status
Simulation time 55009652322 ps
CPU time 412.2 seconds
Started Mar 17 01:33:41 PM PDT 24
Finished Mar 17 01:40:33 PM PDT 24
Peak memory 200504 kb
Host smart-8611b871-2f10-402f-a78f-2a8f98c884ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552682610 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.1552682610
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3214752089
Short name T591
Test name
Test status
Simulation time 70226921937 ps
CPU time 65.97 seconds
Started Mar 17 01:33:42 PM PDT 24
Finished Mar 17 01:34:49 PM PDT 24
Peak memory 200556 kb
Host smart-aa56c092-a935-4897-994d-a9db0b0b3077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214752089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3214752089
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.348544373
Short name T65
Test name
Test status
Simulation time 15330172373 ps
CPU time 209.89 seconds
Started Mar 17 01:37:14 PM PDT 24
Finished Mar 17 01:40:44 PM PDT 24
Peak memory 212724 kb
Host smart-ff1290d8-9423-46c3-af55-3c103529ec12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=348544373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.348544373
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2675995269
Short name T554
Test name
Test status
Simulation time 36514283 ps
CPU time 0.61 seconds
Started Mar 17 01:33:47 PM PDT 24
Finished Mar 17 01:33:48 PM PDT 24
Peak memory 195904 kb
Host smart-ab02552b-fe99-4a5e-99a9-16d88f60d151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675995269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2675995269
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1288356595
Short name T293
Test name
Test status
Simulation time 85437294 ps
CPU time 2.35 seconds
Started Mar 17 01:33:42 PM PDT 24
Finished Mar 17 01:33:45 PM PDT 24
Peak memory 208360 kb
Host smart-90ccd557-f84b-4c59-89d9-abeca3ef4627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288356595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1288356595
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.4082298649
Short name T258
Test name
Test status
Simulation time 5385583186 ps
CPU time 25.45 seconds
Started Mar 17 01:33:47 PM PDT 24
Finished Mar 17 01:34:13 PM PDT 24
Peak memory 200436 kb
Host smart-8de8f612-7559-4b17-91d0-3a40144dfb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082298649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4082298649
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3195276495
Short name T210
Test name
Test status
Simulation time 14942758073 ps
CPU time 95.33 seconds
Started Mar 17 01:33:42 PM PDT 24
Finished Mar 17 01:35:18 PM PDT 24
Peak memory 200240 kb
Host smart-c133cc4f-2262-451b-bc48-d2893843ff97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3195276495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3195276495
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.434264748
Short name T303
Test name
Test status
Simulation time 21513078171 ps
CPU time 105.49 seconds
Started Mar 17 01:33:41 PM PDT 24
Finished Mar 17 01:35:26 PM PDT 24
Peak memory 200536 kb
Host smart-c2cf7247-0452-4272-803b-01da71a349c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434264748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.434264748
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1422482617
Short name T174
Test name
Test status
Simulation time 19889092458 ps
CPU time 110 seconds
Started Mar 17 01:33:49 PM PDT 24
Finished Mar 17 01:35:39 PM PDT 24
Peak memory 200448 kb
Host smart-ea0b44f0-17f2-4dd1-8cc4-d22d2e8945c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422482617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1422482617
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2266581029
Short name T322
Test name
Test status
Simulation time 1537537179 ps
CPU time 6.3 seconds
Started Mar 17 01:33:48 PM PDT 24
Finished Mar 17 01:33:55 PM PDT 24
Peak memory 200392 kb
Host smart-16ef1675-ea7e-4905-9d64-ab7969bbb8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266581029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2266581029
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3771721313
Short name T245
Test name
Test status
Simulation time 206484287020 ps
CPU time 2007.33 seconds
Started Mar 17 01:33:44 PM PDT 24
Finished Mar 17 02:07:12 PM PDT 24
Peak memory 242520 kb
Host smart-c8784b5a-c1ae-4e75-9714-5962dacf3dda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771721313 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3771721313
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.199988713
Short name T290
Test name
Test status
Simulation time 149119689 ps
CPU time 1.45 seconds
Started Mar 17 01:33:46 PM PDT 24
Finished Mar 17 01:33:48 PM PDT 24
Peak memory 200232 kb
Host smart-95c96adf-5178-4dec-b92f-9dc8898dd949
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199988713 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_hmac_vectors.199988713
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.113618203
Short name T68
Test name
Test status
Simulation time 42333946814 ps
CPU time 416.71 seconds
Started Mar 17 01:33:47 PM PDT 24
Finished Mar 17 01:40:44 PM PDT 24
Peak memory 200476 kb
Host smart-b724b052-b55f-414c-bbe9-7a35d9a52b55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113618203 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.113618203
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1093968535
Short name T67
Test name
Test status
Simulation time 1962081235 ps
CPU time 7.3 seconds
Started Mar 17 01:33:49 PM PDT 24
Finished Mar 17 01:33:56 PM PDT 24
Peak memory 200392 kb
Host smart-039b9210-0a43-4c9d-a586-aaa68a3d82a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093968535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1093968535
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2520919709
Short name T350
Test name
Test status
Simulation time 14026660 ps
CPU time 0.59 seconds
Started Mar 17 01:33:52 PM PDT 24
Finished Mar 17 01:33:53 PM PDT 24
Peak memory 195892 kb
Host smart-f9e48e1e-a96a-46c4-bc05-037b1fcc9a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520919709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2520919709
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2519891283
Short name T255
Test name
Test status
Simulation time 2009195638 ps
CPU time 49.76 seconds
Started Mar 17 01:33:46 PM PDT 24
Finished Mar 17 01:34:36 PM PDT 24
Peak memory 232120 kb
Host smart-1095eb1f-aaee-41fc-9168-5c2546a49c60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519891283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2519891283
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2033202424
Short name T388
Test name
Test status
Simulation time 2196372037 ps
CPU time 53.42 seconds
Started Mar 17 01:33:46 PM PDT 24
Finished Mar 17 01:34:40 PM PDT 24
Peak memory 200488 kb
Host smart-713ac3af-1cbb-47fe-aa01-5e0827813c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033202424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2033202424
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3931214014
Short name T369
Test name
Test status
Simulation time 8939255572 ps
CPU time 142.25 seconds
Started Mar 17 01:33:45 PM PDT 24
Finished Mar 17 01:36:08 PM PDT 24
Peak memory 200464 kb
Host smart-7198035f-d3ef-408d-8fec-8f00efec82ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931214014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3931214014
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.422525761
Short name T512
Test name
Test status
Simulation time 11245216456 ps
CPU time 104.75 seconds
Started Mar 17 01:33:46 PM PDT 24
Finished Mar 17 01:35:31 PM PDT 24
Peak memory 200500 kb
Host smart-05ccc781-a45e-43a8-93d5-517eab912005
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422525761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.422525761
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.461995406
Short name T514
Test name
Test status
Simulation time 8267208606 ps
CPU time 73.89 seconds
Started Mar 17 01:33:45 PM PDT 24
Finished Mar 17 01:34:59 PM PDT 24
Peak memory 200428 kb
Host smart-44423907-9aae-4d48-a26e-09d9ab424900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461995406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.461995406
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1334383298
Short name T234
Test name
Test status
Simulation time 481156327 ps
CPU time 7.53 seconds
Started Mar 17 01:33:46 PM PDT 24
Finished Mar 17 01:33:54 PM PDT 24
Peak memory 200432 kb
Host smart-b9087a92-bbe9-4aaa-b03a-9eadd5118dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334383298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1334383298
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2160742187
Short name T238
Test name
Test status
Simulation time 1073292040825 ps
CPU time 1472.65 seconds
Started Mar 17 01:33:45 PM PDT 24
Finished Mar 17 01:58:18 PM PDT 24
Peak memory 208720 kb
Host smart-d3cdd2d2-b696-4cb0-8d14-0aaf73961a3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160742187 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2160742187
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3397264006
Short name T530
Test name
Test status
Simulation time 65898595 ps
CPU time 1.32 seconds
Started Mar 17 01:33:46 PM PDT 24
Finished Mar 17 01:33:48 PM PDT 24
Peak memory 200392 kb
Host smart-d47eb1b5-0543-4b4d-b2b9-c1e02ad384d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397264006 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3397264006
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2069193418
Short name T494
Test name
Test status
Simulation time 189834897664 ps
CPU time 589.91 seconds
Started Mar 17 01:33:46 PM PDT 24
Finished Mar 17 01:43:36 PM PDT 24
Peak memory 200444 kb
Host smart-9424bd7d-b5cc-4228-b937-7f06e2e408e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069193418 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2069193418
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3474716128
Short name T513
Test name
Test status
Simulation time 7918330681 ps
CPU time 70.67 seconds
Started Mar 17 01:33:46 PM PDT 24
Finished Mar 17 01:34:56 PM PDT 24
Peak memory 200504 kb
Host smart-cb95162d-52f2-4f64-ae44-ce274121b7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474716128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3474716128
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3388337835
Short name T256
Test name
Test status
Simulation time 30862721 ps
CPU time 0.57 seconds
Started Mar 17 01:33:53 PM PDT 24
Finished Mar 17 01:33:53 PM PDT 24
Peak memory 195880 kb
Host smart-9485ca63-9d9b-4f9e-b84f-73379bdd8fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388337835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3388337835
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2705564095
Short name T449
Test name
Test status
Simulation time 6514002311 ps
CPU time 64.74 seconds
Started Mar 17 01:33:52 PM PDT 24
Finished Mar 17 01:34:57 PM PDT 24
Peak memory 225052 kb
Host smart-ff791e53-f8a0-4c07-a0e5-56c6842014ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705564095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2705564095
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1730959978
Short name T265
Test name
Test status
Simulation time 2691084729 ps
CPU time 64.38 seconds
Started Mar 17 01:33:50 PM PDT 24
Finished Mar 17 01:34:54 PM PDT 24
Peak memory 200536 kb
Host smart-af9d0057-9853-4cc2-a728-60e5b6973c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730959978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1730959978
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2763194117
Short name T526
Test name
Test status
Simulation time 521877406 ps
CPU time 20.84 seconds
Started Mar 17 01:33:52 PM PDT 24
Finished Mar 17 01:34:13 PM PDT 24
Peak memory 200416 kb
Host smart-14f0ea2a-660f-47f9-857f-b3ad2f0b9358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763194117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2763194117
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3362840246
Short name T325
Test name
Test status
Simulation time 7929939766 ps
CPU time 87.95 seconds
Started Mar 17 01:33:52 PM PDT 24
Finished Mar 17 01:35:20 PM PDT 24
Peak memory 200540 kb
Host smart-335f668c-0859-44c3-9952-1bcd6c8b8c48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362840246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3362840246
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3008288065
Short name T156
Test name
Test status
Simulation time 3085062102 ps
CPU time 89.28 seconds
Started Mar 17 01:33:52 PM PDT 24
Finished Mar 17 01:35:21 PM PDT 24
Peak memory 200504 kb
Host smart-d63686f2-5b63-4c20-9b27-50cc417733fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008288065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3008288065
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2895013067
Short name T423
Test name
Test status
Simulation time 946634318 ps
CPU time 6.88 seconds
Started Mar 17 01:33:51 PM PDT 24
Finished Mar 17 01:33:58 PM PDT 24
Peak memory 200432 kb
Host smart-f7eedcf1-a920-4695-bc96-54abcdc713e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895013067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2895013067
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2649324304
Short name T596
Test name
Test status
Simulation time 5499506076 ps
CPU time 27.86 seconds
Started Mar 17 01:33:52 PM PDT 24
Finished Mar 17 01:34:20 PM PDT 24
Peak memory 200432 kb
Host smart-4da92ff2-90e2-4698-87e1-b8176bd3b5be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649324304 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2649324304
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.668440831
Short name T191
Test name
Test status
Simulation time 165884101 ps
CPU time 1.11 seconds
Started Mar 17 01:33:52 PM PDT 24
Finished Mar 17 01:33:53 PM PDT 24
Peak memory 200232 kb
Host smart-76e29cb4-af01-4163-9d5c-08dfd3e6dfd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668440831 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.668440831
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2529863039
Short name T316
Test name
Test status
Simulation time 31912549784 ps
CPU time 498.15 seconds
Started Mar 17 01:33:54 PM PDT 24
Finished Mar 17 01:42:12 PM PDT 24
Peak memory 200524 kb
Host smart-bae0be85-a0f1-4cca-a1be-321c8426fc8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529863039 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.2529863039
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1668100719
Short name T391
Test name
Test status
Simulation time 4238257708 ps
CPU time 14.48 seconds
Started Mar 17 01:33:52 PM PDT 24
Finished Mar 17 01:34:07 PM PDT 24
Peak memory 200496 kb
Host smart-3e543518-35bc-4fe6-bdfe-dd0fff835d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668100719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1668100719
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1789542552
Short name T312
Test name
Test status
Simulation time 54549258 ps
CPU time 0.62 seconds
Started Mar 17 01:34:02 PM PDT 24
Finished Mar 17 01:34:02 PM PDT 24
Peak memory 195860 kb
Host smart-68cc0bbe-dd28-4983-900b-424538ce9337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789542552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1789542552
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.241859184
Short name T211
Test name
Test status
Simulation time 914767337 ps
CPU time 45.98 seconds
Started Mar 17 01:34:03 PM PDT 24
Finished Mar 17 01:34:49 PM PDT 24
Peak memory 248352 kb
Host smart-a8add28a-5ea8-4ccb-83ea-1e8c0114ef2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=241859184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.241859184
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2278223138
Short name T85
Test name
Test status
Simulation time 486086923 ps
CPU time 19.38 seconds
Started Mar 17 01:33:59 PM PDT 24
Finished Mar 17 01:34:19 PM PDT 24
Peak memory 200396 kb
Host smart-c76a51d5-87ad-492a-9d94-2e78c7f23884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278223138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2278223138
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3817583004
Short name T251
Test name
Test status
Simulation time 8746066389 ps
CPU time 131.9 seconds
Started Mar 17 01:34:00 PM PDT 24
Finished Mar 17 01:36:12 PM PDT 24
Peak memory 200484 kb
Host smart-6c2f5074-e235-4b7c-9c06-f2c1d02132e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817583004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3817583004
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3385970404
Short name T46
Test name
Test status
Simulation time 8865789261 ps
CPU time 159.87 seconds
Started Mar 17 01:33:58 PM PDT 24
Finished Mar 17 01:36:39 PM PDT 24
Peak memory 200504 kb
Host smart-bd0617ea-d2e3-484b-917f-76882dfda7f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385970404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3385970404
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.87802106
Short name T375
Test name
Test status
Simulation time 1653704061 ps
CPU time 9.35 seconds
Started Mar 17 01:33:57 PM PDT 24
Finished Mar 17 01:34:07 PM PDT 24
Peak memory 200476 kb
Host smart-ba063626-e2af-4bb3-a951-7a8884b9497e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87802106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.87802106
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1046410169
Short name T442
Test name
Test status
Simulation time 182301201 ps
CPU time 5.82 seconds
Started Mar 17 01:33:53 PM PDT 24
Finished Mar 17 01:33:59 PM PDT 24
Peak memory 200444 kb
Host smart-70399ff9-b198-48d8-ae25-65b11f91b59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046410169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1046410169
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1684306847
Short name T202
Test name
Test status
Simulation time 45697547883 ps
CPU time 394.23 seconds
Started Mar 17 01:33:59 PM PDT 24
Finished Mar 17 01:40:34 PM PDT 24
Peak memory 200528 kb
Host smart-1c01c870-665a-4da1-99bb-f6034ca8f05a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684306847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1684306847
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1881123129
Short name T428
Test name
Test status
Simulation time 122903662 ps
CPU time 1 seconds
Started Mar 17 01:33:58 PM PDT 24
Finished Mar 17 01:33:59 PM PDT 24
Peak memory 198864 kb
Host smart-16258a88-670e-41d7-90ca-974ce3676510
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881123129 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1881123129
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1144666350
Short name T317
Test name
Test status
Simulation time 152157106407 ps
CPU time 507.32 seconds
Started Mar 17 01:34:01 PM PDT 24
Finished Mar 17 01:42:28 PM PDT 24
Peak memory 200420 kb
Host smart-f993b5f0-07a1-450d-89ea-2272cda11d38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144666350 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.1144666350
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2493495673
Short name T572
Test name
Test status
Simulation time 3579148480 ps
CPU time 73.89 seconds
Started Mar 17 01:33:59 PM PDT 24
Finished Mar 17 01:35:13 PM PDT 24
Peak memory 200488 kb
Host smart-99ce0cb8-9755-4368-8e56-b2b1c16ed8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493495673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2493495673
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.123584222
Short name T468
Test name
Test status
Simulation time 45781281 ps
CPU time 0.65 seconds
Started Mar 17 01:33:00 PM PDT 24
Finished Mar 17 01:33:01 PM PDT 24
Peak memory 195984 kb
Host smart-3e698acd-a3dd-497e-898b-2f530c57c8cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123584222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.123584222
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.29004973
Short name T193
Test name
Test status
Simulation time 2627903770 ps
CPU time 46.39 seconds
Started Mar 17 01:33:00 PM PDT 24
Finished Mar 17 01:33:47 PM PDT 24
Peak memory 208760 kb
Host smart-213e6efa-8243-4562-8ada-ed66437c960d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29004973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.29004973
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1855750956
Short name T171
Test name
Test status
Simulation time 7852298914 ps
CPU time 42.65 seconds
Started Mar 17 01:32:58 PM PDT 24
Finished Mar 17 01:33:42 PM PDT 24
Peak memory 200480 kb
Host smart-67858885-9550-4eb9-abba-0128dfbcbcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855750956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1855750956
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3688294328
Short name T54
Test name
Test status
Simulation time 1145520436 ps
CPU time 24.62 seconds
Started Mar 17 01:32:59 PM PDT 24
Finished Mar 17 01:33:24 PM PDT 24
Peak memory 200416 kb
Host smart-11ccc305-2b29-47f6-b67b-3db40fdae472
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3688294328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3688294328
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3031628616
Short name T42
Test name
Test status
Simulation time 811159150 ps
CPU time 49.73 seconds
Started Mar 17 01:33:02 PM PDT 24
Finished Mar 17 01:33:52 PM PDT 24
Peak memory 200428 kb
Host smart-ea7ff0fe-9f00-4c96-b9e1-4a1a8ba43433
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031628616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3031628616
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1584720083
Short name T411
Test name
Test status
Simulation time 13812776784 ps
CPU time 59.33 seconds
Started Mar 17 01:33:00 PM PDT 24
Finished Mar 17 01:34:00 PM PDT 24
Peak memory 200456 kb
Host smart-04ef9132-c78c-465e-9798-7c15f89299b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584720083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1584720083
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3172974476
Short name T30
Test name
Test status
Simulation time 38091048 ps
CPU time 0.83 seconds
Started Mar 17 01:33:00 PM PDT 24
Finished Mar 17 01:33:01 PM PDT 24
Peak memory 218888 kb
Host smart-372f3e47-a63b-4357-961d-d62f777bfbc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172974476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3172974476
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.13114587
Short name T27
Test name
Test status
Simulation time 144603261 ps
CPU time 4.65 seconds
Started Mar 17 01:33:02 PM PDT 24
Finished Mar 17 01:33:07 PM PDT 24
Peak memory 200456 kb
Host smart-8b90f6f7-4151-4819-8887-6a1cf5abff4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13114587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.13114587
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2430268253
Short name T439
Test name
Test status
Simulation time 159483189855 ps
CPU time 487.13 seconds
Started Mar 17 01:33:02 PM PDT 24
Finished Mar 17 01:41:09 PM PDT 24
Peak memory 200524 kb
Host smart-0d3eb049-74c4-4259-965f-1f342b314a85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430268253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2430268253
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3327808484
Short name T356
Test name
Test status
Simulation time 175984910 ps
CPU time 1.05 seconds
Started Mar 17 01:33:00 PM PDT 24
Finished Mar 17 01:33:02 PM PDT 24
Peak memory 198300 kb
Host smart-d2e4e5b6-c462-4e40-9fb8-4c4816be32f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327808484 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.3327808484
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3256124737
Short name T194
Test name
Test status
Simulation time 126725823754 ps
CPU time 429.18 seconds
Started Mar 17 01:33:01 PM PDT 24
Finished Mar 17 01:40:11 PM PDT 24
Peak memory 200400 kb
Host smart-e9f6ee02-477e-4239-b0ed-cea12cae91ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256124737 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.3256124737
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2823676095
Short name T532
Test name
Test status
Simulation time 1625338202 ps
CPU time 64.92 seconds
Started Mar 17 01:32:59 PM PDT 24
Finished Mar 17 01:34:04 PM PDT 24
Peak memory 200468 kb
Host smart-b72b37af-bda2-4a1b-b112-43ceb2f5a67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823676095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2823676095
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1644807202
Short name T544
Test name
Test status
Simulation time 511972435 ps
CPU time 17.61 seconds
Started Mar 17 01:34:01 PM PDT 24
Finished Mar 17 01:34:18 PM PDT 24
Peak memory 208584 kb
Host smart-dbd73796-1255-4844-bd8e-76c26382bbde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644807202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1644807202
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.918174151
Short name T143
Test name
Test status
Simulation time 1790426214 ps
CPU time 43.5 seconds
Started Mar 17 01:34:10 PM PDT 24
Finished Mar 17 01:34:53 PM PDT 24
Peak memory 200448 kb
Host smart-cc2743a8-3e10-465d-bc20-6461089cda67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918174151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.918174151
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1739439131
Short name T212
Test name
Test status
Simulation time 3219803076 ps
CPU time 64.47 seconds
Started Mar 17 01:34:02 PM PDT 24
Finished Mar 17 01:35:07 PM PDT 24
Peak memory 200464 kb
Host smart-9c7f3eaa-f0ab-43de-93f8-bf9fdf05fd2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739439131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1739439131
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.623058314
Short name T144
Test name
Test status
Simulation time 15227973912 ps
CPU time 88.29 seconds
Started Mar 17 01:34:09 PM PDT 24
Finished Mar 17 01:35:37 PM PDT 24
Peak memory 200460 kb
Host smart-a079be46-90ab-4d5d-9261-aa6a62d6bfa5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623058314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.623058314
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2570129337
Short name T186
Test name
Test status
Simulation time 10047480264 ps
CPU time 54.18 seconds
Started Mar 17 01:34:03 PM PDT 24
Finished Mar 17 01:34:58 PM PDT 24
Peak memory 200484 kb
Host smart-3f7b2044-fef5-4a93-a4fc-350f55632358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570129337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2570129337
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.880404348
Short name T296
Test name
Test status
Simulation time 336657126 ps
CPU time 3.17 seconds
Started Mar 17 01:34:04 PM PDT 24
Finished Mar 17 01:34:07 PM PDT 24
Peak memory 200392 kb
Host smart-3d2c0e23-ef83-4187-8416-ea8dc63c215f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880404348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.880404348
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.490294946
Short name T73
Test name
Test status
Simulation time 468424790420 ps
CPU time 942.78 seconds
Started Mar 17 01:34:09 PM PDT 24
Finished Mar 17 01:49:52 PM PDT 24
Peak memory 208756 kb
Host smart-3e9a319c-ae04-46b8-84bd-8fc78ef230d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490294946 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.490294946
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3040133507
Short name T275
Test name
Test status
Simulation time 133025545 ps
CPU time 1.09 seconds
Started Mar 17 01:34:09 PM PDT 24
Finished Mar 17 01:34:10 PM PDT 24
Peak memory 199776 kb
Host smart-5f203f0c-378f-4e9a-8661-37931f269c46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040133507 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3040133507
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1971248020
Short name T587
Test name
Test status
Simulation time 105501243435 ps
CPU time 527.88 seconds
Started Mar 17 01:34:08 PM PDT 24
Finished Mar 17 01:42:56 PM PDT 24
Peak memory 200420 kb
Host smart-6d296138-b7d8-471a-aacf-a336e0b2675b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971248020 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.1971248020
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1853101001
Short name T128
Test name
Test status
Simulation time 3742081838 ps
CPU time 39.32 seconds
Started Mar 17 01:34:09 PM PDT 24
Finished Mar 17 01:34:48 PM PDT 24
Peak memory 200544 kb
Host smart-48d11f26-2731-42f3-babf-416161941576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853101001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1853101001
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1189287340
Short name T20
Test name
Test status
Simulation time 25247876 ps
CPU time 0.62 seconds
Started Mar 17 01:34:17 PM PDT 24
Finished Mar 17 01:34:18 PM PDT 24
Peak memory 195808 kb
Host smart-acb28530-6d11-4c68-b02e-02dde6f97d1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189287340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1189287340
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.878997580
Short name T52
Test name
Test status
Simulation time 1624387106 ps
CPU time 15.75 seconds
Started Mar 17 01:34:08 PM PDT 24
Finished Mar 17 01:34:24 PM PDT 24
Peak memory 208692 kb
Host smart-c1f22724-24fc-44a2-aad9-982dd8d82db9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=878997580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.878997580
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3617695608
Short name T184
Test name
Test status
Simulation time 1123397121 ps
CPU time 58.72 seconds
Started Mar 17 01:34:08 PM PDT 24
Finished Mar 17 01:35:07 PM PDT 24
Peak memory 200432 kb
Host smart-da477443-0e7c-49e7-95b2-22aaf3a00384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617695608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3617695608
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.280111089
Short name T294
Test name
Test status
Simulation time 4499876006 ps
CPU time 153.96 seconds
Started Mar 17 01:34:08 PM PDT 24
Finished Mar 17 01:36:42 PM PDT 24
Peak memory 200480 kb
Host smart-fc34e98a-a797-4fda-9af6-269217fee3a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280111089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.280111089
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2652397132
Short name T14
Test name
Test status
Simulation time 20414206644 ps
CPU time 110.03 seconds
Started Mar 17 01:34:07 PM PDT 24
Finished Mar 17 01:35:57 PM PDT 24
Peak memory 200552 kb
Host smart-01b7ec4e-bed0-4cf3-a573-d4332e3bea93
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652397132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2652397132
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3297696428
Short name T457
Test name
Test status
Simulation time 2202831142 ps
CPU time 67.18 seconds
Started Mar 17 01:34:08 PM PDT 24
Finished Mar 17 01:35:16 PM PDT 24
Peak memory 200480 kb
Host smart-fd3b0cd5-10bf-4384-91cb-203b647d20fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297696428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3297696428
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.967231829
Short name T289
Test name
Test status
Simulation time 220476477 ps
CPU time 3.03 seconds
Started Mar 17 01:34:07 PM PDT 24
Finished Mar 17 01:34:10 PM PDT 24
Peak memory 200396 kb
Host smart-f4c55f10-1c87-4a92-9f2b-8a141f0f3c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967231829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.967231829
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3213176799
Short name T242
Test name
Test status
Simulation time 207546551063 ps
CPU time 1118.92 seconds
Started Mar 17 01:34:15 PM PDT 24
Finished Mar 17 01:52:55 PM PDT 24
Peak memory 249460 kb
Host smart-8cbfba8d-9aad-49e8-8f39-020a37ca3964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213176799 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3213176799
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.123310082
Short name T64
Test name
Test status
Simulation time 76995114939 ps
CPU time 1279.41 seconds
Started Mar 17 01:34:14 PM PDT 24
Finished Mar 17 01:55:34 PM PDT 24
Peak memory 248208 kb
Host smart-d4f4c4a3-f423-499c-9304-c8b37686dba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123310082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.123310082
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.452422756
Short name T272
Test name
Test status
Simulation time 292505464 ps
CPU time 1.37 seconds
Started Mar 17 01:34:14 PM PDT 24
Finished Mar 17 01:34:16 PM PDT 24
Peak memory 200476 kb
Host smart-4f262bb7-12a8-41ff-8a9d-295ff7066113
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452422756 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.452422756
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.401498740
Short name T198
Test name
Test status
Simulation time 261197595674 ps
CPU time 473.36 seconds
Started Mar 17 01:34:15 PM PDT 24
Finished Mar 17 01:42:09 PM PDT 24
Peak memory 200580 kb
Host smart-c1446a85-9aa1-4bd6-9038-683f43961514
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401498740 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.401498740
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.296917029
Short name T319
Test name
Test status
Simulation time 10933327736 ps
CPU time 53.41 seconds
Started Mar 17 01:34:08 PM PDT 24
Finished Mar 17 01:35:02 PM PDT 24
Peak memory 200588 kb
Host smart-15d87702-c64f-4e3c-9e2a-1d4620df4b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296917029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.296917029
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.733798219
Short name T396
Test name
Test status
Simulation time 12474193 ps
CPU time 0.58 seconds
Started Mar 17 01:34:17 PM PDT 24
Finished Mar 17 01:34:18 PM PDT 24
Peak memory 194900 kb
Host smart-5452ed37-3be8-458b-a712-15cb8dd4cbda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733798219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.733798219
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1825297525
Short name T51
Test name
Test status
Simulation time 2245167455 ps
CPU time 45.36 seconds
Started Mar 17 01:34:13 PM PDT 24
Finished Mar 17 01:34:59 PM PDT 24
Peak memory 225548 kb
Host smart-94cf781b-7b45-42d4-bd9c-0aaf2e8f49ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825297525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1825297525
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3036375103
Short name T163
Test name
Test status
Simulation time 17219976444 ps
CPU time 56.43 seconds
Started Mar 17 01:34:13 PM PDT 24
Finished Mar 17 01:35:10 PM PDT 24
Peak memory 200512 kb
Host smart-b74fd751-da77-4e32-aa54-be3b187d2e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036375103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3036375103
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3950688523
Short name T410
Test name
Test status
Simulation time 17964106 ps
CPU time 0.65 seconds
Started Mar 17 01:34:14 PM PDT 24
Finished Mar 17 01:34:14 PM PDT 24
Peak memory 197580 kb
Host smart-58e4f797-17ef-49a7-b114-89a8707b596e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3950688523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3950688523
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2569063796
Short name T178
Test name
Test status
Simulation time 2470939950 ps
CPU time 148.45 seconds
Started Mar 17 01:34:13 PM PDT 24
Finished Mar 17 01:36:42 PM PDT 24
Peak memory 200512 kb
Host smart-a2009301-6f33-4132-a89d-7b3e28e19b68
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569063796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2569063796
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1999883320
Short name T138
Test name
Test status
Simulation time 5021234261 ps
CPU time 67.18 seconds
Started Mar 17 01:34:15 PM PDT 24
Finished Mar 17 01:35:22 PM PDT 24
Peak memory 200516 kb
Host smart-6a04695e-cdba-4510-99f9-1378ae4254c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999883320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1999883320
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3980473573
Short name T130
Test name
Test status
Simulation time 904493641 ps
CPU time 2.77 seconds
Started Mar 17 01:34:14 PM PDT 24
Finished Mar 17 01:34:16 PM PDT 24
Peak memory 200340 kb
Host smart-c0ae70ae-5c6c-4e05-ad1b-e0ef4b730972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980473573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3980473573
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3967198225
Short name T483
Test name
Test status
Simulation time 37986985455 ps
CPU time 577.88 seconds
Started Mar 17 01:34:16 PM PDT 24
Finished Mar 17 01:43:54 PM PDT 24
Peak memory 200512 kb
Host smart-dcfb2cfe-dab5-4e57-a69d-50f4d5237e78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967198225 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3967198225
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2202712760
Short name T360
Test name
Test status
Simulation time 70888773 ps
CPU time 1.3 seconds
Started Mar 17 01:34:15 PM PDT 24
Finished Mar 17 01:34:16 PM PDT 24
Peak memory 200560 kb
Host smart-e27c1524-a516-44f3-bcf3-328993123fa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202712760 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2202712760
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.6728611
Short name T295
Test name
Test status
Simulation time 34322642273 ps
CPU time 466.34 seconds
Started Mar 17 01:34:18 PM PDT 24
Finished Mar 17 01:42:04 PM PDT 24
Peak memory 200488 kb
Host smart-a1306992-67d9-4ae5-888a-5c92029feafc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6728611 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.6728611
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.388561375
Short name T120
Test name
Test status
Simulation time 890176013 ps
CPU time 33.13 seconds
Started Mar 17 01:34:14 PM PDT 24
Finished Mar 17 01:34:48 PM PDT 24
Peak memory 200468 kb
Host smart-b8bdc8ef-7952-4a49-8ec7-28bb66b4cfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388561375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.388561375
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.689938448
Short name T525
Test name
Test status
Simulation time 95904248 ps
CPU time 0.59 seconds
Started Mar 17 01:34:20 PM PDT 24
Finished Mar 17 01:34:21 PM PDT 24
Peak memory 195908 kb
Host smart-f32ec68f-f13d-42de-9f63-b9a1c3307f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689938448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.689938448
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1670747882
Short name T534
Test name
Test status
Simulation time 972120978 ps
CPU time 37.42 seconds
Started Mar 17 01:34:17 PM PDT 24
Finished Mar 17 01:34:55 PM PDT 24
Peak memory 231796 kb
Host smart-b8af89f6-f33e-4044-b595-ea21c871a970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670747882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1670747882
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2272042884
Short name T477
Test name
Test status
Simulation time 636261622 ps
CPU time 31.83 seconds
Started Mar 17 01:34:15 PM PDT 24
Finished Mar 17 01:34:47 PM PDT 24
Peak memory 200408 kb
Host smart-e1f201d1-84ee-4c9f-88c3-a9a32564e4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272042884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2272042884
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3228538125
Short name T168
Test name
Test status
Simulation time 5245812143 ps
CPU time 96.05 seconds
Started Mar 17 01:34:18 PM PDT 24
Finished Mar 17 01:35:54 PM PDT 24
Peak memory 200580 kb
Host smart-1a393b94-f912-4126-b39e-c79d66f130db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228538125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3228538125
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3758105934
Short name T220
Test name
Test status
Simulation time 7595328564 ps
CPU time 101.97 seconds
Started Mar 17 01:34:15 PM PDT 24
Finished Mar 17 01:35:58 PM PDT 24
Peak memory 200464 kb
Host smart-424faa16-735d-4dde-b3ed-449dfceae93c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758105934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3758105934
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1812706612
Short name T501
Test name
Test status
Simulation time 2829006973 ps
CPU time 60.85 seconds
Started Mar 17 01:34:18 PM PDT 24
Finished Mar 17 01:35:19 PM PDT 24
Peak memory 200588 kb
Host smart-e3dee6bf-1902-45a3-aede-452dc43be039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812706612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1812706612
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2346169529
Short name T413
Test name
Test status
Simulation time 287250479 ps
CPU time 4.84 seconds
Started Mar 17 01:34:17 PM PDT 24
Finished Mar 17 01:34:22 PM PDT 24
Peak memory 200424 kb
Host smart-e494ce26-9af5-4e80-9c3e-7d3fec48d94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346169529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2346169529
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2406198020
Short name T140
Test name
Test status
Simulation time 44550448123 ps
CPU time 2455.13 seconds
Started Mar 17 01:34:19 PM PDT 24
Finished Mar 17 02:15:14 PM PDT 24
Peak memory 200504 kb
Host smart-79e9fa0c-b069-40d4-8c31-c1d0b951cd44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406198020 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2406198020
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.526401030
Short name T129
Test name
Test status
Simulation time 263493413 ps
CPU time 1.33 seconds
Started Mar 17 01:34:21 PM PDT 24
Finished Mar 17 01:34:22 PM PDT 24
Peak memory 200432 kb
Host smart-9a60807b-1cbd-42ef-ba3d-b76d818b2cb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526401030 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.526401030
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3945719886
Short name T502
Test name
Test status
Simulation time 7912082354 ps
CPU time 466.42 seconds
Started Mar 17 01:34:16 PM PDT 24
Finished Mar 17 01:42:03 PM PDT 24
Peak memory 200424 kb
Host smart-9031536c-7283-4db3-b8a3-ed90d8ce65d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945719886 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3945719886
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2602683734
Short name T440
Test name
Test status
Simulation time 1633357912 ps
CPU time 14.46 seconds
Started Mar 17 01:34:16 PM PDT 24
Finished Mar 17 01:34:30 PM PDT 24
Peak memory 200456 kb
Host smart-f0a6334b-73bf-4e7f-8769-5633b3a950c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602683734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2602683734
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.361450357
Short name T476
Test name
Test status
Simulation time 15905239 ps
CPU time 0.61 seconds
Started Mar 17 01:34:26 PM PDT 24
Finished Mar 17 01:34:27 PM PDT 24
Peak memory 195912 kb
Host smart-ca940f51-fbe6-40c2-8aad-6c6193e9702f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361450357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.361450357
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.373881426
Short name T435
Test name
Test status
Simulation time 1455589260 ps
CPU time 13.21 seconds
Started Mar 17 01:34:18 PM PDT 24
Finished Mar 17 01:34:32 PM PDT 24
Peak memory 216608 kb
Host smart-94c81ef9-fcb9-4d62-bd68-efe48defb329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373881426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.373881426
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.4206534063
Short name T83
Test name
Test status
Simulation time 1976065128 ps
CPU time 27.52 seconds
Started Mar 17 01:34:20 PM PDT 24
Finished Mar 17 01:34:48 PM PDT 24
Peak memory 200460 kb
Host smart-59c5fcba-1a5a-49cb-9b36-ba468151eb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206534063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.4206534063
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.518208439
Short name T355
Test name
Test status
Simulation time 1542519914 ps
CPU time 94.44 seconds
Started Mar 17 01:34:21 PM PDT 24
Finished Mar 17 01:35:56 PM PDT 24
Peak memory 200364 kb
Host smart-c9fdb7d3-306a-439d-8c25-f79421771d4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518208439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.518208439
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.378978344
Short name T549
Test name
Test status
Simulation time 52094759018 ps
CPU time 221.96 seconds
Started Mar 17 01:34:19 PM PDT 24
Finished Mar 17 01:38:02 PM PDT 24
Peak memory 200472 kb
Host smart-3c937300-87eb-41b1-bcee-0d5bd6a16a09
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378978344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.378978344
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2681046234
Short name T189
Test name
Test status
Simulation time 2316366844 ps
CPU time 31.91 seconds
Started Mar 17 01:34:20 PM PDT 24
Finished Mar 17 01:34:53 PM PDT 24
Peak memory 200508 kb
Host smart-c0e1ae22-12f9-4281-b259-b9f424a938db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681046234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2681046234
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2591162063
Short name T578
Test name
Test status
Simulation time 69913175 ps
CPU time 1.07 seconds
Started Mar 17 01:34:19 PM PDT 24
Finished Mar 17 01:34:21 PM PDT 24
Peak memory 200136 kb
Host smart-ba9e5705-ce72-42d1-bb50-6c646ec26f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591162063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2591162063
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2136553827
Short name T456
Test name
Test status
Simulation time 349518617140 ps
CPU time 1165.58 seconds
Started Mar 17 01:34:25 PM PDT 24
Finished Mar 17 01:53:51 PM PDT 24
Peak memory 200524 kb
Host smart-fefc5ce9-179f-4ec7-95bd-eee0e7412801
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136553827 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2136553827
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1301962599
Short name T328
Test name
Test status
Simulation time 237853454 ps
CPU time 1.27 seconds
Started Mar 17 01:34:25 PM PDT 24
Finished Mar 17 01:34:26 PM PDT 24
Peak memory 200188 kb
Host smart-1ae0e884-8388-43ec-8c4b-ed03226ba27e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301962599 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1301962599
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3428700546
Short name T181
Test name
Test status
Simulation time 436934775802 ps
CPU time 471.69 seconds
Started Mar 17 01:34:26 PM PDT 24
Finished Mar 17 01:42:18 PM PDT 24
Peak memory 200436 kb
Host smart-4fdf6cef-1947-400f-a3d4-8b4d03f4e337
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428700546 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3428700546
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3169711911
Short name T487
Test name
Test status
Simulation time 8557079802 ps
CPU time 60.68 seconds
Started Mar 17 01:34:25 PM PDT 24
Finished Mar 17 01:35:26 PM PDT 24
Peak memory 200484 kb
Host smart-4e9f83c3-a7c4-4db6-b023-432c9e0fec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169711911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3169711911
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2460936243
Short name T21
Test name
Test status
Simulation time 15121768 ps
CPU time 0.6 seconds
Started Mar 17 01:34:34 PM PDT 24
Finished Mar 17 01:34:38 PM PDT 24
Peak memory 195924 kb
Host smart-051b32a6-e256-4033-af47-b1d0f441a87b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460936243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2460936243
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.465834558
Short name T546
Test name
Test status
Simulation time 344605634 ps
CPU time 11.79 seconds
Started Mar 17 01:34:26 PM PDT 24
Finished Mar 17 01:34:37 PM PDT 24
Peak memory 215824 kb
Host smart-eba49568-3ba0-471c-b3df-965da91f3c79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465834558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.465834558
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3738916307
Short name T445
Test name
Test status
Simulation time 4860495709 ps
CPU time 37.96 seconds
Started Mar 17 01:34:26 PM PDT 24
Finished Mar 17 01:35:04 PM PDT 24
Peak memory 200476 kb
Host smart-c857224b-8866-410b-bbfa-6b170e673b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738916307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3738916307
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.711425065
Short name T489
Test name
Test status
Simulation time 737587192 ps
CPU time 41.28 seconds
Started Mar 17 01:34:27 PM PDT 24
Finished Mar 17 01:35:08 PM PDT 24
Peak memory 200508 kb
Host smart-bae0249b-1553-483b-a69d-ad647b9a3255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=711425065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.711425065
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3301482435
Short name T421
Test name
Test status
Simulation time 82117777307 ps
CPU time 139.61 seconds
Started Mar 17 01:34:26 PM PDT 24
Finished Mar 17 01:36:45 PM PDT 24
Peak memory 200540 kb
Host smart-ad1aca5c-7bb5-426d-a756-3fa305f460bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301482435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3301482435
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1233786827
Short name T167
Test name
Test status
Simulation time 40546570208 ps
CPU time 114.02 seconds
Started Mar 17 01:34:24 PM PDT 24
Finished Mar 17 01:36:19 PM PDT 24
Peak memory 200472 kb
Host smart-e00138c9-a1a9-4c3c-9da1-4cd428e9d848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233786827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1233786827
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.940675654
Short name T257
Test name
Test status
Simulation time 606771750 ps
CPU time 6.2 seconds
Started Mar 17 01:34:24 PM PDT 24
Finished Mar 17 01:34:30 PM PDT 24
Peak memory 200412 kb
Host smart-73f0a4d6-f430-4665-83d7-aa8b5e7d27f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940675654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.940675654
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.601918742
Short name T136
Test name
Test status
Simulation time 37642805176 ps
CPU time 663.53 seconds
Started Mar 17 01:34:33 PM PDT 24
Finished Mar 17 01:45:37 PM PDT 24
Peak memory 221788 kb
Host smart-2ddbe21a-5b96-4eb8-8fbd-f69f6dd578e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601918742 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.601918742
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3470980846
Short name T146
Test name
Test status
Simulation time 103797104 ps
CPU time 1.22 seconds
Started Mar 17 01:34:31 PM PDT 24
Finished Mar 17 01:34:34 PM PDT 24
Peak memory 200408 kb
Host smart-0ea3b3e8-e7d1-4ad9-8aae-d5cdfdf68b47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470980846 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3470980846
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.1034068464
Short name T162
Test name
Test status
Simulation time 8428468450 ps
CPU time 488.27 seconds
Started Mar 17 01:34:31 PM PDT 24
Finished Mar 17 01:42:40 PM PDT 24
Peak memory 200368 kb
Host smart-9d8b7903-e2bd-4e81-bc88-3b857e301deb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034068464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.1034068464
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.146020946
Short name T22
Test name
Test status
Simulation time 844657916 ps
CPU time 16.56 seconds
Started Mar 17 01:34:32 PM PDT 24
Finished Mar 17 01:34:50 PM PDT 24
Peak memory 200476 kb
Host smart-ab763620-02a5-4ee4-b1b6-53447389d76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146020946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.146020946
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.170512034
Short name T158
Test name
Test status
Simulation time 73360143 ps
CPU time 0.58 seconds
Started Mar 17 01:34:43 PM PDT 24
Finished Mar 17 01:34:44 PM PDT 24
Peak memory 195932 kb
Host smart-abc4efa0-2278-4984-a844-b0a1ddbc975c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170512034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.170512034
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3249412286
Short name T260
Test name
Test status
Simulation time 1368507518 ps
CPU time 25.26 seconds
Started Mar 17 01:34:31 PM PDT 24
Finished Mar 17 01:34:57 PM PDT 24
Peak memory 216688 kb
Host smart-7c30e375-14b6-4dd5-a154-6b2500e3be84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249412286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3249412286
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1301056964
Short name T342
Test name
Test status
Simulation time 2376076386 ps
CPU time 35.53 seconds
Started Mar 17 01:34:34 PM PDT 24
Finished Mar 17 01:35:13 PM PDT 24
Peak memory 200448 kb
Host smart-d8119ab7-73e8-4dd6-b6bd-d91443b0a7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301056964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1301056964
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2795984935
Short name T343
Test name
Test status
Simulation time 1614585175 ps
CPU time 92.83 seconds
Started Mar 17 01:34:33 PM PDT 24
Finished Mar 17 01:36:06 PM PDT 24
Peak memory 200436 kb
Host smart-8c55926d-75e5-4d36-9aea-c0c19d9d667f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2795984935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2795984935
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3961846148
Short name T26
Test name
Test status
Simulation time 10881645301 ps
CPU time 144.53 seconds
Started Mar 17 01:34:33 PM PDT 24
Finished Mar 17 01:36:58 PM PDT 24
Peak memory 200504 kb
Host smart-9b6e19a7-861f-4dd4-a1a8-032bcb836688
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961846148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3961846148
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.375101401
Short name T170
Test name
Test status
Simulation time 3074364390 ps
CPU time 55.46 seconds
Started Mar 17 01:34:33 PM PDT 24
Finished Mar 17 01:35:30 PM PDT 24
Peak memory 200472 kb
Host smart-fce6d417-b469-46f2-b59e-4e542e0d1b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375101401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.375101401
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2922771101
Short name T232
Test name
Test status
Simulation time 466209601 ps
CPU time 6.42 seconds
Started Mar 17 01:34:33 PM PDT 24
Finished Mar 17 01:34:40 PM PDT 24
Peak memory 200424 kb
Host smart-d499202b-2636-4f65-9c07-5c146be28a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922771101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2922771101
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1221316160
Short name T76
Test name
Test status
Simulation time 12449729931 ps
CPU time 195.18 seconds
Started Mar 17 01:34:36 PM PDT 24
Finished Mar 17 01:37:53 PM PDT 24
Peak memory 200568 kb
Host smart-98beed81-afa3-42bf-9150-96c305b9892e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221316160 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1221316160
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2722779907
Short name T235
Test name
Test status
Simulation time 76806143 ps
CPU time 1.03 seconds
Started Mar 17 01:34:43 PM PDT 24
Finished Mar 17 01:34:45 PM PDT 24
Peak memory 199652 kb
Host smart-67e5ea60-c44f-4dd2-b137-c40a526c91bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722779907 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2722779907
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.709386365
Short name T204
Test name
Test status
Simulation time 107647540215 ps
CPU time 465.26 seconds
Started Mar 17 01:34:42 PM PDT 24
Finished Mar 17 01:42:28 PM PDT 24
Peak memory 200384 kb
Host smart-900223a1-168a-4912-901d-605237f1d0f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709386365 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.709386365
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1874094513
Short name T563
Test name
Test status
Simulation time 910622909 ps
CPU time 7.69 seconds
Started Mar 17 01:34:28 PM PDT 24
Finished Mar 17 01:34:37 PM PDT 24
Peak memory 200464 kb
Host smart-b9b47948-3cf6-4e12-8949-cace26d16460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874094513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1874094513
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3566271040
Short name T310
Test name
Test status
Simulation time 15215956 ps
CPU time 0.57 seconds
Started Mar 17 01:34:43 PM PDT 24
Finished Mar 17 01:34:43 PM PDT 24
Peak memory 194820 kb
Host smart-887e5d1b-bd78-4d1a-b425-75cb9be6e0f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566271040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3566271040
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1873473024
Short name T217
Test name
Test status
Simulation time 4572028333 ps
CPU time 40.46 seconds
Started Mar 17 01:34:35 PM PDT 24
Finished Mar 17 01:35:21 PM PDT 24
Peak memory 215824 kb
Host smart-1403fc0e-ecbe-4702-a041-97989d21ec60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1873473024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1873473024
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2091353997
Short name T84
Test name
Test status
Simulation time 3392547262 ps
CPU time 32.01 seconds
Started Mar 17 01:34:38 PM PDT 24
Finished Mar 17 01:35:14 PM PDT 24
Peak memory 200448 kb
Host smart-b559a462-c187-4637-b3e1-bbfcfa2db7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091353997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2091353997
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3362804084
Short name T335
Test name
Test status
Simulation time 4407887085 ps
CPU time 125.8 seconds
Started Mar 17 01:34:38 PM PDT 24
Finished Mar 17 01:36:47 PM PDT 24
Peak memory 200540 kb
Host smart-69ea04b8-6387-4149-ae75-a06204d62fed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362804084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3362804084
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2563877161
Short name T115
Test name
Test status
Simulation time 52182062154 ps
CPU time 122.35 seconds
Started Mar 17 01:34:36 PM PDT 24
Finished Mar 17 01:36:40 PM PDT 24
Peak memory 200524 kb
Host smart-7c58f13f-d13b-4537-bcab-c2a97f8dcadd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563877161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2563877161
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.937267675
Short name T416
Test name
Test status
Simulation time 546523153 ps
CPU time 7.47 seconds
Started Mar 17 01:34:36 PM PDT 24
Finished Mar 17 01:34:45 PM PDT 24
Peak memory 200424 kb
Host smart-f9b40359-2ebf-4677-950b-d9c56e44790c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937267675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.937267675
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3432602086
Short name T318
Test name
Test status
Simulation time 89288342 ps
CPU time 2.74 seconds
Started Mar 17 01:34:37 PM PDT 24
Finished Mar 17 01:34:44 PM PDT 24
Peak memory 200428 kb
Host smart-e575c24e-16e4-4b98-b813-6a4e32506902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432602086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3432602086
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2188219326
Short name T565
Test name
Test status
Simulation time 3293763144 ps
CPU time 118.59 seconds
Started Mar 17 01:34:34 PM PDT 24
Finished Mar 17 01:36:36 PM PDT 24
Peak memory 225756 kb
Host smart-636592e5-9ba9-41c5-ba1a-97cd68ce6f21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188219326 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2188219326
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1581056229
Short name T359
Test name
Test status
Simulation time 220551744 ps
CPU time 1.28 seconds
Started Mar 17 01:34:38 PM PDT 24
Finished Mar 17 01:34:43 PM PDT 24
Peak memory 200392 kb
Host smart-32879e9d-cd2c-4d0b-b43e-491ece8f1a44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581056229 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1581056229
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1899795604
Short name T576
Test name
Test status
Simulation time 28279854619 ps
CPU time 503.28 seconds
Started Mar 17 01:34:42 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 200404 kb
Host smart-b300000f-7995-417e-964f-c220deb73f07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899795604 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.1899795604
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.460416968
Short name T337
Test name
Test status
Simulation time 12586189329 ps
CPU time 73.33 seconds
Started Mar 17 01:34:37 PM PDT 24
Finished Mar 17 01:35:51 PM PDT 24
Peak memory 200524 kb
Host smart-d684eae5-f44f-42db-8cba-b0db67fa0fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460416968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.460416968
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2408483461
Short name T431
Test name
Test status
Simulation time 75467478 ps
CPU time 0.58 seconds
Started Mar 17 01:34:42 PM PDT 24
Finished Mar 17 01:34:42 PM PDT 24
Peak memory 194984 kb
Host smart-169ae46f-04cd-467d-941e-ac4d25602879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408483461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2408483461
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3360840588
Short name T216
Test name
Test status
Simulation time 1440726098 ps
CPU time 50.42 seconds
Started Mar 17 01:34:41 PM PDT 24
Finished Mar 17 01:35:32 PM PDT 24
Peak memory 224364 kb
Host smart-047c6b3d-985a-42a6-af52-40a966fca3aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360840588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3360840588
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.411846370
Short name T371
Test name
Test status
Simulation time 4745846062 ps
CPU time 41.14 seconds
Started Mar 17 01:34:41 PM PDT 24
Finished Mar 17 01:35:23 PM PDT 24
Peak memory 200420 kb
Host smart-b04010e1-d754-42fb-a7ce-8f9d15c8427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411846370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.411846370
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3054464784
Short name T79
Test name
Test status
Simulation time 5847221628 ps
CPU time 84.37 seconds
Started Mar 17 01:34:41 PM PDT 24
Finished Mar 17 01:36:06 PM PDT 24
Peak memory 200536 kb
Host smart-a8711c56-e2bc-4a3e-8185-5990555add24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054464784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3054464784
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1018971332
Short name T542
Test name
Test status
Simulation time 131751319 ps
CPU time 7.17 seconds
Started Mar 17 01:34:42 PM PDT 24
Finished Mar 17 01:34:50 PM PDT 24
Peak memory 200400 kb
Host smart-7792e3dd-2a8b-4962-93f9-a5b5b166646f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018971332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1018971332
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.756898545
Short name T529
Test name
Test status
Simulation time 664705356 ps
CPU time 12.82 seconds
Started Mar 17 01:34:38 PM PDT 24
Finished Mar 17 01:34:54 PM PDT 24
Peak memory 200420 kb
Host smart-8d4f6ee6-2e6f-4850-9404-d435d45dcfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756898545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.756898545
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.255394761
Short name T378
Test name
Test status
Simulation time 44971531 ps
CPU time 1.77 seconds
Started Mar 17 01:34:34 PM PDT 24
Finished Mar 17 01:34:39 PM PDT 24
Peak memory 200360 kb
Host smart-342a05de-a116-4c91-a94a-c261e97d0cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255394761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.255394761
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3172868554
Short name T78
Test name
Test status
Simulation time 199987322755 ps
CPU time 1532.04 seconds
Started Mar 17 01:34:41 PM PDT 24
Finished Mar 17 02:00:14 PM PDT 24
Peak memory 235148 kb
Host smart-7a09c47b-9600-45a1-b5d4-054f5172ef23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172868554 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3172868554
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1898858989
Short name T41
Test name
Test status
Simulation time 728020461 ps
CPU time 1.04 seconds
Started Mar 17 01:34:42 PM PDT 24
Finished Mar 17 01:34:43 PM PDT 24
Peak memory 199708 kb
Host smart-32992c4d-bb36-43c0-a08e-b599e3707168
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898858989 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1898858989
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.4170944637
Short name T199
Test name
Test status
Simulation time 15522729416 ps
CPU time 432.19 seconds
Started Mar 17 01:34:50 PM PDT 24
Finished Mar 17 01:42:02 PM PDT 24
Peak memory 200404 kb
Host smart-7285fcfb-0cd3-4328-9956-4eaace45b1b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170944637 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.4170944637
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2437515796
Short name T507
Test name
Test status
Simulation time 74670235997 ps
CPU time 90.35 seconds
Started Mar 17 01:34:42 PM PDT 24
Finished Mar 17 01:36:13 PM PDT 24
Peak memory 200448 kb
Host smart-bd6d687a-032e-4c82-a51f-56e508bd2c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437515796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2437515796
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1953269521
Short name T157
Test name
Test status
Simulation time 12114027 ps
CPU time 0.61 seconds
Started Mar 17 01:34:53 PM PDT 24
Finished Mar 17 01:34:54 PM PDT 24
Peak memory 195988 kb
Host smart-c2e4f0ba-4c60-456b-83a0-bccf7ff20fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953269521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1953269521
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1427319131
Short name T367
Test name
Test status
Simulation time 5355415860 ps
CPU time 52.89 seconds
Started Mar 17 01:34:52 PM PDT 24
Finished Mar 17 01:35:45 PM PDT 24
Peak memory 227116 kb
Host smart-92edf90a-8ad5-4d1e-b68c-60a11924ea37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1427319131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1427319131
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3902206758
Short name T315
Test name
Test status
Simulation time 1007517757 ps
CPU time 5.24 seconds
Started Mar 17 01:34:52 PM PDT 24
Finished Mar 17 01:34:57 PM PDT 24
Peak memory 200476 kb
Host smart-d3503e41-1ac4-46f0-950f-2c4f900bdfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902206758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3902206758
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1678673566
Short name T347
Test name
Test status
Simulation time 347018317 ps
CPU time 10.63 seconds
Started Mar 17 01:34:51 PM PDT 24
Finished Mar 17 01:35:02 PM PDT 24
Peak memory 200340 kb
Host smart-ad5b0f96-c6a1-4477-a65c-6a723a19fc19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678673566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1678673566
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3733473222
Short name T384
Test name
Test status
Simulation time 10034500714 ps
CPU time 89.72 seconds
Started Mar 17 01:34:52 PM PDT 24
Finished Mar 17 01:36:22 PM PDT 24
Peak memory 200440 kb
Host smart-61060d2a-d26c-45c8-a5c6-a720535e679d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733473222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3733473222
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1854352268
Short name T225
Test name
Test status
Simulation time 5267795424 ps
CPU time 73.93 seconds
Started Mar 17 01:34:53 PM PDT 24
Finished Mar 17 01:36:08 PM PDT 24
Peak memory 200684 kb
Host smart-05c8a365-6d34-492c-a5e3-ce96d799af19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854352268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1854352268
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3038929254
Short name T37
Test name
Test status
Simulation time 207136569 ps
CPU time 1.6 seconds
Started Mar 17 01:34:54 PM PDT 24
Finished Mar 17 01:34:56 PM PDT 24
Peak memory 200448 kb
Host smart-b036e364-efe1-486b-a1fc-d7a27df8a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038929254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3038929254
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1213346760
Short name T201
Test name
Test status
Simulation time 709863607653 ps
CPU time 2314.7 seconds
Started Mar 17 01:34:52 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 219972 kb
Host smart-ce00c448-e85d-4062-95a0-ddfcb73ea308
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213346760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1213346760
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1952978423
Short name T134
Test name
Test status
Simulation time 61311142 ps
CPU time 1.41 seconds
Started Mar 17 01:34:51 PM PDT 24
Finished Mar 17 01:34:53 PM PDT 24
Peak memory 199392 kb
Host smart-81f31410-7eb5-422b-8297-d4aa24fbf4bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952978423 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1952978423
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1373406780
Short name T139
Test name
Test status
Simulation time 93501576337 ps
CPU time 602.99 seconds
Started Mar 17 01:34:52 PM PDT 24
Finished Mar 17 01:44:55 PM PDT 24
Peak memory 200432 kb
Host smart-bb01afde-060c-4a14-85e6-b5bfb033e101
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373406780 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.1373406780
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2808616541
Short name T438
Test name
Test status
Simulation time 14336792893 ps
CPU time 94.89 seconds
Started Mar 17 01:34:51 PM PDT 24
Finished Mar 17 01:36:26 PM PDT 24
Peak memory 200552 kb
Host smart-cb9474f4-9c28-457c-a3da-72b238636f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808616541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2808616541
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3325651739
Short name T82
Test name
Test status
Simulation time 22875339 ps
CPU time 0.58 seconds
Started Mar 17 01:33:06 PM PDT 24
Finished Mar 17 01:33:07 PM PDT 24
Peak memory 194864 kb
Host smart-a94bbefe-b8bf-4c66-8535-aa4de96baa9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325651739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3325651739
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.368036095
Short name T281
Test name
Test status
Simulation time 725853489 ps
CPU time 25.1 seconds
Started Mar 17 01:33:02 PM PDT 24
Finished Mar 17 01:33:27 PM PDT 24
Peak memory 216824 kb
Host smart-1a9df33f-eaaa-42c9-8125-2400031c5caf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=368036095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.368036095
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.843596686
Short name T400
Test name
Test status
Simulation time 6453724022 ps
CPU time 10.2 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:33:21 PM PDT 24
Peak memory 200460 kb
Host smart-9fb9a630-5477-4d79-b0cb-1bf6bdd4f181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843596686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.843596686
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.223062577
Short name T56
Test name
Test status
Simulation time 5767991087 ps
CPU time 85.69 seconds
Started Mar 17 01:33:01 PM PDT 24
Finished Mar 17 01:34:28 PM PDT 24
Peak memory 200540 kb
Host smart-079ea135-7180-4dd3-be8b-d2e6848a5815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223062577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.223062577
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.10775264
Short name T446
Test name
Test status
Simulation time 37587825976 ps
CPU time 177.47 seconds
Started Mar 17 01:33:08 PM PDT 24
Finished Mar 17 01:36:05 PM PDT 24
Peak memory 200452 kb
Host smart-fd4f8fc4-6e44-4607-9c1d-d54b8ededed0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10775264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.10775264
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2106432647
Short name T561
Test name
Test status
Simulation time 5464846581 ps
CPU time 71.39 seconds
Started Mar 17 01:33:01 PM PDT 24
Finished Mar 17 01:34:13 PM PDT 24
Peak memory 200548 kb
Host smart-ab3763df-672f-48af-89c8-0fe2f201f795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106432647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2106432647
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.693785387
Short name T31
Test name
Test status
Simulation time 56365977 ps
CPU time 0.9 seconds
Started Mar 17 01:33:09 PM PDT 24
Finished Mar 17 01:33:10 PM PDT 24
Peak memory 218676 kb
Host smart-5e44dd25-848f-4ca8-9efa-a8b31efcdcf0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693785387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.693785387
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2168309063
Short name T176
Test name
Test status
Simulation time 1662857762 ps
CPU time 5.95 seconds
Started Mar 17 01:32:59 PM PDT 24
Finished Mar 17 01:33:05 PM PDT 24
Peak memory 200396 kb
Host smart-dc01ec27-a9d6-4556-96be-582269d84036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168309063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2168309063
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2638195455
Short name T180
Test name
Test status
Simulation time 41881055599 ps
CPU time 203.09 seconds
Started Mar 17 01:33:05 PM PDT 24
Finished Mar 17 01:36:30 PM PDT 24
Peak memory 200480 kb
Host smart-1492101b-a5f5-4334-ad14-fbcc9a0c9dd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638195455 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2638195455
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.402011851
Short name T374
Test name
Test status
Simulation time 75733434 ps
CPU time 1.46 seconds
Started Mar 17 01:33:06 PM PDT 24
Finished Mar 17 01:33:08 PM PDT 24
Peak memory 200436 kb
Host smart-34091eee-03f8-45df-852d-3d350fd40a4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402011851 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_hmac_vectors.402011851
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2615064555
Short name T223
Test name
Test status
Simulation time 58621625219 ps
CPU time 389.06 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:39:41 PM PDT 24
Peak memory 200420 kb
Host smart-935e0989-c71b-47db-ac2c-a8d05ab6fbbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615064555 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2615064555
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1447758269
Short name T264
Test name
Test status
Simulation time 5302645931 ps
CPU time 87.45 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:34:40 PM PDT 24
Peak memory 200332 kb
Host smart-f604b681-1532-493a-8c54-21d1df099259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447758269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1447758269
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2101231694
Short name T305
Test name
Test status
Simulation time 16168969 ps
CPU time 0.58 seconds
Started Mar 17 01:34:58 PM PDT 24
Finished Mar 17 01:34:59 PM PDT 24
Peak memory 195972 kb
Host smart-132f0494-58a8-4b67-a415-c927edde8eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101231694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2101231694
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1873031115
Short name T537
Test name
Test status
Simulation time 5721773649 ps
CPU time 47.27 seconds
Started Mar 17 01:34:51 PM PDT 24
Finished Mar 17 01:35:39 PM PDT 24
Peak memory 228436 kb
Host smart-d8a8cee5-9104-4b0c-b5ba-1b231bd69415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1873031115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1873031115
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.442560671
Short name T585
Test name
Test status
Simulation time 1024318868 ps
CPU time 25.68 seconds
Started Mar 17 01:34:57 PM PDT 24
Finished Mar 17 01:35:23 PM PDT 24
Peak memory 200488 kb
Host smart-be64493b-d82e-4990-ad71-70f152e36d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442560671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.442560671
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1599326317
Short name T240
Test name
Test status
Simulation time 8967868732 ps
CPU time 38.38 seconds
Started Mar 17 01:34:58 PM PDT 24
Finished Mar 17 01:35:37 PM PDT 24
Peak memory 200472 kb
Host smart-81d69efe-6212-450b-8686-520831529875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599326317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1599326317
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.191382477
Short name T389
Test name
Test status
Simulation time 2201866804 ps
CPU time 30.45 seconds
Started Mar 17 01:34:57 PM PDT 24
Finished Mar 17 01:35:28 PM PDT 24
Peak memory 200528 kb
Host smart-eae61a93-f3be-4244-b8a4-34158852ba2c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191382477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.191382477
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2638899657
Short name T86
Test name
Test status
Simulation time 67909581843 ps
CPU time 84.82 seconds
Started Mar 17 01:34:52 PM PDT 24
Finished Mar 17 01:36:17 PM PDT 24
Peak memory 200452 kb
Host smart-97aa3413-e496-4fc3-b828-87d6649e145b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638899657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2638899657
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2018835935
Short name T470
Test name
Test status
Simulation time 399661158 ps
CPU time 2.96 seconds
Started Mar 17 01:34:56 PM PDT 24
Finished Mar 17 01:35:00 PM PDT 24
Peak memory 200408 kb
Host smart-eaac16e4-b25e-4fb0-98e5-25fa9052a08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018835935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2018835935
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1858202852
Short name T387
Test name
Test status
Simulation time 74189845684 ps
CPU time 2060.08 seconds
Started Mar 17 01:34:57 PM PDT 24
Finished Mar 17 02:09:18 PM PDT 24
Peak memory 200572 kb
Host smart-1ffe3885-02ff-4603-81ff-fdd779654e2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858202852 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1858202852
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1533322606
Short name T403
Test name
Test status
Simulation time 49811716 ps
CPU time 0.97 seconds
Started Mar 17 01:34:59 PM PDT 24
Finished Mar 17 01:35:00 PM PDT 24
Peak memory 198760 kb
Host smart-f5c1d54c-2699-42c3-a475-71e644360b35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533322606 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1533322606
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.752982080
Short name T338
Test name
Test status
Simulation time 75057191051 ps
CPU time 562.59 seconds
Started Mar 17 01:34:58 PM PDT 24
Finished Mar 17 01:44:21 PM PDT 24
Peak memory 200448 kb
Host smart-79297838-9b58-4f78-9a67-e51f663644b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752982080 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.752982080
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.480397834
Short name T169
Test name
Test status
Simulation time 9713915529 ps
CPU time 97.47 seconds
Started Mar 17 01:35:05 PM PDT 24
Finished Mar 17 01:36:43 PM PDT 24
Peak memory 200484 kb
Host smart-bfbb22cb-f9a8-4f47-a7a0-a822ebeba2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480397834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.480397834
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3731884807
Short name T284
Test name
Test status
Simulation time 38204615 ps
CPU time 0.59 seconds
Started Mar 17 01:34:57 PM PDT 24
Finished Mar 17 01:34:58 PM PDT 24
Peak memory 196024 kb
Host smart-d83e11e6-9399-4f63-a345-31153756246c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731884807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3731884807
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1570628259
Short name T402
Test name
Test status
Simulation time 1110759710 ps
CPU time 40.51 seconds
Started Mar 17 01:34:59 PM PDT 24
Finished Mar 17 01:35:40 PM PDT 24
Peak memory 216496 kb
Host smart-147549e5-b41f-44aa-8681-1fb5f22efc61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570628259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1570628259
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.334921934
Short name T510
Test name
Test status
Simulation time 3558659720 ps
CPU time 37.14 seconds
Started Mar 17 01:34:58 PM PDT 24
Finished Mar 17 01:35:35 PM PDT 24
Peak memory 200500 kb
Host smart-801c0f87-287e-4f47-acf7-b348fb28b014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334921934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.334921934
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3053882445
Short name T461
Test name
Test status
Simulation time 8358055028 ps
CPU time 137.87 seconds
Started Mar 17 01:34:58 PM PDT 24
Finished Mar 17 01:37:16 PM PDT 24
Peak memory 200496 kb
Host smart-7935bff6-5cdb-43e8-9b0f-773c2c8f52ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053882445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3053882445
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.220752400
Short name T283
Test name
Test status
Simulation time 5971527586 ps
CPU time 84.96 seconds
Started Mar 17 01:34:58 PM PDT 24
Finished Mar 17 01:36:24 PM PDT 24
Peak memory 200472 kb
Host smart-e2b136b5-e056-4881-bf6d-10323cad29e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220752400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.220752400
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1055325240
Short name T117
Test name
Test status
Simulation time 4873887148 ps
CPU time 100.36 seconds
Started Mar 17 01:34:58 PM PDT 24
Finished Mar 17 01:36:39 PM PDT 24
Peak memory 200492 kb
Host smart-aaee8b8b-5247-437a-a6a5-bd5f2d4d590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055325240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1055325240
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.12846270
Short name T173
Test name
Test status
Simulation time 381232058 ps
CPU time 4.88 seconds
Started Mar 17 01:34:57 PM PDT 24
Finished Mar 17 01:35:02 PM PDT 24
Peak memory 200420 kb
Host smart-b3d5facd-5cf4-48a4-ba91-f21813a6825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12846270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.12846270
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2213940250
Short name T302
Test name
Test status
Simulation time 30754425 ps
CPU time 1.28 seconds
Started Mar 17 01:34:58 PM PDT 24
Finished Mar 17 01:35:00 PM PDT 24
Peak memory 200404 kb
Host smart-d9933a2c-ea35-4e29-b3b5-a97ac1821ff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213940250 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.2213940250
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.170838439
Short name T172
Test name
Test status
Simulation time 46870204925 ps
CPU time 566.53 seconds
Started Mar 17 01:34:57 PM PDT 24
Finished Mar 17 01:44:24 PM PDT 24
Peak memory 200428 kb
Host smart-1cfde9d2-e5f1-43e8-a978-694135c34118
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170838439 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.170838439
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2845017752
Short name T118
Test name
Test status
Simulation time 1886959317 ps
CPU time 13.67 seconds
Started Mar 17 01:34:59 PM PDT 24
Finished Mar 17 01:35:13 PM PDT 24
Peak memory 200436 kb
Host smart-6b274d94-e493-4909-a15a-1b9ef5238cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845017752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2845017752
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1342022424
Short name T471
Test name
Test status
Simulation time 14799343 ps
CPU time 0.62 seconds
Started Mar 17 01:35:07 PM PDT 24
Finished Mar 17 01:35:08 PM PDT 24
Peak memory 195932 kb
Host smart-1ac0e32f-5eb8-4a55-bc0b-18b0c1cd4cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342022424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1342022424
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3676088275
Short name T437
Test name
Test status
Simulation time 49603152 ps
CPU time 1.75 seconds
Started Mar 17 01:35:01 PM PDT 24
Finished Mar 17 01:35:04 PM PDT 24
Peak memory 200416 kb
Host smart-b1df332c-2744-49e4-9ec5-29aaccb3808e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676088275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3676088275
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2031374185
Short name T582
Test name
Test status
Simulation time 1386917458 ps
CPU time 12.32 seconds
Started Mar 17 01:35:03 PM PDT 24
Finished Mar 17 01:35:16 PM PDT 24
Peak memory 200420 kb
Host smart-fc906c35-5f8c-4fb2-99b9-3cd587c34494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031374185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2031374185
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1542359448
Short name T135
Test name
Test status
Simulation time 11099003085 ps
CPU time 168.4 seconds
Started Mar 17 01:35:08 PM PDT 24
Finished Mar 17 01:37:57 PM PDT 24
Peak memory 200568 kb
Host smart-f5213a11-28b1-4601-8ef0-efbeb01ab62e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1542359448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1542359448
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1034665335
Short name T491
Test name
Test status
Simulation time 1276840330 ps
CPU time 72.89 seconds
Started Mar 17 01:35:02 PM PDT 24
Finished Mar 17 01:36:15 PM PDT 24
Peak memory 200460 kb
Host smart-dc9538ef-4557-4992-903e-d89a4bdf2e18
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034665335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1034665335
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3321807208
Short name T111
Test name
Test status
Simulation time 24902515473 ps
CPU time 87.28 seconds
Started Mar 17 01:35:07 PM PDT 24
Finished Mar 17 01:36:34 PM PDT 24
Peak memory 200484 kb
Host smart-4ef18a44-18c7-457b-aa5d-cc1fbd610a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321807208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3321807208
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1693046362
Short name T478
Test name
Test status
Simulation time 1042949208 ps
CPU time 3.3 seconds
Started Mar 17 01:35:02 PM PDT 24
Finished Mar 17 01:35:06 PM PDT 24
Peak memory 200504 kb
Host smart-fc5a5617-7a7b-4d62-bfb3-353b571deb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693046362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1693046362
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.4159474531
Short name T227
Test name
Test status
Simulation time 26360451529 ps
CPU time 1425.97 seconds
Started Mar 17 01:35:09 PM PDT 24
Finished Mar 17 01:58:55 PM PDT 24
Peak memory 227152 kb
Host smart-6ba6ce8f-69bf-417b-b8d0-56ec74f9a573
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159474531 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.4159474531
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1918540525
Short name T451
Test name
Test status
Simulation time 32309653 ps
CPU time 1.25 seconds
Started Mar 17 01:35:02 PM PDT 24
Finished Mar 17 01:35:04 PM PDT 24
Peak memory 200060 kb
Host smart-847c01c6-753e-4cc2-a6ba-7cabb873728b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918540525 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1918540525
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1838301779
Short name T341
Test name
Test status
Simulation time 37078535662 ps
CPU time 463.57 seconds
Started Mar 17 01:35:05 PM PDT 24
Finished Mar 17 01:42:49 PM PDT 24
Peak memory 200380 kb
Host smart-71481106-0f0a-48cd-9a1d-81eec2b9fded
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838301779 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1838301779
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3638241618
Short name T511
Test name
Test status
Simulation time 996990949 ps
CPU time 23.49 seconds
Started Mar 17 01:35:03 PM PDT 24
Finished Mar 17 01:35:27 PM PDT 24
Peak memory 200480 kb
Host smart-dc1b2b09-d2dc-46c2-90ec-82f2c128a89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638241618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3638241618
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1535916355
Short name T323
Test name
Test status
Simulation time 16127332 ps
CPU time 0.59 seconds
Started Mar 17 01:35:13 PM PDT 24
Finished Mar 17 01:35:14 PM PDT 24
Peak memory 195808 kb
Host smart-dc6a36f6-8a5e-49a7-a56f-a82baf0dcba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535916355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1535916355
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3760127035
Short name T521
Test name
Test status
Simulation time 77094305 ps
CPU time 3.07 seconds
Started Mar 17 01:35:08 PM PDT 24
Finished Mar 17 01:35:11 PM PDT 24
Peak memory 200440 kb
Host smart-63a15baa-3168-46e2-b8d7-3664a7a30fba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3760127035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3760127035
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.574266521
Short name T190
Test name
Test status
Simulation time 548618883 ps
CPU time 4.69 seconds
Started Mar 17 01:35:10 PM PDT 24
Finished Mar 17 01:35:15 PM PDT 24
Peak memory 200320 kb
Host smart-a2479d4f-bd0c-4959-b8c2-1738e0b37af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574266521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.574266521
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1041408353
Short name T370
Test name
Test status
Simulation time 8778061617 ps
CPU time 133.22 seconds
Started Mar 17 01:35:08 PM PDT 24
Finished Mar 17 01:37:22 PM PDT 24
Peak memory 200420 kb
Host smart-28c15ad9-4ee7-4b28-99ae-f6c3adf6808e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1041408353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1041408353
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.401764814
Short name T508
Test name
Test status
Simulation time 1077341651 ps
CPU time 9.59 seconds
Started Mar 17 01:35:08 PM PDT 24
Finished Mar 17 01:35:18 PM PDT 24
Peak memory 200332 kb
Host smart-9c026502-d5f7-47b3-8f19-04a0c76e2e82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401764814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.401764814
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2719586865
Short name T531
Test name
Test status
Simulation time 18785774859 ps
CPU time 89.27 seconds
Started Mar 17 01:35:08 PM PDT 24
Finished Mar 17 01:36:38 PM PDT 24
Peak memory 200520 kb
Host smart-893e5bac-fa25-4b9e-951c-d3f78cc6a89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719586865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2719586865
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.312723736
Short name T584
Test name
Test status
Simulation time 235867176 ps
CPU time 6.48 seconds
Started Mar 17 01:35:07 PM PDT 24
Finished Mar 17 01:35:14 PM PDT 24
Peak memory 200412 kb
Host smart-e3e4ab4a-45bb-47b8-b4ac-1f4849385a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312723736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.312723736
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1687121963
Short name T45
Test name
Test status
Simulation time 14462884013 ps
CPU time 227.13 seconds
Started Mar 17 01:35:15 PM PDT 24
Finished Mar 17 01:39:03 PM PDT 24
Peak memory 200520 kb
Host smart-87da308d-08e8-4328-badc-fb78b787de0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687121963 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1687121963
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.701182745
Short name T262
Test name
Test status
Simulation time 280876152 ps
CPU time 1.27 seconds
Started Mar 17 01:35:14 PM PDT 24
Finished Mar 17 01:35:15 PM PDT 24
Peak memory 200296 kb
Host smart-0ebec9af-dad1-4b06-be82-60cc34ee3d8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701182745 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_hmac_vectors.701182745
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3659907055
Short name T414
Test name
Test status
Simulation time 83953856642 ps
CPU time 473.42 seconds
Started Mar 17 01:35:10 PM PDT 24
Finished Mar 17 01:43:04 PM PDT 24
Peak memory 200432 kb
Host smart-73ea263d-b184-49a9-9536-972907ae0678
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659907055 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3659907055
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1175669681
Short name T25
Test name
Test status
Simulation time 1272900496 ps
CPU time 18.53 seconds
Started Mar 17 01:35:08 PM PDT 24
Finished Mar 17 01:35:27 PM PDT 24
Peak memory 200436 kb
Host smart-0d7cf2bd-470a-4d27-882c-a67c4ca2c7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175669681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1175669681
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1327197923
Short name T346
Test name
Test status
Simulation time 13727033 ps
CPU time 0.6 seconds
Started Mar 17 01:35:23 PM PDT 24
Finished Mar 17 01:35:24 PM PDT 24
Peak memory 195984 kb
Host smart-57945a13-29c3-4e3f-923d-6794ce033239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327197923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1327197923
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1373657176
Short name T247
Test name
Test status
Simulation time 73180447 ps
CPU time 2.5 seconds
Started Mar 17 01:35:32 PM PDT 24
Finished Mar 17 01:35:34 PM PDT 24
Peak memory 200448 kb
Host smart-2ebffff2-5fe9-4f57-b8d5-d259c02ed07a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373657176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1373657176
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3125079400
Short name T226
Test name
Test status
Simulation time 2159381360 ps
CPU time 56.71 seconds
Started Mar 17 01:35:13 PM PDT 24
Finished Mar 17 01:36:10 PM PDT 24
Peak memory 200496 kb
Host smart-a3f1f49b-921d-44cc-8c5f-dcbfad6e479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125079400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3125079400
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.4177277936
Short name T200
Test name
Test status
Simulation time 9002996792 ps
CPU time 136.23 seconds
Started Mar 17 01:35:13 PM PDT 24
Finished Mar 17 01:37:30 PM PDT 24
Peak memory 200492 kb
Host smart-7b53a970-b99c-4570-81ab-23cf43fc9485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177277936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4177277936
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1504352643
Short name T333
Test name
Test status
Simulation time 28250118963 ps
CPU time 98.25 seconds
Started Mar 17 01:35:12 PM PDT 24
Finished Mar 17 01:36:51 PM PDT 24
Peak memory 200496 kb
Host smart-d760427a-7903-4592-b9dc-5f9cba93761e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504352643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1504352643
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1259842399
Short name T221
Test name
Test status
Simulation time 17106774033 ps
CPU time 121.88 seconds
Started Mar 17 01:35:23 PM PDT 24
Finished Mar 17 01:37:25 PM PDT 24
Peak memory 200496 kb
Host smart-7d30973f-7e45-4b35-9119-78adba1431b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259842399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1259842399
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2216405156
Short name T306
Test name
Test status
Simulation time 230243906 ps
CPU time 1.78 seconds
Started Mar 17 01:35:13 PM PDT 24
Finished Mar 17 01:35:15 PM PDT 24
Peak memory 200452 kb
Host smart-340613ff-2185-4ee3-b9dc-c07bf7e848b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216405156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2216405156
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2047035165
Short name T75
Test name
Test status
Simulation time 360639484180 ps
CPU time 1084.15 seconds
Started Mar 17 01:35:14 PM PDT 24
Finished Mar 17 01:53:19 PM PDT 24
Peak memory 237624 kb
Host smart-c57af030-5c11-4f04-9c79-eb3f96904721
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047035165 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2047035165
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1753787283
Short name T282
Test name
Test status
Simulation time 84065324 ps
CPU time 1.14 seconds
Started Mar 17 01:35:15 PM PDT 24
Finished Mar 17 01:35:17 PM PDT 24
Peak memory 199720 kb
Host smart-c2c6784b-3d3a-4ac0-ac02-50efd408e08c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753787283 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1753787283
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1599973295
Short name T538
Test name
Test status
Simulation time 30379592905 ps
CPU time 410.47 seconds
Started Mar 17 01:35:13 PM PDT 24
Finished Mar 17 01:42:04 PM PDT 24
Peak memory 200416 kb
Host smart-f334db4b-0e3a-4eae-b43c-ee711cd8d2fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599973295 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1599973295
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3894956515
Short name T475
Test name
Test status
Simulation time 2998552802 ps
CPU time 79.3 seconds
Started Mar 17 01:35:16 PM PDT 24
Finished Mar 17 01:36:36 PM PDT 24
Peak memory 200536 kb
Host smart-218b4e48-6a0a-494c-9e83-fb53ef5758f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894956515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3894956515
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3941670292
Short name T595
Test name
Test status
Simulation time 12865977 ps
CPU time 0.61 seconds
Started Mar 17 01:35:18 PM PDT 24
Finished Mar 17 01:35:19 PM PDT 24
Peak memory 195912 kb
Host smart-aab946c7-f6d9-44e8-857e-446177e01984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941670292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3941670292
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3215486733
Short name T570
Test name
Test status
Simulation time 2972316543 ps
CPU time 29.75 seconds
Started Mar 17 01:35:17 PM PDT 24
Finished Mar 17 01:35:47 PM PDT 24
Peak memory 222560 kb
Host smart-4f5c8b78-e4ad-477e-bc4e-8709946a80ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215486733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3215486733
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.987917843
Short name T205
Test name
Test status
Simulation time 1561127978 ps
CPU time 9.78 seconds
Started Mar 17 01:35:19 PM PDT 24
Finished Mar 17 01:35:29 PM PDT 24
Peak memory 200380 kb
Host smart-bf24dce1-fb9d-4502-a8cf-989ea9270739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987917843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.987917843
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.474600334
Short name T179
Test name
Test status
Simulation time 499862721 ps
CPU time 28.37 seconds
Started Mar 17 01:35:20 PM PDT 24
Finished Mar 17 01:35:49 PM PDT 24
Peak memory 200428 kb
Host smart-b5055cfb-8227-4416-9b8f-9eab534c34e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474600334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.474600334
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1658401752
Short name T150
Test name
Test status
Simulation time 38527851289 ps
CPU time 171.85 seconds
Started Mar 17 01:35:19 PM PDT 24
Finished Mar 17 01:38:11 PM PDT 24
Peak memory 200516 kb
Host smart-6a9fdea8-9528-4701-931b-bdc05a71c8b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658401752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1658401752
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.416744497
Short name T230
Test name
Test status
Simulation time 658862084 ps
CPU time 42.47 seconds
Started Mar 17 01:35:13 PM PDT 24
Finished Mar 17 01:35:56 PM PDT 24
Peak memory 200420 kb
Host smart-6bc7a1e3-d773-4bc2-ae0e-639eb7e9a1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416744497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.416744497
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1075805978
Short name T209
Test name
Test status
Simulation time 391267692 ps
CPU time 5.62 seconds
Started Mar 17 01:35:23 PM PDT 24
Finished Mar 17 01:35:29 PM PDT 24
Peak memory 200432 kb
Host smart-65cd4ce9-710c-467f-a479-b3d8d575c91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075805978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1075805978
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4217039702
Short name T70
Test name
Test status
Simulation time 39906632362 ps
CPU time 149.91 seconds
Started Mar 17 01:35:18 PM PDT 24
Finished Mar 17 01:37:48 PM PDT 24
Peak memory 216360 kb
Host smart-19817d76-6cad-4bba-8116-ce710547ac9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217039702 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4217039702
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1180546380
Short name T298
Test name
Test status
Simulation time 149180654 ps
CPU time 1.24 seconds
Started Mar 17 01:35:27 PM PDT 24
Finished Mar 17 01:35:29 PM PDT 24
Peak memory 200316 kb
Host smart-71bb26b8-f82a-43f8-b3fd-07f29446506e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180546380 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1180546380
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1370373590
Short name T498
Test name
Test status
Simulation time 28748499983 ps
CPU time 500.26 seconds
Started Mar 17 01:35:19 PM PDT 24
Finished Mar 17 01:43:39 PM PDT 24
Peak memory 200492 kb
Host smart-1e44c749-69e0-4e3d-beea-1768adf05cbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370373590 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1370373590
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2933292060
Short name T203
Test name
Test status
Simulation time 8401970341 ps
CPU time 42.75 seconds
Started Mar 17 01:35:18 PM PDT 24
Finished Mar 17 01:36:01 PM PDT 24
Peak memory 200500 kb
Host smart-3b134621-c859-46ca-bb16-75d8f5d06c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933292060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2933292060
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4096049562
Short name T362
Test name
Test status
Simulation time 50648367 ps
CPU time 0.56 seconds
Started Mar 17 01:35:26 PM PDT 24
Finished Mar 17 01:35:27 PM PDT 24
Peak memory 194868 kb
Host smart-b2e55c29-beb9-46f2-ae49-03f104caa53e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096049562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4096049562
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2032169757
Short name T276
Test name
Test status
Simulation time 3062380455 ps
CPU time 24.84 seconds
Started Mar 17 01:35:18 PM PDT 24
Finished Mar 17 01:35:42 PM PDT 24
Peak memory 200468 kb
Host smart-a593d3ac-6778-4685-bd93-fcda75508e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032169757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2032169757
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1186724147
Short name T152
Test name
Test status
Simulation time 142497890 ps
CPU time 3.22 seconds
Started Mar 17 01:35:25 PM PDT 24
Finished Mar 17 01:35:28 PM PDT 24
Peak memory 200416 kb
Host smart-1fee50f5-7675-4d63-81a2-757ce2357272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186724147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1186724147
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1861898761
Short name T125
Test name
Test status
Simulation time 107744120 ps
CPU time 2.52 seconds
Started Mar 17 01:35:18 PM PDT 24
Finished Mar 17 01:35:21 PM PDT 24
Peak memory 200384 kb
Host smart-047ab2e1-f04c-441c-a46b-e3284c2d4430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861898761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1861898761
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.442680475
Short name T392
Test name
Test status
Simulation time 2698353841 ps
CPU time 147.81 seconds
Started Mar 17 01:35:27 PM PDT 24
Finished Mar 17 01:37:55 PM PDT 24
Peak memory 200528 kb
Host smart-5ff35495-51f2-4673-8792-e85fdda1af99
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442680475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.442680475
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3902040781
Short name T455
Test name
Test status
Simulation time 2922408063 ps
CPU time 23.87 seconds
Started Mar 17 01:35:19 PM PDT 24
Finished Mar 17 01:35:43 PM PDT 24
Peak memory 200492 kb
Host smart-a8252157-d3f0-4d10-a829-613834f9b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902040781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3902040781
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.248271805
Short name T516
Test name
Test status
Simulation time 325215573 ps
CPU time 5.16 seconds
Started Mar 17 01:35:20 PM PDT 24
Finished Mar 17 01:35:25 PM PDT 24
Peak memory 200432 kb
Host smart-d7e1c787-bda6-46ae-94eb-e35048a4c237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248271805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.248271805
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1635882147
Short name T104
Test name
Test status
Simulation time 5276217025 ps
CPU time 94.15 seconds
Started Mar 17 01:35:25 PM PDT 24
Finished Mar 17 01:36:59 PM PDT 24
Peak memory 200568 kb
Host smart-e7247520-86c1-4ff2-9728-1f64cbb88966
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635882147 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1635882147
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.267825601
Short name T308
Test name
Test status
Simulation time 261553019 ps
CPU time 1.33 seconds
Started Mar 17 01:35:25 PM PDT 24
Finished Mar 17 01:35:27 PM PDT 24
Peak memory 200108 kb
Host smart-1066d9bd-0791-4eff-8dbb-98ad3ecd16ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267825601 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_hmac_vectors.267825601
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.4234205673
Short name T147
Test name
Test status
Simulation time 34606786986 ps
CPU time 465.57 seconds
Started Mar 17 01:35:24 PM PDT 24
Finished Mar 17 01:43:09 PM PDT 24
Peak memory 200468 kb
Host smart-7a87d129-8438-4679-af5c-81c24e67a831
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234205673 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.4234205673
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2206177861
Short name T24
Test name
Test status
Simulation time 21841417408 ps
CPU time 27.82 seconds
Started Mar 17 01:35:26 PM PDT 24
Finished Mar 17 01:35:54 PM PDT 24
Peak memory 200548 kb
Host smart-79298803-2113-467b-8b10-ec91567e3c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206177861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2206177861
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.604874150
Short name T228
Test name
Test status
Simulation time 20688229 ps
CPU time 0.58 seconds
Started Mar 17 01:35:31 PM PDT 24
Finished Mar 17 01:35:31 PM PDT 24
Peak memory 194812 kb
Host smart-d1462a3e-acab-4a65-95ad-e96680279ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604874150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.604874150
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1429751338
Short name T81
Test name
Test status
Simulation time 4357961963 ps
CPU time 26.73 seconds
Started Mar 17 01:35:24 PM PDT 24
Finished Mar 17 01:35:51 PM PDT 24
Peak memory 223056 kb
Host smart-c7f9aeeb-c752-4236-a716-c7b47a90085c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1429751338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1429751338
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.305836808
Short name T330
Test name
Test status
Simulation time 3980571601 ps
CPU time 19.12 seconds
Started Mar 17 01:35:27 PM PDT 24
Finished Mar 17 01:35:46 PM PDT 24
Peak memory 200480 kb
Host smart-4ea50546-35fb-435c-be91-1004953b0038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305836808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.305836808
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.749636158
Short name T465
Test name
Test status
Simulation time 1424470848 ps
CPU time 39.92 seconds
Started Mar 17 01:35:26 PM PDT 24
Finished Mar 17 01:36:06 PM PDT 24
Peak memory 200392 kb
Host smart-20697f62-2d80-4ba6-b737-09a3728a94dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=749636158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.749636158
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1339594274
Short name T497
Test name
Test status
Simulation time 11009080045 ps
CPU time 88.87 seconds
Started Mar 17 01:35:44 PM PDT 24
Finished Mar 17 01:37:14 PM PDT 24
Peak memory 200532 kb
Host smart-e5c6bfe4-9b55-4585-8a77-0171660b814e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339594274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1339594274
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.4229326314
Short name T492
Test name
Test status
Simulation time 5579738833 ps
CPU time 46.14 seconds
Started Mar 17 01:35:27 PM PDT 24
Finished Mar 17 01:36:13 PM PDT 24
Peak memory 200472 kb
Host smart-74623f9a-46a9-4e47-a0d7-69111330dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229326314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.4229326314
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2811586441
Short name T579
Test name
Test status
Simulation time 322347406 ps
CPU time 2.68 seconds
Started Mar 17 01:35:26 PM PDT 24
Finished Mar 17 01:35:29 PM PDT 24
Peak memory 200472 kb
Host smart-a4a5fb3f-d5c7-48f2-91d4-25745e2d6483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811586441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2811586441
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3232257846
Short name T399
Test name
Test status
Simulation time 45079228165 ps
CPU time 212.87 seconds
Started Mar 17 01:35:30 PM PDT 24
Finished Mar 17 01:39:03 PM PDT 24
Peak memory 216472 kb
Host smart-fd0e5664-04a6-42e7-81cf-d85d1278cf1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232257846 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3232257846
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3247139770
Short name T300
Test name
Test status
Simulation time 199408892 ps
CPU time 1.14 seconds
Started Mar 17 01:35:44 PM PDT 24
Finished Mar 17 01:35:45 PM PDT 24
Peak memory 200436 kb
Host smart-f0a0c90b-b31c-494f-97bc-e63f6939a3ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247139770 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3247139770
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.4042000013
Short name T273
Test name
Test status
Simulation time 90654922239 ps
CPU time 563.71 seconds
Started Mar 17 01:35:31 PM PDT 24
Finished Mar 17 01:44:55 PM PDT 24
Peak memory 200424 kb
Host smart-19ce1491-92ec-46de-96a0-6cdb85caaec8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042000013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.4042000013
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1952417060
Short name T407
Test name
Test status
Simulation time 1801673637 ps
CPU time 30.34 seconds
Started Mar 17 01:35:30 PM PDT 24
Finished Mar 17 01:36:00 PM PDT 24
Peak memory 200468 kb
Host smart-8b5ff5ff-68f5-4327-b4ac-64e0fd00463b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952417060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1952417060
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3209387179
Short name T292
Test name
Test status
Simulation time 29036567 ps
CPU time 0.62 seconds
Started Mar 17 01:35:31 PM PDT 24
Finished Mar 17 01:35:32 PM PDT 24
Peak memory 195720 kb
Host smart-d12c9261-8649-4f62-bae2-6f81fad42f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209387179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3209387179
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3432613659
Short name T488
Test name
Test status
Simulation time 561994029 ps
CPU time 20.48 seconds
Started Mar 17 01:35:31 PM PDT 24
Finished Mar 17 01:35:51 PM PDT 24
Peak memory 216852 kb
Host smart-786368be-87f3-47d4-9339-588837e3c09a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432613659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3432613659
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3260036531
Short name T566
Test name
Test status
Simulation time 1500269607 ps
CPU time 18.41 seconds
Started Mar 17 01:35:31 PM PDT 24
Finished Mar 17 01:35:50 PM PDT 24
Peak memory 200416 kb
Host smart-47bdd7b3-b55a-43d8-992e-62232e716aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260036531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3260036531
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.846401261
Short name T132
Test name
Test status
Simulation time 1549184809 ps
CPU time 23.93 seconds
Started Mar 17 01:35:30 PM PDT 24
Finished Mar 17 01:35:54 PM PDT 24
Peak memory 200392 kb
Host smart-45f842f7-6327-44e8-943e-8f04a5db41bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846401261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.846401261
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.736484816
Short name T44
Test name
Test status
Simulation time 291570361 ps
CPU time 15.5 seconds
Started Mar 17 01:35:30 PM PDT 24
Finished Mar 17 01:35:46 PM PDT 24
Peak memory 200356 kb
Host smart-6329619d-eafb-4b26-bb3a-08125d8fa00d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736484816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.736484816
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3783634610
Short name T233
Test name
Test status
Simulation time 22312553528 ps
CPU time 64.22 seconds
Started Mar 17 01:35:31 PM PDT 24
Finished Mar 17 01:36:36 PM PDT 24
Peak memory 200460 kb
Host smart-e26ac871-f264-493e-8585-9fcf8c4249f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783634610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3783634610
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3364492293
Short name T424
Test name
Test status
Simulation time 437190348 ps
CPU time 4.73 seconds
Started Mar 17 01:35:44 PM PDT 24
Finished Mar 17 01:35:50 PM PDT 24
Peak memory 200432 kb
Host smart-aee0e8b0-a342-40d5-895c-da7c29372085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364492293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3364492293
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2146406993
Short name T72
Test name
Test status
Simulation time 334655354265 ps
CPU time 2337.47 seconds
Started Mar 17 01:35:31 PM PDT 24
Finished Mar 17 02:14:29 PM PDT 24
Peak memory 240880 kb
Host smart-6a60b063-aaa9-4cef-be0e-2f47ce6f590c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146406993 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2146406993
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3871544788
Short name T326
Test name
Test status
Simulation time 222783789 ps
CPU time 1.28 seconds
Started Mar 17 01:35:44 PM PDT 24
Finished Mar 17 01:35:46 PM PDT 24
Peak memory 200436 kb
Host smart-4d125342-f2df-4b6f-8c03-36b89bcc6b59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871544788 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3871544788
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.582544313
Short name T377
Test name
Test status
Simulation time 122160489162 ps
CPU time 559.04 seconds
Started Mar 17 01:35:31 PM PDT 24
Finished Mar 17 01:44:50 PM PDT 24
Peak memory 200376 kb
Host smart-b08773ba-8337-4d19-bc08-d7e38c600984
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582544313 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.582544313
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2673170539
Short name T277
Test name
Test status
Simulation time 3106037109 ps
CPU time 47.73 seconds
Started Mar 17 01:35:39 PM PDT 24
Finished Mar 17 01:36:27 PM PDT 24
Peak memory 200540 kb
Host smart-a8d71e59-37fa-460b-96dd-e07cac17344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673170539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2673170539
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1302388746
Short name T229
Test name
Test status
Simulation time 15957981 ps
CPU time 0.61 seconds
Started Mar 17 01:35:37 PM PDT 24
Finished Mar 17 01:35:38 PM PDT 24
Peak memory 195896 kb
Host smart-352bb9b1-41c3-47fc-95dd-af6fb1ff0951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302388746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1302388746
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.944744499
Short name T422
Test name
Test status
Simulation time 848902941 ps
CPU time 29.67 seconds
Started Mar 17 01:35:36 PM PDT 24
Finished Mar 17 01:36:06 PM PDT 24
Peak memory 208680 kb
Host smart-244a7af8-cd64-4d6f-9008-383d4a921ad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944744499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.944744499
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2342141705
Short name T222
Test name
Test status
Simulation time 3037777405 ps
CPU time 12.87 seconds
Started Mar 17 01:35:36 PM PDT 24
Finished Mar 17 01:35:49 PM PDT 24
Peak memory 200472 kb
Host smart-4437abd5-4378-4616-abd7-258d2f403b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342141705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2342141705
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.125934727
Short name T495
Test name
Test status
Simulation time 1420182271 ps
CPU time 66.31 seconds
Started Mar 17 01:35:37 PM PDT 24
Finished Mar 17 01:36:44 PM PDT 24
Peak memory 200396 kb
Host smart-21dd475f-992c-4270-8cba-79457a5b5b44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=125934727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.125934727
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3428246267
Short name T550
Test name
Test status
Simulation time 6281571547 ps
CPU time 81.36 seconds
Started Mar 17 01:35:36 PM PDT 24
Finished Mar 17 01:36:58 PM PDT 24
Peak memory 200488 kb
Host smart-4495790f-6e1c-40dc-8463-21802f4ac48b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428246267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3428246267
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3538746559
Short name T166
Test name
Test status
Simulation time 5418662668 ps
CPU time 84.12 seconds
Started Mar 17 01:35:37 PM PDT 24
Finished Mar 17 01:37:01 PM PDT 24
Peak memory 200496 kb
Host smart-8de057a7-a27d-4e2c-b81e-cc8e5e3f4640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538746559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3538746559
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3799333569
Short name T321
Test name
Test status
Simulation time 79209650 ps
CPU time 1.39 seconds
Started Mar 17 01:35:30 PM PDT 24
Finished Mar 17 01:35:32 PM PDT 24
Peak memory 200480 kb
Host smart-03ab37ee-8ba2-4f89-a16b-cc39484a098c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799333569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3799333569
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.4095027106
Short name T434
Test name
Test status
Simulation time 159693602196 ps
CPU time 722.62 seconds
Started Mar 17 01:35:36 PM PDT 24
Finished Mar 17 01:47:39 PM PDT 24
Peak memory 200548 kb
Host smart-6eb777d6-a483-4d3f-812e-dec3f7738bd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095027106 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4095027106
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1176091025
Short name T505
Test name
Test status
Simulation time 145703205 ps
CPU time 1.02 seconds
Started Mar 17 01:35:37 PM PDT 24
Finished Mar 17 01:35:38 PM PDT 24
Peak memory 199608 kb
Host smart-c1af9e42-9f0c-46eb-abf1-668914e5c338
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176091025 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1176091025
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2333949830
Short name T490
Test name
Test status
Simulation time 82736572737 ps
CPU time 527.77 seconds
Started Mar 17 01:35:35 PM PDT 24
Finished Mar 17 01:44:23 PM PDT 24
Peak memory 200416 kb
Host smart-64a3292f-3012-4b27-8904-ed940cd0e8c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333949830 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.2333949830
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2871547242
Short name T249
Test name
Test status
Simulation time 409441267 ps
CPU time 10.83 seconds
Started Mar 17 01:35:39 PM PDT 24
Finished Mar 17 01:35:50 PM PDT 24
Peak memory 200388 kb
Host smart-cbcff48a-d29d-4890-91a1-716ce8594672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871547242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2871547242
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.909691659
Short name T197
Test name
Test status
Simulation time 45323034 ps
CPU time 0.59 seconds
Started Mar 17 01:33:05 PM PDT 24
Finished Mar 17 01:33:07 PM PDT 24
Peak memory 195924 kb
Host smart-22c1440e-60ec-4499-8775-58878f0928c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909691659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.909691659
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.99831368
Short name T243
Test name
Test status
Simulation time 3004695069 ps
CPU time 28.14 seconds
Started Mar 17 01:33:07 PM PDT 24
Finished Mar 17 01:33:35 PM PDT 24
Peak memory 208752 kb
Host smart-b65572ee-c259-43b6-b572-404adffa539a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99831368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.99831368
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.431750211
Short name T363
Test name
Test status
Simulation time 2466006792 ps
CPU time 51.58 seconds
Started Mar 17 01:33:05 PM PDT 24
Finished Mar 17 01:33:58 PM PDT 24
Peak memory 200684 kb
Host smart-554db8d5-e068-4ae3-a594-425ff6e26a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431750211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.431750211
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.917933423
Short name T436
Test name
Test status
Simulation time 1651121920 ps
CPU time 48.57 seconds
Started Mar 17 01:33:09 PM PDT 24
Finished Mar 17 01:33:58 PM PDT 24
Peak memory 200260 kb
Host smart-12fbd0b7-7ac6-4578-8115-bbf40419c916
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917933423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.917933423
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2173171648
Short name T18
Test name
Test status
Simulation time 2660207067 ps
CPU time 9.35 seconds
Started Mar 17 01:33:12 PM PDT 24
Finished Mar 17 01:33:21 PM PDT 24
Peak memory 200304 kb
Host smart-f90d6745-e494-4213-aff1-918c6a22033b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173171648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2173171648
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2234794864
Short name T1
Test name
Test status
Simulation time 9856101705 ps
CPU time 37.47 seconds
Started Mar 17 01:33:06 PM PDT 24
Finished Mar 17 01:33:44 PM PDT 24
Peak memory 200464 kb
Host smart-dc0a9ddb-54e9-41c2-8411-d57c957e19bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234794864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2234794864
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.842608968
Short name T29
Test name
Test status
Simulation time 348917205 ps
CPU time 0.8 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:33:13 PM PDT 24
Peak memory 218584 kb
Host smart-d958ab85-48ef-4d4a-8e22-de81ef6335e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842608968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.842608968
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1205253636
Short name T361
Test name
Test status
Simulation time 288695249 ps
CPU time 4.53 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:33:17 PM PDT 24
Peak memory 200424 kb
Host smart-33f4c206-99b1-46b0-8980-512ef799c8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205253636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1205253636
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3149750895
Short name T5
Test name
Test status
Simulation time 34918260516 ps
CPU time 115.43 seconds
Started Mar 17 01:33:08 PM PDT 24
Finished Mar 17 01:35:04 PM PDT 24
Peak memory 200512 kb
Host smart-eb0041f8-8391-4052-97d6-e75a47dd4e07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149750895 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3149750895
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2030061316
Short name T484
Test name
Test status
Simulation time 15591272990 ps
CPU time 831.66 seconds
Started Mar 17 01:33:07 PM PDT 24
Finished Mar 17 01:46:59 PM PDT 24
Peak memory 225156 kb
Host smart-bc10a716-d291-4d8c-8e1b-493f36066594
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030061316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2030061316
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2345002783
Short name T160
Test name
Test status
Simulation time 194455471 ps
CPU time 1.26 seconds
Started Mar 17 01:33:06 PM PDT 24
Finished Mar 17 01:33:08 PM PDT 24
Peak memory 200000 kb
Host smart-15b0374f-dbdf-43af-82d0-bdaec3f033ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345002783 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2345002783
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1158944018
Short name T299
Test name
Test status
Simulation time 53898407807 ps
CPU time 488.78 seconds
Started Mar 17 01:33:08 PM PDT 24
Finished Mar 17 01:41:17 PM PDT 24
Peak memory 200440 kb
Host smart-c1fa429d-d89f-4850-a475-9f77f458cb72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158944018 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.1158944018
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3794129667
Short name T253
Test name
Test status
Simulation time 2633309214 ps
CPU time 59.07 seconds
Started Mar 17 01:33:05 PM PDT 24
Finished Mar 17 01:34:04 PM PDT 24
Peak memory 200492 kb
Host smart-f6a084a9-6de4-4625-bcf5-aca27edc6aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794129667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3794129667
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1973840645
Short name T218
Test name
Test status
Simulation time 12243966 ps
CPU time 0.58 seconds
Started Mar 17 01:35:40 PM PDT 24
Finished Mar 17 01:35:41 PM PDT 24
Peak memory 195776 kb
Host smart-cba21b12-8826-48e8-91c1-9d77cc7731a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973840645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1973840645
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2766258605
Short name T524
Test name
Test status
Simulation time 3570140865 ps
CPU time 60.56 seconds
Started Mar 17 01:35:40 PM PDT 24
Finished Mar 17 01:36:41 PM PDT 24
Peak memory 216940 kb
Host smart-b482d4cf-a3c9-4769-baf3-323a5bf45115
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2766258605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2766258605
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3979819656
Short name T113
Test name
Test status
Simulation time 1809144282 ps
CPU time 36.91 seconds
Started Mar 17 01:35:42 PM PDT 24
Finished Mar 17 01:36:19 PM PDT 24
Peak memory 200420 kb
Host smart-de0e55ac-f598-4853-82d1-5ff7061801c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979819656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3979819656
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.182696180
Short name T398
Test name
Test status
Simulation time 9798656298 ps
CPU time 42.67 seconds
Started Mar 17 01:35:41 PM PDT 24
Finished Mar 17 01:36:24 PM PDT 24
Peak memory 200508 kb
Host smart-eb450391-66b9-4909-881b-bc0fa233e380
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182696180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.182696180
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4091187598
Short name T124
Test name
Test status
Simulation time 12040541813 ps
CPU time 82.98 seconds
Started Mar 17 01:35:42 PM PDT 24
Finished Mar 17 01:37:05 PM PDT 24
Peak memory 200584 kb
Host smart-fd39c9d5-d672-4f7f-91d2-877ab8b0b1f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091187598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4091187598
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.24368896
Short name T244
Test name
Test status
Simulation time 8060196568 ps
CPU time 123.46 seconds
Started Mar 17 01:35:40 PM PDT 24
Finished Mar 17 01:37:44 PM PDT 24
Peak memory 200536 kb
Host smart-d70c0cab-95bc-4a5c-b429-7a02951e6ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24368896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.24368896
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1837412266
Short name T515
Test name
Test status
Simulation time 304091432 ps
CPU time 4.62 seconds
Started Mar 17 01:35:39 PM PDT 24
Finished Mar 17 01:35:44 PM PDT 24
Peak memory 200388 kb
Host smart-a53e82d5-5c8f-4b39-85b2-f2639a0c07d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837412266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1837412266
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1391994571
Short name T593
Test name
Test status
Simulation time 4873228895 ps
CPU time 213.89 seconds
Started Mar 17 01:35:42 PM PDT 24
Finished Mar 17 01:39:17 PM PDT 24
Peak memory 200572 kb
Host smart-3a87640e-45af-45ef-82bd-38d5ba0cac40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391994571 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1391994571
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3264025930
Short name T142
Test name
Test status
Simulation time 91415543 ps
CPU time 1.13 seconds
Started Mar 17 01:35:47 PM PDT 24
Finished Mar 17 01:35:48 PM PDT 24
Peak memory 199964 kb
Host smart-ecbd27f9-5e16-4d18-a081-54ef552637ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264025930 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3264025930
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3601146099
Short name T429
Test name
Test status
Simulation time 139981414353 ps
CPU time 508.5 seconds
Started Mar 17 01:35:46 PM PDT 24
Finished Mar 17 01:44:14 PM PDT 24
Peak memory 200408 kb
Host smart-14a285ec-4a6b-4459-8725-77b5220dbf2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601146099 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3601146099
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1117532981
Short name T354
Test name
Test status
Simulation time 3796370356 ps
CPU time 83.92 seconds
Started Mar 17 01:35:40 PM PDT 24
Finished Mar 17 01:37:05 PM PDT 24
Peak memory 200520 kb
Host smart-6e9f788d-ada3-4b84-b611-8df50c1efb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117532981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1117532981
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2558269090
Short name T185
Test name
Test status
Simulation time 68890966 ps
CPU time 0.54 seconds
Started Mar 17 01:35:49 PM PDT 24
Finished Mar 17 01:35:50 PM PDT 24
Peak memory 194840 kb
Host smart-af1e7962-9c3c-4063-bb2f-f20ea16f2166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558269090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2558269090
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2392141889
Short name T17
Test name
Test status
Simulation time 7419160338 ps
CPU time 76.22 seconds
Started Mar 17 01:35:50 PM PDT 24
Finished Mar 17 01:37:06 PM PDT 24
Peak memory 240852 kb
Host smart-82369ec9-f60e-43d3-867a-729f980c49ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392141889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2392141889
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.4135120703
Short name T23
Test name
Test status
Simulation time 716772157 ps
CPU time 10.29 seconds
Started Mar 17 01:35:50 PM PDT 24
Finished Mar 17 01:36:00 PM PDT 24
Peak memory 200444 kb
Host smart-fb5a2c1f-4724-40fc-aaf2-564f6f8dccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135120703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.4135120703
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2612909354
Short name T540
Test name
Test status
Simulation time 2523455798 ps
CPU time 74.24 seconds
Started Mar 17 01:35:47 PM PDT 24
Finished Mar 17 01:37:02 PM PDT 24
Peak memory 200484 kb
Host smart-fe8c502b-e981-4088-809b-7e86718ccafd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612909354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2612909354
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1705637934
Short name T519
Test name
Test status
Simulation time 1120165064 ps
CPU time 19.5 seconds
Started Mar 17 01:35:47 PM PDT 24
Finished Mar 17 01:36:07 PM PDT 24
Peak memory 200440 kb
Host smart-70f24245-dcad-4af9-a860-e8231fe0e85c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705637934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1705637934
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3132020855
Short name T417
Test name
Test status
Simulation time 5748554595 ps
CPU time 125.67 seconds
Started Mar 17 01:35:51 PM PDT 24
Finished Mar 17 01:37:57 PM PDT 24
Peak memory 200544 kb
Host smart-ccc8faff-353b-40d3-84df-cfe84fc42793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132020855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3132020855
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3307577211
Short name T69
Test name
Test status
Simulation time 978646679 ps
CPU time 6.11 seconds
Started Mar 17 01:35:46 PM PDT 24
Finished Mar 17 01:35:52 PM PDT 24
Peak memory 200416 kb
Host smart-503d32cf-91c9-4341-b7b3-07fa6eb4452d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307577211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3307577211
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3212247362
Short name T444
Test name
Test status
Simulation time 8217206010 ps
CPU time 453.84 seconds
Started Mar 17 01:35:47 PM PDT 24
Finished Mar 17 01:43:21 PM PDT 24
Peak memory 200496 kb
Host smart-9e884598-f95d-404a-a910-493224067b6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212247362 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3212247362
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.532557636
Short name T539
Test name
Test status
Simulation time 71055863 ps
CPU time 1.33 seconds
Started Mar 17 01:35:48 PM PDT 24
Finished Mar 17 01:35:50 PM PDT 24
Peak memory 200252 kb
Host smart-0b9edef2-78ae-48e9-a967-ffbb39de0fa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532557636 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.532557636
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3597520659
Short name T559
Test name
Test status
Simulation time 101384740044 ps
CPU time 458.01 seconds
Started Mar 17 01:35:48 PM PDT 24
Finished Mar 17 01:43:26 PM PDT 24
Peak memory 200424 kb
Host smart-b480afc9-e828-4ee0-83f9-c6defd688e60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597520659 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3597520659
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2945225977
Short name T175
Test name
Test status
Simulation time 4355662989 ps
CPU time 53.97 seconds
Started Mar 17 01:35:48 PM PDT 24
Finished Mar 17 01:36:42 PM PDT 24
Peak memory 200520 kb
Host smart-0378bfd8-278c-47f0-a860-284b7535aeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945225977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2945225977
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1350072757
Short name T463
Test name
Test status
Simulation time 31586435 ps
CPU time 0.58 seconds
Started Mar 17 01:35:55 PM PDT 24
Finished Mar 17 01:35:55 PM PDT 24
Peak memory 195904 kb
Host smart-d36c875c-d418-4588-a598-a278e1cd44b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350072757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1350072757
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.4283558956
Short name T418
Test name
Test status
Simulation time 2999955784 ps
CPU time 36.72 seconds
Started Mar 17 01:35:48 PM PDT 24
Finished Mar 17 01:36:25 PM PDT 24
Peak memory 241516 kb
Host smart-7630670a-be07-4b8a-b871-fd60849f8266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283558956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.4283558956
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3380336102
Short name T320
Test name
Test status
Simulation time 8286455618 ps
CPU time 54.3 seconds
Started Mar 17 01:35:52 PM PDT 24
Finished Mar 17 01:36:47 PM PDT 24
Peak memory 200488 kb
Host smart-b1e5f802-1ed9-4a8b-9258-c8f6c2efe0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380336102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3380336102
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.815492278
Short name T340
Test name
Test status
Simulation time 2157108380 ps
CPU time 140.36 seconds
Started Mar 17 01:35:55 PM PDT 24
Finished Mar 17 01:38:15 PM PDT 24
Peak memory 200572 kb
Host smart-29fbeceb-2e76-4626-8b64-751defea4ace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815492278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.815492278
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3106524562
Short name T406
Test name
Test status
Simulation time 2095019443 ps
CPU time 59.75 seconds
Started Mar 17 01:35:53 PM PDT 24
Finished Mar 17 01:36:53 PM PDT 24
Peak memory 200424 kb
Host smart-5cb29fbd-8d14-455b-8706-11dd2c9079cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106524562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3106524562
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.357628186
Short name T365
Test name
Test status
Simulation time 2493800660 ps
CPU time 35.41 seconds
Started Mar 17 01:35:48 PM PDT 24
Finished Mar 17 01:36:24 PM PDT 24
Peak memory 200500 kb
Host smart-706b79ef-0f20-4756-8a22-29f646952929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357628186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.357628186
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1326241355
Short name T133
Test name
Test status
Simulation time 1620091004 ps
CPU time 6.06 seconds
Started Mar 17 01:35:47 PM PDT 24
Finished Mar 17 01:35:54 PM PDT 24
Peak memory 200460 kb
Host smart-379d7465-63a2-4e69-94b2-f3a5eb3ceec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326241355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1326241355
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3390105375
Short name T103
Test name
Test status
Simulation time 49021498109 ps
CPU time 2718.14 seconds
Started Mar 17 01:35:54 PM PDT 24
Finished Mar 17 02:21:13 PM PDT 24
Peak memory 200512 kb
Host smart-efc88b80-cbd2-4333-b679-c44e0cd5a13e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390105375 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3390105375
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1089210529
Short name T575
Test name
Test status
Simulation time 29931131 ps
CPU time 1.13 seconds
Started Mar 17 01:35:52 PM PDT 24
Finished Mar 17 01:35:53 PM PDT 24
Peak memory 199856 kb
Host smart-91f4743d-cca3-42c3-9eeb-b2b2e532447a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089210529 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1089210529
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2573070889
Short name T568
Test name
Test status
Simulation time 7355978357 ps
CPU time 414.21 seconds
Started Mar 17 01:35:56 PM PDT 24
Finished Mar 17 01:42:51 PM PDT 24
Peak memory 200424 kb
Host smart-88a006ff-c65c-4c3d-a531-0110db5ca9fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573070889 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2573070889
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3537867392
Short name T533
Test name
Test status
Simulation time 2440973562 ps
CPU time 78.56 seconds
Started Mar 17 01:35:54 PM PDT 24
Finished Mar 17 01:37:13 PM PDT 24
Peak memory 200532 kb
Host smart-22f10d51-e994-4e7c-b6e7-9b397e5a2200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537867392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3537867392
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2171260116
Short name T349
Test name
Test status
Simulation time 160526701 ps
CPU time 0.59 seconds
Started Mar 17 01:36:01 PM PDT 24
Finished Mar 17 01:36:01 PM PDT 24
Peak memory 195864 kb
Host smart-6ccd5fed-ea9d-40f1-aafb-d328067bdcf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171260116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2171260116
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1170627964
Short name T401
Test name
Test status
Simulation time 431315509 ps
CPU time 14.46 seconds
Started Mar 17 01:35:52 PM PDT 24
Finished Mar 17 01:36:06 PM PDT 24
Peak memory 200392 kb
Host smart-9f3bee32-48e8-4309-91e1-86e7e60e1cb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170627964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1170627964
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1363547830
Short name T547
Test name
Test status
Simulation time 2154001534 ps
CPU time 4.84 seconds
Started Mar 17 01:35:58 PM PDT 24
Finished Mar 17 01:36:03 PM PDT 24
Peak memory 200520 kb
Host smart-b0150b67-b1f0-44d1-ba58-306dd9cabe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363547830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1363547830
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.260970577
Short name T151
Test name
Test status
Simulation time 1245967131 ps
CPU time 77.55 seconds
Started Mar 17 01:35:52 PM PDT 24
Finished Mar 17 01:37:09 PM PDT 24
Peak memory 200368 kb
Host smart-2f96677b-f438-4e3f-a064-2ddc1245616f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260970577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.260970577
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1256519546
Short name T564
Test name
Test status
Simulation time 1195783311 ps
CPU time 11.19 seconds
Started Mar 17 01:35:59 PM PDT 24
Finished Mar 17 01:36:11 PM PDT 24
Peak memory 200296 kb
Host smart-3a145294-7f85-42d0-aa16-2ba2df028d0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256519546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1256519546
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2345420044
Short name T267
Test name
Test status
Simulation time 4677954233 ps
CPU time 93.35 seconds
Started Mar 17 01:35:54 PM PDT 24
Finished Mar 17 01:37:27 PM PDT 24
Peak memory 200556 kb
Host smart-28fe2665-1e76-43d6-8e2f-f7ea3ad3b54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345420044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2345420044
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2752665736
Short name T110
Test name
Test status
Simulation time 172280806 ps
CPU time 2.88 seconds
Started Mar 17 01:35:53 PM PDT 24
Finished Mar 17 01:35:56 PM PDT 24
Peak memory 200380 kb
Host smart-b10d2cfc-d79c-4c2a-8e0b-d079f83a77a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752665736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2752665736
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.988699010
Short name T288
Test name
Test status
Simulation time 10751457815 ps
CPU time 558.62 seconds
Started Mar 17 01:35:59 PM PDT 24
Finished Mar 17 01:45:18 PM PDT 24
Peak memory 224016 kb
Host smart-531a24a0-9cb0-4594-af8c-93e45a46af58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988699010 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.988699010
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1363797593
Short name T427
Test name
Test status
Simulation time 31214957 ps
CPU time 1.23 seconds
Started Mar 17 01:36:03 PM PDT 24
Finished Mar 17 01:36:04 PM PDT 24
Peak memory 200396 kb
Host smart-c0c17237-38d3-4e0f-b357-ab9626170192
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363797593 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1363797593
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.4024305595
Short name T545
Test name
Test status
Simulation time 27002844394 ps
CPU time 497.1 seconds
Started Mar 17 01:35:59 PM PDT 24
Finished Mar 17 01:44:17 PM PDT 24
Peak memory 200496 kb
Host smart-077b0329-489b-44da-90af-3abb435ab9d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024305595 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.4024305595
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2635320444
Short name T562
Test name
Test status
Simulation time 2023327681 ps
CPU time 45.97 seconds
Started Mar 17 01:36:01 PM PDT 24
Finished Mar 17 01:36:48 PM PDT 24
Peak memory 200396 kb
Host smart-0718b841-bf14-463a-8c6c-8d35eea2e2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635320444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2635320444
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2607190591
Short name T182
Test name
Test status
Simulation time 11604087 ps
CPU time 0.58 seconds
Started Mar 17 01:36:07 PM PDT 24
Finished Mar 17 01:36:08 PM PDT 24
Peak memory 195892 kb
Host smart-070c43c8-439a-4cc4-8063-69d38d1164ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607190591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2607190591
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2761939247
Short name T50
Test name
Test status
Simulation time 86483328 ps
CPU time 2.52 seconds
Started Mar 17 01:35:59 PM PDT 24
Finished Mar 17 01:36:01 PM PDT 24
Peak memory 216120 kb
Host smart-198c0f21-b9e7-4d2d-bd66-87a9338178c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2761939247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2761939247
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3348603624
Short name T382
Test name
Test status
Simulation time 5406220051 ps
CPU time 72.39 seconds
Started Mar 17 01:36:01 PM PDT 24
Finished Mar 17 01:37:14 PM PDT 24
Peak memory 200452 kb
Host smart-46c5fa4e-963d-4818-b024-d16d123686e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348603624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3348603624
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2857484369
Short name T351
Test name
Test status
Simulation time 3378079919 ps
CPU time 54.27 seconds
Started Mar 17 01:36:01 PM PDT 24
Finished Mar 17 01:36:55 PM PDT 24
Peak memory 200572 kb
Host smart-6bbdd2a6-edf6-418c-914c-705d865e09c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857484369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2857484369
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.853831167
Short name T509
Test name
Test status
Simulation time 11241717877 ps
CPU time 69.33 seconds
Started Mar 17 01:36:01 PM PDT 24
Finished Mar 17 01:37:10 PM PDT 24
Peak memory 200468 kb
Host smart-bce3ed48-122f-41aa-b005-2bdf27eb0c56
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853831167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.853831167
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4126154404
Short name T252
Test name
Test status
Simulation time 5820113743 ps
CPU time 85.23 seconds
Started Mar 17 01:35:59 PM PDT 24
Finished Mar 17 01:37:25 PM PDT 24
Peak memory 200536 kb
Host smart-85578326-2563-420d-a037-832095d8e214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126154404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4126154404
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2386127261
Short name T192
Test name
Test status
Simulation time 547742412 ps
CPU time 6.56 seconds
Started Mar 17 01:36:00 PM PDT 24
Finished Mar 17 01:36:07 PM PDT 24
Peak memory 200420 kb
Host smart-668a6379-e09e-486d-a62a-06b4dbc11683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386127261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2386127261
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2893419519
Short name T148
Test name
Test status
Simulation time 7442071556 ps
CPU time 260.39 seconds
Started Mar 17 01:36:03 PM PDT 24
Finished Mar 17 01:40:24 PM PDT 24
Peak memory 200540 kb
Host smart-0ee63b96-c279-4e84-8649-c279b86fdec0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893419519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2893419519
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3724065004
Short name T324
Test name
Test status
Simulation time 94882859 ps
CPU time 0.99 seconds
Started Mar 17 01:36:05 PM PDT 24
Finished Mar 17 01:36:06 PM PDT 24
Peak memory 198600 kb
Host smart-df6256c3-eb61-4a9f-ad03-1934e144271b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724065004 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3724065004
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2056061065
Short name T503
Test name
Test status
Simulation time 7404803502 ps
CPU time 422.55 seconds
Started Mar 17 01:36:09 PM PDT 24
Finished Mar 17 01:43:12 PM PDT 24
Peak memory 200476 kb
Host smart-b248f4e3-1b9c-4d28-aaaa-4701c1caa26d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056061065 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.2056061065
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.4000332885
Short name T379
Test name
Test status
Simulation time 5813009311 ps
CPU time 55.07 seconds
Started Mar 17 01:35:58 PM PDT 24
Finished Mar 17 01:36:53 PM PDT 24
Peak memory 200548 kb
Host smart-3694d6d0-482c-471a-800e-727a8ac5cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000332885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.4000332885
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2120907547
Short name T285
Test name
Test status
Simulation time 158298338 ps
CPU time 0.62 seconds
Started Mar 17 01:36:03 PM PDT 24
Finished Mar 17 01:36:04 PM PDT 24
Peak memory 195960 kb
Host smart-02d20127-1b7e-4098-b79c-cd20fcaeba0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120907547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2120907547
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1136427892
Short name T430
Test name
Test status
Simulation time 65658620 ps
CPU time 2.71 seconds
Started Mar 17 01:36:05 PM PDT 24
Finished Mar 17 01:36:08 PM PDT 24
Peak memory 200448 kb
Host smart-189aff7a-b200-4d96-994b-fb14fdfa2433
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136427892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1136427892
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3834180383
Short name T499
Test name
Test status
Simulation time 6280436903 ps
CPU time 54.62 seconds
Started Mar 17 01:36:06 PM PDT 24
Finished Mar 17 01:37:00 PM PDT 24
Peak memory 200552 kb
Host smart-8d203bbf-bd8b-4888-b51a-99ca59df5462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834180383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3834180383
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3531831489
Short name T339
Test name
Test status
Simulation time 328881730 ps
CPU time 8.91 seconds
Started Mar 17 01:36:04 PM PDT 24
Finished Mar 17 01:36:13 PM PDT 24
Peak memory 200404 kb
Host smart-cbe78826-1b5e-411c-9eba-635154a5e0b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531831489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3531831489
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4232033660
Short name T313
Test name
Test status
Simulation time 189578384569 ps
CPU time 167.97 seconds
Started Mar 17 01:36:05 PM PDT 24
Finished Mar 17 01:38:53 PM PDT 24
Peak memory 200540 kb
Host smart-6c172e05-1254-4a32-aa21-09bd2b978a37
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232033660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4232033660
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4290578112
Short name T594
Test name
Test status
Simulation time 5892319188 ps
CPU time 23.08 seconds
Started Mar 17 01:36:04 PM PDT 24
Finished Mar 17 01:36:27 PM PDT 24
Peak memory 200484 kb
Host smart-7385d817-cd9c-449a-9846-37a0f7fb03a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290578112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4290578112
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.281773646
Short name T522
Test name
Test status
Simulation time 475025741 ps
CPU time 6.62 seconds
Started Mar 17 01:36:05 PM PDT 24
Finished Mar 17 01:36:12 PM PDT 24
Peak memory 200480 kb
Host smart-8ad48484-8272-4ad1-867b-bfa7c6a786d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281773646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.281773646
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.878945734
Short name T13
Test name
Test status
Simulation time 77055374027 ps
CPU time 1506.59 seconds
Started Mar 17 01:36:05 PM PDT 24
Finished Mar 17 02:01:12 PM PDT 24
Peak memory 216896 kb
Host smart-a0ffbea0-77f6-4f40-aefd-e1722a685571
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878945734 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.878945734
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.4265799470
Short name T122
Test name
Test status
Simulation time 30052602 ps
CPU time 1.29 seconds
Started Mar 17 01:36:05 PM PDT 24
Finished Mar 17 01:36:06 PM PDT 24
Peak memory 200428 kb
Host smart-9f2603d8-1663-4217-8112-7ce0c4804317
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265799470 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.4265799470
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3122137633
Short name T415
Test name
Test status
Simulation time 147438649440 ps
CPU time 496.33 seconds
Started Mar 17 01:36:04 PM PDT 24
Finished Mar 17 01:44:21 PM PDT 24
Peak memory 200356 kb
Host smart-274420d7-96c5-46ea-830c-404182a3660d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122137633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.3122137633
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.610443516
Short name T404
Test name
Test status
Simulation time 3063841154 ps
CPU time 7.08 seconds
Started Mar 17 01:36:05 PM PDT 24
Finished Mar 17 01:36:12 PM PDT 24
Peak memory 200492 kb
Host smart-23424b8d-b7f8-4c1e-b516-786a65a291f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610443516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.610443516
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3556716789
Short name T459
Test name
Test status
Simulation time 45975783 ps
CPU time 0.59 seconds
Started Mar 17 01:36:16 PM PDT 24
Finished Mar 17 01:36:17 PM PDT 24
Peak memory 195840 kb
Host smart-2a3f13ae-536c-41bd-929c-9522a3d1a1b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556716789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3556716789
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2158477073
Short name T358
Test name
Test status
Simulation time 4763860835 ps
CPU time 20.99 seconds
Started Mar 17 01:36:13 PM PDT 24
Finished Mar 17 01:36:35 PM PDT 24
Peak memory 208612 kb
Host smart-b6f7bcf4-61c6-43a9-978a-80958a70420c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158477073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2158477073
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3091667253
Short name T592
Test name
Test status
Simulation time 16773727149 ps
CPU time 37.82 seconds
Started Mar 17 01:36:11 PM PDT 24
Finished Mar 17 01:36:49 PM PDT 24
Peak memory 200488 kb
Host smart-29959ae7-bd0e-4cfb-b8dd-62f666e9ca7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091667253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3091667253
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2517551625
Short name T408
Test name
Test status
Simulation time 1115417493 ps
CPU time 70 seconds
Started Mar 17 01:36:13 PM PDT 24
Finished Mar 17 01:37:24 PM PDT 24
Peak memory 200424 kb
Host smart-9663bda2-7e9f-40e8-a158-32ae3115a081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517551625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2517551625
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1204363849
Short name T16
Test name
Test status
Simulation time 13853638460 ps
CPU time 63.63 seconds
Started Mar 17 01:36:12 PM PDT 24
Finished Mar 17 01:37:17 PM PDT 24
Peak memory 200516 kb
Host smart-416ae8fc-6f55-4702-b512-a8cb36c832ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204363849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1204363849
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3820798429
Short name T474
Test name
Test status
Simulation time 362295639 ps
CPU time 16.46 seconds
Started Mar 17 01:36:13 PM PDT 24
Finished Mar 17 01:36:30 PM PDT 24
Peak memory 200432 kb
Host smart-75240d68-9579-4382-afc5-a5b86f355525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820798429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3820798429
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2039152659
Short name T504
Test name
Test status
Simulation time 909593232 ps
CPU time 6.91 seconds
Started Mar 17 01:36:13 PM PDT 24
Finished Mar 17 01:36:21 PM PDT 24
Peak memory 200412 kb
Host smart-d6b33b3b-e0a6-461b-96a4-70f83e8a3e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039152659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2039152659
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3714067516
Short name T383
Test name
Test status
Simulation time 65782018073 ps
CPU time 885.76 seconds
Started Mar 17 01:36:14 PM PDT 24
Finished Mar 17 01:51:01 PM PDT 24
Peak memory 208736 kb
Host smart-03fcadf2-fd05-423e-abd8-ce0c320ec790
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714067516 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3714067516
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2071564231
Short name T472
Test name
Test status
Simulation time 88932423 ps
CPU time 1.26 seconds
Started Mar 17 01:36:11 PM PDT 24
Finished Mar 17 01:36:12 PM PDT 24
Peak memory 200344 kb
Host smart-6e55051d-79a9-4098-b310-6c515d295119
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071564231 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.2071564231
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1352269532
Short name T432
Test name
Test status
Simulation time 15075311111 ps
CPU time 446.42 seconds
Started Mar 17 01:36:12 PM PDT 24
Finished Mar 17 01:43:39 PM PDT 24
Peak memory 200512 kb
Host smart-8d4de7e7-f62a-44cb-bad0-851819ea5952
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352269532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.1352269532
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3479936655
Short name T127
Test name
Test status
Simulation time 1616203430 ps
CPU time 20 seconds
Started Mar 17 01:36:12 PM PDT 24
Finished Mar 17 01:36:32 PM PDT 24
Peak memory 200480 kb
Host smart-0b87061e-5f21-4dae-b095-87d05f1a4a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479936655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3479936655
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.414865046
Short name T39
Test name
Test status
Simulation time 14168262 ps
CPU time 0.59 seconds
Started Mar 17 01:36:17 PM PDT 24
Finished Mar 17 01:36:19 PM PDT 24
Peak memory 195744 kb
Host smart-f4c459a7-b987-4e5a-8493-1fcf478b57e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414865046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.414865046
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.585599796
Short name T53
Test name
Test status
Simulation time 5835927598 ps
CPU time 55.44 seconds
Started Mar 17 01:36:16 PM PDT 24
Finished Mar 17 01:37:14 PM PDT 24
Peak memory 216148 kb
Host smart-a6cee1e2-4b15-48ee-a122-8721831adb86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585599796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.585599796
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2832139810
Short name T280
Test name
Test status
Simulation time 4315547880 ps
CPU time 43.67 seconds
Started Mar 17 01:36:19 PM PDT 24
Finished Mar 17 01:37:04 PM PDT 24
Peak memory 200460 kb
Host smart-4b1fb26f-cd51-49c1-b131-6707b13df6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832139810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2832139810
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1039019016
Short name T241
Test name
Test status
Simulation time 3360892728 ps
CPU time 37.54 seconds
Started Mar 17 01:36:17 PM PDT 24
Finished Mar 17 01:36:56 PM PDT 24
Peak memory 200472 kb
Host smart-37879d19-e5a4-4f5d-8f4e-d4d85298ae37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039019016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1039019016
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1399659866
Short name T556
Test name
Test status
Simulation time 423142917 ps
CPU time 22.4 seconds
Started Mar 17 01:36:18 PM PDT 24
Finished Mar 17 01:36:42 PM PDT 24
Peak memory 200464 kb
Host smart-cb581f02-30b1-496b-aca8-16ac3e9e384e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399659866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1399659866
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1220064618
Short name T590
Test name
Test status
Simulation time 9677066546 ps
CPU time 70.04 seconds
Started Mar 17 01:36:15 PM PDT 24
Finished Mar 17 01:37:26 PM PDT 24
Peak memory 200488 kb
Host smart-78a65cbe-736b-414b-b5d6-37c2b47612ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220064618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1220064618
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3544590257
Short name T231
Test name
Test status
Simulation time 527520622 ps
CPU time 4.57 seconds
Started Mar 17 01:36:18 PM PDT 24
Finished Mar 17 01:36:24 PM PDT 24
Peak memory 200408 kb
Host smart-a3ccab61-7acd-453a-8007-2cfa18de28b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544590257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3544590257
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2105773006
Short name T77
Test name
Test status
Simulation time 94594726216 ps
CPU time 1287.19 seconds
Started Mar 17 01:36:16 PM PDT 24
Finished Mar 17 01:57:44 PM PDT 24
Peak memory 249012 kb
Host smart-00f020ae-7d72-4588-933a-d2d421252a89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105773006 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2105773006
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.76895177
Short name T412
Test name
Test status
Simulation time 133402035 ps
CPU time 1.31 seconds
Started Mar 17 01:36:16 PM PDT 24
Finished Mar 17 01:36:19 PM PDT 24
Peak memory 200380 kb
Host smart-a59248ef-2c50-4099-992d-6031693adc9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76895177 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.hmac_test_hmac_vectors.76895177
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2862602551
Short name T164
Test name
Test status
Simulation time 17497798494 ps
CPU time 474.99 seconds
Started Mar 17 01:36:16 PM PDT 24
Finished Mar 17 01:44:12 PM PDT 24
Peak memory 200452 kb
Host smart-966736d1-e350-4f1c-b453-ec84cf7f239d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862602551 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2862602551
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2821469578
Short name T153
Test name
Test status
Simulation time 11476209153 ps
CPU time 69.77 seconds
Started Mar 17 01:36:18 PM PDT 24
Finished Mar 17 01:37:28 PM PDT 24
Peak memory 200472 kb
Host smart-e9d9ae10-21ba-473d-a37d-03d81db1a8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821469578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2821469578
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1229128934
Short name T517
Test name
Test status
Simulation time 36600183 ps
CPU time 0.56 seconds
Started Mar 17 01:36:27 PM PDT 24
Finished Mar 17 01:36:28 PM PDT 24
Peak memory 195756 kb
Host smart-b78223f5-5733-41df-811a-c767f21b4ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229128934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1229128934
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.349779439
Short name T420
Test name
Test status
Simulation time 898150440 ps
CPU time 40.43 seconds
Started Mar 17 01:36:21 PM PDT 24
Finished Mar 17 01:37:01 PM PDT 24
Peak memory 239732 kb
Host smart-60b56539-c7a4-4c86-8a91-053c2b91094d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349779439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.349779439
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1228185501
Short name T155
Test name
Test status
Simulation time 5093458207 ps
CPU time 28.35 seconds
Started Mar 17 01:36:23 PM PDT 24
Finished Mar 17 01:36:51 PM PDT 24
Peak memory 200532 kb
Host smart-be1a6adb-2a87-481e-858a-da2ad7c27461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228185501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1228185501
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2779845174
Short name T551
Test name
Test status
Simulation time 3148969609 ps
CPU time 105.13 seconds
Started Mar 17 01:36:21 PM PDT 24
Finished Mar 17 01:38:06 PM PDT 24
Peak memory 200564 kb
Host smart-4693c117-8837-447b-9e81-9d6c748fb054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779845174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2779845174
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.453577072
Short name T246
Test name
Test status
Simulation time 7013637178 ps
CPU time 94.3 seconds
Started Mar 17 01:36:21 PM PDT 24
Finished Mar 17 01:37:56 PM PDT 24
Peak memory 200484 kb
Host smart-3f1a61ba-fae8-4a16-9460-47bf202a2ff0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453577072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.453577072
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2621341854
Short name T586
Test name
Test status
Simulation time 972264609 ps
CPU time 14.73 seconds
Started Mar 17 01:36:20 PM PDT 24
Finished Mar 17 01:36:35 PM PDT 24
Peak memory 200508 kb
Host smart-bbde84f4-d358-413d-92bb-d2c6d88db414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621341854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2621341854
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.4097100424
Short name T380
Test name
Test status
Simulation time 429975595 ps
CPU time 5.89 seconds
Started Mar 17 01:36:15 PM PDT 24
Finished Mar 17 01:36:21 PM PDT 24
Peak memory 200528 kb
Host smart-d9697117-0b06-4034-a25f-c7a62dcec678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097100424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4097100424
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2599730158
Short name T187
Test name
Test status
Simulation time 15663433785 ps
CPU time 58.84 seconds
Started Mar 17 01:36:21 PM PDT 24
Finished Mar 17 01:37:20 PM PDT 24
Peak memory 209740 kb
Host smart-17b673c3-2d68-4312-9e53-09da1735622c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599730158 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2599730158
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2027464144
Short name T393
Test name
Test status
Simulation time 188070728 ps
CPU time 1.22 seconds
Started Mar 17 01:36:21 PM PDT 24
Finished Mar 17 01:36:23 PM PDT 24
Peak memory 200060 kb
Host smart-c6640699-5a59-4c36-8344-aa0bdb74e8e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027464144 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2027464144
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3419320333
Short name T580
Test name
Test status
Simulation time 31921215201 ps
CPU time 453.98 seconds
Started Mar 17 01:36:20 PM PDT 24
Finished Mar 17 01:43:54 PM PDT 24
Peak memory 200444 kb
Host smart-4d6dcc2f-4bd9-40e9-be27-d1a91c0fc59c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419320333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.3419320333
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2136423584
Short name T405
Test name
Test status
Simulation time 10118075525 ps
CPU time 38.94 seconds
Started Mar 17 01:36:22 PM PDT 24
Finished Mar 17 01:37:01 PM PDT 24
Peak memory 200500 kb
Host smart-d06d2572-cdab-48fa-aa73-ffad4406aed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136423584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2136423584
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2438594830
Short name T137
Test name
Test status
Simulation time 19487005 ps
CPU time 0.57 seconds
Started Mar 17 01:36:28 PM PDT 24
Finished Mar 17 01:36:29 PM PDT 24
Peak memory 194844 kb
Host smart-321646a5-260b-4874-a9c4-c3aba62dc632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438594830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2438594830
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3985160631
Short name T467
Test name
Test status
Simulation time 501340680 ps
CPU time 4.49 seconds
Started Mar 17 01:36:27 PM PDT 24
Finished Mar 17 01:36:31 PM PDT 24
Peak memory 200448 kb
Host smart-19f87160-80e4-4e74-90ac-2dd30186f116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985160631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3985160631
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4278085082
Short name T154
Test name
Test status
Simulation time 803702501 ps
CPU time 37.39 seconds
Started Mar 17 01:36:30 PM PDT 24
Finished Mar 17 01:37:07 PM PDT 24
Peak memory 200340 kb
Host smart-6ef3d88e-491c-433e-8261-a5cff9409cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278085082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4278085082
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2899274462
Short name T395
Test name
Test status
Simulation time 839810747 ps
CPU time 51.48 seconds
Started Mar 17 01:36:29 PM PDT 24
Finished Mar 17 01:37:21 PM PDT 24
Peak memory 200428 kb
Host smart-4487e390-ad70-478d-a2de-abac27bace13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899274462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2899274462
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.453431829
Short name T527
Test name
Test status
Simulation time 17393333532 ps
CPU time 158.15 seconds
Started Mar 17 01:36:28 PM PDT 24
Finished Mar 17 01:39:06 PM PDT 24
Peak memory 200484 kb
Host smart-0c04cfdf-2c7e-4d9d-9169-60e5851b24be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453431829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.453431829
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.960294496
Short name T161
Test name
Test status
Simulation time 564443112 ps
CPU time 16.45 seconds
Started Mar 17 01:36:28 PM PDT 24
Finished Mar 17 01:36:44 PM PDT 24
Peak memory 200440 kb
Host smart-c9cb1c75-df48-4aa0-b4c6-490c00d0c928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960294496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.960294496
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.169013500
Short name T486
Test name
Test status
Simulation time 190227620 ps
CPU time 3.35 seconds
Started Mar 17 01:36:31 PM PDT 24
Finished Mar 17 01:36:34 PM PDT 24
Peak memory 200432 kb
Host smart-066881ac-0443-4bf5-995c-97002660a048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169013500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.169013500
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1024010624
Short name T248
Test name
Test status
Simulation time 36868798417 ps
CPU time 944.61 seconds
Started Mar 17 01:36:30 PM PDT 24
Finished Mar 17 01:52:15 PM PDT 24
Peak memory 234972 kb
Host smart-7800e444-1287-472a-8592-2897768aa921
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024010624 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1024010624
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2843789974
Short name T332
Test name
Test status
Simulation time 32069325 ps
CPU time 1.16 seconds
Started Mar 17 01:36:27 PM PDT 24
Finished Mar 17 01:36:29 PM PDT 24
Peak memory 200376 kb
Host smart-2c963f96-af2c-42fa-b9a5-b21cb48a79ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843789974 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2843789974
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.669081059
Short name T141
Test name
Test status
Simulation time 29910838732 ps
CPU time 416.99 seconds
Started Mar 17 01:36:29 PM PDT 24
Finished Mar 17 01:43:27 PM PDT 24
Peak memory 200360 kb
Host smart-78e8865f-84bb-4cc0-aa7b-382d252e5794
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669081059 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.669081059
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2032860530
Short name T469
Test name
Test status
Simulation time 1258099225 ps
CPU time 54.63 seconds
Started Mar 17 01:36:27 PM PDT 24
Finished Mar 17 01:37:22 PM PDT 24
Peak memory 200428 kb
Host smart-4fa9611a-82ac-4c9f-a0d4-b0e120dbff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032860530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2032860530
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.195034297
Short name T453
Test name
Test status
Simulation time 30691653 ps
CPU time 0.59 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:33:13 PM PDT 24
Peak memory 195876 kb
Host smart-fd485c16-6131-45b8-9dab-c338ffeaf0b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195034297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.195034297
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3041313819
Short name T460
Test name
Test status
Simulation time 1738446951 ps
CPU time 84.81 seconds
Started Mar 17 01:33:06 PM PDT 24
Finished Mar 17 01:34:32 PM PDT 24
Peak memory 249092 kb
Host smart-8148df98-e5c8-45a9-8a37-48b0ccb5f01f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3041313819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3041313819
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1713509960
Short name T496
Test name
Test status
Simulation time 8496712607 ps
CPU time 64.4 seconds
Started Mar 17 01:33:13 PM PDT 24
Finished Mar 17 01:34:17 PM PDT 24
Peak memory 200464 kb
Host smart-dee09733-6dcd-4d62-86df-2ee8ed0928f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713509960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1713509960
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2250780265
Short name T266
Test name
Test status
Simulation time 4109721991 ps
CPU time 112.3 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:35:04 PM PDT 24
Peak memory 200496 kb
Host smart-36e374d9-1851-4d75-a255-ded013edf5a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2250780265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2250780265
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2986079835
Short name T571
Test name
Test status
Simulation time 2959770423 ps
CPU time 88.96 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:34:40 PM PDT 24
Peak memory 200484 kb
Host smart-f3597278-5d69-4f62-bc8e-ebccdac0ccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986079835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2986079835
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2786252138
Short name T348
Test name
Test status
Simulation time 151689204 ps
CPU time 1.54 seconds
Started Mar 17 01:33:05 PM PDT 24
Finished Mar 17 01:33:08 PM PDT 24
Peak memory 200360 kb
Host smart-f19a74e6-1ceb-4881-986c-f203bad66b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786252138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2786252138
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3749740717
Short name T71
Test name
Test status
Simulation time 15791076483 ps
CPU time 122.49 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:35:13 PM PDT 24
Peak memory 200564 kb
Host smart-8ab6e0ba-d486-4f8a-9124-18f9df436472
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749740717 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3749740717
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3018923606
Short name T207
Test name
Test status
Simulation time 40561932 ps
CPU time 0.99 seconds
Started Mar 17 01:33:12 PM PDT 24
Finished Mar 17 01:33:13 PM PDT 24
Peak memory 198828 kb
Host smart-7d9ac879-1743-4f92-910e-bfdaa5e1f964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018923606 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3018923606
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.332050775
Short name T454
Test name
Test status
Simulation time 74348900723 ps
CPU time 476.55 seconds
Started Mar 17 01:33:13 PM PDT 24
Finished Mar 17 01:41:09 PM PDT 24
Peak memory 200196 kb
Host smart-1d8242df-74ce-4ff2-849c-904465c339a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332050775 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.332050775
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4239205193
Short name T390
Test name
Test status
Simulation time 9924642296 ps
CPU time 84.66 seconds
Started Mar 17 01:33:15 PM PDT 24
Finished Mar 17 01:34:40 PM PDT 24
Peak memory 200492 kb
Host smart-bc3b63d8-5ab0-4f53-8c24-9976e6e2c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239205193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4239205193
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.2636782781
Short name T12
Test name
Test status
Simulation time 57130238777 ps
CPU time 3138.05 seconds
Started Mar 17 01:36:28 PM PDT 24
Finished Mar 17 02:28:46 PM PDT 24
Peak memory 249656 kb
Host smart-40503b9c-8307-42a2-b0b2-c43573897006
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2636782781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.2636782781
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2921271189
Short name T33
Test name
Test status
Simulation time 18013535 ps
CPU time 0.56 seconds
Started Mar 17 01:33:09 PM PDT 24
Finished Mar 17 01:33:10 PM PDT 24
Peak memory 195788 kb
Host smart-d3d09e22-67b6-482f-96bc-7fb03ec293ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921271189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2921271189
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2714909416
Short name T443
Test name
Test status
Simulation time 2210908823 ps
CPU time 20.78 seconds
Started Mar 17 01:33:10 PM PDT 24
Finished Mar 17 01:33:31 PM PDT 24
Peak memory 208716 kb
Host smart-03767049-fff9-4cb0-8fb1-e50575b27b12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2714909416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2714909416
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3101581869
Short name T589
Test name
Test status
Simulation time 1886487416 ps
CPU time 22.56 seconds
Started Mar 17 01:33:12 PM PDT 24
Finished Mar 17 01:33:35 PM PDT 24
Peak memory 200420 kb
Host smart-6ec51d49-3b56-46ce-ad49-a28c965b5834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101581869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3101581869
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1169611079
Short name T553
Test name
Test status
Simulation time 4205608097 ps
CPU time 73.25 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:34:25 PM PDT 24
Peak memory 200484 kb
Host smart-25071303-e651-4d44-ba5e-17b15f16c449
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1169611079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1169611079
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1399586717
Short name T452
Test name
Test status
Simulation time 6321708170 ps
CPU time 171.65 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:36:04 PM PDT 24
Peak memory 200428 kb
Host smart-73663b5b-fa17-497e-a5ec-7565016bb158
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399586717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1399586717
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3098376599
Short name T334
Test name
Test status
Simulation time 605661812 ps
CPU time 18.3 seconds
Started Mar 17 01:33:13 PM PDT 24
Finished Mar 17 01:33:31 PM PDT 24
Peak memory 200504 kb
Host smart-f9391d92-e8af-4a96-96e1-21bdeccd5a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098376599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3098376599
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1738239828
Short name T458
Test name
Test status
Simulation time 884619622 ps
CPU time 6.62 seconds
Started Mar 17 01:33:10 PM PDT 24
Finished Mar 17 01:33:17 PM PDT 24
Peak memory 200432 kb
Host smart-526679d6-b205-40dc-9860-51df90bf9af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738239828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1738239828
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.758614904
Short name T426
Test name
Test status
Simulation time 24552906269 ps
CPU time 1296.07 seconds
Started Mar 17 01:33:14 PM PDT 24
Finished Mar 17 01:54:51 PM PDT 24
Peak memory 208676 kb
Host smart-7a8efe44-6aba-4755-b0af-b05e179fb75c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758614904 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.758614904
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2445924431
Short name T195
Test name
Test status
Simulation time 52874995 ps
CPU time 1.11 seconds
Started Mar 17 01:33:12 PM PDT 24
Finished Mar 17 01:33:13 PM PDT 24
Peak memory 199780 kb
Host smart-40ac14db-90bf-4a27-b784-2588a15118d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445924431 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2445924431
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3686880620
Short name T479
Test name
Test status
Simulation time 49101586505 ps
CPU time 407.03 seconds
Started Mar 17 01:33:10 PM PDT 24
Finished Mar 17 01:39:57 PM PDT 24
Peak memory 200456 kb
Host smart-307fdf5f-26d3-4467-a7de-6bad4974df13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686880620 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3686880620
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1043535903
Short name T345
Test name
Test status
Simulation time 9391283817 ps
CPU time 87.51 seconds
Started Mar 17 01:33:13 PM PDT 24
Finished Mar 17 01:34:40 PM PDT 24
Peak memory 200236 kb
Host smart-df1ded70-9915-4ee4-910f-9cd2e668bdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043535903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1043535903
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3817026605
Short name T336
Test name
Test status
Simulation time 33100086 ps
CPU time 0.6 seconds
Started Mar 17 01:33:26 PM PDT 24
Finished Mar 17 01:33:29 PM PDT 24
Peak memory 195812 kb
Host smart-b3814aae-3750-4c28-b851-ddf2c6fc9dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817026605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3817026605
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.717689829
Short name T425
Test name
Test status
Simulation time 805486326 ps
CPU time 30.02 seconds
Started Mar 17 01:33:26 PM PDT 24
Finished Mar 17 01:33:59 PM PDT 24
Peak memory 224416 kb
Host smart-a444e9a8-f171-4579-aae7-9c53a9efe810
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=717689829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.717689829
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1728118910
Short name T536
Test name
Test status
Simulation time 5998016231 ps
CPU time 60.4 seconds
Started Mar 17 01:33:16 PM PDT 24
Finished Mar 17 01:34:18 PM PDT 24
Peak memory 200556 kb
Host smart-c6c6f291-17f2-4fa0-bda4-2d89beebda06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728118910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1728118910
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2218386714
Short name T573
Test name
Test status
Simulation time 2708566756 ps
CPU time 123.79 seconds
Started Mar 17 01:33:19 PM PDT 24
Finished Mar 17 01:35:22 PM PDT 24
Peak memory 200544 kb
Host smart-1b849845-467a-4552-a91e-6ef9d6aaeee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2218386714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2218386714
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.513935242
Short name T121
Test name
Test status
Simulation time 14172040033 ps
CPU time 179.53 seconds
Started Mar 17 01:33:19 PM PDT 24
Finished Mar 17 01:36:18 PM PDT 24
Peak memory 200496 kb
Host smart-b05aa457-d89c-4ba4-b2d6-0cce17b16228
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513935242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.513935242
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1652047680
Short name T112
Test name
Test status
Simulation time 2066205660 ps
CPU time 39.99 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:33:52 PM PDT 24
Peak memory 200412 kb
Host smart-8da9f158-2845-497d-8578-8859e3fbc636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652047680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1652047680
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2288938302
Short name T473
Test name
Test status
Simulation time 230490758 ps
CPU time 6.52 seconds
Started Mar 17 01:33:11 PM PDT 24
Finished Mar 17 01:33:19 PM PDT 24
Peak memory 200436 kb
Host smart-d0197fa6-90e1-4dd4-98ae-a1eebbe7f5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288938302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2288938302
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.820419508
Short name T183
Test name
Test status
Simulation time 106330952684 ps
CPU time 488.2 seconds
Started Mar 17 01:33:26 PM PDT 24
Finished Mar 17 01:41:37 PM PDT 24
Peak memory 200492 kb
Host smart-49198613-7c49-460d-9d53-7da0b17bc295
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820419508 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.820419508
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1575829195
Short name T40
Test name
Test status
Simulation time 238412111 ps
CPU time 1.35 seconds
Started Mar 17 01:33:26 PM PDT 24
Finished Mar 17 01:33:30 PM PDT 24
Peak memory 200340 kb
Host smart-74564072-dd3c-43da-81d0-2ce04303ed6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575829195 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1575829195
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2946858483
Short name T567
Test name
Test status
Simulation time 8331928059 ps
CPU time 487.83 seconds
Started Mar 17 01:33:28 PM PDT 24
Finished Mar 17 01:41:36 PM PDT 24
Peak memory 200512 kb
Host smart-15e1c7c9-b512-466b-b707-42935bc82d7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946858483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2946858483
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3076215076
Short name T286
Test name
Test status
Simulation time 1664458429 ps
CPU time 34.68 seconds
Started Mar 17 01:33:15 PM PDT 24
Finished Mar 17 01:33:51 PM PDT 24
Peak memory 200456 kb
Host smart-17083f4f-744e-419d-82f3-c36de126b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076215076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3076215076
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.1740259588
Short name T543
Test name
Test status
Simulation time 110631992669 ps
CPU time 597.23 seconds
Started Mar 17 01:36:47 PM PDT 24
Finished Mar 17 01:46:44 PM PDT 24
Peak memory 216552 kb
Host smart-1a192f74-b906-4592-9f40-3a58393c3e09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740259588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.1740259588
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.134201312
Short name T307
Test name
Test status
Simulation time 34569191 ps
CPU time 0.61 seconds
Started Mar 17 01:33:27 PM PDT 24
Finished Mar 17 01:33:29 PM PDT 24
Peak memory 194864 kb
Host smart-5f217b4f-f7c4-4e82-81e7-6d8d90daa5f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134201312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.134201312
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1170785364
Short name T49
Test name
Test status
Simulation time 151906412 ps
CPU time 5.51 seconds
Started Mar 17 01:33:16 PM PDT 24
Finished Mar 17 01:33:23 PM PDT 24
Peak memory 216416 kb
Host smart-bf477f6a-659f-4399-abd8-70cbd8ad40f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170785364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1170785364
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1152694980
Short name T149
Test name
Test status
Simulation time 1215071015 ps
CPU time 6.78 seconds
Started Mar 17 01:33:17 PM PDT 24
Finished Mar 17 01:33:24 PM PDT 24
Peak memory 200448 kb
Host smart-da45965b-424a-4957-8b7a-1e2b0d75a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152694980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1152694980
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1903510363
Short name T376
Test name
Test status
Simulation time 2929375559 ps
CPU time 32.14 seconds
Started Mar 17 01:33:18 PM PDT 24
Finished Mar 17 01:33:51 PM PDT 24
Peak memory 200496 kb
Host smart-74d6789a-2fc2-435a-99e8-d9b84a891f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1903510363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1903510363
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1783579204
Short name T560
Test name
Test status
Simulation time 812223210 ps
CPU time 45.02 seconds
Started Mar 17 01:33:18 PM PDT 24
Finished Mar 17 01:34:03 PM PDT 24
Peak memory 200472 kb
Host smart-b4e42bf0-5a86-43f0-8301-507fbc231f4c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783579204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1783579204
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.6269779
Short name T385
Test name
Test status
Simulation time 1240526568 ps
CPU time 79.07 seconds
Started Mar 17 01:33:18 PM PDT 24
Finished Mar 17 01:34:37 PM PDT 24
Peak memory 200460 kb
Host smart-e6707272-0299-41ad-bf49-914175546db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6269779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.6269779
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2462595179
Short name T291
Test name
Test status
Simulation time 287552075 ps
CPU time 3.73 seconds
Started Mar 17 01:33:19 PM PDT 24
Finished Mar 17 01:33:23 PM PDT 24
Peak memory 200496 kb
Host smart-25b337ce-f525-4dbc-8f87-56c3247b5a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462595179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2462595179
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.89689528
Short name T36
Test name
Test status
Simulation time 35839905782 ps
CPU time 511.8 seconds
Started Mar 17 01:33:26 PM PDT 24
Finished Mar 17 01:42:00 PM PDT 24
Peak memory 200512 kb
Host smart-0bff9110-5d82-46b1-8e2c-8983b19ac92c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89689528 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.89689528
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2825850205
Short name T259
Test name
Test status
Simulation time 98429031 ps
CPU time 1 seconds
Started Mar 17 01:33:19 PM PDT 24
Finished Mar 17 01:33:20 PM PDT 24
Peak memory 199904 kb
Host smart-5bb86027-1aff-4565-9d5e-4a4ffb5e86e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825850205 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2825850205
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2096613939
Short name T287
Test name
Test status
Simulation time 84910276299 ps
CPU time 432.81 seconds
Started Mar 17 01:33:18 PM PDT 24
Finished Mar 17 01:40:31 PM PDT 24
Peak memory 200576 kb
Host smart-d4b62932-c348-436e-a40b-4ff62dfde787
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096613939 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2096613939
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.527185303
Short name T523
Test name
Test status
Simulation time 7389313804 ps
CPU time 29.95 seconds
Started Mar 17 01:33:18 PM PDT 24
Finished Mar 17 01:33:48 PM PDT 24
Peak memory 200528 kb
Host smart-949e68d9-6cc7-455c-aee9-933530e5a0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527185303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.527185303
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.2550531782
Short name T558
Test name
Test status
Simulation time 168716509178 ps
CPU time 176.38 seconds
Started Mar 17 01:36:45 PM PDT 24
Finished Mar 17 01:39:41 PM PDT 24
Peak memory 225168 kb
Host smart-db72ef3e-55bb-4001-bc9a-c5e46fc74d1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550531782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.2550531782
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2031099436
Short name T394
Test name
Test status
Simulation time 13954654 ps
CPU time 0.59 seconds
Started Mar 17 01:33:26 PM PDT 24
Finished Mar 17 01:33:29 PM PDT 24
Peak memory 195824 kb
Host smart-67af3ea9-ed41-4aa5-9f71-30aa322a63a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031099436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2031099436
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1060224867
Short name T368
Test name
Test status
Simulation time 1515622851 ps
CPU time 65.94 seconds
Started Mar 17 01:33:25 PM PDT 24
Finished Mar 17 01:34:34 PM PDT 24
Peak memory 230744 kb
Host smart-dc266028-8987-46a9-9e2b-d7455e559d62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060224867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1060224867
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3829693755
Short name T506
Test name
Test status
Simulation time 3300621789 ps
CPU time 16.31 seconds
Started Mar 17 01:33:24 PM PDT 24
Finished Mar 17 01:33:44 PM PDT 24
Peak memory 200588 kb
Host smart-4189ea9a-7b1a-44bd-8a1d-b4a6e1a91760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829693755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3829693755
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3926411701
Short name T373
Test name
Test status
Simulation time 7840876670 ps
CPU time 124.14 seconds
Started Mar 17 01:33:24 PM PDT 24
Finished Mar 17 01:35:32 PM PDT 24
Peak memory 200440 kb
Host smart-353157a5-8e4b-4f90-93be-7bdd45df25bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926411701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3926411701
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.848528589
Short name T301
Test name
Test status
Simulation time 952214674 ps
CPU time 13.39 seconds
Started Mar 17 01:33:24 PM PDT 24
Finished Mar 17 01:33:38 PM PDT 24
Peak memory 200284 kb
Host smart-4591380c-34d3-409c-b70b-4be5c9c623fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848528589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.848528589
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1921462222
Short name T188
Test name
Test status
Simulation time 681723204 ps
CPU time 39.61 seconds
Started Mar 17 01:33:23 PM PDT 24
Finished Mar 17 01:34:03 PM PDT 24
Peak memory 200424 kb
Host smart-bcc31e49-5225-4b38-b409-c9ca003a643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921462222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1921462222
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3963196507
Short name T254
Test name
Test status
Simulation time 652648082 ps
CPU time 4.76 seconds
Started Mar 17 01:33:26 PM PDT 24
Finished Mar 17 01:33:33 PM PDT 24
Peak memory 200396 kb
Host smart-985809f4-810e-4f82-801b-7153dea16b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963196507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3963196507
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.400675293
Short name T493
Test name
Test status
Simulation time 198636607215 ps
CPU time 2473.48 seconds
Started Mar 17 01:33:25 PM PDT 24
Finished Mar 17 02:14:42 PM PDT 24
Peak memory 249144 kb
Host smart-ef4e7fd9-3bd1-4be8-93f4-b186ec8e80b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400675293 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.400675293
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2609096960
Short name T482
Test name
Test status
Simulation time 31909443 ps
CPU time 1.23 seconds
Started Mar 17 01:33:25 PM PDT 24
Finished Mar 17 01:33:30 PM PDT 24
Peak memory 200408 kb
Host smart-e74a3bdb-ea4e-44d9-92c8-63ab49e6f322
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609096960 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2609096960
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3247571393
Short name T557
Test name
Test status
Simulation time 469627403025 ps
CPU time 535 seconds
Started Mar 17 01:33:24 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 200504 kb
Host smart-f40ce31e-0086-4513-a906-9dafe4078d80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247571393 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3247571393
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.4009437565
Short name T450
Test name
Test status
Simulation time 2135803447 ps
CPU time 42.04 seconds
Started Mar 17 01:33:25 PM PDT 24
Finished Mar 17 01:34:11 PM PDT 24
Peak memory 200480 kb
Host smart-9123b404-7726-4f6c-b01b-01f5f2d03689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009437565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.4009437565
Directory /workspace/9.hmac_wipe_secret/latest
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