Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14195458	1			T1	71		T2	40		T3	69968
all_values[1]	14195458	1			T1	71		T2	40		T3	69968
all_values[2]	14195458	1			T1	71		T2	40		T3	69968

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100668

1

T4

84

T5

3

T17

612

auto[1]

42485706

1

T1

213

T2

120

T3

209904

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40421698

1

T1

201

T2

116

T3

201699

auto[1]

2164676

1

T1

12

T2

4

T3

8205

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	28729	1			T4	40		T27	190		T15	70
all_values[0]	auto[0]	auto[1]	459	1			T4	2		T27	8		T15	5
all_values[0]	auto[1]	auto[0]	14118557	1			T1	67		T2	36		T3	69774
all_values[0]	auto[1]	auto[1]	47713	1			T1	4		T2	4		T3	194
all_values[1]	auto[0]	auto[0]	30878	1			T5	3		T13	436		T27	3
all_values[1]	auto[0]	auto[1]	197	1			T27	4		T15	4		T21	1
all_values[1]	auto[1]	auto[0]	14163870	1			T1	71		T2	40		T3	69968
all_values[1]	auto[1]	auto[1]	513	1			T27	3		T15	2		T21	3
all_values[2]	auto[0]	auto[0]	35473	1			T4	42		T17	1		T27	4
all_values[2]	auto[0]	auto[1]	4932	1			T17	611		T27	4		T15	2
all_values[2]	auto[1]	auto[0]	12044191	1			T1	63		T2	40		T3	61957
all_values[2]	auto[1]	auto[1]	2110862	1			T1	8		T3	8011		T19	15